Chip integrating PD power receiving detection and DC / DC conversion and power receiving circuit

Abstract

The invention relates to the technical field of Ethernet power supply, and discloses a chip and a power receiving circuit integrating PD power receiving detection and DC / DC conversion, the chip comprises a chip body, and the chip body is provided with a VDD pin, a VSS pin, a GND pin and an SW pin; the chip body is provided with a logic control unit, an under-voltage detection unit, an over-temperature protection unit, an over-current detection unit, an impedance detection unit and a DC / DC conversion unit. When the chip is used, the MOS tube M1 is connected with the GND pin and the VSS pin, and the logic control unit controls the on-off of the MOS tube M1 based on an impedance state detection signal, an under-voltage detection signal, an over-temperature detection signal and an over-current detection signal, so that on one hand, common ground of PD power receiving detection and DC / DC conversion is realized; and on the other hand, the logic control unit controls the on-off of the MOS tube M1 according to whether the temperature is over-high or not, so that the temperature of the chip can be prevented from being over-high, the common ground of PD power receiving detection and DC / DC conversion is realized, and the problem that the temperature is over-high when the two chips are integrated together is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of Ethernet power supply, and in particular to a chip and a power receiving circuit integrating PD power receiving detection and DC / DC conversion. Background Art

[0002] Power over Ethernet (PoE), also known as PoE, is a technology that can transmit power to devices via Ethernet. This technology is compatible with existing Ethernet cabling infrastructure and allows devices to be powered through their network ports, thus eliminating the need for power cables and saving cabling and hardware costs. Power over Ethernet technology has been widely used in video phones, security, IoT devices and other fields.

[0003] The Ethernet power supply system generally includes a power supply device (Power Sourcing Equipment, which can be referred to as PSE), a power receiving device (Power Device, which can be referred to as PD), and an Ethernet cable that transmits power and data between the two. The power receiving device usually includes the following modules: 1: The powered interface circuit connected to the Ethernet cable, also known as the PD interface circuit; 2: DC / DC converter, used to receive power transmitted by Ethernet cable and realize DC voltage conversion; 3: Powered devices, such as webcams, IoT devices, and wireless IP.

[0004] The circuit diagram of the existing receiving end equipment is as follows Figure 1 As shown, it mainly includes two chips, namely, a PD interface chip and a DC / DC converter chip. Figure 1 The circuit shown is implemented by two chips, so there are problems such as high system cost and high failure rate. In serious cases, it will seriously affect the reliability and maintainability of the POE system application.

[0005] The reason why the existing receiving-end device circuit is implemented with two chips is due to the following two reasons: 1: There is a potential difference between the power ground of the PD interface chip and the power ground of the DC / DC converter chip, that is, the PD interface chip cannot be designed with a common ground with the DC / DC converter chip, so the two chips cannot be integrated on the same substrate using conventional low-cost processes. They need to be made into two separate chips, which makes the tape-out cost and packaging cost high; 2: If the two chips are integrated together, the heat generated by the two chips cannot be dissipated in time, resulting in an increase in chip heat and temperature, thus affecting the normal operation of the chip. Summary of the invention

[0006] In view of the shortcomings of the background technology, the present invention provides a chip and a power receiving circuit that integrates PD power receiving detection and DC / DC conversion. The technical solution to be solved is that the existing PD power receiving circuit cannot integrate the PD interface chip and the DC / DC converter chip on one chip due to the inability to achieve a common ground for the PD interface chip and the high heat and other reasons, which will lead to problems such as high cost and high failure rate of the power receiving end equipment in the Ethernet power supply system.

[0007] In order to solve the above technical problems, in the first aspect, the present invention provides the following technical solutions: a chip integrating PD power detection and DC / DC conversion, comprising a chip body, wherein the chip body is provided with a VDD pin, a VSS pin, a GND pin and a SW pin; The chip body is also provided with a logic control unit, an undervoltage detection unit, an overtemperature protection unit, an overcurrent detection unit, an impedance detection unit and a DC / DC conversion unit; The impedance detection unit is electrically connected to the VDD pin, provides a path from the VDD pin to the ground terminal based on the voltage of the VDD pin, and inputs an impedance detection state signal to the logic control unit, and an impedance detection resistor is set on the path; The undervoltage detection unit is electrically connected to the VDD pin, and inputs an undervoltage detection signal to the logic control unit based on the voltage of the VDD pin; The over-temperature protection unit is used to detect the chip temperature and input an over-temperature detection signal to the logic control unit; The GND pin is electrically connected to the VSS pin through the MOS tube M1, the overcurrent detection unit inputs an overcurrent detection signal to the logic control unit based on the current on the branch from the GND pin to the VSS pin, the logic control unit is electrically connected to the gate of the MOS tube M1, and controls the on and off of the MOS tube M1 based on the impedance state detection signal, the undervoltage detection signal, the overtemperature detection signal and the overcurrent detection signal; The DC / DC conversion unit is electrically connected to the VDD pin, and is used to output a DC voltage through the SW pin when the MOS tube M1 is turned on.

[0008] In a certain implementation manner of the first aspect, a first voltage reference unit is further provided on the chip body, and the first voltage reference unit is electrically connected to the VDD pin and is used to generate a first reference voltage and a second reference voltage; The impedance detection unit includes a first comparator and a MOS tube M2, wherein the positive input terminal of the first comparator is used to input a first reference voltage, the negative input terminal of the first comparator is electrically connected to the VDD pin, the output terminal of the first comparator is electrically connected to the logic control unit and the gate of the MOS tube M2 respectively, the source of the MOS tube M2 is grounded, and the drain of the MOS tube M2 is electrically connected to the VDD pin through the impedance detection resistor.

[0009] In a certain embodiment of the first aspect, the undervoltage detection unit includes a second comparator, the positive input terminal of the second comparator is used to input a second reference voltage, the negative input terminal of the second comparator is electrically connected to the VDD pin, and the output terminal of the second comparator is electrically connected to the logic control unit.

[0010] In a certain implementation manner of the first aspect, the chip body is further provided with an FB pin and a BST pin; The DC / DC conversion unit includes a second voltage reference unit, an error amplifier, a PWM comparator, a current limiting comparator, an oscillator, a ramp generator, an adder, a current detection amplifier, a current detection resistor, a MOS tube M3, a first voltage stabilizing unit, and a driving unit; The second voltage reference unit is electrically connected to the VDD pin, and is used to generate a third reference voltage and a fourth reference voltage; the FB pin is electrically connected to the positive input terminal of the error amplifier, the input terminal of the oscillator, one end of the capacitor C1 and one end of the capacitor C2 respectively; the oscillator is electrically connected to the S input terminal of the RS trigger and the input terminal of the ramp generator respectively, and is used to provide a clock signal for the S input terminal of the RS trigger and the input terminal of the ramp generator; the negative input terminal of the error amplifier is used to input the third reference voltage; the output terminal of the error amplifier is electrically connected to the negative input terminal of the PWM comparator, one end of the resistor R2 and one end of the capacitor C2; the other end of the resistor R2 is electrically connected to the other end of the capacitor C1; The output end of the ramp generator is electrically connected to one input end of the adder, the other input end of the adder is electrically connected to the output end of the current detection amplifier, the output end of the adder is electrically connected to the positive input end of the current limiting comparator and the positive input end of the PWM comparator respectively, and the negative input end of the current limiting comparator is used to input a fourth reference voltage; the output end of the current limiting comparator is electrically connected to the first R input end of the RS trigger, the output end of the PWM comparator is electrically connected to the second R input end of the RS trigger, and the Q output end of the RS trigger is electrically connected to the control signal input end of the driving unit; The positive input terminal of the current detection amplifier is electrically connected to one end of the current detection resistor and the VDD pin respectively, the negative input terminal of the current detection amplifier is electrically connected to the other end of the current detection resistor and the drain of the MOS tube M3 respectively, and the source of the MOS tube M1 is electrically connected to the SW pin; The first voltage stabilizing unit is electrically connected to the VDD pin, and provides an operating voltage to the driving unit through a diode D1 based on the voltage of the VDD pin. The driving output end of the driving unit is electrically connected to the gate of the MOS tube M3, and the ground end of the first voltage stabilizing unit and the ground end of the driving unit are both electrically connected to the SW pin.

[0011] In a certain embodiment of the first aspect, an EN pin is also provided on the chip body, and the second voltage reference unit includes a second voltage stabilizing unit and a reference unit, the second voltage stabilizing unit is electrically connected to the VDD pin and the EN pin, and is used to provide a regulated voltage to the reference unit after an enable signal is input to the EN pin, and the reference unit outputs a third reference voltage and a fourth reference voltage based on the regulated voltage.

[0012] In a certain implementation of the first aspect, the EN pin is electrically connected to the GND pin through the zener diode.

[0013] In a certain embodiment of the first aspect, the VDD pin, EN pin and VSS pin are distributed from top to bottom on the left side of the chip body, the SW pin and FB pin are distributed from top to bottom on the right side of the chip body, the BST pin is located on the upper side of the chip body, and the GND pin is located on the lower side of the chip body.

[0014] In a certain implementation of the first aspect, the MOS transistor M3 is an NMOS transistor.

[0015] In certain implementations of the first aspect, the frequency of the clock signal output by the oscillator is positively correlated with the voltage of the FB pin.

[0016] In a second aspect, the present invention provides a power receiving circuit, comprising the above-mentioned chip integrating PD power receiving detection and DC / DC conversion, and also comprising two rectifier units, wherein the DC voltage output end of each rectifier unit is electrically connected to each other, and is electrically connected to the cathode of the voltage zener diode ZD10, one end of the capacitor C10, one end of the capacitor C11, one end of the capacitor C12 and the VDD pin of the chip, the anode of the voltage zener diode ZD10 and the other end of the capacitor C10 are electrically connected to the VSS pin respectively, the other end of the capacitor C11 and the other end of the capacitor C12 are electrically connected to the GND pin respectively, and the SW pin is electrically connected to the VDD pin respectively. The cathode of the Zener diode ZD11 is electrically connected to one end of the inductor L10, and is electrically connected to the BST pin of the chip through the capacitor C16. The anode of the Zener diode ZD11 is electrically connected to the GND pin. The other end of the inductor L10 is electrically connected to one end of the capacitor C13, one end of the capacitor C14, one end of the resistor R10 and one end of the capacitor C15 respectively. The other end of the capacitor C13 and the other end of the capacitor C14 are electrically connected to the GND pin respectively. The other end of the resistor R10 is electrically connected to one end of the capacitor C15, the FB pin and one end of the resistor R11 respectively. The other end of the resistor R11 is electrically connected to the GND pin.

[0017] Compared with the prior art, the present invention has the following beneficial effects: the chip of the present invention connects the GND pin and the VSS pin by setting the MOS tube M1, and allows the logic control unit to control the on-off of the MOS tube M1 based on the impedance state detection signal, the undervoltage detection signal, the overtemperature detection signal and the overcurrent detection signal, so that the MOS tube M1 can realize the common ground of PD power reception detection and DC / DC conversion on the one hand, and the logic control unit controls the on-off of the MOS tube M1 according to whether the temperature is over, so as to avoid the chip temperature being too high, realize the common ground of PD power reception detection and DC / DC conversion, and avoid the problem of too high temperature when the two chips are integrated together. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a circuit diagram of an existing PD powered device; Figure 2 is a structural diagram of the chip in Example 1; Figure 3 It is a circuit diagram of the power receiving circuit in the second embodiment. DETAILED DESCRIPTION

[0019] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0020] Embodiment 1 like Figure 2As shown, the present embodiment provides a chip integrating PD power detection and DC / DC conversion, including a chip body 1, on which a VDD pin, a VSS pin, a GND pin and a SW pin are provided; The chip body 1 is also provided with a logic control unit 10, an undervoltage detection unit 13, an overtemperature protection unit 14, an overcurrent detection unit 15, an impedance detection unit 11 and a DC / DC conversion unit; The impedance detection unit 11 is electrically connected to the VDD pin, provides a path from the VDD pin to the ground terminal based on the voltage of the VDD pin, and inputs an impedance detection state signal to the logic control unit 10, and an impedance detection resistor R1 is set on the path; The undervoltage detection unit 13 is electrically connected to the VDD pin, and inputs an undervoltage detection signal to the logic control unit 10 based on the voltage of the VDD pin; The over-temperature protection unit 13 is used to detect the chip temperature and input an over-temperature detection signal to the logic control unit 10; The GND pin is electrically connected to the VSS pin through the MOS tube M1. The overcurrent detection unit 15 is used to input an overcurrent detection signal to the logic control unit 10 based on the current on the branch from the GND pin to the VSS pin. The logic control unit 10 is electrically connected to the gate of the MOS tube M1 and controls the on and off of the MOS tube M1 based on the impedance state detection signal, the undervoltage detection signal, the overtemperature detection signal and the overcurrent detection signal. The DC / DC conversion unit is electrically connected to the VDD pin, and is used to output a DC voltage through the SW pin when the MOS tube M1 is turned on.

[0021] In actual use, the chip of the present invention connects the GND pin and the VSS pin by setting the MOS tube M1, and allows the logic control unit 10 to control the on and off of the MOS tube M1 based on the impedance state detection signal, the undervoltage detection signal, the overtemperature detection signal and the overcurrent detection signal, so that the MOS tube M1 can realize the common ground of the PD power reception detection and the DC / DC conversion on the one hand, and the logic control unit 10 controls the on and off of the MOS tube M1 according to whether the temperature is over, so as to avoid the chip temperature being too high, realize the common ground of the PD power reception detection and the DC / DC conversion, and avoid the problem of too high temperature when the two chips are integrated together.

[0022] like Figure 2 As shown, in this embodiment, the chip body 1 is further provided with a first voltage reference unit 12, which is electrically connected to the VDD pin and is used to generate a first reference voltage and a second reference voltage; In addition, the impedance detection unit 11 includes a first comparator 16 and a MOS tube M2. The positive input terminal of the first comparator 16 is used to input a first reference voltage, the negative input terminal of the first comparator 16 is electrically connected to the VDD pin, the output terminal of the first comparator 16 is electrically connected to the logic control unit 10 and the gate of the MOS tube M2 respectively, the source of the MOS tube M2 is grounded, and the drain of the MOS tube M2 is electrically connected to the VDD pin through the impedance detection resistor R1.

[0023] In actual use, when the voltage of the VDD pin is lower than the first reference voltage, the output end of the first comparator 16 outputs a high-level impedance state detection signal, and the high-level impedance state detection signal drives the MOS tube M2 to turn on at the same time. At this time, the resistance value of the impedance detection resistor R1 can be known by detecting the impedance detection resistor R1, thereby realizing impedance detection; when the voltage of the pin VDD is higher than the first reference voltage, the output end of the first comparator 16 outputs a low-level impedance state detection signal. Exemplarily, the magnitude of the first reference voltage can be 11.6V.

[0024] like Figure 2 As shown, in this embodiment, the undervoltage detection unit 13 includes a second comparator, the positive input terminal of the second comparator is used to input the second reference voltage, the negative input terminal of the second comparator is electrically connected to the VDD pin, and the output terminal of the second comparator is electrically connected to the logic control unit 10. Exemplarily, the second reference voltage can be 31V.

[0025] In actual use, when the voltage of the VDD pin is lower than the second reference voltage, the output end of the second comparator outputs a high-level undervoltage detection signal; when the voltage of the pin VDD is higher than the second reference voltage, the output end of the second comparator outputs a low-level undervoltage detection signal.

[0026] In this embodiment, when the over-temperature protection unit 14 detects that the temperature is greater than the threshold temperature, a high-level over-temperature detection signal is input to the logic control unit 10 , otherwise, a low-level over-temperature detection signal is input to the logic control unit 10 .

[0027] In actual use, in order to avoid repeated over-temperature protection, the over-temperature protection unit 14 in this embodiment has a hysteresis temperature detection interval when performing temperature detection. For example, when the temperature threshold is 150°C and the hysteresis temperature detection interval is 20°C, the over-temperature protection is triggered when the chip temperature exceeds 150°C. After the over-temperature protection is triggered, when the temperature is lower than 130°C, the over-temperature protection unit 14 inputs a low-level over-temperature detection signal to the logic control unit 10.

[0028] In this embodiment, when the overcurrent detection unit 15 detects that the current is greater than the threshold current, a high-level overcurrent detection signal is input to the logic control unit 10 , otherwise a low-level overcurrent detection signal is input to the logic control unit 10 .

[0029] In this embodiment, the logic control unit 10 is a state machine circuit, and the process of controlling the on and off of the MOS tube M1 based on the impedance state detection signal, the undervoltage detection signal, the overtemperature detection signal and the overcurrent detection signal is as follows: When the impedance state detection signal is at a high level, the logic control unit 10 drives the MOS tube M1 to turn off. When the impedance state detection signal is at a low level, the following judgment is made: When the over-temperature detection signal is at a high level, the logic control unit 10 drives the MOS tube M1 to turn off; Alternatively, when the undervoltage detection signal is at a high level, the logic control unit 10 drives the MOS tube M1 to turn off; Alternatively, when the overcurrent detection signal is at a high level, the logic control unit 10 drives the MOS tube M1 to turn off; Alternatively, when the over-temperature detection signal is at a low level, the under-voltage detection signal is at a low level, and the over-current detection signal is at a low level, the logic control unit 10 drives the MOS tube M1 to be turned on.

[0030] In addition, in this embodiment, the voltage of the VDD pin of the chip is determined according to the voltage provided by the PSE device. The VDD voltage during impedance state detection is set by the PSE device. The present invention only needs to provide the first reference voltage.

[0031] like Figure 2 As shown, in this embodiment, the chip body 1 is also provided with an FB pin and a BST pin; The DC / DC conversion unit includes a second voltage reference unit 20, an error amplifier 25, a PWM comparator 26, a current limiting comparator 27, an oscillator 21, a ramp generator 22, an adder 29, a current detection amplifier 28, a current detection resistor R3, a MOS tube M3, a first voltage stabilizing unit 23, a driving unit 24 and an RS trigger 31; The second voltage reference unit 20 is electrically connected to the VDD pin, and is used to generate a third reference voltage and a fourth reference voltage; the FB pin is electrically connected to the positive input terminal of the error amplifier 25, the input terminal of the oscillator 21, one end of the capacitor C1 and one end of the capacitor C2 respectively; the oscillator 21 is electrically connected to the S input terminal of the RS trigger 31 and the input terminal of the ramp generator 22 respectively, and is used to provide a clock signal for the S input terminal of the RS trigger 31 and the input terminal of the ramp generator 22; the negative input terminal of the error amplifier 25 is used to input the third reference voltage; the output terminal of the error amplifier 25 is electrically connected to the negative input terminal of the PWM comparator 26, one end of the resistor R2 and one end of the capacitor C2; the other end of the resistor R2 is electrically connected to the other end of the capacitor C1; The output end of the ramp generator 22 is electrically connected to one input end of the adder 29, the other input end of the adder 29 is electrically connected to the output end of the current detection amplifier 28, the output end of the adder 29 is electrically connected to the positive input end of the current limiting comparator 27 and the positive input end of the PWM comparator 26 respectively, and the negative input end of the current limiting comparator 27 is used to input the fourth reference voltage; the output end of the current limiting comparator 27 is electrically connected to the first R input end of the RS trigger 31, the output end of the PWM comparator 26 is electrically connected to the second R input end of the RS trigger 31, and the Q output end of the RS trigger 31 is electrically connected to the control signal input end of the driving unit 24; The positive input terminal of the current detection amplifier 28 is electrically connected to one end of the current detection resistor R3 and the VDD pin respectively, the negative input terminal of the current detection amplifier 28 is electrically connected to the other end of the current detection resistor R3 and the drain of the MOS tube M3 respectively, and the source of the MOS tube M1 is electrically connected to the SW pin; The first voltage stabilizing unit 23 is electrically connected to the VDD pin, and provides an operating voltage to the driving unit through the diode D1 based on the voltage of the VDD pin. The driving output end of the driving unit 24 is electrically connected to the gate of the MOS tube M3, and the ground end of the first voltage stabilizing unit 23 and the ground end of the driving unit 24 are both electrically connected to the SW pin.

[0032] Specifically, in this embodiment, an EN pin is also provided on the chip body 1, and the second voltage reference unit 20 includes a second voltage stabilizing unit 32 and a reference unit 30. The second voltage stabilizing unit 32 is electrically connected to the VDD pin and the EN pin, and is used to provide a regulated voltage to the reference unit 30 after an enable signal is input to the EN pin. The reference unit 30 outputs a third reference voltage and a fourth reference voltage based on the regulated voltage.

[0033] In this embodiment, the second voltage stabilizing unit 32 provides a regulated voltage to the reference unit 30 after a high level enable signal is input to the EN pin.

[0034] In addition, Figure 2 As shown, the EN pin is electrically connected to the GND pin through a Zener diode ZD1.

[0035] In this embodiment, the pin distribution relationship on the chip body 1 is as follows: The VDD pin, EN pin and VSS pin are distributed from top to bottom on the left side of the chip body 1, the SW pin and FB pin are distributed from top to bottom on the right side of the chip body 1, the BST pin is located on the upper side of the chip body 1, and the GND pin is located on the lower side of the chip body 1. Figure 2 The pins above are for illustration only. For specific pin distribution, refer to Figure 3 .

[0036] In addition, in this embodiment, the MOS transistor M3 is an NMOS transistor. Moreover, the frequency of the clock signal output by the oscillator 21 is positively correlated with the voltage of the FB pin.

[0037] Embodiment 2 like Figure 3 As shown, this embodiment provides a power receiving circuit, including a chip integrating PD power receiving detection and DC / DC conversion in the first embodiment, and also including two rectifier units 3, the DC voltage output end of each rectifier unit 3 is electrically connected to each other, and is electrically connected to the cathode of the voltage zener diode ZD10, one end of the capacitor C10, one end of the capacitor C11, one end of the capacitor C12 and the VDD pin of the chip, the anode of the voltage zener diode ZD10 and the other end of the capacitor C10 are electrically connected to the VSS pin respectively, the other end of the capacitor C11 and the other end of the capacitor C12 are electrically connected to the GND pin respectively, and the SW pin is electrically connected to the VDD pin. The anode of the Zener diode ZD11 is electrically connected to the GND pin, the other end of the inductor L10 is electrically connected to one end of the capacitor C13, one end of the capacitor C14, one end of the resistor R10 and one end of the capacitor C15, the other end of the capacitor C13 and the other end of the capacitor C14 are electrically connected to the GND pin, the other end of the resistor R10 is electrically connected to one end of the capacitor C15, the FB pin and one end of the resistor R11, and the other end of the resistor R11 is electrically connected to the GND pin.

[0038] In actual use, Figure 2 The output voltage VOUT of the circuit shown is fed back to the chip through the resistor R10 and the resistor R11. The oscillator 21 outputs a clock signal of corresponding frequency based on the voltage of the FB pin. At the same time, the error amplifier 25, the PWM comparator 26 and the current limiting comparator 27 adjust the state of the RS trigger 31 according to the feedback voltage, thereby inputting the corresponding control signal to the driving unit 24. The driving unit 24 controls the on and off of the MOS tube M3 according to the control signal, thereby adjusting the size of the output voltage VOUT.

[0039] The above is based on the present invention as an inspiration. Through the above description, relevant staff can make various changes and modifications without departing from the technical idea of ​​this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A chip integrating PD power detection and DC / DC conversion, characterized in that: The chip body comprises a VDD pin, a VSS pin, a GND pin and a SW pin. The chip body is also provided with a logic control unit, an undervoltage detection unit, an overtemperature protection unit, an overcurrent detection unit, an impedance detection unit and a DC / DC conversion unit; The impedance detection unit is electrically connected to the VDD pin, provides a path from the VDD pin to the ground terminal based on the voltage of the VDD pin, and inputs an impedance detection state signal to the logic control unit, and an impedance detection resistor is set on the path; The undervoltage detection unit is electrically connected to the VDD pin, and inputs an undervoltage detection signal to the logic control unit based on the voltage of the VDD pin; The over-temperature protection unit is used to detect the chip temperature and input an over-temperature detection signal to the logic control unit; The GND pin is electrically connected to the VSS pin through the MOS tube M1, the overcurrent detection unit inputs an overcurrent detection signal to the logic control unit based on the current on the branch from the GND pin to the VSS pin, the logic control unit is electrically connected to the gate of the MOS tube M1, and controls the on and off of the MOS tube M1 based on the impedance state detection signal, the undervoltage detection signal, the overtemperature detection signal and the overcurrent detection signal; The DC / DC conversion unit is electrically connected to the VDD pin, and is used to output a DC voltage through the SW pin when the MOS tube M1 is turned on.

2. The chip integrating PD power detection and DC / DC conversion according to claim 1, characterized in that: The chip body is also provided with a first voltage reference unit, which is electrically connected to the VDD pin and is used to generate a first reference voltage and a second reference voltage; The impedance detection unit includes a first comparator and a MOS tube M2, wherein the positive input terminal of the first comparator is used to input a first reference voltage, the negative input terminal of the first comparator is electrically connected to the VDD pin, the output terminal of the first comparator is electrically connected to the logic control unit and the gate of the MOS tube M2 respectively, the source of the MOS tube M2 is grounded, and the drain of the MOS tube M2 is electrically connected to the VDD pin through the impedance detection resistor.

3. The chip integrating PD power detection and DC / DC conversion according to claim 2, characterized in that: The undervoltage detection unit includes a second comparator, a positive input terminal of the second comparator is used to input a second reference voltage, a negative input terminal of the second comparator is electrically connected to the VDD pin, and an output terminal of the second comparator is electrically connected to the logic control unit.

4. A chip integrating PD power detection and DC / DC conversion according to any one of claims 1 to 3, characterized in that: The chip body is also provided with an FB pin and a BST pin; The DC / DC conversion unit includes a second voltage reference unit, an error amplifier, a PWM comparator, a current limiting comparator, an oscillator, a ramp generator, an adder, a current detection amplifier, a current detection resistor, a MOS tube M3, a first voltage stabilizing unit, and a driving unit; The second voltage reference unit is electrically connected to the VDD pin, and is used to generate a third reference voltage and a fourth reference voltage; the FB pin is electrically connected to the positive input terminal of the error amplifier, the input terminal of the oscillator, one end of the capacitor C1 and one end of the capacitor C2 respectively; the oscillator is electrically connected to the S input terminal of the RS trigger and the input terminal of the ramp generator respectively, and is used to provide a clock signal for the S input terminal of the RS trigger and the input terminal of the ramp generator; the negative input terminal of the error amplifier is used to input the third reference voltage; the output terminal of the error amplifier is electrically connected to the negative input terminal of the PWM comparator, one end of the resistor R2 and one end of the capacitor C2; the other end of the resistor R2 is electrically connected to the other end of the capacitor C1; The output end of the ramp generator is electrically connected to one input end of the adder, the other input end of the adder is electrically connected to the output end of the current detection amplifier, the output end of the adder is electrically connected to the positive input end of the current limiting comparator and the positive input end of the PWM comparator respectively, and the negative input end of the current limiting comparator is used to input a fourth reference voltage; the output end of the current limiting comparator is electrically connected to the first R input end of the RS trigger, the output end of the PWM comparator is electrically connected to the second R input end of the RS trigger, and the Q output end of the RS trigger is electrically connected to the control signal input end of the driving unit; The positive input terminal of the current detection amplifier is electrically connected to one end of the current detection resistor and the VDD pin respectively, the negative input terminal of the current detection amplifier is electrically connected to the other end of the current detection resistor and the drain of the MOS tube M3 respectively, and the source of the MOS tube M1 is electrically connected to the SW pin; The first voltage stabilizing unit is electrically connected to the VDD pin, and provides an operating voltage to the driving unit through a diode D1 based on the voltage of the VDD pin. The driving output end of the driving unit is electrically connected to the gate of the MOS tube M3, and the ground end of the first voltage stabilizing unit and the ground end of the driving unit are both electrically connected to the SW pin.

5. The chip integrating PD power detection and DC / DC conversion according to claim 4, characterized in that: An EN pin is also provided on the chip body, and the second voltage reference unit includes a second voltage stabilizing unit and a reference unit. The second voltage stabilizing unit is electrically connected to the VDD pin and the EN pin, and is used to provide a regulated voltage to the reference unit after an enable signal is input to the EN pin. The reference unit outputs a third reference voltage and a fourth reference voltage based on the regulated voltage.

6. The chip integrating PD power detection and DC / DC conversion according to claim 5, characterized in that: The EN pin is electrically connected to the GND pin through the voltage stabilizing diode.

7. The chip integrating PD power detection and DC / DC conversion according to claim 5, characterized in that: The VDD pin, EN pin and VSS pin are distributed from top to bottom on the left side of the chip body, the SW pin and FB pin are distributed from top to bottom on the right side of the chip body, the BST pin is located on the upper side of the chip body, and the GND pin is located on the lower side of the chip body.

8. The chip integrating PD power detection and DC / DC conversion according to claim 4, characterized in that: The MOS tube M3 is an NMOS tube.

9. The chip integrating PD power detection and DC / DC conversion according to claim 4, characterized in that: The frequency of the clock signal output by the oscillator is positively correlated with the voltage of the FB pin.

10. A power receiving circuit, characterized in that: A chip integrating PD power detection and DC / DC conversion as claimed in claim 7, further comprising two rectifier units, wherein the DC voltage output end of each rectifier unit is electrically connected to each other, and is electrically connected to the cathode of the voltage zener diode ZD10, one end of the capacitor C10, one end of the capacitor C11, one end of the capacitor C12 and the VDD pin of the chip, the anode of the voltage zener diode ZD10 and the other end of the capacitor C10 are electrically connected to the VSS pin respectively, the other end of the capacitor C11 and the other end of the capacitor C12 are electrically connected to the GND pin respectively, and the SW pin is electrically connected to the voltage zener diode ZD10, the VDD pin is electrically connected to the SW pin of the zener diode ZD10, and the VDD pin is electrically connected to the SW pin of the zener diode ZD10. The cathode of D11 is electrically connected to one end of the inductor L10, and is electrically connected to the BST pin of the chip through the capacitor C16. The anode of the voltage zener diode ZD11 is electrically connected to the GND pin. The other end of the inductor L10 is electrically connected to one end of the capacitor C13, one end of the capacitor C14, one end of the resistor R10 and one end of the capacitor C15 respectively. The other end of the capacitor C13 and the other end of the capacitor C14 are electrically connected to the GND pin respectively. The other end of the resistor R10 is electrically connected to one end of the capacitor C15, the FB pin and one end of the resistor R11 respectively. The other end of the resistor R11 is electrically connected to the GND pin.

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