PCIe link training method, electronic equipment and computer readable storage medium

Abstract

The invention relates to the technical field of PCIe communication, and discloses a PCIe link training method, an electronic device and a computer readable storage medium, in the link training process, the negotiation state of a link is monitored in the DLInit stage, when the negotiation state of the link does not meet the expected state, the PCIe link is controlled to enter the Disabled or Recovery. Equation state, so that the PCIe link negotiates again, and the negotiation efficiency is improved. When the negotiation state of the PCIe link does not meet the expected state, the link training state machine is controlled to enter the preset sub-state, and the expected state is negotiated again. According to the invention, the negotiation state of the link is monitored in the DLInit stage, so that the risk of disk dropping caused by the fact that one end of the link forcibly enters the predetermined sub-state in the DLActive stage is avoided, and the stability of the PCIe link is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of PCIe communication technology, and in particular to a PCIe link training method, electronic device, and computer-readable storage medium. Background Art

[0002] PCI-Express (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard used to connect various hardware devices on the motherboard, such as graphics cards, network adapters, storage controllers, etc. PCIe has the advantages of high speed, scalability and flexibility. Due to the high transmission rate of PCIe, a series of important functions such as equalization, PLL improvement and clock recovery are added to PCIe transmitters and receivers to improve data transmission and ensure the accuracy and integrity of data at both ends.

[0003] In actual use, in order to ensure normal communication between devices at both ends of the link and achieve high-speed and reliable data transmission, PCIe link training is required. Link training includes initializing the physical layer, detecting and configuring link width, link rate handshake negotiation and other processes. At both ends of the PCIe link, the entire link training negotiation process is basically handled by hardware. During the link training process, poor link signal quality may lead to reduced link transmission speed and reduced number of channels in the link, making it impossible to fully utilize the performance of the PCIe link, resulting in insufficient stability of the PCIe link.

[0004] At present, the relevant technology obtains the status data of the LTSSM state machine in real time through software, and determines whether the LTSSM state machine is in a normal working state based on the status data; if not, based on the status data and the judgment logic corresponding to the target sub-state machine in the LTSSM state machine, it is determined whether the target sub-state machine has a state abnormality; if there is a state abnormality, the state of the LTSSM state machine is transferred from the target sub-state machine to the LTSSM training entry, that is, the initial state of the LTSSM state machine, so that the LTSSM state machine can re-execute the PCIe link training logic.

[0005] However, this method requires real-time monitoring of the LTSSM state through software. Since the jump of the LTSSM state is implemented by hardware, the jump speed of the LTSSM state is fast, which may cause the software to fail to detect the abnormal point in time and handle it in time, which may still cause the speed to drop and the physical channel (lane) to drop, thus affecting the performance of the PCIe link. In addition, if the software recognizes the abnormality and intervenes after the link has entered the DL_Active state, it may cause greater risks such as disk drop, resulting in insufficient stability of the PCIe link. Summary of the invention

[0006] The embodiment of the present application provides a training method, electronic device and computer-readable storage medium for a PCIe link, which monitors the negotiation status of the link in the DL_Init stage during the link training process, and controls the PCIe link to enter the Disabled or Recovery.Equalization state when the negotiation status of the link does not meet the expected state, so that the PCIe link can be renegotiated, and controls the link training state machine to enter a predetermined sub-state when the negotiation status of the PCIe link does not meet the expected state, and renegotiates to the expected state. The present application monitors the negotiation status of the link in the DL_Init stage, avoids the risk of disk drop caused by forcing one end of the link to enter a predetermined sub-state in the DL_Active stage, and improves the stability of the PCIe link.

[0007] The embodiments of the present application provide the following technical solutions:

[0008] In a first aspect, an embodiment of the present application provides a PCIe link training method, the method comprising:

[0009] Disable the data link layer link enable to allow the PCIe link to perform link auto-negotiation.

[0010] When the data link control and management state machine is in the DL_Init state, determining whether the negotiation information of the PCIe link meets the expected conditions;

[0011] If yes, then enable the data link layer link;

[0012] If not, the link training state machine is controlled to enter a sub-state to renegotiate the PCIe link, wherein the sub-state includes a Disabled state or a Recovery state.

[0013] In some embodiments, the negotiation information of the PCIe link includes a link width, and the expected condition includes a link width threshold;

[0014] Determine whether the negotiation information of the PCIe link meets the expected conditions, including:

[0015] Determine whether the link width is equal to the link width threshold;

[0016] If yes, it is determined that the negotiation information of the PCIe link meets the expected conditions;

[0017] If not, it is determined that the negotiation information of the PCIe link does not meet the expected conditions;

[0018] Control link training state machine to enter sub-states, including:

[0019] Controls the link training state machine to enter the Disabled state.

[0020] In some embodiments, when the negotiation information of the PCIe link does not meet the expected condition, the method further includes:

[0021] Determine whether a first negotiation number of the PCIe link is greater than a first negotiation number threshold, wherein the first negotiation number is used to count the number of times the PCIe link performs link width negotiation;

[0022] If yes, the first negotiation times are cleared to zero, and the data link layer link enable is turned on to end the PCIe link training;

[0023] If not, the first negotiation times are increased, and the link training state machine is controlled to enter a sub-state, so that the PCIe link re-negotiates the link width.

[0024] In some embodiments, when the negotiation information of the PCIe link meets the expected condition, the method further includes:

[0025] The first negotiation times are cleared to zero, and the data link layer link enable is turned on to end the PCIe link training.

[0026] In some embodiments, the negotiation information of the PCIe link includes a link rate, and the expected condition includes a link rate threshold;

[0027] Determine whether the negotiation information of the PCIe link meets the expected conditions, including:

[0028] Determine whether the link rate is equal to the link rate threshold;

[0029] If yes, it is determined that the negotiation information of the PCIe link meets the expected conditions;

[0030] If not, it is determined that the negotiation information of the PCIe link does not meet the expected condition.

[0031] In some embodiments, when the negotiation information of the PCIe link does not meet the expected condition, the method further includes:

[0032] Determine whether a second negotiation number of the PCIe link is greater than a second negotiation number threshold, wherein the second negotiation number is used to count the number of times the PCIe link performs link rate negotiation;

[0033] If yes, then enable the data link layer link;

[0034] If not, further determining whether the link rate of the last negotiation is equal to the link rate threshold, and whether the current second negotiation number is zero;

[0035] If the link rate of the last negotiation is equal to the link rate threshold, and the current second negotiation number is zero, the current signal parameter is set to the signal parameter of the last negotiation, and the link training state machine is controlled to enter a sub-state, and the second negotiation number is increased;

[0036] If the link rate of the last negotiation is not equal to the link rate threshold, or the current second negotiation number is not zero, the link training state machine is controlled to enter a sub-state, and the second negotiation number is increased.

[0037] In some embodiments, controlling the link training state machine to enter a sub-state includes:

[0038] Control link training state machine to enter Recovery state, including:

[0039] Control link training state machine to enter Recovery.Equalization state;

[0040] If the link rate is equal to the link rate threshold, the method further includes:

[0041] Save the current signal parameters.

[0042] In some embodiments, after saving the current signal parameters, the method further includes:

[0043] The data link layer link enable is turned on, and the second negotiation times are cleared to end the training of the PCIe link.

[0044] In some embodiments, the method is applied to a flash memory device, the flash memory device is connected to a host;

[0045] After enabling the data link layer link enable, the method further includes:

[0046] The data link control and management state machine is controlled to enter the DL_Active state from the DL_Init state, wherein in the DL_Active state, transaction layer messages can be transmitted between the flash memory device and the host.

[0047] In a second aspect, an embodiment of the present application provides an electronic device, including:

[0048] A processor and a memory, the processor is used to execute an executable program code in the memory, and when the executable program code is executed, the processor executes instructions of the PCIe link training method of the first aspect.

[0049] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed, the training method of the PCIe link as in the first aspect is implemented.

[0050] The beneficial effect of the implementation mode of the present application is: different from the prior art, the implementation mode of the present application provides a training method for a PCIe link, the method comprising: turning off the data link layer link enable to enable the PCIe link to perform link self-negotiation; when the data link control and management state machine is in the DL_Init state, judging whether the negotiation information of the PCIe link meets the expected conditions; if so, turning on the data link layer link enable; if not, controlling the link training state machine to enter a sub-state to enable the PCIe link to renegotiate, wherein the sub-state includes a Disabled state or a Recovery state.

[0051] During the link training process, the negotiation state of the link is monitored in the DL_Init stage. When the negotiation state of the link does not meet the expected state, the PCIe link is controlled to enter the Disabled or Recovery.Equalization state to allow the PCIe link to renegotiate. When the negotiation state of the PCIe link does not meet the expected state, the link training state machine is controlled to enter a predetermined sub-state. Compared with the current related technology of real-time monitoring of the LTSSM state by software, since the jump of the LTSSM state is implemented by hardware, the jump speed of the LTSSM state is faster, which may cause the software to be unable to detect the abnormal point in time and handle it in time, which may still cause the speed to drop and the physical channel (lane) to drop. , which in turn affects the performance of the PCIe link. The present application can monitor the negotiation status of the link in the DL_Init stage, and when the negotiation status of the link does not meet the expected status, control the PCIe link to renegotiate, thereby not affecting the performance of the PCIe link; and, compared with the current related technology in which the software recognizes the abnormality and intervenes only after the link has entered the DL_Active state, the present application monitors the negotiation status of the link in the DL_Init stage, and when the negotiation status of the PCIe link does not meet the expected status, controls the link training state machine to enter a predetermined sub-state, and renegotiates to the expected state, thereby avoiding the risk of disk drop caused by one end of the link being forced to enter a predetermined sub-state in the DL_Active stage, thereby improving the stability of the PCIe link. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] One or more embodiments are exemplarily described by corresponding drawings, which do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and the figures in the drawings do not constitute proportional limitations unless otherwise stated.

[0053] Figure 1 It is a flow chart of a PCIe link training provided in an embodiment of the present application;

[0054] Figure 2 It is a flow chart of a PCIe link balancing process provided by an embodiment of the present application;

[0055] Figure 3 It is a flow chart of a data link control and management state machine provided in an embodiment of the present application;

[0056] Figure 4 It is a flowchart of a PCIe link training method provided in an embodiment of the present application;

[0057] Figure 5 yes Figure 4 A detailed flow chart of step S402 in FIG.

[0058] Figure 6 It is a flowchart of ending PCIe link training provided by an embodiment of the present application;

[0059] Figure 7 yes Figure 4 A detailed flow chart of step S404 in FIG.

[0060] Figure 8 It is a flowchart of determining whether the first negotiation number of a PCIe link is greater than the first negotiation number threshold provided by an embodiment of the present application;

[0061] Fig. 9 It is a schematic diagram of the overall process of a PCIe link training method provided in an embodiment of the present application;

[0062] Fig.10 yes Figure 4 Another detailed flow chart of step S402 in FIG.

[0063] Fig.11 It is a flowchart of determining whether the second negotiation number of a PCIe link is greater than the second negotiation number threshold provided by an embodiment of the present application;

[0064] Fig.12 yes Figure 4 Another detailed flow chart of step S404 in FIG.

[0065] Fig.13 This is a schematic diagram of a process for saving current signal parameters provided by an embodiment of the present application;

[0066] Fig.14 It is a schematic diagram of the overall process of a PCIe link training method provided in an embodiment of the present application;

[0067] Fig.15 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application.

[0068] Description of Figure Numbers:

[0069] Label name Label name 150 Electronic devices 151 processor 152 Memory DETAILED DESCRIPTION

[0070] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0071] In addition, the technical features involved in each embodiment of the present application described below can be combined with each other as long as they do not conflict with each other.

[0072] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in this specification and in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used in this specification includes any and all combinations of one or more of the related listed items.

[0073] The technical solution of the present application is described in detail below in conjunction with the accompanying drawings:

[0074] See also Figure 1 , Figure 1 It is a flowchart of a PCIe link training provided in an embodiment of the present application.

[0075] like Figure 1As shown in the figure, LTSSM stands for Link Training and Status State Machine, which is located in the physical layer of the PCIe bus and is used to manage and control the training and status of the PCIe link. The LTSSM state machine has a total of 11 states, including Detect, Polling, Configuration, Recovery, L0, L0s, L1, L2, Hot Reset, Loopback, and Disabled. Logical conversions are used between these states to ensure that the PCIe link can work properly. For example, the normal PCIe link training state conversion process is Detect->Polling->Configuration->L0, where L0 is the power state in which the PCIe link can work normally; when the system starts or resets, PCIe starts from Detect, enters L0 through Polling and Configuration, and officially starts the transmission of user commands and data.

[0076] Specifically, Detect is the entry state of LTSSM. When the Downstream Port detects the existence of the PCIe peer device (Upstream Port, such as PCIe SSD), it will enter the Polling state.

[0077] The Polling state is the process of establishing "barrier-free" communication between the devices at both ends of the link. TS messages are sent to each other to complete operations such as Bit Lock, Symbol Lock or Block Alignment, and signal polarity flipping.

[0078] Bit Lock means bit locking, accurately identifying 0 and 1 in the data stream.

[0079] Symbol Lock means character lock, which is applicable to PCIe 1.0 and PCIe 2.0 and determines the start and end of each character.

[0080] Block Alignment indicates block alignment, which is applicable to PCIe 3.0, PCIe 4.0, PCIe 5.0 and PCIe 6.0. EIEOS (Electrical Idle Exit Ordered Set) is used to obtain the position of Block Sync Header.

[0081] Configuration refers to the process by which the devices at both ends of the link determine the link width, assign channel numbers, and align the channels. For example, determining whether a PCIe SSD works with a link width of PCIe x4 or PCIe x8 and making these links work together is also done through TS messages.

[0082] In the embodiment of the present application, during the first entry into L0, the PCIe device always operates at a transmission rate of 2.5GT / s; after entering L0, if the devices at both ends of the PCIe support a higher rate, it will enter the Recovery state. This state allows the device to change the transmission rate of the signal, re-perform Bit Lock, Symbol Lock or Block Alignment, signal polarity flipping and other operations, and adjust the signal quality. In addition, when the device exits from the L0s, L1 state, and when a link error occurs, it will also enter the Recovery state.

[0083] In some embodiments, for PCIe 2.0, due to the relatively low signal rate, it only needs to re-perform Bit Lock, Symbol Lock, signal polarity flipping and other operations at a rate of 5GT / s after entering L0 for the first time to meet the rate and signal quality requirements. For PCIe 3.0 and higher rates, an equalization process called "Equalization Procedure" is required in the Recovery state. During this process, the ports at both ends of the PCIe link - Downstream Port (host) and Upstream Port (such as PCIe SSD) will negotiate signal parameters with each other through TS messages to achieve the best link state.

[0084] Please refer to Figure 2 , Figure 2 It is a flow chart of PCIe link balancing provided in an embodiment of the present application.

[0085] like Figure 2 As shown, Downstream first enters the Recovery.RcvrLock state, and then continues to send TS1 to Upstream and sets the speed_change bit to 1.

[0086] After seeing TS1 coming in, the Upstream also enters the Recovery.RcvrLock state and sends back the TS1 sequence. However, at this time, the speed_change bit is still 0. When the Upstream receives 8 consecutive TS1s and the speed_change bit is set to 1, the speed_change bit in the TS1 and TS2 sent back by Upstream is set to 1, and the Downstream is told the recommended working rate, and then enters the Recovery.RcvrCfg state.

[0087] After receiving the rate feedback recommended by the upstream, the downstream also returns the TS2 sequence and sends the EIOS sequence, preparing to enter the Electrical Idle state. At this time, the LTSSM is in the Recovery.RcvrCfg state.

[0088] After that, Downstream and Upstream enter Electrical Idle successively, and LTSSM is in Recovery.Speed ​​state.

[0089] After a timeout period (the specification requires at least 800ns, and the trace shows ~8us), the upstream sends EIEOS, exits Electrical Idle, and attempts to run at the maximum rate of 8GT / s.

[0090] Then, Downstream also exited Electrical Idle and tried running at the maximum rate of 8GT / s.

[0091] Finally, both sides start EQ. After EQ, the PCIe link can return to normal working state.

[0092] Please refer to Figure 3 , Figure 3 It is a flow chart of a data link control and management state machine provided in an embodiment of the present application.

[0093] like Figure 3As shown, the data link layer tracks the status of the link. It communicates the link status with the transaction layer and the physical layer, and performs link management through the physical layer. The data link layer contains a data link control and management state machine (DLCMSM) to perform these tasks. Among them, the status output includes the following 6 states: DL_Inactive (link inactive) means that the physical layer reports that the link is not operational, or no device is connected to the port; DL_Feature means that the physical layer reports that the link is operational and performs data link feature exchange; DL_Init means that the physical layer reports that the link is operational and initializes flow control for the default virtual channel; DL_Active means normal operation mode; DL_Down means that the data link layer is not communicating with the component on the other side of the link; DL_Up means that the data link layer is communicating with the component on the other side of the link.

[0094] In the embodiment of the present application, the rules for each state are as follows:

[0095] The DL_Inactive (link inactive) state is the initial state after a PCI Express hot reset, warm reset, or cold reset.

[0096] In some embodiments, when the state machine enters the DL_Inactive state, all data link layer state information is reset to default values. If the port supports optional data link feature exchange, the Remote Data Link Feature Supported and Remote Data Link Feature Support Valid fields must be cleared.

[0097] In some embodiments, the conditions for exiting from the DL_Inactive state to the DL_Feature state are: if the port supports optional data link feature exchange, the data link feature exchange enable bit is set, the transaction layer indicates that the link is not disabled by software, and the physical layer reports LinkUp=1b on the physical link, then exit to the DL_Feature state.

[0098] In some embodiments, the conditions for exiting from the DL_Inactive state to the DL_Init state are: if the port does not support optional data link feature exchange, or the data link feature exchange enable bit is cleared, the transaction layer indicates that the link is not disabled by software, and the physical layer reports LinkUp=1b on the physical link, then exit to the DL_Init state.

[0099] In some embodiments, when the state machine is in the DL_feature state, the data link feature exchange protocol is executed. The DL_Down state is reported. The data link layer with the DL_Down state is allowed to discard any received TLPs if it does not acknowledge these TLPs by sending one or more acknowledgement DLLPs.

[0100] In some embodiments, the condition for exiting from the DL_feature state to the DL_Init state is: if the data link feature exchange is completed successfully and the physical layer continues to report LinkUp=1b on the physical link, or the data link feature exchange determines that the remote data link layer does not support the optional data link feature exchange protocol and the physical layer continues to report LinkUp=1b on the physical link, then exit to the DL_Init state.

[0101] In some embodiments, the condition for exiting from the DL_feature state to the DL_Inactive state is: if the physical layer reports LinkUp=0b on the physical link, the data link feature exchange protocol is terminated and the state is exited to the DL_Inactive state.

[0102] In some embodiments, when the state machine is in the DL_Init state, flow control is initialized for the default virtual channel VCo according to a flow control initialization protocol.

[0103] In some embodiments, the DL_Down state is reported when the state machine is in the FC_INIT1 state; the DL_Up state is reported when the state machine is in the FC_INIT2 state. The data link layer with the DL_Down state is allowed to discard any received TLPs, provided that it does not acknowledge these TLPs by sending one or more acknowledgement DLLPs (data link layer packets).

[0104] In some embodiments, the condition for exiting from the DL_Init state to the DL_Active state is that the flow control initialization is successfully completed and the physical layer continues to report LinkUp=1b on the physical link. The condition for terminating the attempt to initialize flow control for VC0 and exiting to the DL_Inactive state is that the physical layer reports LinkUp=0b on the physical link.

[0105] DL_Active is called the normal operating state. When the state machine is in the DL_Active state, it accepts and transmits TLP information to the transaction layer and physical layer. It generates and accepts DLLPs. It reports the DL_Up state to the transaction layer and data link layer.

[0106] In some embodiments, the condition for exiting from the DL_Active state to the DL_Inactive state is: if the physical layer reports LinkUp=0b on the physical link. If the downstream port is capable of reporting an unexpected offline error, the transition from DL_Active to DL_Inactive must be considered an unexpected offline error, unless error detection is blocked in the following cases: If the secondary bus reset bit in the bridge control register has been set by software, then a subsequent transition to DL_Inactive should not be considered an error. If the link disable bit has been set by software, then a subsequent transition to DL_Inactive should not be considered an error. If the switch downstream port transitions to DL_Inactive due to an event above the port, then the transition to DL_Inactive should not be considered an error. Example events include the switch upstream port propagating a hot reset, the switch upstream link transitioning to DL_Down, and the secondary bus reset bit in the switch upstream port being set. If a PME_Turn_Off message is sent through this port, then a subsequent transition to DL_Inactive should not be considered an error.

[0107] Note that in this case, the transition to DL_Inactive will not occur until power is turned off, reset, or a request is sent to the physical layer to restore the link.

[0108] Additionally, an unexpected off-line error may be detected if the PME_Turn_Off / PME_TO_Ack handshake does not complete successfully.

[0109] If the port is associated with a hot-plug slot (the Hot-Plug Capable bit in the Slot Capability Register is set) and the Hot-Plug Exception bit in the Slot Capability Register is set, then any transition to DL_Inactive shall not be considered an error, and, if the port is associated with a hot-plug slot (the Hot-Plug Capable bit in the Slot Capability Register is set) and the Power Controller Control bit in the Slot Control Register is set (power off), then any transition to DL_Inactive shall not be considered an error.

[0110] Error prevention initiated by one or more of the above cases must remain in effect until the port exits the DL_Active state, and upon subsequent return to the DL_Active state, none of the prevention cases are in effect upon return to the DL_Active state.

[0111] See also Figure 4 , Figure 4 It is a flowchart of a PCIe link training method provided in an embodiment of the present application.

[0112] The PCIe link training method is applied to an electronic device, and the electronic device includes at least one processor and at least one memory. Specifically, the PCIe link training method is applied to at least one processor in the electronic device.

[0113] like Figure 4 As shown, the PCIe link training method includes:

[0114] Step S401: turn off the data link layer link enable to enable the PCIe link to perform link auto-negotiation.

[0115] Specifically, the electronic device includes a PCIe controller, and a register or configuration bit is obtained in the PCIe controller on the disk side, where the register or configuration bit is used to control link enable, and the register or configuration bit is set to a disabled state, thereby turning off the data link layer link enable to prevent the DLL from receiving and processing the initialization flow control message from the host, so that the PCIe link can perform link self-negotiation.

[0116] In an embodiment of the present application, the data link layer link enable is turned off by setting the register or configuration bit of the PCIe controller to the disabled state, that is, the disk does not receive the initialization flow control message sent by the host, so that the link cannot enter the DL_Active stage, that is, when the link state enters DL_Init, it will not actively enter the DL_Active stage, giving the software sufficient time to detect the PCIe negotiation state. Only when the flow control is completed at both ends of the link can the link enter the DL_Active stage.

[0117] Step S402: When the data link control and management state machine is in the DL_Init state, it is determined whether the negotiation information of the PCIe link meets the expected conditions.

[0118] Specifically, in the data link control and management state machine (DLCMSM), the DL_Init state (Data Link Initialization) indicates that the physical layer notifies the data link layer that the current PCIe link is available and that the physical layer is in the link initialization state. When the data link control and management state machine is in the DL_Init state, it determines whether the negotiation information of the PCIe link meets the expected conditions. If the negotiation information of the PCIe link meets the expected conditions, step S403 is entered; if the negotiation information of the PCIe link does not meet the expected conditions, step S404 is entered.

[0119] Please refer to Figure 5 , Figure 5 yes Figure 4 A detailed flowchart of step S402 in FIG.

[0120] In the embodiment of the present application, the negotiation information of the PCIe link includes the link width, and the expected condition includes the link width threshold.

[0121] like Figure 5 As shown, step S402: when the data link control and management state machine is in the DL_Init state, judging whether the negotiation information of the PCIe link meets the expected conditions includes:

[0122] Step S421: Obtain link width.

[0123] Specifically, link width refers to the number of active physical channels (lanes) in a PCIe (Peripheral Component Interconnect Express) link. Link width is used to characterize the number of data channels that can be transmitted simultaneously between two PCIe devices, thereby affecting the total bandwidth of the link. In an embodiment of the present application, the software on the disk side (such as firmware or driver) accesses the PCIe controller register or configuration space through the programming interface of the PCIe controller, searches and reads the register containing the link width information, and then parses the read register value to obtain the link width, and stores the link width in a variable or data structure inside the software.

[0124] In some embodiments, link widths include but are not limited to x1, x2, x4, x8, x16 and x32, and different link widths correspond to different bandwidths, where x1 refers to 1 channel with a bandwidth of approximately 250MB / s (Gen1), x2 refers to 2 channels with a bandwidth of approximately 500MB / s (Gen1), x4 refers to 4 channels with a bandwidth of approximately 1GB / s (Gen1), x8 refers to 8 channels with a bandwidth of approximately 2GB / s (Gen1), x16 refers to 16 channels with a bandwidth of approximately 4GB / s (Gen1), and x32 refers to 32 channels with a bandwidth of approximately 8GB / s (Gen1).

[0125] Step S422: Determine whether the link width is equal to the link width threshold.

[0126] Specifically, when the data link control and management state machine is in the DL_Init state, it is determined whether the link width is equal to the link width threshold. If the link width is equal to the link width threshold, step S423 is entered; if the link width is not equal to the link width threshold, step S424 is entered. It should be noted that the link width threshold can be set according to actual needs. The present application does not limit the specific value of the link width threshold. In some embodiments, the link width threshold is determined based on the design specifications of the device and the support capabilities of the slot. For example, if the device is designed as PCIe Gen4 x16, but a slot that only supports PCIe Gen3 x8 is inserted, then the actual link width will be limited by the capacity of the slot, that is, x8, and the link width threshold is determined to be x8 at this time.

[0127] Step S423: Determine whether the negotiation information of the PCIe link meets the expected conditions.

[0128] Specifically, if the link width is equal to the link width threshold, it is determined that the negotiation information of the PCIe link meets the expected condition.

[0129] Step S424: Determine that the negotiation information of the PCIe link does not meet the expected condition.

[0130] Specifically, if the link width is not equal to the link width threshold, it is determined that the negotiation information of the PCIe link does not meet the expected condition.

[0131] Step S403: Turn on the data link layer link enable.

[0132] Specifically, if the negotiation information of the PCIe link meets the expected conditions, the data link layer link enable is turned on, that is, the disk side enables DLL Link En, the link state enters the normal operation mode (DL_Active state), and the first negotiation count is cleared to 0. In the PCIe (Peripheral Component Interconnect Express) protocol, the data link layer is responsible for processing data transmission between the transaction layer and the physical layer. The data link layer contains a data link control and management state machine (DLCMSM), which is used to track the status of the link and communicate the link status with the transaction layer and the physical layer. When the negotiation information of the PCIe link meets the expected conditions, it means that the devices at both ends of the link have successfully completed the link training and the negotiation of parameters such as link width and rate. In this process, the physical layer will report that the link is operational, and the data link layer will perform a series of initialization operations, including initializing flow control for the default virtual channel. Once these initialization operations are completed and the link negotiation information (such as link width, rate, error detection mechanism, etc.) is consistent with the expected conditions, the data link layer will turn on the link enable and enter the DL_Active state. In the DL_Active state, the data link layer can normally receive and send TLP (Transaction Layer Packets) and DLLP (Data Link Layer Packets) to achieve reliable data transmission.

[0133] Please refer to Figure 6 , Figure 6 It is a flowchart of ending PCIe link training provided in an embodiment of the present application.

[0134] like Figure 6 As shown, the process of ending the training of the PCIe link includes:

[0135] Step S601: when the negotiation information of the PCIe link meets the expected conditions, the first negotiation times are cleared to zero, and the data link layer link enable is turned on to end the training of the PCIe link.

[0136] Specifically, in the PCIe (Peripheral Component Interconnect Express) link training, the number of negotiations is recorded as the first negotiation number, and the first negotiation number is increased once for each additional negotiation. When the negotiation information of the PCIe link meets the expected conditions, where the negotiation information includes the link width, if the link width is equal to the link width threshold, the expected conditions are met, indicating that the link has successfully negotiated the expected link width, and the first negotiation number is cleared. When the link width and other related parameters are negotiated successfully, the data link layer (Data Link Layer, DLL) can turn on the link enable, indicating that the DLL is now ready to receive and send transaction layer packets (Transaction Layer Packets, TLPs) and data link layer packets (Data Link Layer Packets, DLLPs), so as to perform normal PCIe communication. When the link width is equal to the link width threshold, and the data link layer link enable has been turned on, it can be considered that the training phase of the PCIe link has ended, thereby entering the normal PCIe communication mode.

[0137] In an embodiment of the present application, by determining whether the negotiation information of the PCIe link meets the expected conditions, if the expected conditions are met, the data link layer link enable is turned on. The present application can ensure the normal transmission of data and the stable operation of the link.

[0138] Step S404: Control the link training state machine to enter a sub-state to allow the PCIe link to renegotiate.

[0139] Specifically, the sub-states include the Recovery state. If the negotiation information of the PCIe link does not meet the expected conditions, the control link training state machine (LTSSM) will enter the Re-Training (Recovery) state to renegotiate the PCIe link. In PCIe (Peripheral Component Interconnect Express) technology, the link training state machine (LTSSM) is responsible for managing and controlling the initialization, configuration, and subsequent state transitions of the link. When the PCIe device is reset or the link needs to be re-established, the LTSSM will perform link training according to the predetermined state process to ensure that the devices at both ends of the link can communicate normally. If the negotiation information does not meet the expected conditions, the LTSSM will trigger the retraining process, wherein the Re-Training state, also known as the Recovery state, is a top-level state of the LTSSM, which is used to handle the situation where the link needs to renegotiate parameters. After entering the Re-Training state, the LTSSM will restart the link training process, including receiver detection, polling, and configuration steps, in an attempt to achieve the expected link parameters and stability.

[0140] Please refer to Figure 7 , Figure 7 yes Figure 4 A detailed flow chart of step S404 in FIG.

[0141] like Figure 7 As shown, step S404: controlling the link training state machine to enter a sub-state so that the PCIe link can be renegotiated, including:

[0142] Step S441: Control the link training state machine to enter the Disabled state.

[0143] Specifically, the Disabled state is a top-level state of the PCIe link training state machine (LTSSM). When the PCIe link needs to be renegotiated, it can be achieved by controlling the link training state machine to enter the Disabled state. After controlling the link training state machine to enter the Disabled state, the link will be placed in an inactive state and no longer perform data transmission. In the Disabled state, the link retraining process can be started through software control or hardware triggering. The retraining process will include renegotiation of link parameters, such as link width, rate, error detection mechanism, etc., to ensure that the link can meet current communication needs. It can be understood that after the retraining is completed, the link will return to an active state and normal data transmission can be performed.

[0144] Please refer to Figure 8 , Figure 8It is a flowchart provided by an embodiment of the present application for determining whether the first negotiation number of a PCIe link is greater than the first negotiation number threshold.

[0145] like Figure 8 As shown, the process of determining whether the first negotiation number of the PCIe link is greater than the first negotiation number threshold includes:

[0146] Step S801: If the link width is not equal to the link width threshold, the first negotiation number of the PCIe link is obtained.

[0147] Specifically, in PCIe (Peripheral Component Interconnect Express) link training, the number of negotiations is recorded as the first negotiation number, and the first negotiation number is increased once for each additional negotiation. When the negotiation information of the PCIe link does not meet the expected conditions, where the negotiation information includes the link width, if the link width is not equal to the link width threshold, the first negotiation number of the current PCIe link is obtained.

[0148] Step S802: Determine whether the first negotiation count of the PCIe link is greater than a first negotiation count threshold.

[0149] Specifically, determine whether the first negotiation number of the PCIe link is greater than the first negotiation number threshold. If the first negotiation number of the PCIe link is greater than the first negotiation number threshold, enter step S803; if the first negotiation number of the PCIe link is less than or equal to the first negotiation number threshold, enter step S804. It should be noted that the first negotiation number threshold can be set according to actual needs. For example, the first negotiation number threshold is set to 3 times.

[0150] Step S803: clear the first negotiation times and enable the data link layer link to end the PCIe link training.

[0151] Specifically, if the first negotiation number of the PCIe link is greater than the first negotiation number threshold, the first negotiation number is cleared to zero, and the data link layer link enable is turned on to end the training of the PCIe link.

[0152] Step S804: increase the first negotiation times, and control the link training state machine to enter a sub-state, so that the PCIe link re-negotiates the link width.

[0153] Specifically, if the first negotiation number of the PCIe link is less than or equal to the first negotiation number threshold, the first negotiation number is increased by one, and the link training state machine is controlled to enter a sub-state, so that the PCIe link re-negotiates the link width.

[0154] Please refer to Fig. 9, Fig. 9 It is a schematic diagram of the overall process of a PCIe link training method provided in an embodiment of the present application.

[0155] like Fig. 9 As shown, the overall process of the PCIe link training method includes:

[0156] Step S901: turn off the data link layer link enable.

[0157] Specifically, the electronic device includes a PCIe controller, and a register or configuration bit is obtained in the PCIe controller on the disk side, where the register or configuration bit is used to control link enable, and the register or configuration bit is set to a disabled state, thereby turning off the data link layer link enable to prevent the DLL from receiving and processing the initialization flow control message from the host, so that the PCIe link can perform link self-negotiation.

[0158] Step S902: Control the data link control and management state machine to be in the DL_Init state.

[0159] Specifically, the data link control and management state machine is in the DL_Init state. In the data link control and management state machine (DLCMSM), the DL_Init state indicates that the physical layer notifies the data link layer that the current PCIe link is available and that the physical layer is in the link initialization state, so as to determine whether the negotiation information of the PCIe link meets the expected conditions in subsequent steps.

[0160] Step S903: Determine whether the link width is equal to the link width threshold.

[0161] Specifically, determining whether the negotiation information of the PCIe link meets the expected conditions includes: determining whether the link width is equal to the link width threshold. If the link width is equal to the link width threshold, proceed to step S905; if the link width is not equal to the link width threshold, proceed to step S904.

[0162] Step S904: Determine whether the first negotiation count of the PCIe link is greater than a first negotiation count threshold.

[0163] Specifically, determine whether the first negotiation number of the PCIe link is greater than the first negotiation number threshold. If the first negotiation number of the PCIe link is greater than the first negotiation number threshold, proceed to step S905; if the first negotiation number of the PCIe link is less than or equal to the first negotiation number threshold, proceed to step S906.

[0164] Step S905: clear the first negotiation times and enable the data link layer link.

[0165] Specifically, if the link width is equal to the link width threshold, or the first negotiation number of the PCIe link is greater than the first negotiation number threshold, the first negotiation number is cleared and the data link layer link enable is turned on.

[0166] Step S906: increase the first negotiation times, and control the link training state machine to enter a sub-state, so that the PCIe link re-negotiates the link width.

[0167] Specifically, the sub-states include the Recovery state. If the negotiation information of the PCIe link does not meet the expected conditions, the control link training state machine (LTSSM) will enter the Re-Training (Recovery) state to allow the PCIe link to re-negotiate the link width. In PCIe (Peripheral Component Interconnect Express) technology, the link training state machine (LTSSM) is responsible for managing and controlling the initialization, configuration, and subsequent state transitions of the link. When the PCIe device is reset or the link needs to be re-established, the LTSSM will perform link training according to the predetermined state process to ensure that the devices at both ends of the link can communicate normally. If the negotiation information does not meet the expected conditions, the LTSSM will trigger the retraining process, where the Re-Training state, also known as the Recovery state, is a top-level state of the LTSSM, which is used to handle situations where the link needs to renegotiate parameters. After entering the Re-Training state, the LTSSM will restart the link training process.

[0168] Please refer to Fig.10 , Fig.10 yes Figure 4 Another detailed flowchart of step S402 in FIG.

[0169] In the embodiment of the present application, the negotiation information of the PCIe link includes the link rate, and the expected condition includes the link rate threshold.

[0170] like Fig.10 As shown, step S402: when the data link control and management state machine is in the DL_Init state, judging whether the negotiation information of the PCIe link meets the expected conditions includes:

[0171] Step S425: Obtain link rate.

[0172] Specifically, the link rate refers to the speed at which a host or router sends data to a link, also known as the data rate or bit rate, which describes the number of bits transmitted through the link per unit time. The unit of the link rate is bit per second (bit / s). In some embodiments, the unit of the link rate also includes kb / s (kilobits per second), Mb / s (megabits per second), Gb / s (gigabits per second) and Tb / s (terabit per second). When the data link control and management state machine is in the DL_Init state, the actual rate of the current PCIe link is obtained, that is, the number of bits that the link can transmit per second.

[0173] In some embodiments, the maximum link rate of PCIe Gen1 is 2.5 Gb / s (per channel); the maximum link rate of PCIe Gen2 is 5 Gb / s (per channel), the maximum link rate of PCIe Gen3 is 8 Gb / s (per channel), the maximum link rate of PCIe Gen4 can reach 16 Gb / s (per channel), the maximum link rate of PCIe Gen5 can reach 32 Gb / s (per channel), and the link rate per channel of PCIe Gen6 is up to 64 GT / s, which is twice the link rate of PCIe 5.0.

[0174] Step S426: Determine whether the link rate is equal to the link rate threshold.

[0175] Specifically, when the data link control and management state machine is in the DL_Init state, determine whether the link rate is equal to the link rate threshold. If the link rate is equal to the link rate threshold, enter step S4237; if the link rate is not equal to the link rate threshold, enter step S428. It should be noted that the link rate threshold can be set according to actual needs. This application does not limit the specific value of the link rate threshold. For example, the link rate threshold can be set to 16Gb / s.

[0176] Step S427: Determine whether the negotiation information of the PCIe link meets the expected conditions.

[0177] Specifically, if the link rate is equal to the link rate threshold, it is determined that the negotiation information of the PCIe link meets the expected condition.

[0178] Step S428: Determine that the negotiation information of the PCIe link does not meet the expected condition.

[0179] Specifically, if the link rate is not equal to the link rate threshold, it is determined that the negotiation information of the PCIe link does not meet the expected condition.

[0180] Please refer to Fig.11 , Fig.11It is a flowchart provided by an embodiment of the present application for determining whether the second negotiation number of a PCIe link is greater than a second negotiation number threshold.

[0181] like Fig.11 As shown, the process of determining whether the second negotiation number of the PCIe link is greater than the second negotiation number threshold includes:

[0182] Step S1101: when the negotiation information of the PCIe link does not meet the expected condition, obtain a second negotiation number of the PCIe link.

[0183] Specifically, in PCIe (Peripheral Component Interconnect Express) link training, the number of negotiations is recorded as the second negotiation number, and the second negotiation number is increased once for each additional negotiation. When the negotiation information of the PCIe link does not meet the expected conditions, where the negotiation information includes the link rate, if the link rate is not equal to the link rate threshold, the second negotiation number of the current PCIe link is obtained.

[0184] Step S1102: Determine whether the second negotiation count of the PCIe link is greater than a second negotiation count threshold.

[0185] Specifically, determine whether the second negotiation times of the PCIe link is greater than the second negotiation times threshold. If the second negotiation times of the PCIe link is greater than the second negotiation times threshold, proceed to step S1103; if the second negotiation times of the PCIe link is less than or equal to the second negotiation times threshold, proceed to step S1104. It should be noted that the second negotiation times threshold can be set according to actual needs. For example, the second negotiation times threshold is set to 3 times.

[0186] Step S1103: Turn on the data link layer link enable.

[0187] Specifically, if the second negotiation number of the PCIe link is greater than the second negotiation number threshold, the second negotiation number is cleared to zero, and the data link layer link enable is turned on to end the training of the PCIe link.

[0188] Step S1104: Determine whether the link rate of the last negotiation is equal to the link rate threshold, and whether the current second negotiation number is zero.

[0189] Specifically, if the second negotiation number of the PCIe link is less than or equal to the second negotiation number threshold, it is further determined whether the link rate of the last negotiation is equal to the link rate threshold, and the current second negotiation number is zero. If the link rate of the last negotiation is equal to the link rate threshold, and the current second negotiation number is zero, then step S1105 is entered; if the link rate of the last negotiation is not equal to the link rate threshold, and the current second negotiation number is not zero, then step S1106 is entered.

[0190] Step S1105: Set the current signal parameters as the signal parameters of the last negotiation, control the link training state machine to enter a sub-state, and increase the second negotiation times.

[0191] Specifically, if the link rate of the last negotiation is equal to the link rate threshold, and the current second negotiation number is zero, the current signal parameters are set to the signal parameters of the last negotiation, and the link training state machine is controlled to enter the sub-state, and the second negotiation number is increased.

[0192] Step S1106: Control the link training state machine to enter a sub-state, and increase the second negotiation times.

[0193] Specifically, if the link rate of the last negotiation is not equal to the link rate threshold, and the current second negotiation number is not zero, the link training state machine is controlled to enter a sub-state, and the second negotiation number is increased.

[0194] Please refer to Fig.12 , Fig.12 yes Figure 4 Another detailed flowchart of step S404 in FIG.

[0195] In the embodiment of the present application, the sub-state includes the Recovery state, and the Recovery state includes the Recovery.Equalization state.

[0196] like Fig.12 As shown, step S404: controlling the link training state machine to enter a sub-state so that the PCIe link can be renegotiated, including:

[0197] Step S442: Control the link training state machine to enter the Recovery state.

[0198] For details, please refer to Fig.13 , Fig.13 yes Fig.11 A detailed flowchart of step S442 in FIG.

[0199] like Fig.13As shown, step S442: controlling the link training state machine to enter the Recovery state, including:

[0200] Step S4421: Control the link training state machine to enter the Recovery.Equalization state.

[0201] Specifically, the link training state machine (LTSSM) is controlled to enter the Recovery.Equalization state, usually to optimize the signal quality by renegotiating the link parameters (including rate, width, etc.) when the link is unstable or the error rate is too high. LTSSM (Link Training and Status State Machine) is a state machine implemented by the PCIe physical layer, which is used to control and manage the data link on the PCIe bus. It is responsible for link training and link negotiation to ensure the optimal link speed and width. The Recovery state is an important state in the LTSSM, which is used to renegotiate and recover when there is a problem with the link. When the link rate of the last negotiation is not equal to the link rate threshold, and the current second negotiation number is not zero, the LTSSM will automatically or manually trigger to enter the Recovery.Equalization state, where the Recovery.Equalization state is a sub-state of Recovery, which is specifically used for link balancing. When the link needs to enter the Recovery.Equalization state, it is usually because the link signal quality has degraded or retraining is required. In the Recovery.Equalization substate, the receiver (Rx) attempts to relock the signal of the transmitter (Tx) and configures and optimizes the receive equalization (Rx Equalization) to compensate for the signal attenuation, distortion, and crosstalk on the link so that the PCIe link can be renegotiated.

[0202] Please refer to Fig.13 , Fig.13 It is a flowchart of saving current signal parameters provided in an embodiment of the present application.

[0203] like Fig.13 As shown in FIG. 1 , the process of saving the current signal parameters includes:

[0204] Step S1301: Save current signal parameters.

[0205] Specifically, if the link rate of the last negotiation is equal to the link rate threshold, and the current second negotiation number is zero, then the current signal parameters are saved, where the signal parameters include.

[0206] Please refer to Fig.14 , Fig.14 It is a flowchart of ending PCIe link training provided in an embodiment of the present application.

[0207] like Fig.14 As shown, the process of ending the training of the PCIe link includes:

[0208] Step S1401: Turn on the data link layer link enable, and clear the second negotiation times to end the PCIe link training.

[0209] Specifically, in PCIe (Peripheral Component Interconnect Express) link training, the number of negotiations is recorded as the second negotiation number. Each additional negotiation will increase the second negotiation number by one. If the link width is equal to the link width threshold, it means that the link has successfully negotiated the desired link width, and the second negotiation number is cleared. When the link width and other related parameters are negotiated successfully, the data link layer (Data Link Layer, DLL) can turn on the link enable, indicating that the DLL is now ready to receive and send transaction layer packets (Transaction Layer Packets, TLPs) and data link layer packets (Data Link Layer Packets, DLLPs), so as to carry out normal PCIe communication. When the link width is equal to the link width threshold, and the data link layer link enable has been turned on, it can be considered that the training phase of the PCIe link has ended, thus entering the normal PCIe communication mode.

[0210] In an embodiment of the present application, by determining whether the negotiation information of the PCIe link meets the expected conditions, if the expected conditions are met, the data link layer link enable is turned on. The present application can ensure the normal transmission of data and the stable operation of the link.

[0211] Please refer to Fig.14 , Fig.14 It is a schematic diagram of the overall process of a PCIe link training method provided in an embodiment of the present application.

[0212] like Fig.14 As shown, the overall process of the PCIe link training method includes:

[0213] Step S1401: turn off the data link layer link enable.

[0214] Specifically, the electronic device includes a PCIe controller, and a register or configuration bit is obtained in the PCIe controller on the disk side, where the register or configuration bit is used to control link enable, and the register or configuration bit is set to a disabled state, thereby turning off the data link layer link enable to prevent the DLL from receiving and processing the initialization flow control message from the host, so that the PCIe link can perform link self-negotiation.

[0215] In an embodiment of the present application, the data link layer link enable is turned off by setting the register or configuration bit of the PCIe controller to the disabled state, that is, the disk does not receive the initialization flow control message sent by the host, so that the link cannot enter the DL_Active stage, that is, when the link state enters DL_Init, it will not actively enter the DL_Active stage, giving the software sufficient time to detect the PCIe negotiation state. Only when the flow control is completed at both ends of the link can the link enter the DL_Active stage.

[0216] Step S1402: Control the data link control and management state machine to be in the DL_Init state.

[0217] Specifically, the data link control and management state machine is in the DL_Init state. In the data link control and management state machine (DLCMSM), the DL_Init state indicates that the physical layer notifies the data link layer that the current PCIe link is available and that the physical layer is in the link initialization state, so as to determine whether the negotiation information of the PCIe link meets the expected conditions in subsequent steps.

[0218] Step S1403: Determine whether the link rate is equal to the link rate threshold.

[0219] Specifically, determine whether the link rate is equal to the link rate threshold. If the link rate is equal to the link rate threshold, proceed to step S1408; if the link rate is not equal to the link rate threshold, proceed to step S1404; wherein, the link rate threshold can be set according to actual needs, for example, the link rate threshold is set to 5 Gb / s.

[0220] Step S1404: Determine whether the second negotiation count of the PCIe link is greater than a second negotiation count threshold.

[0221] Specifically, if the link rate is not equal to the link rate threshold, it is further determined whether the second negotiation times of the PCIe link is greater than the second negotiation times threshold. If the second negotiation times of the PCIe link is greater than the second negotiation times threshold, the process proceeds to step S1410; if the second negotiation times of the PCIe link is less than or equal to the second negotiation times threshold, the process proceeds to step S1405, wherein the second negotiation times threshold can be set according to actual needs, for example, the second negotiation times threshold is set to 3 times.

[0222] Step S1405: Determine whether the link rate of the last negotiation is equal to the link rate threshold, and whether the current second negotiation number is zero.

[0223] Specifically, after each negotiation, the negotiated link rate will be recorded. If the second negotiation number of the PCIe link is less than or equal to the second negotiation number threshold, it is further determined whether the link rate of the previous negotiation is equal to the link rate threshold, and whether the current second negotiation number is zero. If so, it goes to step S1406; if not, it goes to step S1407; it can be understood that this step is used to detect whether the correct rate has been negotiated before in this environment. If the correct rate has been negotiated, the signal parameters of the correct rate are determined as the signal parameters of this negotiation.

[0224] Step S1406: Set the current signal parameters as the signal parameters of the last negotiation, control the link training state machine to enter a sub-state, and increase the second negotiation times.

[0225] Specifically, if the link rate of the last negotiation is equal to the link rate threshold and the current second negotiation number is zero, the current signal parameters are set to the signal parameters of the last negotiation, and the link training state machine is controlled to enter the sub-state, and the second negotiation number is increased, that is, the disk side sets the signal parameters of this negotiation to the pre-cursor of the last negotiation.

[0226] Step S1407: Control the link training state machine to enter a sub-state, and increase the second negotiation times.

[0227] Specifically, the sub-states include the Recovery.Equalization state, which controls the PCIe link to enter the Recovery.Equalization state so that the PCIe link can be renegotiated, and the second negotiation number is increased by one. When the negotiation state of the PCIe link does not meet the expected state, the link training state machine is controlled to enter a predetermined sub-state. The present application can reduce the process of the PCIe link, thereby saving the negotiation time of the PCIe link and improving the stability of the PCIe link.

[0228] Step S1408: Save the current signal parameters.

[0229] Specifically, if the link rate is equal to the link rate threshold, it means that the negotiation is successful at this time, and the current signal parameters are saved, where the signal parameters include pre-cursor, main-cursor, and post-cursor.

[0230] In the embodiment of the present application, in signal processing and high-speed serial communication, pre-cursor, main-cursor and post-cursor are key parameters used in the equalization process, which are used to adjust the amplitude and shape of the signal to reduce inter-symbol interference (ISI) and improve transmission quality. Pre-cursor (pre-mark / leading) is also called Pre-shoot coefficient, which is used to adjust the signal amplitude before the transition edge of the current bit signal. By increasing the signal amplitude before the transition edge, the pre-cursor can compensate for the front tailing phenomenon of the signal, which helps to reduce ISI. In the equalization process, the absolute value of the pre-cursor coefficient (C-1) should be less than or equal to 1, and is usually a negative value, indicating an adjustment to the amplitude of the previous bit signal. Main-cursor (main mark) mainly affects the swing of the output signal, that is, the amplitude of the current bit signal. In the equalization process, the absolute value of the main-cursor coefficient (C0) should be less than or equal to 1, and is usually a positive value, indicating an adjustment to the amplitude of the current bit signal. By adjusting the main-cursor coefficient, the overall amplitude of the signal can be controlled to achieve the best transmission effect. Post-cursor is also called de-emphasis coefficient, which is used to adjust the signal amplitude after the transition edge of the current bit signal. By increasing the signal amplitude after the transition edge, post-cursor can compensate for the signal's tailing phenomenon, which helps reduce ISI. During the equalization process, the absolute value of the post-cursor coefficient (C+1) should be less than or equal to 1, and is usually a negative value, indicating an adjustment to the amplitude of the next bit signal.

[0231] Step S1409: Control the data link control and management state machine to enter the DL_Active state from the DL_Init state.

[0232] In an embodiment of the present application, to control the data link control and management state machine (DLCMSM) to enter the DL_Active state from the DL_Init state, it is necessary to ensure that the PCIe link has completed all necessary steps in the initialization process, including the initialization of the flow control mechanism, the physical connection and training of the link, etc.

[0233] Specifically, in the DL_Init state, the physical layer needs to report that the link is operational and that the physical connection and training of the link have been completed. It is understandable that if the physical layer reports that the link is not operational or no device is connected, the state machine will remain in the DL_Inactive state or cannot enter the DL_Active state, and the flow control mechanism of the default virtual channel (VC0) needs to be initialized. This usually includes two stages: FC_INIT1 and FC_INIT2. In the FC_INIT1 stage, the data link layer will submit DL_Down status information to the transaction layer; in the FC_INIT2 stage, the data link layer will submit DL_Up status information to the transaction layer, indicating that the flow control initialization is complete. Before entering the DL_Active state, it is necessary to confirm that the LinkUp status bit of the physical layer is 1, that is, to verify the Link Up state, which indicates that the other end of the PCIe link is connected to a PCIe device and the link is operational. When the flow control mechanism is initialized and the Link Up status bit of the physical layer is 1, the state machine will automatically enter the DL_Active state from the DL_Init state.

[0234] It should be noted that if any exceptions or errors are encountered during the initialization process (such as link training failure, flow control initialization failure, etc.), the state machine may remain in the DL_Init state or return to the DL_Inactive state. These exceptions and errors need to be handled to ensure that the link can be initialized correctly.

[0235] Step S1410: Turn on the data link layer link enable, and clear the second negotiation times to end the PCIe link training.

[0236] Specifically, when the link rate and other related parameters are negotiated successfully, the data link layer (DLL) can turn on the link enable, and clear the second negotiation number to zero, indicating that the DLL is now ready to receive and send transaction layer packets (TLPs) and data link layer packets (DLLPs) for normal PCIe communication. When the link rate is equal to the link width threshold and the data link layer link enable is turned on, it can be considered that the training phase of the PCIe link has ended, thus entering the normal PCIe communication mode.

[0237] In an embodiment of the present application, by determining whether the negotiation information of the PCIe link meets the expected conditions, if the expected conditions are met, the data link layer link enable is turned on. The present application can ensure the normal transmission of data and the stable operation of the link.

[0238] In an embodiment of the present application, the present application provides a training method for a PCIe link, the method comprising: turning off the data link layer link enable to enable the PCIe link to perform link self-negotiation; when the data link control and management state machine is in the DL_Init state, determining whether the negotiation information of the PCIe link meets the expected conditions; if so, turning on the data link layer link enable; if not, controlling the link training state machine to enter a sub-state to enable the PCIe link to renegotiate, wherein the sub-state includes a Disabled state or a Recovery state.

[0239] During the link training process, the negotiation state of the link is monitored in the DL_Init stage. When the negotiation state of the link does not meet the expected state, the PCIe link is controlled to enter the Disabled or Recovery.Equalization state to allow the PCIe link to renegotiate. When the negotiation state of the PCIe link does not meet the expected state, the link training state machine is controlled to enter a predetermined sub-state. Compared with the current related technology of real-time monitoring of the LTSSM state by software, since the jump of the LTSSM state is implemented by hardware, the jump speed of the LTSSM state is faster, which may cause the software to be unable to detect the abnormal point in time and handle it in time, which may still cause the speed to drop and the physical channel (lane) to drop. , which in turn affects the performance of the PCIe link. The present application can monitor the negotiation status of the link in the DL_Init stage, and when the negotiation status of the link does not meet the expected status, control the PCIe link to renegotiate, thereby not affecting the performance of the PCIe link; and, compared with the current related technology in which the software recognizes the abnormality and intervenes only after the link has entered the DL_Active state, the present application monitors the negotiation status of the link in the DL_Init stage, and when the negotiation status of the PCIe link does not meet the expected status, controls the link training state machine to enter a predetermined sub-state, and renegotiates to the expected state, thereby avoiding the risk of disk drop caused by one end of the link being forced to enter a predetermined sub-state in the DL_Active stage, thereby improving the stability of the PCIe link.

[0240] Please refer to Fig.15 , Fig.15 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application.

[0241] like Fig.15 As shown, the electronic device 150 includes one or more processors 151 and a memory 152. Fig.15 A processor 151 is taken as an example.

[0242] The processor 151 and the memory 152 may be connected via a bus or other means. Fig.15 The example of connecting through bus is taken in the following.

[0243] The processor 151 is used to provide computing and control capabilities to control the electronic device 150 to perform corresponding tasks, for example, to control the electronic device 150 to perform the PCIe link training method in any one of the above-mentioned method embodiments, the method comprising: turning off the data link layer link enable to enable the PCIe link to perform link self-negotiation; when the data link control and management state machine is in the DL_Init state, determining whether the negotiation information of the PCIe link meets the expected conditions; if so, turning on the data link layer link enable; if not, controlling the link training state machine to enter a sub-state to enable the PCIe link to renegotiate, wherein the sub-state includes a Disabled state or a Recovery state.

[0244] During the link training process, the negotiation state of the link is monitored in the DL_Init stage. When the negotiation state of the link does not meet the expected state, the PCIe link is controlled to enter the Disabled or Recovery.Equalization state to allow the PCIe link to renegotiate. When the negotiation state of the PCIe link does not meet the expected state, the link training state machine is controlled to enter a predetermined sub-state. Compared with the current related technology of real-time monitoring of the LTSSM state by software, since the jump of the LTSSM state is implemented by hardware, the jump speed of the LTSSM state is faster, which may cause the software to be unable to detect the abnormal point in time and handle it in time, which may still cause the speed to drop and the physical channel (lane) to drop. , which in turn affects the performance of the PCIe link. The present application can monitor the negotiation status of the link in the DL_Init stage, and when the negotiation status of the link does not meet the expected status, control the PCIe link to renegotiate, thereby not affecting the performance of the PCIe link; and, compared with the current related technology in which the software recognizes the abnormality and intervenes only after the link has entered the DL_Active state, the present application monitors the negotiation status of the link in the DL_Init stage, and when the negotiation status of the PCIe link does not meet the expected status, controls the link training state machine to enter a predetermined sub-state, and renegotiates to the expected state, thereby avoiding the risk of disk drop caused by one end of the link being forced to enter a predetermined sub-state in the DL_Active stage, thereby improving the stability of the PCIe link.

[0245] The processor 151 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a hardware chip or any combination thereof; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0246] The memory 152, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer executable programs and modules, such as the program instructions / modules corresponding to the PCIe link training method in the embodiment of the present application. The processor 151 can implement the PCIe link training method in any of the above method embodiments by running the non-transitory software programs, instructions and modules stored in the memory 152. Specifically, the memory 152 may include a volatile memory (VM), such as a random access memory (RAM); the memory 152 may also include a non-volatile memory (NVM), such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD) or other non-transitory solid-state storage device; the memory 152 may also include a combination of the above types of memories.

[0247] The memory 152 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 152 may optionally include a memory remotely arranged relative to the processor 151, and these remote memories may be connected to the processor 151 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0248] One or more modules are stored in the memory 152, and when executed by one or more processors 151, the training method of the PCIe link in any of the above method embodiments is executed, for example, the training method described above is executed. Figure 4 The steps shown.

[0249] In the embodiment of the present application, the electronic device 150 may also have components such as a wired or wireless network interface, a keyboard, and an input / output interface for input and output. The electronic device 150 may also include other components for realizing device functions, which will not be described in detail here.

[0250] The embodiment of the present application also provides a non-volatile computer-readable storage medium, such as a memory including a program code, and the program code can be executed by a processor to complete the PCIe link training method in the above embodiment. For example, the non-volatile computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CDROM), a magnetic tape, a floppy disk, and an optical data storage device.

[0251] The embodiment of the present application also provides a non-volatile computer-readable storage medium, such as a memory including a program code, and the program code can be executed by a processor to complete the PCIe link training method in the above embodiment. For example, the non-volatile computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CDROM), a magnetic tape, a floppy disk, and an optical data storage device.

[0252] The present application also provides a computer program product, which includes one or more program codes stored in a non-volatile computer-readable storage medium. The processor of the flash memory device reads the program code from the non-volatile computer-readable storage medium, and the processor executes the program code to complete the method steps of the PCIe link training method provided in the above embodiment.

[0253] A person skilled in the art will appreciate that all or part of the steps for implementing the above embodiments may be accomplished by hardware or by hardware associated with a program code, and the program may be stored in a non-volatile computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0254] Through the description of the above implementation methods, a person of ordinary skill in the art can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, can also be implemented by hardware. A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a non-volatile computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0255] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Under the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes in different aspects of the present application as mentioned above, which are not provided in detail for the sake of simplicity. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A PCIe link training method, characterized in that: The method comprises: Disable the data link layer link enable to allow the PCIe link to perform link auto-negotiation. When the data link control and management state machine is in the DL_Init state, determining whether the negotiation information of the PCIe link meets the expected conditions; If yes, enabling the data link layer link enable; If not, the link training state machine is controlled to enter a sub-state to allow the PCIe link to renegotiate, wherein the sub-state includes a Disabled state or a Recovery state.

2. The method according to claim 1, characterized in that: The negotiation information of the PCIe link includes a link width, and the expected condition includes a link width threshold; The determining whether the negotiation information of the PCIe link meets the expected condition includes: Determining whether the link width is equal to the link width threshold; If yes, determining that the negotiation information of the PCIe link meets the expected conditions; If not, determining that the negotiation information of the PCIe link does not meet the expected condition; The control link training state machine enters a sub-state, including: Control the link training state machine to enter the Disabled state.

3. The method according to claim 2, characterized in that When the negotiation information of the PCIe link does not meet the expected condition, the method further includes: Determine whether a first negotiation number of the PCIe link is greater than a first negotiation number threshold, wherein the first negotiation number is used to count the number of times the PCIe link performs link width negotiation; If yes, clearing the first negotiation times to zero and enabling the data link layer link enable to terminate the training of the PCIe link; If not, the first negotiation times are increased, and the link training state machine is controlled to enter a sub-state, so that the PCIe link re-negotiates the link width.

4. The method according to claim 3, characterized in that: When the negotiation information of the PCIe link meets the expected condition, the method further includes: The first negotiation times are cleared to zero, and the data link layer link enable is turned on to end the training of the PCIe link.

5. The method according to claim 1, characterized in that The negotiation information of the PCIe link includes a link rate, and the expected condition includes a link rate threshold; The determining whether the negotiation information of the PCIe link meets the expected condition includes: Determining whether the link rate is equal to the link rate threshold; If yes, determining that the negotiation information of the PCIe link meets the expected conditions; If not, it is determined that the negotiation information of the PCIe link does not meet the expected conditions.

6. The method according to claim 5, characterized in that When the negotiation information of the PCIe link does not meet the expected condition, the method further includes: Determine whether a second negotiation number of the PCIe link is greater than a second negotiation number threshold, wherein the second negotiation number is used to count the number of times the PCIe link performs link rate negotiation; If yes, enabling the data link layer link enable; If not, further determining whether the link rate of the last negotiation is equal to the link rate threshold, and whether the current second negotiation number is zero; If the link rate of the last negotiation is equal to the link rate threshold, and the current second negotiation number is zero, setting the current signal parameter to the signal parameter of the last negotiation, controlling the link training state machine to enter a sub-state, and increasing the second negotiation number; If the link rate of the last negotiation is not equal to the link rate threshold, or the current second negotiation number is not zero, the link training state machine is controlled to enter a sub-state, and the second negotiation number is increased.

7. The method according to claim 6, characterized in that The control link training state machine enters a sub-state, including: Controlling the link training state machine to enter the Recovery state specifically includes: Control the link training state machine to enter the Recovery.Equalization state; If the link rate is equal to the link rate threshold, the method further includes: Save the current signal parameters.

8. The method according to claim 7, characterized in that After saving the current signal parameters, the method further includes: The data link layer link enable is turned on, and the second negotiation times are cleared to end the training of the PCIe link.

9. The method according to any one of claims 1 to 8, characterized in that: The method is applied to a flash memory device, the flash memory device being connected to a host; After enabling the data link layer link enable, the method further includes: The data link control and management state machine is controlled to enter the DL_Active state from the DL_Init state, wherein in the DL_Active state, transaction layer messages can be transmitted between the flash memory device and the host.

10. An electronic device, characterized in that: include: A processor and a memory, wherein the processor is used to execute an executable program code in the memory, and when the executable program code is executed, the processor executes instructions of the PCIe link training method as described in any one of claims 1 to 9.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed, the PCIe link training method according to any one of claims 1 to 9 is implemented.

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