High-frame-rate data transmission system based on FPGA

Abstract

The invention provides a high-frame-rate data transmission system based on an FPGA (Field Programmable Gate Array), which belongs to the field of communication of digital circuits and comprises the FPGA, an analog-to-digital converter (ADC), a microcontroller, gigabit Ethernet MAC (Media Access Control) equipment and Ethernet physical layer (PHY) equipment. By adopting advanced technologies such as an FPGA (Field Programmable Gate Array) chip, an innovative algorithm, a high-speed Ethernet interface technology and a high-speed memory technology, high-speed and efficient data acquisition and transmission are realized, so that the frame rate of equipment is improved.

Description

Technical Field

[0001] The present invention relates to the communication field of digital circuits, and in particular to a high frame rate data transmission system based on FPGA. Background Art

[0002] With the rapid development of electronic technology and computer vision technology, the amount of communication data is increasing, and the demand for high frame rate data acquisition and transmission is growing. However, due to the limitations of data acquisition and processing capabilities, traditional equipment is difficult to meet the requirements of high frame rates. In recent years, with the rapid development of FPGA technology, its application in high-performance computing and real-time data processing has become increasingly widespread. FPGA has a high degree of parallel processing capabilities and flexible programmability, which is very suitable for data acquisition and processing of high frame rate equipment.

[0003] In high frame rate devices, multi-line acquisition is one of the key technologies to achieve high frame rate. By acquiring data from multiple scan lines at the same time, the frame rate can be significantly improved. However, multi-line acquisition brings about the problem of processing and transmitting a large amount of data. Traditional data processing methods often use serial processing, which leads to slow processing speed and cannot meet the requirements of high frame rate. In addition, the transmission of large amounts of data also requires efficient data interfaces to support it. Ethernet, as a high-speed and reliable data transmission protocol, is widely used in data transmission. However, when transmitting large amounts of data through Ethernet, problems such as data encapsulation and protocol conversion need to be solved. Especially in the case of high frame rates, these problems become more complicated.

[0004] Therefore, considering the above factors, it is necessary to propose a new solution to overcome the shortcomings of the prior art. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a high frame rate data transmission system based on FPGA, which can realize the efficient acquisition, processing and transmission of high frame rate data, improve the frame rate and data processing efficiency of the system, while reducing costs and improving the flexibility and scalability of the system, which has obvious advantages over traditional methods.

[0006] The technical solution of the present invention is:

[0007] A high frame rate data transmission solution based on FPGA, the system mainly includes FPGA, analog-to-digital converter (ADC), microcontroller, Gigabit Ethernet MAC device and Ethernet physical layer (PHY) device. As the core processing unit, FPGA undertakes key tasks such as multi-line data acquisition, processing, temporary storage and Ethernet frame construction. The microcontroller is responsible for communicating with FPGA to realize FPGA control and parameter configuration, and coordinates the interaction between the system and external devices. ADC is responsible for converting the received ultrasonic analog signal into a digital signal to provide a data source for subsequent processing. Gigabit Ethernet MAC device is responsible for the generation and transmission control of Ethernet frames to ensure that data can be accurately and efficiently transmitted in the network. Ethernet PHY device realizes signal conversion and transmission at the physical layer, and sends data to external devices such as computers or servers through the Ethernet interface.

[0008] Multiple functional modules are integrated inside the FPGA, including data receiving module, signal processing module, storage module, clock generation module, data packet generation module and interface control module. The data receiving module is responsible for receiving digital signals from the ADC, and realizes multi-channel parallel acquisition through multiple receivers (each receiver has eight channels) to ensure efficient data acquisition. The signal processing module performs a series of processing on the collected data, such as envelope detection and other operations, to extract useful ultrasonic information. The storage module uses a dual-block random access memory (RAM) to alternately store frame data to ensure continuous storage and reading of data. The clock generation module provides an accurate clock signal for the entire system to ensure the synchronous operation of each module. The data packet generation module encapsulates the processed data into Ethernet frames according to a specific protocol for transmission over the network. The interface control module is responsible for managing the communication interface between the FPGA and the microcontroller, Ethernet MAC device, etc., to realize data interaction and control signal transmission.

[0009] Further, data collection and processing

[0010] The present invention adopts a multi-line acquisition module to receive multi-line signals from the data source and convert them into digital signals for acquisition. In order to achieve high frame rate acquisition, the present invention adopts parallel acquisition technology, that is, data of multiple signal lines are collected simultaneously. The multi-line acquisition module converts analog signals into digital signals through ADC (analog-to-digital converter). In order to improve the acquisition accuracy and speed, the present invention selects high-performance ADC chips and adopts differential signal transmission technology to reduce noise interference. In addition, the multi-line acquisition module also designs reasonable signal amplification, filtering and conditioning circuits to ensure the quality of the collected digital signals. In order to ensure the accuracy and integrity of the data, the data receiving module performs data verification and error detection when receiving data. By adding a check bit or using a cyclic redundancy check (CRC) and other methods, the received data is verified. Once an error is found, error correction or retransmission is requested in time to ensure the reliability of the data.

[0011] In order to further reduce the amount of data and improve the data transmission speed and processing efficiency, the present invention implements a variety of innovative algorithms in the FPGA chip, including a moving window algorithm, a key window capture algorithm, and an envelope detection algorithm. These algorithms can effectively reduce the amount of data, thereby reducing the load of data transmission and improving the overall performance of the system.

[0012] The envelope detection algorithm is an algorithm for extracting the envelope of a signal. It can be applied when the high frame rate data is a signal in the fields of communication, audio processing, biomedical signal processing, etc. The algorithm determines the envelope of the signal by comparing continuous byte data. Specifically, the algorithm can compare 1, 2, 4 or 8 consecutive bytes according to user needs or system configuration, and select the maximum value as the envelope value. This flexibly programmable comparison byte number setting enables the system to select the most appropriate envelope detection method according to different application scenarios and data characteristics to improve the accuracy and efficiency of detection. For example, when detecting weak signals, a larger number of comparison bytes can be selected to enhance the detection capability of the signal; and when processing rapidly changing ultrasonic signals, a smaller number of comparison bytes can be selected to increase the processing speed. The present invention implements the envelope detection algorithm in the FPGA chip, extracts the envelope information of the signal by real-time processing of the collected high frame rate data, thereby improving the accuracy of the data.

[0013] In addition to the above-mentioned envelope detection algorithm, an innovative moving window algorithm (MWA) is also used. The moving window algorithm is a data processing technology based on sliding windows. It slides a fixed-size window on the data stream and only processes the data within the window, thereby avoiding the huge amount of calculation required to process the entire data set. MWA divides a frame of data into 23 windows. When transmitting data, for the first 256 frames, only the data of window 1 is sent, and the data of other windows are discarded; in the next 256 frames, the data of window 2 is sent, and so on. In this way, the data rate can be reduced by 23 times, effectively reducing the amount of data transmission, while still maintaining the required high frame rate in each window. In the FPGA system of the present invention, the moving window algorithm is used to process the collected high-frame rate data in real time, retaining only key information and reducing the amount of data. In addition, the system also supports a key window capture function. The key window capture algorithm is an algorithm based on user settings, which is used to capture data in a specific area of ​​concern to the user. The user can select to focus on specific windows through the microcontroller to further reduce the amount of data. While reducing the number of windows, the microcontroller can also adjust the average number of bits of envelope detection to improve the pertinence and accuracy of the data, thereby more accurately detecting and analyzing the target area.

[0014] Further, data interface and storage

[0015] In addition, the present invention also adopts high-speed Ethernet interface technology, including a Gigabit Ethernet controller and a physical layer interface (PHY). The Gigabit Ethernet controller is used to achieve high-speed data transmission, and the physical layer interface is used to transmit data to the Ethernet physical medium. By adopting these high-speed interface technologies, the present invention can ensure that a large amount of high frame rate data can be efficiently transmitted to external devices.

[0016] In the interface design between the microcontroller and the FPGA chip, the present invention adopts the SPI (Serial Peripheral Interface) bus technology. The SPI bus has the characteristics of high speed, simplicity and low power consumption, and is very suitable for data transmission between the microcontroller and the FPGA chip. Through the SPI bus, the microcontroller can configure the working mode of the FPGA chip and control the sampling process of the ADC. At the same time, the FPGA chip can also feedback the working status and data transmission status to the microcontroller through the SPI bus.

[0017] In terms of memory design, the present invention adopts high-speed memory technology, and the storage module uses dual-block RAM in the FPGA to store frame data. When one RAM is being written with data (new data from the ADC), the data packet formation logic can read and process the data from another RAM, realizing the alternating storage and reading of data and improving the working efficiency of the system. The design of the dual-block RAM avoids data read and write conflicts and ensures the continuity and stability of the data. In order to facilitate data management and access, the storage module adopts a reasonable address mapping and indexing mechanism. Each storage unit has a unique address, and the required data can be quickly located and accessed through the address bus. At the same time, the storage module is also equipped with corresponding control logic for managing data writing, reading, erasing and other operations to ensure the correct storage and use of data.

[0018] In summary, the present invention realizes high-speed and efficient data acquisition and transmission by adopting advanced technologies such as FPGA chips, innovative algorithms, high-speed Ethernet interface technology and high-speed memory technology, thereby improving the frame rate of the device. The system of the present invention has the advantages of simple structure, superior performance, easy expansion and maintenance, and can be widely used in medical diagnosis, biological research, industrial detection and other fields.

[0019] The beneficial effects of the present invention are

[0020] 1. High efficiency and high quality

[0021] The system of the present invention can achieve ultra-high frame rate transmission, and through the innovative moving window algorithm and efficient data processing flow, while ensuring the high frame rate, the quality of transmission is effectively improved. Data acquisition, processing, storage and transmission work efficiently and collaboratively inside the FPGA, reducing the delay and bottleneck of data processing. At the same time, through the innovative data packet generation algorithm and high-speed Ethernet interface, rapid data transmission is achieved, improving the overall efficiency of the system. In the data transmission process, the UDP protocol and moving window algorithm are adopted to effectively reduce the data transmission volume, reduce the occupation of network bandwidth, and ensure the real-time and accuracy of the data.

[0022] 2. Flexibility and scalability

[0023] The programmable nature of FPGA makes the system highly flexible. The system parameters (such as frequency, frame rate, window selection, resolution, etc.) can be programmed and configured through the microcontroller, which is convenient for adjustment according to different application requirements. In addition, the system architecture is easy to expand, and new functional modules can be easily added or existing modules can be upgraded to adapt to future technological developments and application changes, extending the service life of the system.

[0024] 3. Significant cost-effectiveness

[0025] The use of general-purpose FPGA chips and low-cost microcontrollers greatly reduces the hardware cost of the system compared to traditional dedicated hardware design. At the same time, due to the programmability of FPGA, the system can be upgraded and optimized without replacing the hardware, reducing the cost of hardware updates. In addition, the modular design of the system allows each module to be independently developed and tested, making it easy to integrate into different devices, improving the versatility and portability of the system and further reducing development and production costs. In large-scale production and application, it can bring significant economic benefits to enterprises. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a working structure diagram of the present invention;

[0027] Figure 2 This is the SPI interface connection diagram;

[0028] Figure 3 This is a schematic diagram of MAC interface connection;

[0029] Figure 4 This is a schematic diagram of the FPGA data path. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0031] The present invention proposes a high frame rate data transmission system based on FPGA. The present invention can realize the efficient acquisition, processing and transmission of high frame rate data, improve the frame rate and data processing efficiency of the system, reduce costs, and improve the flexibility and scalability of the system, which has obvious advantages over traditional methods.

[0032] Figure 1The hardware architecture block diagram of the receiving end of the FPGA design scheme of the present invention is shown. As can be seen from the figure, the receiving end part includes components such as a microcontroller, FPGA, ADC, Gigabit Ethernet MAC chip and PHY chip. There are multiple receivers, each of which integrates a low noise amplifier (LNA), a time gain compensation (TGC), an anti-aliasing filter (AAF) and an analog-to-digital converter (ADC), which is responsible for converting the ultrasonic analog signal into a digital signal and transmitting it to the FPGA. The microcontroller communicates with the FPGA through the SPI interface and transmits control instructions to realize data interaction and control signal transmission; it is connected to the Gigabit Ethernet MAC device through the data bus, and the processed ultrasonic data is encapsulated into an Ethernet frame and sent to the MAC device; at the same time, it is connected to the ADC of each receiver to receive ultrasonic digital data. The FPGA is responsible for multi-line acquisition, data storage and processing, and Ethernet interface functions; the ADC is used to convert analog ultrasonic signals into digital signals for acquisition; the Gigabit Ethernet MAC device is connected to the Ethernet PHY device through the RGMII interface, and the Ethernet PHY device is then connected to the Ethernet interface to realize Ethernet transmission of data.

[0033] Therefore, according to the system architecture design, the selected hardware components such as FPGA, microcontroller, analog-to-digital converter, Gigabit Ethernet MAC device and Ethernet PHY device are assembled. Ensure that the FPGA and microcontroller are properly connected through the SPI interface, and set the master-slave mode, data transmission lines (MOSI, MISO), clock lines and chip select lines. Figure 2 The SPI interface circuit diagram between the microcontroller and FPGA is shown. As can be seen from the figure, the SPI interface includes a clock signal (SCK), a data input signal (MISO), a data output signal (MOSI), and a chip select signal (CS). The microcontroller acts as the master (MASTER) of the SPI bus, and the FPGA acts as the slave (SLAVE). The microcontroller programs the FPGA and reads and writes data through the SPI bus, and configures the FPGA's working mode and parameters. The microcontroller sends control instructions and data to the FPGA through the SPI interface; the FPGA receives control instructions and data through the SPI interface and performs corresponding operations according to the instructions.

[0034] Connect the FPGA's SPI interface related pins to the corresponding SPI pins of the microcontroller to ensure stable electrical connection for data transmission. Connect the FPGA to the ADC through a high-speed data interface to ensure the stability and accuracy of data transmission. Connect the FPGA to the Gigabit Ethernet MAC device to ensure the correct connection of the data bus, address bus, and control signals. According to the interface specification, connect the FPGA's data bus pins to the data input and output pins of the MAC device, and connect the address bus pins accordingly. At the same time, connect the control signal pins, such as reset, interrupt, clock enable, and other signal pins. Figure 3 The interface connection and data transmission method between FPGA and Gigabit Ethernet MAC device are demonstrated. This interface is the key part of data communication and is responsible for efficiently transmitting the data processed by FPGA to the Ethernet device. It includes address bus (Address Bus 16Bit), data bus (Data Bus 32Bit), reset (Reset), interrupt (Interrupt), clock (Clock) and enable (Enable) signals to realize the transmission of data, control and status signals between FPGA and Ethernet MAC device. FPGA sends the processed ultrasound data to Ethernet MAC device through the data bus and specifies the data storage location through the address bus. Ethernet MAC device generates and controls the transmission of Ethernet frames according to the received data and control signals.

[0035] Connect the Ethernet MAC device to the Ethernet PHY device through the RGMII interface, and connect the Ethernet PHY device to the Ethernet interface. Use a network cable or flat cable that complies with the RGMII interface standard to connect the MAC device and the PHY device, and connect the Ethernet interface of the PHY device to an external network device (such as a switch, router, or computer network interface) to ensure that the physical link of the network connection is unobstructed. Install an external 24MHz crystal oscillator as the system clock source and ensure that it is correctly connected to the clock input pin of the FPGA. The output pin of the crystal oscillator is connected to the clock input pin of the FPGA through appropriate wiring, and necessary clock buffers and filters are added to the circuit to ensure the stability and purity of the clock signal.

[0036] After the system is powered on, each module is initialized and configured, and then it can start to operate. After the ultrasonic signal is received by the ultrasonic probe, it is converted by the ADC. After the ADC amplifies and filters the received ultrasonic analog signal, it performs analog-to-digital conversion with 12-bit accuracy to convert the analog signal into a digital signal. The converted digital signal is transmitted to the data receiving module of the FPGA through the high-speed data interface according to the predetermined timing and format. The data receiving module uses its parallel processing capability to receive data from 32 channels at the same time. When receiving data, the data receiving module samples and aligns the data according to the clock signal and synchronization signal. In order to ensure the accuracy and integrity of the data, the data receiving module performs data check and error detection when receiving data. The cyclic redundancy check (CRC) algorithm is used to calculate the checksum of each batch of received data and compare it with the checksum provided by the sending end. If the checksum is found to be inconsistent, it is determined that an error occurred during the data transmission process, and the data receiving module will send a retransmission request to the ADC to ensure the accuracy of the data.

[0037] After receiving the parallel data, the signal processing module performs envelope detection. According to the system configuration, the appropriate number of comparison bytes (such as 4 bytes) is selected for envelope detection. The signal processing module compares the continuous 4 bytes of data and selects the maximum value as the envelope value of this part of the data. In this way, the envelope characteristics of the ultrasonic signal are effectively extracted and the amount of data is reduced.

[0038] Next, the moving window algorithm (MWA) is used to further compress the data. One frame of ultrasound data is divided into 23 windows. During the initial 256-frame data acquisition process, only the data in window 1 is selected for processing and transmission, and the data in other windows is discarded. In the subsequent 256 frames, the data in window 2 is selected for processing, and so on. In this way, the data rate is reduced by 23 times, greatly reducing the pressure on data transmission and storage. At the same time, during the processing process, the microcontroller can adjust the average number of bits of envelope detection as needed to improve the resolution of the image.

[0039] In order to improve data processing efficiency, the signal processing module adopts pipeline processing technology. Envelope detection, data compression and other operations are divided into multiple stages and executed in parallel in different clock cycles to reduce data processing delays. This can make full use of the parallel processing capabilities of FPGA and improve the overall performance of the system. In addition, the signal processing module can also perform adaptive filtering according to the frequency characteristics of the ultrasonic signal. By real-time analysis of the spectrum of the ultrasonic signal, the parameters of the filter are adjusted, noise interference is removed, and the quality of the signal is improved.

[0040] The processed signal data is stored in the dual RAM of the FPGA under the control of the control signal. The control signal of the storage module is generated by the internal control signal generator module, which generates write address and read address signals according to the system clock signal and operation status to control the writing and reading operations of the data. When one RAM is being written with data (using new data from the ADC), the data packet formation logic will read the data from another RAM for subsequent processing to achieve alternating storage and reading of data. At the same time, the storage module is also equipped with corresponding cache and pre-fetch mechanisms to improve the reading and writing speed of data.

[0041] After the data is processed and stored in the FPGA, the data packet generation module encapsulates it into an Ethernet frame. The User Datagram Protocol (UDP) is used to ensure the compatibility and standardization of the data. During the encapsulation process, the data is added to the Ethernet frame according to the predetermined timing according to the clock signal provided by the clock generation module. During the generation of the Ethernet frame, the innovative moving window algorithm (MWA) is used to organize the data. According to the rules of the MWA, the data of different windows are encapsulated into the Ethernet frame in a predetermined order, and the necessary frame synchronization, CRC bytes and other information are added to ensure the integrity and accuracy of the Ethernet frame. The encapsulated Ethernet frame is sent to the MAC device through the interface between the FPGA and the Gigabit Ethernet MAC device. After receiving the Ethernet frame, the MAC device adds the Ethernet frame header, checksum and other information according to the RGMII interface specification, and converts the data into a format suitable for transmission on the physical medium, and then sends it to the external device (such as a computer or server) through the Ethernet PHY device. In this process, ensure that the RGMII interface communication between the MAC device and the PHY device is normal and the data transmission is stable.

[0042] Figure 4The schematic diagram of the FPGA data path module is shown, and the process of data processing and storage inside the FPGA and the connection of related modules are explained. The ultrasonic digital signal from the ADC (through four 8-channel receivers) is first sent to the data receiving module (SR, Serial to Parallel), which converts the serial data into byte parallel data for subsequent processing. The parallel data then enters the signal processing module to perform operations such as envelope detection to extract the characteristic information of the ultrasonic signal. Under the action of the control signal, the processed data is stored in the dual-block RAM (Storage Block RAM-1 and Storage Block RAM-2) to achieve temporary storage of data. The data stored in the RAM is read by the packet formation logic (Packet formation Logic), encapsulated into Ethernet frames according to the set protocol (such as UDP), and then sent to the Ethernet MAC device through the interface control module, and finally transmitted to the external device through the Ethernet interface. The entire process is provided by the clock generation module (Clock Generator) Various clock signals control data sampling, processing, storage and transmission operations. The control signal generator (ControlSignals Generator) generates various control signals, such as the write address, read address, enable signal of the RAM, the enable and reset signals of the envelope detector, etc., to ensure the coordinated work of each module.

[0043] The present invention realizes real-time acquisition and processing of high frame rate data by adopting parallel acquisition technology and reasonable signal processing algorithm; realizes high-speed data transmission by adopting Gigabit Ethernet interface and reasonable data encapsulation protocol; reduces the hardware cost and maintenance cost of the equipment by adopting FPGA technology for design and implementation; and has good scalability. By adding or modifying modules and algorithms inside FPGA, new functions and performance improvements can be easily realized, showing good performance and application prospects.

[0044] The above description is only a preferred embodiment of the present invention, which is only used to illustrate the technical solution of the present invention, and is not used to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A high frame rate data transmission system based on FPGA, characterized in that: include FPGA, as the core processing unit, is responsible for the multi-line acquisition, processing, temporary storage and Ethernet frame construction of data; The microcontroller is responsible for communicating with the FPGA to control and configure the parameters of the FPGA, and coordinate the interaction between the system and external devices; Analog-to-digital converter ADC is responsible for converting the received ultrasonic analog signal into a digital signal, providing a data source for subsequent processing; Gigabit Ethernet MAC device, responsible for the generation and transmission control of Ethernet frames; Ethernet PHY devices implement signal conversion and transmission at the physical layer and send data to external devices through the Ethernet interface.

2. The system according to claim 1, characterized in that Several functional modules are integrated inside the FPGA, including: The data receiving module is responsible for receiving the digital signal from the ADC and realizing multi-channel parallel acquisition through several receivers, each of which has eight channels; The signal processing module processes the collected data to extract useful ultrasonic information; The storage module uses dual random access memory RAM to alternately store frame data to ensure continuous storage and reading of data; The clock generation module provides clock signals for the entire system to ensure the synchronous operation of each module; The data packet generation module encapsulates the processed data into Ethernet frames according to a specific protocol for transmission over the network; The interface control module is responsible for managing the communication interface between the FPGA and the microcontroller and Ethernet MAC device to achieve data interaction and control signal transmission.

3. The system according to claim 1, characterized in that The parallel acquisition technology is adopted, that is, the data of several signal lines are collected at the same time; the analog signal is converted into a digital signal through the analog-to-digital converter ADC.

4. The system according to claim 3, characterized in that Select ADC chip and adopt differential signal transmission technology to reduce noise interference.

5. The system according to claim 4, characterized in that Signal amplification, filtering and conditioning circuits are also designed to ensure the quality of the collected digital signals.

6. The system according to claim 1, characterized in that: Data verification and error detection are performed when receiving data; the received data is verified by adding check bits or using cyclic redundancy check (CRC). Once an error is found, error correction is performed in a timely manner or a retransmission request is requested.

7. The system according to claim 1, characterized in that Several innovative algorithms are implemented in the FPGA chip, including a moving window algorithm, a key window capture algorithm, and an envelope detection algorithm.

8. The system according to claim 1, characterized in that Through the SPI bus, the microcontroller can configure the working mode of the FPGA chip and control the sampling process of the analog-to-digital converter ADC; at the same time, the FPGA chip can also feedback the working status and data transmission status to the microcontroller through the SPI bus.

9. The system according to claim 1, characterized in that Dual RAMs are used in the FPGA to store frame data; while data is being written to one RAM, the data packet forming logic can read and process data from the other RAM, thus achieving alternate storage and reading of data.

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