Data transmission method, device and equipment based on FPGA (Field Programmable Gate Array) and medium

Abstract

The invention discloses a data transmission method and device based on an FPGA, equipment and a medium, and relates to the technical field of digital circuit communication, and the method comprises the steps: obtaining initial image video data, and carrying out the data processing of the initial image video data based on a data type corresponding to the initial image video data, so as to obtain target image video data; caching the target image video data by using an FIFO (First In First Out) queue with a ping-pong cache structure to obtain cached data, and encapsulating the cached data into an Ethernet data packet meeting a user datagram protocol; and sending the Ethernet data packet to a target host, so that the target host receives the Ethernet data packet and analyzes the Ethernet data packet to obtain and display target image video data in real time. The target image video data is cached by using the FIFO queue with the ping-pong cache structure, so that the data transmission time is shortened.

Description

Technical Field

[0001] The present invention relates to the field of digital circuit communication technology, and in particular to a data transmission method, device, equipment and medium based on FPGA. Background Art

[0002] With the rapid development of electronic technology and computer vision technology, the amount of communication data is increasing, and the requirements for fast image and video acquisition are increasing. The transmission system of image and video data has requirements such as high bandwidth, high real-time performance, low latency, high reliability and stability.

[0003] In the current image and video data transmission method, due to the multi-level processing and network congestion in the data transmission process, the image and video data transmission process will have a high transmission delay. In summary, how to improve the speed of data transmission is a technical problem that needs to be solved at present. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a data transmission method, device, equipment and medium based on FPGA, which can use a FIFO queue with a ping-pong cache structure to cache target image video data, and use FPGA for data transmission, thereby shortening the data transmission time. The specific scheme is as follows:

[0005] In a first aspect, the present application provides a data transmission method based on FPGA, which is applied to an FPGA chip, comprising:

[0006] Acquire initial image video data collected by a preset image sensor from a target data source, and perform data processing on the initial image video data based on a data type corresponding to the initial image video data to acquire corresponding target image video data;

[0007] Utilizing each preset FIFO queue with a ping-pong cache structure to cache the target image video data to obtain cache data corresponding to the target image video data, and encapsulating the cache data into an Ethernet data packet that meets the user datagram protocol;

[0008] The Ethernet data packet corresponding to the target image video data is sent to a target host so that the target host receives the Ethernet data packet and parses the Ethernet data packet to obtain and display the target image video data in real time.

[0009] Optionally, the performing data processing on the initial image and video data based on the data type corresponding to the initial image and video data includes:

[0010] The data type corresponding to each of the initial image video data is identified. If there is target data of the infrared image data type in the initial image video data, grayscale stretching processing is performed on the target data to obtain corresponding stretched data.

[0011] Optionally, performing grayscale stretching processing on the target data to obtain corresponding stretched data includes:

[0012] Setting an initial grayscale threshold corresponding to the target data, and performing grayscale stretching processing on the target data based on the initial grayscale threshold to obtain corresponding initial stretched data;

[0013] Sending the initial stretching data to the target host, so that the target host generates a target grayscale threshold corresponding to the target data based on the initial stretching data, and sending the target grayscale threshold to the FPGA chip;

[0014] The target grayscale threshold is received, and grayscale stretching is performed on the target data based on the target grayscale threshold to obtain the stretched data.

[0015] Optionally, sending the Ethernet data packet corresponding to the target image video data to a target host includes:

[0016] A communication connection is established with the target host using a Gigabit Ethernet interface, the Ethernet data packet corresponding to the target image video data is sent to the Gigabit Ethernet interface, and the Ethernet data packet is sent to the target host using the Gigabit Ethernet interface.

[0017] In a second aspect, the present application provides a data transmission method based on FPGA, which is applied to a target host, including:

[0018] Receive an Ethernet data packet corresponding to target image video data sent by the FPGA chip; wherein the target image video data is data type corresponding to initial image video data collected by the FPGA chip from a target data source based on a preset image sensor, and is data obtained after data processing of the initial image video data; the Ethernet data packet is an Ethernet data packet that satisfies the user datagram protocol obtained after the FPGA chip encapsulates the cache data corresponding to the target image video data; the cache data is data obtained after the FPGA chip caches the target image video data using various preset FIFO queues with a ping-pong cache structure;

[0019] The Ethernet data packet is parsed to obtain the target image video data in the Ethernet data packet, and the target image video data is displayed in real time.

[0020] Optionally, the parsing operation on the Ethernet data packet to obtain the target image video data in the Ethernet data packet includes:

[0021] An integrity check is performed on the Ethernet data packet to obtain a corresponding verified data packet, and data extraction is performed on the verified data packet to obtain the target image video data in the verified data packet.

[0022] Optionally, the real-time display of the target image video data includes:

[0023] The image resolution and image format of the local image display device are obtained, the target display parameters corresponding to the target image video data are set according to a preset display parameter setting function, the image resolution and the image format, and the target image video data is displayed in real time based on the target display parameters.

[0024] In a third aspect, the present application provides an FPGA-based data transmission device, which is applied to an FPGA chip, including:

[0025] A data acquisition module, used to acquire initial image video data collected by a preset image sensor from a target data source, and perform data processing on the initial image video data based on a data type corresponding to the initial image video data to acquire corresponding target image video data;

[0026] A data cache module, used to cache the target image video data using each preset FIFO queue with a ping-pong cache structure to obtain cache data corresponding to the target image video data, and encapsulate the cache data into an Ethernet data packet that meets the user datagram protocol;

[0027] The data sending module is used to send the Ethernet data packet corresponding to the target image video data to the target host, so that the target host receives the Ethernet data packet and parses the Ethernet data packet to obtain and display the target image video data in real time.

[0028] In a fourth aspect, the present application provides an electronic device, including:

[0029] Memory, used to store computer programs;

[0030] A processor is used to execute the computer program to implement the aforementioned FPGA-based data transmission method.

[0031] In a fifth aspect, the present application provides a computer-readable storage medium for storing a computer program, which, when executed by a processor, implements the aforementioned FPGA-based data transmission method.

[0032] The present application first obtains the initial image video data collected by the preset image sensor from the target data source, and processes the initial image video data based on the data type corresponding to the initial image video data to obtain the corresponding target image video data, and then uses each preset FIFO queue with a ping-pong cache structure to cache the target image video data to obtain the cache data corresponding to the target image video data, and encapsulates the cache data into an Ethernet data packet that satisfies the user datagram protocol, and finally sends the Ethernet data packet corresponding to the target image video data to the target host, so that the target host receives the Ethernet data packet, and parses the Ethernet data packet to obtain and display the target image video data in real time. It can be seen that the present application caches the image video data by using the FIFO queue with a ping-pong cache structure. When one FIFO queue is being read, another FIFO queue can receive new data at the same time, avoiding the problem of waiting due to the queue being used, shortening the data transmission time and realizing the rapid transmission of data; by encapsulating the image video data into an Ethernet data packet that satisfies the user datagram protocol, the user data packet protocol can be used for data transmission, thereby improving the data transmission rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0034] Figure 1 A flow chart of a data transmission method based on FPGA disclosed in this application;

[0035] Figure 2 A flowchart of a specific FPGA-based data transmission method disclosed in this application;

[0036] Figure 3 A schematic diagram of a UDP data conversion and sending process disclosed in this application;

[0037] Figure 4 A schematic diagram of a process of image stretching method disclosed in this application;

[0038] Figure 5 A flow chart of a data transmission method based on FPGA disclosed in this application;

[0039] Figure 6This is a schematic diagram of the structure of a data transmission device based on FPGA disclosed in this application;

[0040] Figure 7 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] In the current image and video data transmission method, due to the multi-level processing and network congestion in the data transmission process, the transmission process of the image and video data will have a high transmission delay. To this end, the present application provides a data transmission method based on FPGA, which caches the target image and video data by using a FIFO queue with a ping-pong cache structure, and uses FPGA to package the data into Ethernet data packets for transmission, thereby shortening the data transmission time.

[0043] See also Figure 1 As shown, an embodiment of the present invention discloses a data transmission method based on FPGA, which is applied to FPGA chip, including:

[0044] Step S11: acquiring initial image video data collected by a preset image sensor from a target data source, and performing data processing on the initial image video data based on a data type corresponding to the initial image video data to acquire corresponding target image video data.

[0045] In this embodiment, the overall transmission process of image and video data is as follows: Figure 2As shown, it generally includes: using an image sensor to collect image and video data, and transmitting it to an FPGA (Field Programmable Gate Array) processing unit through an interface; FPGA processes the received image and video data, such as format conversion, compression, etc., and then caches the processed data in a FIFO (First In First Out) queue; FPGA encapsulates the cached data in the queue into Ethernet data packets, and sends them to a host or target device through a Gigabit Ethernet interface, and finally the host or target device receives the Ethernet data packets, and parses and displays them; It should be noted that in this embodiment, a high-performance image sensor, such as a CMOS (Complementary Metal-Oxide-Semiconductor) or CCD (Charge-coupled Device) sensor, is used to collect image and video data. The sensor is connected to the FPGA through high-speed interfaces such as Camera Link and LVDS (Low Voltage Differential Signaling, a data transmission interface) to achieve fast data transmission. The above process of processing the initial image and video data based on the data type corresponding to the initial image and video data may specifically include: identifying the data type corresponding to each initial image and video data, and if there is target data of the data type of infrared image in the initial image and video data, grayscale stretching is performed on the target data to obtain the corresponding stretched data. It is understandable that the data type of the initial image and video data received by the FPGA may be of various types, such as infrared images, ultrasonic images, etc. After receiving the image and video data, the FPGA will first pre-process the image and video data according to the data type, such as format conversion, grayscale stretching, etc. There are different data processing methods for image and video data of different data types; then, the processed data is cached in the FIFO queue for subsequent data encapsulation and transmission.

[0046] It can be seen that the FPGA-based data transmission method in this embodiment can be applied to different scenarios; in a specific implementation, the data transmission method of the present application can be applied to the field of medical ultrasound imaging technology. At this time, the ultrasound imaging system corresponding to the data transmission method in this embodiment is composed of a data acquisition module, an FPGA processing unit, a Gigabit Ethernet interface and a host, wherein the data acquisition module is responsible for collecting ultrasound image data; the FPGA processing unit is responsible for data processing and caching, the Gigabit Ethernet interface is responsible for data transmission, and the host is responsible for data reception and display; the data acquisition module includes an ultrasound sensor, an analog front end AFE (Analog Front End, i.e., a multi-circuit system) and an interface circuit, wherein the ultrasound sensor is used to collect ultrasound image data, the analog front end is used to amplify and convert raw data, and the interface circuit is used to transmit digital signals to the FPGA processing unit; the FPGA processing unit includes a data processing module and a FIFO buffer module, etc. The data processing module is responsible for preprocessing and format conversion of the received digital signal; the FIFO buffer module is used to buffer the processed data for subsequent data packaging and transmission. In this system, the FPGA can use the XC7K160T model of Xilinx, which has powerful parallel processing capabilities and rich interface resources, and can meet the needs of high-speed data processing and transmission. In addition, the data encapsulation and transmission module includes a UDP (User Datagram Protocol) data packet generator, a Gigabit Ethernet MAC (Media Access Control) controller, and an SGMII (Serial Gigabit Media Independent Interface, a data transmission interface) interface. The UDP data packet generator is responsible for encapsulating the cached data into UDP data packets. The conversion jump process of the UDP sending module is as follows: Figure 3 As shown in the figure, it contains 18 bytes of frame header data and 1280 bytes of valid data at the end of the frame; the Gigabit Ethernet MAC controller is responsible for controlling the transmission process of the data packet; the SGMII interface is used to connect to the Gigabit Ethernet physical layer to realize the physical transmission of data; and the host receiving and display module includes Ethernet interface card, data processing software and display device. The Ethernet interface card is used to receive the data packet transmitted from the FPGA; the data processing software is responsible for parsing and processing the data packet; the display device is used to present the parsed image data.

[0047] Among them, it can be seen from the UDP data conversion and sending jump diagram that the encapsulation format of the data packet includes a frame header and a frame tail, and the frame header includes the source MAC (Media Access Control, i.e., media access control bit address) address (6 bytes), the destination MAC address (6 bytes), the checksum (2 bytes), the data packet number (2 bytes) and the flag bit (2 bytes); the frame tail contains 1280 bytes of image data. It can be seen from the figure: in the IDLE idle state, when the FIFO is detected to be empty, it jumps from the IDLE idle state to the DST (Destination, i.e., destination address) state, otherwise, it returns to this state; in the DST (destination address) state, it starts counting from 0, and when the detection count reaches 5 (i.e., 6 bytes), the state jumps to the SRC (Source, i.e., source address) state, otherwise, it returns to this state; in the SRC state, it starts counting from 5, and when the detection count reaches 11 (i.e., 6 bytes), the state jumps to the PKT (Packet, i.e., data packet) state, otherwise, it returns to this state; in the PKT (data In the COOE (flag and check) state, it starts counting from 13. When the detection count reaches 17 (i.e., 4 bytes), the state jumps to the DATA state. Otherwise, it returns to this state. In the DATA (data) state, it starts counting from 17. When the detection count reaches 1297 (i.e., 1280 bytes), the state jumps to the DONE state. Otherwise, it returns to this state. In the DONE (done) state, it starts counting from 1297. Once the number is received, the count is cleared and it returns to the IDLE state.

[0048] In another specific embodiment, the data transmission method of the present application can be applied to the field of infrared imaging technology. In this case, the infrared image acquisition system corresponding to the data transmission method in this embodiment is composed of an infrared detector, an FPGA processing unit, a Gigabit Ethernet interface, and a host computer. The infrared detector is responsible for collecting infrared image data, the FPGA processing unit is responsible for data processing and caching, the Gigabit Ethernet interface is responsible for data transmission, and the host computer is responsible for data reception and display; wherein the data acquisition module includes parts such as an infrared detector and a Camera Link interface. The infrared detector is used to collect infrared image data, and the Camera Link interface is used to transmit the collected data to the FPGA processing unit; and the structure and function of the FPGA processing unit are similar to those of the FPGA processing unit in the previous specific embodiment, and also include parts such as a data processing module and a FIFO cache module. However, in this system, the FPGA also needs to perform special processing such as grayscale stretching on the infrared image data to improve the image display effect. The specific stretching process is as follows: Figure 4As shown, the corresponding operation is performed according to the threshold value to determine whether the stretching condition is met; and the structure and function of the data encapsulation and transmission module are also similar to the data encapsulation and transmission module in the previous specific implementation. However, in this system, the data packet follows the UDP protocol for transmission, and a custom encapsulation format is used to improve the efficiency and stability of data transmission; in addition, the structure and function of the host computer receiving and display module are similar to the host receiving and display module in the previous specific implementation; however, in this system, the host computer also needs to further process and display the received infrared image data, such as color mapping, contrast adjustment and other operations.

[0049] It should be noted that grayscale stretching (or histogram equalization) is a method to enhance image contrast, which stretches the distribution of pixel values ​​in the original image to a wider range. The infrared detector outputs image data with a depth of 16 bits, but since the subsequent processing is based on 8-bit image data, the 16-bit image needs to be linearly stretched and converted into an 8-bit image; accordingly, the above-mentioned process of grayscale stretching the target data to obtain the corresponding stretched data may specifically include: setting an initial grayscale threshold corresponding to the target data, and grayscale stretching the target data based on the initial grayscale threshold to obtain the corresponding initial stretched data; sending the initial stretched data to the target host so that the target host generates a target grayscale threshold corresponding to the target data based on the initial stretched data, and sending the target grayscale threshold to the FPGA chip; receiving the target grayscale threshold, and grayscale stretching the target data based on the target grayscale threshold to obtain the stretched data; specifically, Figure 4As shown in the image stretching process, a threshold is initially preset, and based on the preset, the image is initially stretched to obtain and send the stretched image to the computer. At this time, the host computer analyzes the 8-bit image after preliminary mapping, discarding the top and bottom 1% of the pixels to remove the influence of outliers. Then the new minimum grayscale value (hist_min_rx) and maximum grayscale value (hist_max_rx) are calculated. These values ​​correspond to the thresholds of the stretched 16-bit image, i.e., min*256 and max*256, and these thresholds are sent to the FPGA through the RS422 serial interface. The FPGA stretches the image according to the received threshold and converts the 16-bit image into an 8-bit image. According to the specific situation of the image, dynamically determine whether the 1% linear stretching condition is met, and adjust the stretching strategy accordingly (in some cases, the grayscale value distribution of the image may be relatively uniform, or there are no obvious extreme values ​​at both ends of the histogram. In this case, there is no need for 1% linear stretching, or the truncation ratio (such as 0.5% or 2%) can be adjusted to adapt to different image characteristics) to achieve the best image processing effect. After this process, the grayscale value of the image changes from being concentrated in the local area to being evenly distributed in the entire grayscale area. By implementing different data processing methods on the collected image and video data according to the data type, the applicability of the data transmission method of the present application is improved, and the targetedness of the data processing is also improved.

[0050] Step S12: Cache the target image video data using each preset FIFO queue with a ping-pong cache structure to obtain cache data corresponding to the target image video data, and encapsulate the cache data into an Ethernet data packet that meets the user datagram protocol.

[0051] In this embodiment, the FIFO queue used to cache the target image video data is a FIFO queue with a ping-pong cache structure, that is, in this embodiment, two FIFO queues with a ping-pong structure are used alternately. When one FIFO queue is being read, the other FIFO queue can receive new data at the same time, thereby realizing continuous data transmission. In addition, the Ethernet data packet in this embodiment is a data packet that satisfies the user datagram protocol; it should be noted that the reason why the data packet follows the UDP (User Datagram Protocol) network communication protocol is that UDP has the advantages of no connection, low overhead, and high speed, and is very suitable for the transmission of real-time image video data. At the same time, in order to ensure the integrity of the data, the present invention adds information such as a check code and a sequence number to the data packet. Through the design of the ping-pong FIFO structure and the UDP protocol, the real-time transmission and display of data are guaranteed; through a reasonable data cache and processing mechanism, and a stable Ethernet communication module, the stability of data transmission is guaranteed, the data loss rate is reduced, and the integrity and continuity of the image video are ensured. The use of efficient interface standards and verification mechanisms improves the stability and reliability of data transmission; by adding check codes and sequence numbers to the data packets, the reliability of the data transmission process is guaranteed.

[0052] Step S13: sending the Ethernet data packet corresponding to the target image video data to a target host, so that the target host receives the Ethernet data packet and parses the Ethernet data packet to obtain and display the target image video data in real time.

[0053] In this embodiment, the process of sending the Ethernet data packet corresponding to the target image and video data to the target host may specifically include: establishing a communication connection with the target host using a Gigabit Ethernet interface, sending the Ethernet data packet corresponding to the target image and video data to the Gigabit Ethernet interface, and sending the Ethernet data packet to the target host using the Gigabit Ethernet interface. By using the Gigabit Ethernet interface and FPGA parallel processing technology, high-speed transmission of image and video data is achieved; and because the FPGA chip itself has the characteristics of low power consumption, compared with some dedicated chips, it can effectively reduce the energy consumption of the system. In large-scale deployment application scenarios, such as monitoring networks, it can significantly reduce energy consumption and operating costs; at the same time, the FPGA-based solution avoids the use of expensive dedicated hardware equipment and reduces the hardware cost of the system.

[0054] It can be seen that the present application caches image and video data by utilizing a FIFO queue with a ping-pong cache structure. When one FIFO queue is being read, another FIFO queue can simultaneously receive new data, thereby avoiding the problem of waiting due to the queue being used, shortening the data transmission time, and realizing rapid data transmission; by encapsulating the image and video data into Ethernet data packets that meet the user datagram protocol, the user data packet protocol can be used for data transmission, thereby improving the data transmission rate; by adopting a Gigabit Ethernet interface and FPGA parallel processing technology, high-speed transmission of image and video data is realized.

[0055] Based on the previous embodiment, this application describes the workflow of the FPGA chip during data transmission. In order to make the technical solution of this application more complete, this application will describe the workflow of the target host side during data transmission. Figure 5 As shown, the embodiment of the present application discloses a data transmission method based on FPGA, which is applied to a target host and includes:

[0056] Step S21, receiving an Ethernet data packet corresponding to the target image video data sent by the FPGA chip; wherein the target image video data is the data type corresponding to the initial image video data collected by the FPGA chip from the target data source based on a preset image sensor, and is data obtained after data processing of the initial image video data; the Ethernet data packet is an Ethernet data packet that satisfies the user datagram protocol after the FPGA chip encapsulates the cache data corresponding to the target image video data; the cache data is the data obtained after the FPGA chip caches the target image video data using various preset FIFO queues with a ping-pong cache structure.

[0057] It should be noted that, since the Ethernet data packet in this embodiment is a data packet containing a check code and a sequence number, the target host needs to check the data packet after receiving the Ethernet data packet sent by the FPGA chip to determine whether there is a phenomenon of data packet loss during the data transmission process. In a specific implementation, if there is a data packet loss during the data transmission process, a data acquisition request is sent to the FPGA to receive the data packet again; it should be noted that the data acquisition request sent to the FPGA can be a data acquisition request only for missing data or a data acquisition request for all data; in another specific implementation, if there is no problem of data packet loss during the data transmission process, the received data packet is directly parsed. By checking the data packet, the problem of data packet loss during the data transmission process is avoided, and the reliability of the data transmission process is guaranteed.

[0058] Step S22: parsing the Ethernet data packet to obtain the target image video data in the Ethernet data packet, and displaying the target image video data in real time.

[0059] It should be noted that in order to realize the real-time display of data, the present invention adopts efficient image processing algorithms and display technologies. At the same time, in order to support a variety of display devices and resolutions, the present invention also provides a configurable display parameter setting function; accordingly, in this embodiment, the process of real-time display of target image video data may specifically include: obtaining the image resolution and image format of the local image display device, setting the target display parameters corresponding to the target image video data according to the preset display parameter setting function, image resolution and image format, and displaying the target image video data in real time based on the target display parameters. By displaying the image video data obtained by parsing according to the image resolution and image format of the local image display device, it is ensured that the image video data can be applied to different types of image video display devices, thereby improving the applicability of the data display process.

[0060] It can be seen that the present application caches image and video data by utilizing a FIFO queue with a ping-pong cache structure. When one FIFO queue is being read, another FIFO queue can simultaneously receive new data, thereby avoiding the problem of waiting due to the queue being used, shortening the data transmission time and realizing fast data transmission; by encapsulating the image and video data into Ethernet data packets that meet the user datagram protocol, the user data packet protocol can be used for data transmission, thereby improving the data transmission rate.

[0061] See also Figure 6 As shown, the embodiment of the present application discloses a data transmission device based on FPGA, which is applied to FPGA chip, including:

[0062] The data acquisition module 11 is used to acquire the initial image video data collected by the preset image sensor from the target data source, and perform data processing on the initial image video data based on the data type corresponding to the initial image video data to acquire the corresponding target image video data;

[0063] The data cache module 12 is used to cache the target image video data by using each preset FIFO queue with a ping-pong cache structure to obtain cache data corresponding to the target image video data, and encapsulate the cache data into an Ethernet data packet that meets the user datagram protocol;

[0064] The data sending module 13 is used to send the Ethernet data packet corresponding to the target image video data to the target host, so that the target host receives the Ethernet data packet and parses the Ethernet data packet to obtain and display the target image video data in real time.

[0065] It can be seen that the present application caches image and video data by utilizing a FIFO queue with a ping-pong cache structure. When one FIFO queue is being read, another FIFO queue can simultaneously receive new data, thereby avoiding the problem of waiting due to the queue being used, shortening the data transmission time and realizing fast data transmission; by encapsulating the image and video data into Ethernet data packets that meet the user datagram protocol, the user data packet protocol can be used for data transmission, thereby improving the data transmission rate.

[0066] In some specific embodiments, the data acquisition module 11 may specifically include:

[0067] The image stretching submodule is used to identify the data type corresponding to each of the initial image video data. If there is target data of the infrared image data type in the initial image video data, grayscale stretching processing is performed on the target data to obtain corresponding stretched data.

[0068] In some specific embodiments, the image stretching submodule may specifically include:

[0069] A threshold setting unit, used to set an initial grayscale threshold corresponding to the target data, and perform grayscale stretching processing on the target data based on the initial grayscale threshold to obtain corresponding initial stretched data;

[0070] A data sending unit, configured to send the initial stretched data to the target host, so that the target host generates a target grayscale threshold corresponding to the target data based on the initial stretched data, and sends the target grayscale threshold to the FPGA chip;

[0071] The image stretching unit is used to receive the target grayscale threshold and perform grayscale stretching on the target data based on the target grayscale threshold to obtain the stretched data.

[0072] In some specific embodiments, the data sending module 13 may specifically include:

[0073] A data sending unit is used to establish a communication connection with the target host using a Gigabit Ethernet interface, send the Ethernet data packet corresponding to the target image video data to the Gigabit Ethernet interface, and send the Ethernet data packet to the target host using the Gigabit Ethernet interface.

[0074] Furthermore, the present application also discloses an electronic device. Figure 7 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram cannot be regarded as any limitation on the scope of use of the present application.

[0075] Figure 7 A schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the FPGA-based data transmission method disclosed in any of the aforementioned embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0076] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0077] In addition, the memory 22 as a carrier for storing resources may be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon may include an operating system 221, a computer program 222, etc., and the storage method may be temporary storage or permanent storage.

[0078] The operating system 221 is used to manage and control the hardware devices and computer program 222 on the electronic device 20, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the FPGA-based data transmission method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

[0079] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the aforementioned disclosed FPGA-based data transmission method is implemented. The specific steps of the method can refer to the corresponding contents disclosed in the aforementioned embodiments, and will not be repeated here.

[0080] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0081] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0082] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0083] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0084] The technical solution provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technicians in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A data transmission method based on FPGA, characterized in that: Applied to FPGA chips, including: Acquire initial image video data collected by a preset image sensor from a target data source, and perform data processing on the initial image video data based on a data type corresponding to the initial image video data to acquire corresponding target image video data; Utilizing each preset FIFO queue with a ping-pong cache structure to cache the target image video data to obtain cache data corresponding to the target image video data, and encapsulating the cache data into an Ethernet data packet that meets the user datagram protocol; The Ethernet data packet corresponding to the target image video data is sent to a target host so that the target host receives the Ethernet data packet and parses the Ethernet data packet to obtain and display the target image video data in real time.

2. The FPGA-based data transmission method according to claim 1, characterized in that: The performing data processing on the initial image and video data based on the data type corresponding to the initial image and video data includes: The data type corresponding to each of the initial image video data is identified. If there is target data of the infrared image data type in the initial image video data, grayscale stretching processing is performed on the target data to obtain corresponding stretched data.

3. The FPGA-based data transmission method according to claim 2, characterized in that: The grayscale stretching process is performed on the target data to obtain corresponding stretched data, including: Setting an initial grayscale threshold corresponding to the target data, and performing grayscale stretching processing on the target data based on the initial grayscale threshold to obtain corresponding initial stretched data; Sending the initial stretching data to the target host, so that the target host generates a target grayscale threshold corresponding to the target data based on the initial stretching data, and sending the target grayscale threshold to the FPGA chip; The target grayscale threshold is received, and grayscale stretching is performed on the target data based on the target grayscale threshold to obtain the stretched data.

4. The FPGA-based data transmission method according to claim 1, characterized in that: The step of sending the Ethernet data packet corresponding to the target image video data to a target host comprises: A communication connection is established with the target host using a Gigabit Ethernet interface, the Ethernet data packet corresponding to the target image video data is sent to the Gigabit Ethernet interface, and the Ethernet data packet is sent to the target host using the Gigabit Ethernet interface.

5. A data transmission method based on FPGA, characterized in that: Applied to the target host, including: Receive an Ethernet data packet corresponding to target image video data sent by the FPGA chip; wherein the target image video data is data type corresponding to initial image video data collected by the FPGA chip from a target data source based on a preset image sensor, and is data obtained after data processing of the initial image video data; the Ethernet data packet is an Ethernet data packet that satisfies the user datagram protocol obtained after the FPGA chip encapsulates the cache data corresponding to the target image video data; the cache data is data obtained after the FPGA chip caches the target image video data using various preset FIFO queues with a ping-pong cache structure; The Ethernet data packet is parsed to obtain the target image video data in the Ethernet data packet, and the target image video data is displayed in real time.

6. The FPGA-based data transmission method according to claim 5, characterized in that: The parsing operation on the Ethernet data packet to obtain the target image video data in the Ethernet data packet includes: An integrity check is performed on the Ethernet data packet to obtain a corresponding verified data packet, and data extraction is performed on the verified data packet to obtain the target image video data in the verified data packet.

7. The FPGA-based data transmission method according to claim 5, characterized in that: The real-time display of the target image video data includes: The image resolution and image format of the local image display device are obtained, the target display parameters corresponding to the target image video data are set according to a preset display parameter setting function, the image resolution and the image format, and the target image video data is displayed in real time based on the target display parameters.

8. A data transmission device based on FPGA, characterized in that: Applied to FPGA chips, including: A data acquisition module, used to acquire initial image video data collected by a preset image sensor from a target data source, and perform data processing on the initial image video data based on a data type corresponding to the initial image video data to acquire corresponding target image video data; A data cache module, used to cache the target image video data using each preset FIFO queue with a ping-pong cache structure to obtain cache data corresponding to the target image video data, and encapsulate the cache data into an Ethernet data packet that meets the user datagram protocol; The data sending module is used to send the Ethernet data packet corresponding to the target image video data to the target host, so that the target host receives the Ethernet data packet and parses the Ethernet data packet to obtain and display the target image video data in real time.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the FPGA-based data transmission method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store a computer program, which, when executed by a processor, implements the FPGA-based data transmission method according to any one of claims 1 to 7.

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