Data analysis system and method and electronic equipment

Abstract

The invention provides a data analysis system and method and electronic equipment, and belongs to the technical field of data analysis, and the method comprises the following steps: obtaining current configuration information and a current state of a data analysis unit of the data analysis system, and generating a program reading address according to the current configuration information and the current state; reading the target program according to the program reading address; and obtaining a target program, loading the to-be-analyzed data based on the target program, and analyzing the to-be-analyzed data to obtain analyzed data. According to the invention, the data analysis efficiency and flexibility are improved, and the data analysis cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of data analysis, and in particular to a data analysis system, method and electronic device. Background Art

[0002] In wireless communication networks, the baseband processing unit (Building Base band Unit, BBU) and the radio remote unit (Radio Remote Unit, RRU) are deployed in a distributed manner through optical fiber connections. This design allows the baseband processing to be concentrated in the central machine room, while the radio frequency part is distributed to each site, reducing the demand for the machine room and improving the coverage. In addition, in order to improve efficiency and reduce system bandwidth, the service data on the fronthaul interface will be compressed before transmission. Since compression will cause the data bit width to change, and there are many possibilities for the compressed bit width, this leads to the complexity of data parsing.

[0003] The disadvantages of existing data parsing methods based on application-specific integrated circuits (ASICs) are: low flexibility and high silicon overhead; for each compression bit width and source data bit width that needs to be supported, a set of hardware needs to be deployed to support it, which significantly increases the complexity of the design and brings huge silicon overhead; in addition, this method has poor flexibility and can only support fixed requirements, and cannot support new requirements outside the design. The disadvantages of existing software-based data parsing methods are: complex processing flow, slow speed, and large processing delay. Summary of the invention

[0004] The present invention provides a data analysis system, method and electronic device to solve the defects of low flexibility and high silicon cost of ASIC-based data analysis methods and slow speed and large processing delay of software-based data analysis methods in the prior art.

[0005] The present invention provides a data analysis system, the system comprising a state machine, a program storage unit and a data analysis unit, the state machine is communicatively connected with the program storage unit and the data analysis unit, the program storage unit is communicatively connected with the data analysis unit, wherein: A state machine, used to obtain current configuration information and a current state of the data parsing unit, and generate a program read address according to the current configuration information and the current state; A program storage unit, used for reading a target program according to the program reading address; The data parsing unit is used to obtain the target program, load the data to be parsed based on the target program, and parse the data to be parsed to obtain parsed data.

[0006] In some embodiments, the target program includes instruction data, the instruction data includes a shift width, a header shift width, a header output indication, and a read indication, and the data parsing unit includes: A data loading module, used for loading the data to be parsed according to the reading instruction; A register, used to store the newly loaded data to be parsed; A data shift module, used for shifting and intercepting the data to be parsed according to the packet header output indication and the packet header shift width, and outputting the packet header data; The data interception module is used to shift, intercept and expand the high bits of the data to be parsed according to the shift bit width and the bit width of the data to be parsed, and output the parsed data.

[0007] In some embodiments, the state machine is further used to: determine whether the data parsing unit is abnormal based on the current state, and if so, generate an alarm message.

[0008] In some embodiments, the system also includes a user input interface, which is communicatively connected to the state machine, and the user input interface is used to obtain the current configuration information input by the user, and the current configuration information includes the bit width of the data to be parsed and the compressed bit width of the data to be parsed.

[0009] The present invention also provides a data analysis method, comprising: Acquire current configuration information and a current state of a data parsing unit of a data parsing system, and generate a program read address according to the current configuration information and the current state; Reading a target program according to the program reading address; The target program is obtained, the data to be parsed is loaded based on the target program, and the data to be parsed is parsed to obtain parsed data.

[0010] In some embodiments, the target program includes instruction data, and the instruction data includes a shift bit width, a header shift bit width, a header output indication, and a read indication.

[0011] In some embodiments, the step of parsing the data to be parsed based on the target program data to obtain the parsed data includes: According to the read instruction, load the data to be parsed; Storing the newly loaded data to be parsed; According to the packet header output indication and the packet header shift width, the data to be parsed is shifted and intercepted, and the packet header data is output; According to the shift bit width and the bit width of the data to be parsed, the data to be parsed is shifted, truncated and high-bit expanded, and the parsed data is output.

[0012] In some embodiments, the method further comprises: According to the current state, it is determined whether the data parsing unit is abnormal, and if so, an alarm message is generated.

[0013] In some embodiments, the current configuration information includes the bit width of the data to be parsed and the compressed bit width of the data to be parsed.

[0014] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, any of the data analysis methods described above is implemented.

[0015] The data analysis system, method and electronic device provided by the present invention obtain the current configuration information and the current state of the data analysis unit of the data analysis system, generate a program reading address according to the current configuration information and the current state, read the target program according to the program reading address, obtain the target program, load the data to be analyzed based on the target program, analyze the data to be analyzed, and obtain the analyzed data, thereby improving the efficiency and flexibility of data analysis and reducing the cost of data analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 is a structural diagram of a data analysis system provided by an embodiment of the present invention; Figure 2 is a structural schematic diagram of a data parsing unit provided in an embodiment of the present invention; Figure 3 This is one of the flow charts of the data parsing method provided by the embodiment of the present invention; Figure 4 This is the second flow chart of the data analysis method provided by the embodiment of the present invention; Figure 5 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] Figure 1 The structure diagram of the data analysis system provided by the embodiment of the present invention is as follows. Figure 1 As shown, a data analysis system is provided, which includes a state machine 110, a program storage unit 120 and a data analysis unit 130, the state machine 110 is connected in communication with the program storage unit 120 and the data analysis unit 130, and the program storage unit 120 is connected in communication with the data analysis unit 130, wherein: The state machine 110 is used to obtain the current configuration information and the current state of the data parsing unit 130, and generate a program read address according to the current configuration information and the current state; A program storage unit 120, used for reading a target program according to a program reading address; The data parsing unit 130 is used to obtain the target program, load the data to be parsed based on the target program, parse the data to be parsed, and obtain the parsed data.

[0020] Among them, the program storage unit 120 stores multiple pre-written programs, different programs are pre-written according to different configuration information, and are applied to different data analysis scenarios; the program storage unit 120 has strong scalability, and new programs can be stored in the program storage unit 120 according to new user needs.

[0021] It is understandable that by storing new programs in the program storage unit according to new user needs, the flexibility of the data analysis system can be improved and the data analysis system can be adapted to new application scenarios.

[0022] Optionally, the state machine 110 is used to determine whether the data parsing unit 130 is normal according to the current state, and if so, generate a read address of the target program according to the current configuration information.

[0023] In some embodiments, the state machine 110 is further used to: determine whether the data parsing unit is abnormal according to the current state, and if so, generate an alarm message.

[0024] It is understandable that the state machine can timely discover abnormal situations of the data analysis unit by judging the current state of the data analysis unit, which helps to handle the abnormal situations in time and improve the stability of the system.

[0025] In some embodiments, the data parsing system further includes a user input interface, which is in communication with the state machine 110 and is used to obtain current configuration information input by the user, wherein the current configuration information includes the bit width of the data to be parsed and the compressed bit width of the data to be parsed.

[0026] It can be understood that the data analysis system can receive the current configuration information input by the user in real time by setting up a user input interface. It has strong flexibility and facilitates customized data analysis, which improves the user experience. The bit width of the data to be analyzed and the compressed bit width of the data to be analyzed can be configured, and it supports the analysis of compressed data of any compression bit width, which is suitable for a variety of application scenarios.

[0027] Figure 2 A schematic diagram of the structure of a data parsing unit provided in an embodiment of the present invention. Figure 2 As shown, in some embodiments, the target program includes instruction data, the instruction data includes a shift width, a header shift width, a header output indication, and a read indication, and the data parsing unit 130 includes: The data loading module 131 is used to load the data to be parsed according to the reading instruction; Register 132, used to store newly loaded data to be parsed; A data shift module 133, used to shift and intercept the data to be parsed according to the packet header output indication and the packet header shift width, and output the packet header data; The data interception module 134 is used to shift, intercept and high-bit expand the data to be parsed according to the shift width and the bit width of the data to be parsed, and output the parsed data.

[0028] Table 1 is an example of instruction data provided by an embodiment of the present invention. As shown in Table 1, the instruction data includes a shift width A, a packet header shift width B, a packet header output indication E, and a read indication R.

[0029] Table 1 Command data example

[0030] It should be noted that the bit width of the data to be parsed is Mbit, the compressed bit width is Nbit, and Sbit is the extended bit width; where S=MN, the header bit width is Pbit, and in the instruction, the bit width of A is , the bit width of B is , E is 1 to output the packet header data, and R is 1 to load the data to be parsed.

[0031] Optionally, the data loading module 131 is used to load the to-be-parsed data with a bit width of 4*Mbit according to the read indication R (ie, R=1).

[0032] Optionally, register 132 is used to shift the data in register 132 left by 64 bits when R=1, perform an OR operation with the newly loaded data, and transmit it to the data shift module 133; when R=0, directly pass the data in register 132 to the data shift module 133.

[0033] Optionally, the data shift module 133 is used to right-shift the value of the register 132 by Bbit when the packet header output indication E=1, and intercept Pbit as the packet header data output.

[0034] Optionally, the data interception module 134 is used to right-shift the value of the register 132 by A bit, intercept 4 N-bit data from the lower bits, and then copy (MN) copies of the highest bit of each data to form 4 M-bit wide parsed data, and output the parsed data.

[0035] It can be understood that the instruction data of the data analysis system in the embodiment of the present invention is streamlined, and the disassembly of data of different bit widths can be achieved through simple instruction configuration. The data analysis efficiency is high, and it is particularly suitable for scenarios where payload data is arranged in compressed equal-bit-width data, such as in-phase and quadrature (IQ) data of wireless communication systems; the data analysis system supports the analysis of arbitrary IQ data, and its characteristics are that both the input bit width and the output bit width are configurable, and can be reconfigured after a data analysis is completed, and it has strong flexibility; the data analysis system supports the disassembly of data to be analyzed with a packet header, and outputs the packet header and the parsed data separately after the disassembly is completed, and has a very wide application space.

[0036] In an embodiment of the present invention, the data analysis system obtains the current configuration information and the current state of the data analysis unit of the data analysis system, generates a program reading address according to the current configuration information and the current state, reads the target program according to the program reading address, obtains the target program, loads the data to be analyzed based on the target program, analyzes the data to be analyzed, and obtains the analyzed data, thereby improving the efficiency and flexibility of data analysis and reducing the cost of data analysis.

[0037] Figure 3 This is one of the flow charts of the data analysis method provided by the embodiment of the present invention. Figure 3 As shown, a data analysis method is provided, and the data analysis method is applied to Figure 1 The data analysis system in is used as an example to illustrate, which includes the following steps: step 310, step 320, and step 330. The steps of the method flow are only a possible implementation of the present invention.

[0038] The present invention also provides a data analysis method, comprising: Step 310: Acquire current configuration information and a current state of a data parsing unit of the data parsing system, and generate a program read address according to the current configuration information and the current state; Step 320, reading the target program according to the program reading address; Step 330: Obtain the target program, load the data to be parsed based on the target program, parse the data to be parsed, and obtain the parsed data.

[0039] Figure 4 The second flow chart of the data analysis method provided by the embodiment of the present invention. Figure 4 As shown, the data to be parsed (i.e., the payload data) is recovered to obtain the recovered data, and the recovered data is processed to obtain the parsed data; wherein, the data to be parsed includes two IQ data, the bit width of each I and each Q of the data to be parsed is Mbit, the compressed bit width is Nbit, and Sbit is the extended bit; wherein S=MN.

[0040] Optionally, a plurality of pre-written programs are stored, where different programs are pre-written according to different configuration information and are applied to different data analysis scenarios.

[0041] Optionally, new programs are determined and stored based on newly added user needs.

[0042] Optionally, the current configuration information is determined according to user input.

[0043] In some embodiments, the target program includes instruction data, and the instruction data includes a shift bit width A, a header shift bit width B, a header output indication E, and a read indication R.

[0044] In some embodiments, the current configuration information includes the bit width of the data to be parsed and the compressed bit width of the data to be parsed.

[0045] It can be understood that by obtaining the current configuration information, the corresponding target program can be obtained according to the different bit widths and compressed bit widths of the data to be parsed, and then the data to be parsed can be parsed through the corresponding instruction data, thereby improving the efficiency and flexibility of data parsing and being suitable for different application scenarios.

[0046] For example, to deconcatenate data compressed to 9 bits (M=16, N=9), assuming there is no header, the instruction process of the three instructions is as follows: 1) Instruction 1 is "A=28, B=0, E=0, R=1", R=1 so 64-bit data is loaded; first, it is merged with the original register after being shifted left by 64 bits. The original register is empty. After this step, the result in the register is the newly loaded 64-bit data; because E=0, the packet header is not intercepted; A=28, the data is right-shifted 28 bits; 4 9-bits are intercepted from the low bit, that is, 4 9-bit data are intercepted from [35:27], [26:18], [17:9] and [8:0] respectively, and then the high bits of these data are copied 7 times and filled respectively, and finally 4 16-bit data are output; there are 28 bits of valid data left in the register.

[0047] 2) Instruction 2 is "A=56, B=0, E=0, R=1", R=1, so 64 bits of data are loaded; first, the original register is shifted left by 64 bits and then merged. There are 24 bits of valid data left from the last time, so the effective data width after this step of combination is 88 bits; because E=0, the packet header is not intercepted; A=56, the data is shifted right by 56 bits; 4 9 bits are intercepted from the low bit, that is, 4 9 bits of data are intercepted from [35:27], [26:18], [17:9] and [8:0] respectively, and then the high bits of these data are copied 7 times and filled respectively, and finally 4 16-bit data outputs are obtained; 56 bits of valid data remain in the register.

[0048] 3) Instruction 3 is "A=20, B=0, E=0, R=0". No new data is loaded, and the register value is shifted right by 16 bits. Four 9-bits are intercepted from the low order, that is, 4 9-bit data are intercepted from [35:27], [26:18], [17:9] and [8:0] respectively, and then the high order of these data is copied 7 times to fill them respectively, and finally 4 20-bit data outputs are obtained; there are 20 bits of valid data remaining in the register.

[0049] In an embodiment of the present invention, the data analysis system obtains the current configuration information and the current state of the data analysis unit of the data analysis system, generates a read address according to the current configuration information and the current state, reads the target program according to the program read address, obtains the target program, loads the data to be analyzed based on the target program, analyzes the data to be analyzed, and obtains the analyzed data, thereby improving the efficiency and flexibility of data analysis and reducing the cost of data analysis.

[0050] In some embodiments, in step 330, the data to be parsed is parsed based on the target program data to obtain the parsed data, including: Step 331, loading the data to be parsed according to the reading instruction; Step 332: storing the newly loaded data to be parsed; Step 333: Shift and intercept the data to be parsed according to the packet header output indication and the packet header shift width, and output the packet header data; According to the shift width and the width of the data to be parsed, the data to be parsed is shifted, intercepted and high-order expanded, and the parsed data is output.

[0051] It can be understood that by parsing the data to be parsed through streamlined instruction data, the packet header and the parsed data are obtained, thereby improving the efficiency and flexibility of data parsing and being suitable for a variety of application scenarios.

[0052] In some embodiments, the method further comprises: According to the current status, determine whether the data analysis unit is abnormal. If so, generate an alarm message.

[0053] It is understandable that by judging the current state, abnormal situations can be discovered in time, handled, and the stability of the system can be improved.

[0054] Table 2 shows the clock overhead of different data parsing methods. As shown in Table 1, for a 5G New Radio (NR) fronthaul interface resource block (RB) data, a resource element (RE) includes 12 IQ data, each IQ is a 16-bit complex number, and the interface width is 64 bits. The clock overhead of the scheme of this embodiment is consistent with that of the ASIC scheme, which is much lower than the time overhead of the software scheme. For different compressed bit widths, the parsing efficiency of this scheme is dozens of times that of the software scheme. Although the ASIC scheme can also achieve the efficiency of this scheme, the hardware cost is higher and the flexibility is lower.

[0055] Table 2 Clock overhead of different data parsing methods

[0056] Table 3 shows the gate overhead of different data parsing methods. As shown in Table 3, in the case of 8-15 bit compression, the gate overhead of the ASIC solution is much higher than the gate overhead of this solution.

[0057] Table 3 Gate overhead of different data parsing methods

[0058] Figure 5 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention, such as Figure 5As shown, the electronic device may include: a processor 510, a communication interface 520, a memory 530 and a communication bus 540, wherein the processor 510, the communication interface 520 and the memory 530 communicate with each other through the communication bus 540. The processor 510 may call the logic instructions in the memory 530 to execute the data parsing method, which includes: obtaining the current configuration information and the current state of the data parsing unit of the data parsing system, generating a program reading address according to the current configuration information and the current state; reading a target program according to the program reading address; obtaining the target program, loading the data to be parsed based on the target program, parsing the data to be parsed, and obtaining the parsed data.

[0059] In addition, the logic instructions in the above-mentioned memory 530 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0060] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0061] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data analysis system, characterized in that: The system comprises a state machine, a program storage unit and a data parsing unit, wherein the state machine is in communication connection with the program storage unit and the data parsing unit, and the program storage unit is in communication connection with the data parsing unit, wherein: A state machine, used to obtain current configuration information and a current state of the data parsing unit, and generate a program read address according to the current configuration information and the current state; A program storage unit, used for reading a target program according to the program reading address; The data parsing unit is used to obtain the target program, load the data to be parsed based on the target program, and parse the data to be parsed to obtain parsed data.

2. The data analysis system according to claim 1, characterized in that: The target program includes instruction data, the instruction data includes a shift width, a header shift width, a header output indication, and a read indication, and the data parsing unit includes: A data loading module, used for loading the data to be parsed according to the reading instruction; A register, used to store the newly loaded data to be parsed; A data shift module, used for shifting and intercepting the data to be parsed according to the packet header output indication and the packet header shift width, and outputting the packet header data; The data interception module is used to shift, intercept and expand the high bits of the data to be parsed according to the shift bit width and the bit width of the data to be parsed, and output the parsed data.

3. The data analysis system according to claim 1, characterized in that: The state machine is also used to: determine whether the data parsing unit is abnormal according to the current state, and if so, generate alarm information.

4. The data analysis system according to claim 1, characterized in that: The system also includes a user input interface, which is communicatively connected to the state machine, and is used to obtain the current configuration information input by a user, wherein the current configuration information includes the bit width of the data to be parsed and the compressed bit width of the data to be parsed.

5. A data analysis method, characterized in that: include: Acquire current configuration information and a current state of a data parsing unit of the data parsing system, and generate a read address according to the current configuration information and the current state; Read the target program according to the read address; The target program is obtained, the data to be parsed is loaded based on the target program, and the data to be parsed is parsed to obtain parsed data.

6. The data analysis method according to claim 5, characterized in that: The target program includes instruction data, and the instruction data includes a shift bit width, a header shift bit width, a header output indication, and a read indication.

7. The data analysis method according to claim 6, characterized in that: The step of parsing the data to be parsed based on the target program data to obtain the parsed data includes: According to the read instruction, load the data to be parsed; Storing the newly loaded data to be parsed; According to the packet header output indication and the packet header shift width, the data to be parsed is shifted and intercepted, and the packet header data is output; According to the shift bit width and the bit width of the data to be parsed, the data to be parsed is shifted, truncated and high-bit expanded, and the parsed data is output.

8. The data analysis method according to claim 5, characterized in that: The method further comprises: According to the current state, it is determined whether the data parsing unit is abnormal, and if so, an alarm message is generated.

9. The data analysis method according to claim 5, characterized in that: The current configuration information includes the bit width of the data to be parsed and the compressed bit width of the data to be parsed.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the data parsing method according to any one of claims 5 to 9 is implemented.

Images