Flash memory structure and flash memory
By designing a U-shaped source line structure in the end region of the gate-splitter flash memory, the problem of short circuit between the word line contact hole and the source line layer is solved, ensuring sufficient process window and improving the reliability and performance of the flash memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2025-01-16
- Publication Date
- 2026-05-19
AI Technical Summary
In a multi-gate flash memory structure, an excessively large floating gate etching process window leads to an excessively large source polysilicon size, and the insulation layer distance of the sidewall isolation process becomes shorter, resulting in a potential risk of short circuit between the word line contact hole and the source line, causing IM failure.
By designing the source line layer in a U-shape in the end area, the area where the word line layer connects to the word line contact hole is far away from the source line layer, ensuring sufficient process window and preventing short circuit between the word line contact hole and the source line layer.
This effectively prevents short circuits between word line contact holes and source line layers, avoids IM failure, and improves the reliability and performance of flash memory.
Smart Images
Figure CN119947099B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a flash memory structure and a flash memory. Background Technology
[0002] Flash memory is divided into two types: stacked-gate flash memory and split-gate flash memory. Stacked-gate flash memory has a floating gate and a control gate located above the floating gate. Stacked-gate flash memory suffers from the problem of over-source lines. Unlike stacked-gate flash memory, split-gate flash memory forms a word line that serves as the source gate on one side of the floating gate, effectively avoiding the over-source line effect.
[0003] In the design of a gate-based flash memory architecture, a strap region is formed between every few I / O operations, such as... Figure 1 As shown. In the Strap area, the word line contact holes (CT) and source line contact holes (CT) are separated according to their special structure, as follows. Figure 2 and Figure 5 As shown, this is to achieve the function of controlling the word line and the source line respectively.
[0004] In flash cell design, if the floating gate etching process window (FGPL CD) is too large, it will lead to a larger source polysilicon size (SPL CD), and a shorter distance between the insulating layer (SPL) and word line (WL) isolated by the sidewall isolation process (FGSP). Figure 4 As shown, when the overlay (CT OVL) of the contact window is too large, it will cause a potential risk of short circuit between the contact hole of the word line and the source line, thus causing IM to fail. Summary of the Invention
[0005] The purpose of this invention is to provide a flash memory structure and a flash memory, including multiple active array regions and end regions located between adjacent active array regions. By changing the structural design of the end regions, the area where the word line layer connects to the word line contact hole is moved away from the source line layer, ensuring sufficient process window to prevent short circuit between the word line contact hole and the source line layer.
[0006] To achieve the above objectives, the present invention provides a flash memory structure that solves the problem of IM failure caused by the connection between the word line contact hole area and the source line layer. The flash memory structure includes multiple active array regions and a terminator region located between adjacent active array regions. The terminator region includes:
[0007] The semiconductor substrate includes adjacent source line floating gate regions and word line bit line regions;
[0008] A floating grid structure, located in the source line floating grid region, includes a floating grid layer, a first sidewall located in the floating grid layer, a source line layer located between the floating grid layer and the first sidewall, and a source line contact hole located on the source line layer connecting the source line layer.
[0009] The word line structure, located in the word line bit line area, includes a word line layer and word line contact holes located on the word line layer and connected to the word line layer. The word line layer covers the floating grid layer and the sidewall of the first sidewall.
[0010] In the horizontal direction, the source line layer has a U-shaped structure with the opening of the U-shaped structure facing the word line contact hole. The U-shaped structure design keeps the area of the word line layer connected to the word line contact hole away from the source line layer, ensuring sufficient process window to prevent short circuit between the word line contact hole and the source line layer.
[0011] In some alternative embodiments, the floating gate structure further includes a source region located within a semiconductor substrate at the bottom of the source line layer.
[0012] In some alternative embodiments, the word line structure further includes a second sidewall located on the sidewall of the word line layer, a bit line located within the semiconductor substrate of the word line bit line region, and a drain region located within the semiconductor substrate at the bottom of the bit line and the bottom of the second sidewall.
[0013] In some alternative embodiments, a gate oxide layer is disposed between the semiconductor substrate and the floating gate layer.
[0014] In some optional embodiments, within the end area, the U-shaped structure includes a first U-shaped structure and a second U-shaped structure. In the horizontal direction, the first U-shaped structure is nested around the periphery of the second U-shaped structure. The opening directions of the first U-shaped structure and the second U-shaped structure are opposite, and the opening directions of both the first U-shaped structure and the second U-shaped structure are towards the letter contact hole.
[0015] In some alternative embodiments, the first U-shaped structure and the second U-shaped structure do not contact each other in the horizontal direction.
[0016] In some alternative embodiments, the end region includes two sets of the U-shaped structures, the two sets of the U-shaped structures being centrally symmetrical about the center of the end region.
[0017] Secondly, based on the same inventive concept, the present invention also provides a flash memory, the flash memory comprising the flash memory structure described in any of the preceding claims.
[0018] In summary, the present invention provides a flash memory structure and a flash memory, including multiple active array regions and end regions located between adjacent active array regions. In the horizontal direction, the source line layer in the end region has a U-shaped structure, and the opening of the U-shaped structure faces the word line contact hole. The U-shaped structure design keeps the area of the word line layer connected to the word line contact hole away from the source line layer, ensuring sufficient process window to prevent short circuit between the word line contact hole and the source line layer. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of a flash memory structure that includes multiple active array regions and end regions located between adjacent active array regions.
[0020] Figure 2 This is a SEM image of the end region in the flash memory structure in the horizontal direction.
[0021] Figure 3 This is a SEM image of the end region in the flash memory structure in the vertical direction.
[0022] Figure 4 This is a schematic diagram of the structure of a storage cell in a flash memory.
[0023] Figure 5 This is a schematic diagram of the end area layout in a flash memory structure.
[0024] Figure 6 This is a layout of the header region of a flash memory structure provided in an embodiment of the present invention.
[0025] The attached figures are labeled as follows:
[0026] 100 - Semiconductor substrate; 101 - Source region; 102 - Drain region;
[0027] 110 - Floating gate structure; 111 - Gate oxide layer; 112 - Floating gate; 113 - First sidewall; 114 - Source line layer; 115 - Source line contact control;
[0028] 120 - Word line structure; 121 - Word line layer; 122 - Word line contact hole; 123 - Second sidewall; 124 - Position line layer. Detailed Implementation
[0029] To make the content of this invention clearer and easier to understand, the following description, in conjunction with the accompanying drawings, further illustrates the invention. Of course, this invention is not limited to this specific embodiment, and common substitutions well-known to those skilled in the art are also covered within the scope of protection of this invention.
[0030] Secondly, the present invention is described in detail using schematic diagrams. When describing the examples of the present invention in detail, for ease of explanation, the schematic diagrams are not enlarged to a certain extent according to the general proportions, and this should not be regarded as a limitation of the present invention.
[0031] For ease of description, some embodiments of the present invention may use spatially relative terms such as “above,” “below,” “top,” and “under” to describe the relationship between one element or component and another (or more) elements or components as shown in the accompanying drawings of the embodiments. It should be understood that, in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings is flipped, it is described as an element or component “below” or “under” other elements or components, and will subsequently be positioned “above” or “on” other elements or components. The terms “first,” “second,” etc., used below are used to distinguish between similar elements and are not necessarily used to describe a particular order or temporal sequence.
[0032] Figure 4 This is a schematic diagram of the structure of a storage cell in a flash memory. Figure 6 This is a schematic diagram of a flash memory structure provided in an embodiment of the present invention, with reference to... Figure 4 and Figure 6 As shown, the present invention provides a flash memory structure, including: multiple active array regions and an end region located between adjacent active array regions, wherein the end region includes:
[0033] Semiconductor substrate 100 includes adjacent source line floating gate region I and word line bit line region II;
[0034] The floating gate structure 110, located in the source line floating gate region I, includes a floating gate layer 112, a first sidewall 113 on the floating gate structure, a source line 114 layer between the floating gate layer 112 and the first sidewall 113, and a source line contact hole 115 on the source line layer 114 connecting the source line layer.
[0035] The word line structure 120 is located in the word line bit line area II, including a word line layer 121 and a word line contact hole 122 located on the word line layer 121 and connected to the word line layer 121. The word line layer 121 covers the sidewall of the floating grid layer 112 and the first sidewall 113.
[0036] In the horizontal direction (parallel to the semiconductor substrate direction), the source line layer 114 has a U-shaped structure with the opening of the U-shaped structure facing the word line contact hole 122. The U-shaped structure design keeps the area of the word line layer 121 connected to the word line contact hole 122 away from the source line layer 114, ensuring that there is sufficient process window to prevent the word line contact hole 122 from short-circuiting with the source line layer 114.
[0037] Specifically, the floating gate structure 110 further includes a gate oxide layer 111 located between the semiconductor substrate 100 and the floating gate layer 112. Further, the floating gate structure 110 also includes a source region 101 located within the semiconductor substrate 100 at the bottom of the source line layer 114.
[0038] The word line structure 120 further includes a second sidewall 123 located on the sidewall of the word line layer 121, a bit line layer 124 located in the semiconductor substrate of the word line bit line region, and a drain region 102 located in the semiconductor substrate at the bottom of the bit line layer 124 and the bottom of the second sidewall 123.
[0039] Continue to refer to Figure 6 As shown, within the end region, the source line layer 114 has a U-shaped structure. The U-shaped structure includes a first U-shaped structure U1 and a second U-shaped structure U2. In the horizontal direction, the first U-shaped structure U1 and the second U-shaped structure U2 do not contact each other, and the first U-shaped structure U1 is nested around the second U-shaped structure U2. The opening directions of the first U-shaped structure U1 and the second U-shaped structure U2 are opposite, and the opening directions of the first U-shaped structure U1 and the second U-shaped structure U2 are both facing the word line contact hole 122.
[0040] Furthermore, the end area includes at least two sets of the aforementioned U-shaped structures, which are centrally symmetrical about the center of the end area. The first U-shaped structures U1 of the two sets are connected, and the second U-shaped structures U2 of the two sets are separated by the connected first U-shaped structures U1. The word line contact hole 122 is located in the first U-shaped structure U1. The area of the word line layer 121 connected to the word line contact hole 122 is far from the source line layer 114, ensuring sufficient process window to prevent short circuit between the word line contact hole 122 and the source line layer 114.
[0041] Figure 3 This is a SEM image of the end region in the flash memory structure in the vertical direction. Figure 5 This is a schematic diagram of the end-point area layout in a flash memory structure. For example... Figure 3 and Figure 5 As shown, in the original design, an arc-shaped source line (SL) structure was designed in the end area of the flash memory structure to bring out the word line (WL). The word line layer area is along the sidewall of the first sidewall (FGSP). This arc-shaped design fills the word line layer where the word line contact hole is located. However, since the source line layer and the word line layer are only separated by the FGSP, an OVL deviation occurs when connecting the word line contact hole. Figure 3 and Figure 5As shown, a physical verification analysis (PFA) was performed on the abnormal short circuit point P between the word line contact hole and the source line. The PFA results showed that a short circuit occurred between the word line contact hole and the source line (SL), causing IM failure.
[0042] In this embodiment, in the end region of the flash memory structure, a U-shaped structure of the source line layer is used to move the area where the word line layer connects to the word line contact hole away from the source line layer. For example, the word line layer can be grown along the sidewall of the floating gate layer, and the position of the U-shaped structure in the cell will be filled by the word line layer polysilicon, which is then used to connect the word line contact hole, thus keeping the area of the word line contact hole away from the source line layer.
[0043] In other embodiments of the present invention, the present invention also provides a flash memory, wherein the storage unit includes the flash memory structure described above.
[0044] In summary, the present invention provides a flash memory structure and a flash memory, including multiple active array regions and end regions located between adjacent active array regions. In the horizontal direction, the source line layer in the end region has a U-shaped structure, and the opening of the U-shaped structure faces the word line contact hole. The U-shaped structure design keeps the area of the word line layer connected to the word line contact hole away from the source line layer, ensuring sufficient process window to prevent short circuit between the word line contact hole and the source line layer.
[0045] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A flash memory structure, characterized in that, It includes multiple active array regions and end regions located between adjacent active array regions, the end regions including: The semiconductor substrate includes adjacent source line floating gate regions and word line bit line regions; A floating grid structure, located in the source line floating grid region, includes a floating grid layer, a first sidewall located in the floating grid layer, a source line layer located between the floating grid layer and the first sidewall, and a source line contact hole located on the source line layer connecting the source line layer. The word line structure, located in the word line bit line area, includes a word line layer and word line contact holes on the word line layer that connect to the word line layer. The word line layer covers the sidewall of the floating grid layer and the first sidewall. In the horizontal direction, the source line layer has a U-shaped structure with the opening of the U-shaped structure facing the word line contact hole. The U-shaped structure design keeps the area of the word line layer connected to the word line contact hole away from the source line layer, ensuring sufficient process window to prevent short circuit between the word line contact hole and the source line layer. In the end area, the U-shaped structure includes a first U-shaped structure and a second U-shaped structure. In the horizontal direction, the first U-shaped structure is nested around the second U-shaped structure. The opening directions of the first U-shaped structure and the second U-shaped structure are opposite, and the opening directions of the first U-shaped structure and the second U-shaped structure are both facing the word line contact hole.
2. The flash memory structure according to claim 1, characterized in that, The floating gate structure also includes a source region located within the semiconductor substrate at the bottom of the source line layer.
3. The flash memory structure according to claim 1, characterized in that, The word line structure also includes a second sidewall located on the sidewall of the word line layer, a bit line located in the semiconductor substrate of the word line bit line region, and a drain region located in the semiconductor substrate at the bottom of the bit line and the bottom of the second sidewall.
4. The flash memory structure according to claim 1, characterized in that, A gate oxide layer is disposed between the semiconductor substrate and the floating gate layer.
5. The flash memory structure according to claim 1, characterized in that, In the horizontal direction, the first U-shaped structure and the second U-shaped structure do not contact each other.
6. The flash memory structure according to claim 5, characterized in that, The end area includes two sets of the U-shaped structures, and the two sets of the U-shaped structures are symmetrical about the center of the end area.
7. A flash memory, characterized in that, The flash memory includes the flash memory structure as described in any one of claims 1-6.