Display substrate and display device

Abstract

The display substrate includes a substrate and a plurality of pixel driving circuits disposed on the substrate. The display substrate further includes a first level signal input layer and an electrostatic discharge layer. At least part of the electrostatic discharge layer is located on a side of the pixel driving circuit facing the substrate. The electrostatic discharge layer is coupled with the first level signal input layer.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] With the continuous development of display technology, the application fields of display products are becoming more and more extensive, and people's requirements for the quality and yield of display products are also getting higher and higher.

[0003] During the actual manufacturing of display products, static electricity is generated during processes such as side bonding, die bonding, and film application and removal. In order to prevent excessive static electricity accumulation inside the display product from causing circuit damage, related technologies will set up an electrostatic discharge (ESD) structure, including circuit structure, inside the display product. Summary of the Invention

[0004] The purpose of this disclosure is to provide a display substrate and a display device.

[0005] To achieve the above objectives, this disclosure provides the following technical solution: A first aspect of this disclosure provides a display substrate, comprising: a substrate and a plurality of pixel driving circuits disposed on the substrate; the display substrate further comprising a first level signal input layer and an electrostatic discharge layer, wherein at least a portion of the electrostatic discharge layer is located on the side of the pixel driving circuits facing the substrate, and the electrostatic discharge layer is coupled to the first level signal input layer.

[0006] Optionally, the first level signal input layer includes a power layer, and the electrostatic discharge layer is coupled to the power layer.

[0007] Optionally, the first level signal input layer includes a cathode layer, and the electrostatic discharge layer is coupled to the cathode layer.

[0008] Optionally, the first level signal input layer includes a light-shielding layer, at least a portion of which is located between the pixel driving circuit layer and the substrate. The pixel driving circuit includes a plurality of transistors, each transistor including an active layer. The orthographic projection of the light-shielding layer onto the substrate at least partially overlaps with the orthographic projection of the active layer included in at least a portion of the transistors onto the substrate. The electrostatic discharge layer is coupled to the light-shielding layer.

[0009] Optionally, at least a portion of the electrostatic discharge layer is located between the light-shielding layer and the substrate, and the electrostatic discharge layer and the light-shielding layer are coupled through a via; or, the electrostatic discharge layer and the light-shielding layer are disposed in the same layer, and the electrostatic discharge layer and the light-shielding layer are directly overlapped.

[0010] Optionally, the overlap area between the orthographic projection of the electrostatic discharge layer on the substrate and the orthographic projection of the light-shielding layer on the substrate is less than or equal to 10% of the area of ​​the electrostatic discharge layer.

[0011] Optionally, the display substrate further includes a light-shielding layer, at least a portion of which is located between the pixel driving circuit layer and the substrate; the orthographic projection of the electrostatic discharge layer on the substrate does not overlap with the orthographic projection of the light-shielding layer on the substrate.

[0012] Optionally, the display substrate includes a power layer and a cathode layer; the power layer includes a plurality of power lines arranged along a first direction, each power line including at least a portion extending along a second direction, the first direction intersecting the second direction; the cathode layer includes a plurality of cathode lines arranged along the first direction, each cathode line including at least a portion extending along the second direction. The electrostatic discharge layer is formed in a grid shape, and the electrostatic discharge layer includes a plurality of first grid portions extending along a first direction and a plurality of second grid portions extending along a second direction; at least one of the orthographic projections of the second grid portions on the substrate overlaps at least partially with the orthographic projections of the power lines on the substrate; and / or, at least one of the orthographic projections of the second grid portions on the substrate overlaps at least partially with the orthographic projections of the cathode lines on the substrate.

[0013] Optionally, the display substrate includes a plurality of clock signal lines arranged along a second direction, the clock signal lines including at least a portion extending along the first direction, the pixel driving circuit being coupled to the corresponding clock signal line; the orthographic projection of the first grid portion on the substrate overlaps at least partially with the orthographic projection of the clock signal line on the substrate.

[0014] Optionally, the electrostatic discharge layer includes a plurality of first openings, the orthographic projection of the boundary of the first opening on the substrate includes a curved edge; the orthographic projection of the first opening on the substrate at least partially overlaps with the orthographic projection of the pixel driving circuit on the substrate.

[0015] Optionally, the electrostatic discharge layer includes a plurality of second openings, the orthographic projection of the boundary of the second opening on the substrate includes a straight edge; the orthographic projection of the second opening on the substrate does not overlap with the orthographic projection of the pixel driving circuit on the substrate.

[0016] Optionally, the orthographic projection of the boundary of the second opening onto the substrate includes at least one serrated portion.

[0017] Optionally, the pixel driving circuit includes a driving transistor and a storage capacitor, wherein a first plate of the storage capacitor is coupled to the gate of the driving transistor, and a second plate of the storage capacitor is coupled to the power supply layer. The orthographic projection of the second electrode plate on the substrate overlaps with the orthographic projection of the electrostatic discharge layer on the substrate, and the second electrode plate and the electrostatic discharge layer are coupled through a via in the overlapping area.

[0018] Optionally, the display substrate further includes a first conductive connection portion, which is coupled to the power line, and at least a portion of the first conductive connection portion is located on the side of the power line facing away from the substrate. The orthographic projection of the first conductive connection portion on the substrate has an overlapping area with the orthographic projection of the electrostatic discharge layer on the substrate, and the first conductive connection portion and the electrostatic discharge layer are coupled through a via in the overlapping area.

[0019] Optionally, the display substrate further includes a first conductive connection portion and a second conductive connection portion, at least a portion of the second conductive connection portion being located on the side of the first conductive connection portion facing away from the substrate; the first conductive connection portion is coupled to the second conductive connection portion and the power layer respectively; the orthographic projection of the second conductive connection portion on the substrate has an overlapping area with the orthographic projection of the electrostatic discharge layer on the substrate, and the second conductive connection portion and the electrostatic discharge layer are coupled through a via in the overlapping area.

[0020] Optionally, the display substrate further includes a third conductive connection portion, which is coupled to the cathode layer, and at least a portion of the third conductive connection portion is located on the side of the cathode layer facing away from the substrate. The orthographic projection of the third conductive connection portion on the substrate has an overlapping area with the orthographic projection of the electrostatic discharge layer on the substrate, and the third conductive connection portion and the electrostatic discharge layer are coupled through a via in the overlapping area.

[0021] Optionally, the display substrate further includes a first connecting electrode and a third conductive connection portion, at least a portion of the first connecting electrode being located on the side of the third conductive connection portion facing away from the substrate; the third conductive connection portion being coupled to the first connecting electrode and the cathode layer respectively; the orthographic projection of the first connecting electrode on the substrate and the orthographic projection of the electrostatic discharge layer on the substrate have an overlapping area, in which the first connecting electrode and the electrostatic discharge layer are coupled through a via.

[0022] Optionally, the orthographic projection of the cathode layer on the substrate has an overlapping area with the orthographic projection of the electrostatic discharge layer on the substrate, and the cathode layer and the electrostatic discharge layer are coupled through a via in the overlapping area.

[0023] Optionally, the electrostatic discharge layer is made of indium tin oxide or amorphous silicon.

[0024] Based on the above-described display substrate technical solution, a second aspect of this disclosure provides a display device including the above-described display substrate. Attached Figure Description

[0025] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings: Figure 1 A circuit schematic diagram of a pixel driving circuit provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of the layout of the electrostatic discharge layer provided in an embodiment of the present disclosure; Figure 3 The layout position relationship between the electrostatic discharge layer and the pixel driving circuit layout area provided in the embodiments of this disclosure; Figure 4 for Figure 3 Schematic diagram of the layout of the electrostatic discharge layer; Figure 5 for Figure 3 Schematic diagram of the layout of the middle shading layer; Figure 6 for Figure 3 Schematic diagram of the layout of the middle conductive layer; Figure 7 This is a first layout schematic diagram of the electrostatic discharge layer provided in an embodiment of the present disclosure; Figure 8 This is a schematic diagram of the second layout of the electrostatic discharge layer provided in an embodiment of the present disclosure; Figure 9 This is a schematic diagram of the third layout of the electrostatic discharge layer provided in an embodiment of this disclosure; Figure 10 This is a fourth layout schematic diagram of the electrostatic discharge layer provided in an embodiment of the present disclosure; Figure 11 This is a fifth layout schematic diagram of the electrostatic discharge layer provided in an embodiment of the present disclosure; Figure 12 This is a sixth layout schematic diagram of the electrostatic discharge layer provided in an embodiment of the present disclosure; Figure 13 This is a first layout schematic diagram of two adjacent pixel driving circuits in a display substrate provided in an embodiment of the present disclosure; Figure 14 for Figure 13 A schematic diagram of the layout with the conductive layer removed. Figure 15 for Figure 14 An enlarged schematic diagram of part A1 in the middle; Figure 16 for Figure 14 Schematic diagram of the layout of the electrostatic discharge layer and the light-shielding layer; Figure 17 This is a first cross-sectional schematic diagram of a display substrate provided in an embodiment of this disclosure; Figure 18 A process flow diagram illustrating the fabrication process of the structure in which the second electrode plate is coupled to the electrostatic discharge layer, as provided in the embodiments of this disclosure; Figure 19 This is a schematic diagram of a second layout of driving circuits for two adjacent pixels in a display substrate provided in an embodiment of the present disclosure. Figure 20 for Figure 19 Zhongyu Figure 14 An enlarged diagram of the same location as part A1; Figure 21 This is a second cross-sectional schematic diagram of a display substrate provided in an embodiment of this disclosure; Figure 22 This is a third cross-sectional schematic diagram of a display substrate provided in an embodiment of the present disclosure; Figure 23 This is a fourth cross-sectional schematic diagram of the display substrate provided in an embodiment of this disclosure; Figure 24 A process flow diagram illustrating the fabrication process of the structure in which the cathode layer and the electrostatic discharge layer are coupled, as provided in the embodiments of this disclosure. Figure 25 This is a schematic diagram of the first layout of driving circuits for three adjacent pixels in a display substrate provided in an embodiment of the present disclosure. Figure 26 for Figure 25 A schematic diagram of the layout of the electrostatic discharge layer in the middle; Figure 27 A fifth cross-sectional schematic diagram of the display substrate provided in an embodiment of this disclosure; Figure 28 A process flow diagram illustrating the fabrication process of the structure in which the second conductive connection portion is coupled to the electrostatic discharge layer, as provided in the embodiments of this disclosure. Figure 29 This is a schematic diagram of a second layout of driving circuits for three adjacent pixels in a display substrate provided in an embodiment of the present disclosure. Figure 30 This is a sixth cross-sectional schematic diagram of a display substrate provided in an embodiment of this disclosure. Detailed Implementation

[0026] To further illustrate the display substrate and display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0027] To prevent excessive static electricity buildup inside display products from damaging circuitry, related technologies incorporate ESD structures, including circuitry, within the display product. However, such ESD structures cannot completely prevent electrostatic damage caused by ESD during processes such as die bonding.

[0028] Please see Figures 2 to 6 , Figure 17 This disclosure provides a display substrate, including: a substrate 10 and a plurality of pixel driving circuits disposed on the substrate 10 (e.g., located at...). Figure 3 The layout area 40 shown includes a transistor structure TFT); the display substrate also includes a first level signal input layer (e.g., including a power supply layer VDD) and an electrostatic discharge layer 20, at least a portion of which is located on the side of the pixel driving circuit facing the substrate 10, and the electrostatic discharge layer 20 is coupled to the first level signal input layer.

[0029] It should be noted that, Figure 2 The diagram also illustrates the shift register unit GOA included in the display substrate, with the red light-emitting element R corresponding to the position of the coupled pixel driving circuit, the green light-emitting element G corresponding to the position of the coupled pixel driving circuit, and the blue light-emitting element B corresponding to the position of the coupled pixel driving circuit.

[0030] For example, the plurality of pixel driving circuits are arrayed on the substrate 10. The plurality of pixel driving circuits are divided into multiple rows of pixel driving circuits and multiple columns of pixel driving circuits. The multiple rows of pixel driving circuits are arranged along a first direction, and each row includes multiple pixel driving circuits arranged along a second direction. The multiple columns of pixel driving circuits are arranged along the second direction, and each column includes multiple pixel driving circuits arranged along the first direction. For example, the first direction intersects with the second direction. For instance, the first direction includes a vertical direction, and the second direction includes a horizontal direction.

[0031] For example, the display substrate further includes a cathode layer VSS, which can be used to transmit negative power signals, but is not limited to this. The display substrate also includes multiple light-emitting elements, which can be of various types. For example, each light-emitting element includes three light-emitting units, which can be selected as red, green, and blue light-emitting units. Each light-emitting element includes a first pin and three second pins. The first pin is coupled to the cathode layer VSS, and the three second pins correspond one-to-one with the three light-emitting units. The second pins are coupled to the corresponding pixel driving circuit and receive driving signals provided by the pixel driving circuit. Each light-emitting unit can independently control its light emission under the drive of the corresponding pixel driving circuit. For example, each light-emitting element includes one light-emitting unit, which can be a red, green, or blue light-emitting unit. This light-emitting element includes a first pin and a second pin. The first pin is coupled to the cathode layer VSS, and the second pin is coupled to the corresponding pixel driving circuit and receives driving signals provided by the pixel driving circuit. The light-emitting unit can independently control its light emission under the drive of the corresponding pixel driving circuit.

[0032] For example, the display substrate further includes a first level signal input layer, which is used to transmit a first level signal with a stable potential.

[0033] For example, the display substrate further includes an electrostatic discharge layer 20, which is made of a high-resistivity material such as indium tin oxide (ITO) or amorphous silicon, but is not limited thereto. At least a portion of the electrostatic discharge layer 20 is located on the side of the pixel driving circuit facing the substrate 10. The electrostatic discharge layer 20 can be directly coupled or indirectly coupled to the first level signal input layer.

[0034] For example, an ITO conductive film layer is deposited on a substrate 10, the film layer thickness is between 40nm and 100nm, and may include endpoint values. The ITO conductive film layer is then patterned to form the electrostatic discharge film layer.

[0035] As can be seen from the specific structure of the display substrate described above, the display substrate provided in this embodiment includes a first level signal input layer and an electrostatic discharge layer 20. At least a portion of the electrostatic discharge layer 20 is located on the side of the pixel driving circuit facing the substrate 10, and the electrostatic discharge layer 20 is coupled to the first level signal input layer. This arrangement allows the electrostatic discharge layer 20 to have the same stable first level signal as the first level signal input layer. The electrostatic discharge layer 20 can promptly discharge static electricity generated during the manufacturing process of the display substrate, effectively preventing ESD damage generated during side bonding, die bonding, and other stages, thus providing electrostatic protection and improving product yield.

[0036] Furthermore, in the display substrate provided in this embodiment, the electrostatic discharge layer 20 is disposed on the side of the pixel driving circuit facing the substrate 10. This arrangement helps to shorten the distance between the light-emitting element and the corresponding pixel driving circuit, effectively reducing the manufacturing difficulty of the display substrate. Simultaneously, the electrostatic discharge layer 20 can be fabricated during the array process used to manufacture the display substrate, eliminating the need for a separate process after the array process. Therefore, the display substrate provided in this embodiment has lower manufacturing difficulty and a simpler manufacturing process, which helps to reduce the manufacturing cost of the display substrate.

[0037] Furthermore, in the display substrate provided in this embodiment, the electrostatic discharge layer 20 is disposed on the side of the pixel driving circuit facing the substrate 10, so that the electrostatic discharge layer 20 can enhance the protection against laser. When the display substrate undergoes back-side laser etching, the electrostatic discharge layer 20 can reflect part of the laser energy, reducing damage to the transistors in the front-side pixel driving circuit. See also Figure 18 The last sub-figure in the diagram illustrates the reflection of the laser.

[0038] like Figures 13 to 18 As shown, in some embodiments, the first level signal input layer includes a power layer VDD, and the electrostatic discharge layer 20 is coupled to the power layer VDD.

[0039] It needs to be explained that, Figure 15 The cross-sectional view along the B1B2 direction is as follows Figure 17 As shown in section A1 of the document. Figure 18 The insulating layer 81 includes an insulating layer GI0, a first insulating layer GI1, a second insulating layer GI2, and an interlayer insulating layer ILD.

[0040] For example, the power layer VDD is used to transmit power signals, which have a stable potential.

[0041] like Figure 17As shown, exemplarily, the display substrate includes a light-shielding layer LS, a first insulating layer GI1, an active layer Poly, a second insulating layer GI2, a gate metal layer (e.g., including the top gate Tg of a transistor structure TFT), an interlayer insulating layer ILD, a source / drain metal layer, a first passivation layer PVX1, a first planarization layer PLN1, a conductive layer 50, a second passivation layer PVX2, and a second planarization layer PLN2, all sequentially stacked on the substrate 10 in a direction away from the substrate 10.

[0042] For example, the power layer VDD is disposed in the same layer and made of the same material as the gate metal layer, but it is not limited to this.

[0043] For example, the first insulating layer, the active layer, the second insulating layer, the gate metal layer, the interlayer insulating layer, and the source / drain metal layer are used to form the pixel driving circuit.

[0044] In the display substrate provided in the above embodiments, the first level signal input layer includes a power layer VDD, and the electrostatic discharge layer 20 is coupled to the power layer VDD. This allows the existing power layer VDD, used for transmitting stable signals, to be multiplexed as the first level signal transmission layer, avoiding the need for additional patterning processes. This simplifies the structure and manufacturing process of the display substrate and reduces its manufacturing cost. Furthermore, this configuration helps reduce the IRDrop of the power layer VDD, improving the display uniformity of the display substrate.

[0045] The above configuration enables the electrostatic discharge layer 20 to have the same stable power signal as the power layer VDD. The electrostatic discharge layer 20 can promptly discharge the static electricity generated during the display substrate manufacturing process, effectively preventing ESD damage generated during the side, bonding, and die bonding stages, thus providing electrostatic protection and improving product yield.

[0046] like Figures 19 to 24 As shown, in some embodiments, the first level signal input layer includes a cathode layer VSS, and the electrostatic discharge layer 20 is coupled to the cathode layer VSS.

[0047] For example, the cathode layer VSS is used to transmit a negative power signal, which has a stable potential.

[0048] For example, the cathode layer VSS is disposed in the same layer and made of the same material as the gate metal layer, but it is not limited to this.

[0049] In the display substrate provided in the above embodiments, the first level signal input layer includes a cathode layer VSS, and the electrostatic discharge layer 20 is coupled to the cathode layer VSS. This allows the existing cathode layer VSS, used for transmitting stable signals, to be multiplexed as the first level signal transmission layer, avoiding additional patterning processes. This simplifies the structure and manufacturing process of the display substrate and reduces its manufacturing cost. Furthermore, this configuration helps reduce the IRDrop of the cathode layer VSS, improving the display uniformity of the display substrate.

[0050] The above configuration enables the electrostatic discharge layer 20 to have the same stable signal as the cathode layer VSS. The electrostatic discharge layer 20 can promptly discharge the static electricity generated during the display substrate manufacturing process, effectively preventing ESD damage generated during the side, bonding, and die bonding stages, thus providing electrostatic protection and improving product yield.

[0051] In some embodiments, the first level signal input layer includes a light-shielding layer LS, at least a portion of which is located between the pixel driving circuit layer and the substrate 10. The pixel driving circuit includes a plurality of transistors, each transistor including an active layer. The orthographic projection of the light-shielding layer LS onto the substrate 10 at least partially overlaps with the orthographic projection of the active layer included in at least a portion of the transistors onto the substrate 10. The electrostatic discharge layer 20 is coupled to the light-shielding layer LS.

[0052] like Figure 17 As shown, the light-shielding layer LS can be used to form the bottom gate Bg of the transistor structure TFT, but is not limited to this.

[0053] For example, the light-shielding layer LS includes a plurality of first light-shielding patterns and a plurality of second light-shielding patterns. The first light-shielding patterns are coupled to the power layer VDD, so that the first light-shielding patterns have a stable power signal. The orthographic projection of the second light-shielding pattern on the substrate 10 overlaps with the orthographic projection of the channel portion in the active layer Poly on the substrate 10. By blocking the channel portion in the transistor through the second light-shielding pattern, it is beneficial to ensure the characteristic stability of the transistor.

[0054] For example, the second light-shielding pattern is reused as the bottom gate of the transistor it shields, the bottom gate of which is coupled to the top gate, but is not limited thereto.

[0055] For example, the electrostatic discharge layer 20 and the light-shielding layer LS are disposed on different layers, at least a portion of the electrostatic discharge layer 20 is located between the light-shielding layer LS and the substrate 10, and the electrostatic discharge layer 20 and the light-shielding layer LS are coupled through vias; or, the electrostatic discharge layer 20 and the light-shielding layer LS are disposed on the same layer, and the electrostatic discharge layer 20 and the light-shielding layer LS are directly overlapped.

[0056] For example, the overlap area between the orthographic projection of the electrostatic discharge layer 20 on the substrate 10 and the orthographic projection of the light-shielding layer LS on the substrate 10 is less than or equal to 20% of the area of ​​the electrostatic discharge layer 20.

[0057] For example, the overlap area between the orthographic projection of the electrostatic discharge layer 20 on the substrate 10 and the orthographic projection of the light-shielding layer LS on the substrate 10 is less than or equal to 10% of the area of ​​the electrostatic discharge layer 20.

[0058] For example, the overlap area between the orthographic projection of the electrostatic discharge layer 20 on the substrate 10 and the orthographic projection of the light-shielding layer LS on the substrate 10 is less than or equal to 5% of the area of ​​the electrostatic discharge layer 20.

[0059] In the display substrate provided in the above embodiments, the first level signal input layer includes a light-shielding layer LS, and the electrostatic discharge layer 20 is coupled to the light-shielding layer LS. This allows the existing light-shielding layer LS, used for transmitting stable signals, to be multiplexed as the first level signal transmission layer, avoiding the need for additional patterning processes. This simplifies the structure and manufacturing process of the display substrate and reduces its manufacturing cost. Furthermore, this configuration helps reduce the IRDrop of the power supply layer VDD, improving the display uniformity of the display substrate.

[0060] The above configuration enables the electrostatic discharge layer 20 to have the same stable signal as the light-shielding layer LS. The electrostatic discharge layer 20 can promptly discharge the static electricity generated during the display substrate manufacturing process, effectively preventing ESD damage generated during the side, bonding, and die bonding stages, thus providing electrostatic protection and improving product yield.

[0061] The above configuration ensures that the electrostatic discharge layer 20 is coupled to the light-shielding layer LS, while minimizing the overlap area between the orthographic projection of the electrostatic discharge layer 20 on the substrate 10 and the orthographic projection of the light-shielding layer LS on the substrate 10. This allows the electrostatic discharge layer 20 to largely avoid the light-shielding layer LS, preventing damage to the film formation of the light-shielding layer LS due to the presence of the electrostatic discharge layer 20.

[0062] like Figures 3 to 5As shown, in some embodiments, the display substrate further includes a light-shielding layer LS, at least a portion of which is located between the pixel driving circuit layer and the substrate 10; the orthographic projection of the electrostatic discharge layer 20 on the substrate 10 does not overlap with the orthographic projection of the light-shielding layer LS on the substrate 10.

[0063] The above configuration allows the electrostatic discharge layer 20 to completely avoid the light-shielding layer LS, preventing the presence of the electrostatic discharge layer 20 from damaging the film formation of the light-shielding layer LS.

[0064] like Figure 13 , Figure 14 and Figure 16 As shown, in some embodiments, the display substrate includes a power layer VDD and a cathode layer VSS; the power layer VDD includes a plurality of power lines arranged along a first direction. Figure 14 The diagram illustrates a power line, which includes at least a portion extending along a second direction, the first direction intersecting the second direction; the cathode layer VSS includes a plurality of cathode lines arranged along the first direction. Figure 14 The diagram illustrates a cathode line, which includes at least a portion extending in a second direction; The electrostatic discharge layer 20 is formed in a mesh shape, and the electrostatic discharge layer 20 includes a plurality of first mesh portions 201 extending along a first direction and a plurality of second mesh portions 202 extending along a second direction; at least one of the orthographic projections of the second mesh portion 202 on the substrate 10 at least partially overlaps with the orthographic projection of the power line on the substrate 10; and / or, at least one of the orthographic projections of the second mesh portion 202 on the substrate 10 at least partially overlaps with the orthographic projection of the cathode line on the substrate 10.

[0065] For example, the power lines and the cathode lines are arranged alternately along the first direction.

[0066] For example, the electrostatic discharge layer 20 includes a plurality of first grid portions 201 extending along a first direction and a plurality of second grid portions 202 extending along a second direction, wherein the first grid portions 201 and the second grid portions 202 are coupled together to define a grid structure.

[0067] For example, the length of the second grid portion 202 is less than the length of the first grid portion 201, but it is not limited to this.

[0068] The above-mentioned arrangement of at least one second mesh portion 202 on the substrate 10 having its orthogonal projection at least partially overlapping with the orthogonal projection of the power line on the substrate 10; and / or, at least one second mesh portion 202 having its orthogonal projection on the substrate 10 having its orthogonal projection at least partially overlapping with the orthogonal projection of the cathode line on the substrate 10; facilitates the coupling of the electrostatic discharge layer 20 with the power layer VDD or the cathode layer VSS, and reduces the difficulty of coupling between the electrostatic discharge layer 20 and the power layer VDD or the cathode layer VSS.

[0069] The electrostatic discharge layer 20 described above is formed in a grid shape, which helps to collect static electricity generated during the manufacturing process of the display substrate and discharge the static electricity in a timely manner, effectively preventing ESD damage generated during the side, bonding, and die bonding stages, thus playing a role in electrostatic protection and improving product yield.

[0070] like Figures 13 to 16 As shown, in some embodiments, the display substrate includes a plurality of clock signal lines HF arranged along a second direction, the clock signal lines HF including at least a portion extending along the first direction, and the pixel driving circuit is coupled to the corresponding clock signal line HF; the orthographic projection of the first grid portion 201 on the substrate 10 at least partially overlaps with the orthographic projection of the clock signal line HF on the substrate 10.

[0071] For example, the display substrate further includes a plurality of data lines Data arranged along a second direction, each data line Data including at least a portion extending along a first direction, and the pixel driving circuit is coupled to the corresponding data line Data.

[0072] For example, the orthographic projection of the first grid portion 201 on the substrate 10 at least partially overlaps with the orthographic projection of the clock signal line HF on the substrate 10; and / or, the orthographic projection of the first grid portion 201 on the substrate 10 at least partially overlaps with the orthographic projection of the data line Data on the substrate 10.

[0073] The above configuration helps to improve the stability of the clock signal line HF and the data line Data.

[0074] like Figure 8 and Figure 11 As shown, in some embodiments, the electrostatic discharge layer 20 includes a plurality of first openings K1, the orthographic projection of the boundary of the first opening K1 on the substrate 10 includes a curved edge; the orthographic projection of the first opening K1 on the substrate 10 at least partially overlaps with the orthographic projection of the pixel driving circuit on the substrate 10.

[0075] For example, the curved portion is formed into a circle or an ellipse, but is not limited thereto.

[0076] In the display substrate provided in the above embodiments, by setting the orthographic projection of the boundary of the first opening K1 on the substrate 10 to include a curved edge, the first opening K1 can be formed as an opening with a smooth boundary, similar to a circle or ellipse. Such an opening is not prone to accumulating static electricity. Thus, by setting the orthographic projection of the first opening K1 on the substrate 10 to at least partially overlap with the orthographic projection of the pixel driving circuit on the substrate 10, static electricity can be prevented from accumulating in the area where the pixel driving circuit is located, causing the pixel driving circuit to directly release static electricity to the static discharge layer 20, thereby affecting the working stability of the pixel driving circuit and ensuring the yield of the pixel driving circuit.

[0077] like Figure 4 , Figure 7 , Figure 9 , Figure 10 and Figure 12 As shown, in some embodiments, the electrostatic discharge layer 20 includes a plurality of second openings K2, the orthographic projection of the boundary of the second opening K2 on the substrate 10 includes a straight edge; the orthographic projection of the second opening K2 on the substrate 10 does not overlap with the orthographic projection of the pixel driving circuit on the substrate 10.

[0078] For example, the orthographic projection of the boundary of the second opening K2 onto the substrate 10 includes a triangle, a rectangle, or other polygons with straight sides, but is not limited to these.

[0079] like Figure 9 and Figure 12 As shown, by way of example, the orthographic projection of the boundary of the second opening K2 onto the substrate 10 includes at least one serrated portion 203, that is, the second opening K2 includes an opening with a serrated shape.

[0080] In the display substrate provided in the above embodiment, by setting the orthographic projection of the boundary of the second opening K2 on the substrate 10 to include a straight edge, the second opening K2 can be formed as an opening with a sharp corner. Such an opening is prone to accumulating static electricity. Thus, by setting the orthographic projection of the second opening K2 on the substrate 10 to not overlap with the orthographic projection of the pixel driving circuit on the substrate 10, and the orthographic projection of the second opening K2 on the substrate 10 to at least partially overlap with the orthographic projection of the peripheral area of ​​the pixel driving circuit, the second opening K2 can attract static electricity from the peripheral area and discharge the static electricity, thereby ensuring the yield of the display substrate.

[0081] like Figures 13 to 18 As shown, in some embodiments, the pixel driving circuit includes a driving transistor (i.e., a third transistor M3) and a storage capacitor Cs. The first plate Cs1 of the storage capacitor Cs is coupled to the gate of the driving transistor, and the second plate Cs2 of the storage capacitor Cs is coupled to the power supply layer VDD. The orthographic projection of the second electrode plate Cs2 on the substrate 10 overlaps with the orthographic projection of the electrostatic discharge layer 20 on the substrate 10. In this overlap area, the second electrode plate Cs2 and the electrostatic discharge layer 20 are coupled through a via Via3. Simultaneously, the second electrode plate Cs2 is coupled to the power layer VDD through a via Via1, and to the light-shielding layer LS through a via Via2.

[0082] For example, the second electrode plate Cs2 is disposed in the same layer and with the same material as the source and drain metal layers, but it is not limited to this.

[0083] like Figure 17 As shown, exemplarily, the second electrode Cs2 has a first light-shielding pattern (as marked LS) between it and the substrate 10. An electrostatic discharge layer 20 is provided between the first light-shielding pattern and the substrate 10. The orthographic projection of the second electrode Cs2 on the substrate 10 overlaps with the orthographic projection of the electrostatic discharge layer 20 on the substrate 10. At least a portion of the first light-shielding pattern is located in the overlap area. In the overlap area, the second electrode and the electrostatic discharge layer 20 are coupled through a via Via3, which is capable of penetrating the first light-shielding pattern located in the overlap area.

[0084] The above setup eliminates the need to change the layout of the pixel driving circuit and the light-shielding layer LS. Only the electrostatic discharge layer 20 needs to be fabricated at the designated location. This helps to reduce the overall layout difficulty of the display substrate, simplify the manufacturing process, and save manufacturing costs.

[0085] In some embodiments, the display substrate further includes a first conductive connection portion coupled to the power line, and at least a portion of the first conductive connection portion is located on the side of the power line facing away from the substrate 10. The orthographic projection of the first conductive connection portion on the substrate 10 overlaps with the orthographic projection of the electrostatic discharge layer 20 on the substrate 10, and the first conductive connection portion and the electrostatic discharge layer 20 are coupled through a via in the overlapping area.

[0086] For example, the first conductive connection portion is disposed in the same layer and made of the same material as the source and drain metal layers, but it is not limited to this. This arrangement helps to shorten the distance between the first conductive connection portion and the electrostatic discharge layer 20, reduces the difficulty of manufacturing the vias used to connect the first conductive connection portion and the electrostatic discharge layer 20, and is applicable to both large and small pixel driving circuits.

[0087] For example, the thickness of the electrostatic discharge layer 20 and the size of the formed openings can be determined based on the ESD prevention capability and the vertical relationship with the source and drain metal layers.

[0088] In the display substrate provided in the above embodiments, the coupling between the electrostatic discharge layer 20 and the power line is achieved by setting the first conductive connection portion, which enables more flexible layout of the electrostatic discharge layer 20 and reduces the layout difficulty of the display substrate.

[0089] like Figures 25 to 28 As shown, in some embodiments, the display substrate further includes a first conductive connection portion and a second conductive connection portion 62, at least a portion of the second conductive connection portion 62 being located on the side of the first conductive connection portion facing away from the substrate 10; the first conductive connection portion is coupled to the second conductive connection portion 62 and the power layer respectively; the orthographic projection of the second conductive connection portion 62 on the substrate 10 overlaps with the orthographic projection of the electrostatic discharge layer 20 on the substrate 10, and in the overlap area, the second conductive connection portion 62 and the electrostatic discharge layer 20 are coupled through a via Via 5.

[0090] like Figure 28 As shown, by way of example, the second conductive connection portion 62 is disposed in the same layer and with the same material as the conductive layer 50, but is not limited thereto. In this arrangement, the distance between the second conductive connection portion 62 and the electrostatic discharge layer 20 is relatively large, and the via Via5 used to connect the second conductive connection portion 62 and the electrostatic discharge layer 20 has a relatively deep depth. The via Via5 penetrates the insulating layer 83 (including insulating layer GI0, first insulating layer GI1, second insulating layer GI2 and interlayer insulating layer ILD), the first passivation layer PVX1 and the first planarization layer PLN1 between the electrostatic discharge layer 20 and the light-shielding layer LS.

[0091] In the display substrate provided in the above embodiments, the coupling between the electrostatic discharge layer 20 and the power line is achieved by providing the second conductive connection portion 62, which allows for more flexible layout of the electrostatic discharge layer 20 and reduces the layout difficulty of the display substrate.

[0092] like Figure 23As shown, in some embodiments, the display substrate further includes a third conductive connection portion 63, which is coupled to the cathode layer VSS, and at least a portion of the third conductive connection portion 63 is located on the side of the cathode layer VSS facing away from the substrate 10. The orthographic projection of the third conductive connection portion 63 on the substrate 10 overlaps with the orthographic projection of the electrostatic discharge layer 20 on the substrate 10. In this overlapping area, the third conductive connection portion 63 and the electrostatic discharge layer 20 are coupled through a via 7.

[0093] For example, the third conductive connection portion 63 is disposed in the same layer and made of the same material as the source / drain metal layer, but it is not limited to this. This arrangement helps to shorten the distance between the third conductive connection portion 63 and the electrostatic discharge layer 20, and reduces the difficulty of fabricating the vias used to connect the third conductive connection portion 63 and the electrostatic discharge layer 20. It is applicable to both large and small pixel driving circuits.

[0094] In the display substrate provided in the above embodiments, the coupling between the electrostatic discharge layer 20 and the cathode layer VSS is achieved by providing a third conductive connection portion 63, which enables more flexible layout of the electrostatic discharge layer 20 and reduces the layout difficulty of the display substrate.

[0095] like Figure 29 and Figure 30 As shown, in some embodiments, the display substrate further includes a first connecting electrode 71 and a third conductive connection portion 63. At least a portion of the first connecting electrode 71 is located on the side of the third conductive connection portion 63 facing away from the substrate 10. The third conductive connection portion 63 is coupled to the first connecting electrode 71 and the cathode layer VSS, respectively. The orthographic projection of the first connecting electrode 71 on the substrate 10 overlaps with the orthographic projection of the electrostatic discharge layer 20 on the substrate 10. In the overlap area, the first connecting electrode 71 and the electrostatic discharge layer 20 are coupled through a via Via 6.

[0096] For example, the first connecting electrode 71 is disposed in the same layer and made of the same material as the conductive layer 50, but it is not limited to this. In this arrangement, the distance between the first connecting electrode 71 and the electrostatic discharge layer 20 is relatively large, and the via for connecting the first connecting electrode 71 and the electrostatic discharge layer 20 has a relatively deep depth. The via penetrates the insulating layer between the electrostatic discharge layer 20 and the light-shielding layer LS, the first insulating layer, the second insulating layer, the interlayer insulating layer, the first passivation layer, and the first planarization layer.

[0097] In the display substrate provided in the above embodiments, the coupling between the electrostatic discharge layer 20 and the power line is achieved by setting the first connection electrode 71, which allows for more flexible layout of the electrostatic discharge layer 20 and reduces the layout difficulty of the display substrate.

[0098] like Figure 19 , Figure 22 and Figure 24 As shown, in some embodiments, the orthographic projection of the cathode layer VSS on the substrate 10 overlaps with the orthographic projection of the electrostatic discharge layer 20 on the substrate 10 (such as part A2), and the cathode layer VSS and the electrostatic discharge layer 20 are coupled through a via Via4 in the overlapping area.

[0099] It should be noted that, Figure 20 for Figure 19 Zhongyu Figure 14 An enlarged diagram of the same position in part A1. Figure 20 The conductive layer is not included. In this embodiment, Figure 20 The cross-sectional view along the B1B2 direction is as follows Figure 21 As shown in section A3, in this embodiment, the second electrode Cs2 is not coupled to the electrostatic discharge layer 20.

[0100] It is worth noting that, Figure 19 See the cross-sectional view of part A2 in the diagram. Figure 22 Part A2 of the document. Figure 24 The middle insulating layer 82 includes an insulating layer GI0, a first insulating layer GI1, and a second insulating layer GI2.

[0101] The above setup eliminates the need to change the layout of the pixel driving circuit and the light-shielding layer LS. Only the electrostatic discharge layer 20 needs to be fabricated at the designated location. This helps to reduce the overall layout difficulty of the display substrate, simplify the manufacturing process, and save manufacturing costs.

[0102] like Figure 19 and Figure 21 As shown, in some embodiments, the display substrate further includes a cathode layer VSS, a plurality of first connection electrodes 71, a plurality of second connection electrodes 72, and a plurality of light-emitting elements; the first connection electrodes 71 are coupled to the cathode layer VSS; the second connection electrodes 72 are coupled to corresponding pixel driving circuits; the light-emitting elements include a first pin and at least one second pin, the first pin being coupled to the corresponding first connection electrode 71, and the second pin being coupled to the corresponding second connection electrode 72.

[0103] For example, each light-emitting element includes three light-emitting units, which can be selected as a red light-emitting unit, a green light-emitting unit, and a blue light-emitting unit. The light-emitting element includes a first pin and three second pins. The first pin is coupled to the cathode layer VSS, and the three second pins correspond one-to-one with the three light-emitting units. Each second pin is coupled to a corresponding pixel driving circuit and receives a driving signal provided by the pixel driving circuit. Each light-emitting unit can independently control its light emission under the drive of its corresponding pixel driving circuit.

[0104] The specific structure of the pixel driving circuit varies, such as 7T1C (i.e., 7 transistors and 1 capacitor), 8T1C (i.e., 8 transistors and 1 capacitor), 11T3C (i.e., 11 transistors and 3 capacitors), etc. The following description uses 11T3C as an example of the pixel driving circuit.

[0105] like Figure 1 and Figure 14 As shown, the pixel driving circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a storage capacitor Cs, a first capacitor C1, and a second capacitor C2. Figure 1 The ITO shown in the diagram represents the coupling between the electrostatic discharge layer 20 and the power layer VDD.

[0106] The display substrate also includes: multiple light emission control signal lines EM, multiple scan lines Gate, multiple data lines Data, multiple first reset signal lines RST_A, multiple second reset signal lines RST_B, multiple initialization signal lines Vinit, and multiple clock signal lines HF.

[0107] The gate of the first transistor M1 is coupled to the corresponding first reset signal line RST_ARST_A, the first terminal of the first transistor M1 is coupled to the initialization signal line Vinit, and the second terminal of the first transistor M1 is coupled to the gate of the third transistor M3.

[0108] The gate of the second transistor M2 is coupled to the scan line Gate, the first terminal of the second transistor M2 is coupled to the second terminal of the third transistor M3, and the second terminal of the second transistor M2 is coupled to the gate of the third transistor M3.

[0109] The gate of the fourth transistor M4 is coupled to the scan line Gate, the first terminal of the fourth transistor M4 is coupled to the corresponding data line Data, and the second terminal of the fourth transistor M4 is coupled to the first terminal of the third transistor M3.

[0110] The gate of the fifth transistor M5 is coupled to the corresponding light-emitting control signal line EM, the first terminal of the fifth transistor M5 is coupled to the power supply line, and the second terminal of the fifth transistor M5 is coupled to the first terminal of the third transistor M3.

[0111] The first terminal of the sixth transistor M6 is coupled to the second terminal of the third transistor M3, and the second terminal of the sixth transistor M6 is coupled to the corresponding second pin.

[0112] The gate of the seventh transistor is coupled to the corresponding first reset signal line RST_A, the first terminal of the seventh transistor is coupled to the initialization signal line Vinit, and the second terminal of the seventh transistor is coupled to the corresponding second pin.

[0113] The gate of the eighth transistor M8 is coupled to the corresponding first reset signal line RST_A, the first terminal of the eighth transistor M8 is coupled to the corresponding data line Data, and the second terminal of the eighth transistor M8 is coupled to the gate of the ninth transistor M9.

[0114] The first terminal of the ninth transistor M9 is coupled to the corresponding light-emitting control signal line EM, and the second terminal of the ninth transistor M9 is coupled to the gate of the sixth transistor M6.

[0115] The gate of the tenth transistor M10 is coupled to the corresponding second reset signal line RST_B, the first terminal of the tenth transistor M10 is coupled to the corresponding data line Data, and the second terminal of the tenth transistor M10 is coupled to the gate of the eleventh transistor M11.

[0116] The first terminal of the eleventh transistor M11 is coupled to the corresponding clock signal line HF, and the second terminal of the eleventh transistor M11 is coupled to the gate of the sixth transistor M6.

[0117] The first capacitor C1 is coupled to the initialization signal line Vinit and the gate of the ninth transistor M9. The second capacitor C2 is coupled to the initialization signal line Vinit and the gate of the eleventh transistor M11.

[0118] For example, each transistor in the pixel driving circuit includes a low-temperature polycrystalline silicon transistor. The display substrate includes a low-temperature polycrystalline silicon display substrate and employs COG (chip-on-glass) packaging technology, but is not limited to this.

[0119] This disclosure also provides a display device, including the display substrate provided in the above embodiments.

[0120] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0121] The display substrate provided in the above embodiments includes a first-level signal input layer and an electrostatic discharge layer. At least a portion of the electrostatic discharge layer is located on the side of the pixel driving circuit facing the substrate, and the electrostatic discharge layer is coupled to the first-level signal input layer. This arrangement allows the electrostatic discharge layer to have the same stable first-level signal as the first-level signal input layer. The electrostatic discharge layer can promptly discharge static electricity generated during the manufacturing process of the display substrate, effectively preventing ESD damage generated during side bonding, die bonding, and other stages, thus providing electrostatic protection and improving product yield.

[0122] Furthermore, in the display substrate provided in the above embodiments, the electrostatic discharge layer is disposed on the side of the pixel driving circuit facing the substrate. This arrangement helps to shorten the distance between the light-emitting element and the corresponding pixel driving circuit, effectively reducing the manufacturing difficulty of the display substrate. Simultaneously, the electrostatic discharge layer can be fabricated during the array process used to manufacture the display substrate, eliminating the need for a separate process after the array process. Therefore, the display substrate provided in the above embodiments has lower manufacturing difficulty and a simpler manufacturing process, which helps to reduce the manufacturing cost of the display substrate.

[0123] In addition, in the display substrate provided in the above embodiments, the electrostatic discharge layer is disposed on the side of the pixel driving circuit facing the substrate, so that the electrostatic discharge layer can enhance the protection against laser and reduce the damage to the transistors in the front pixel driving circuit when the display substrate is subjected to back laser etching.

[0124] The display device provided in this disclosure, when including the above-described display substrate, also has the above-described beneficial effects, which will not be repeated here.

[0125] It should be noted that the signal line extending along the X direction means that the signal line includes a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along the X direction, and the length of the main part extending along the X direction is greater than the length of the secondary part extending in other directions.

[0126] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0127] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0128] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0129] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0130] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0131] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0132] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, comprising: A substrate and a plurality of pixel driving circuits disposed on the substrate; The display substrate further includes a first level signal input layer and an electrostatic discharge layer, at least a portion of which is located on the side of the pixel driving circuit facing the substrate, and the electrostatic discharge layer is coupled to the first level signal input layer. The electrostatic discharge layer includes a plurality of first grid portions extending along a first direction and a plurality of second grid portions extending along a second direction, wherein the first grid portions and the second grid portions are coupled together to define a grid structure; The electrostatic discharge layer includes a plurality of first openings, and the orthographic projection of the boundary of the first opening on the substrate includes a curved edge. The orthographic projection of the first opening on the substrate overlaps at least partially with the orthographic projection of the pixel driving circuit on the substrate.

2. The display substrate according to claim 1, wherein, The first level signal input layer includes a power layer, and the electrostatic discharge layer is coupled to the power layer.

3. The display substrate according to claim 1, wherein, The first level signal input layer includes a cathode layer, and the electrostatic discharge layer is coupled to the cathode layer.

4. The display substrate according to claim 1, wherein, The first level signal input layer includes a light-shielding layer, at least a portion of which is located between the pixel driving circuit layer and the substrate. The pixel driving circuit includes a plurality of transistors, each transistor including an active layer. The orthographic projection of the light-shielding layer on the substrate at least partially overlaps with the orthographic projection of the active layer included in at least a portion of the transistors on the substrate. The electrostatic discharge layer is coupled to the light-shielding layer.

5. The display substrate according to claim 4, wherein, At least a portion of the electrostatic discharge layer is located between the light-shielding layer and the substrate, and the electrostatic discharge layer and the light-shielding layer are coupled through vias; or, the electrostatic discharge layer and the light-shielding layer are disposed in the same layer, and the electrostatic discharge layer and the light-shielding layer are directly overlapped.

6. The display substrate according to claim 4, wherein, The overlap area between the orthographic projection of the electrostatic discharge layer on the substrate and the orthographic projection of the light-shielding layer on the substrate is less than or equal to 10% of the area of ​​the electrostatic discharge layer.

7. The display substrate according to claim 1, wherein, The display substrate further includes a light-shielding layer, at least a portion of which is located between the pixel driving circuit layer and the substrate; the orthographic projection of the electrostatic discharge layer on the substrate does not overlap with the orthographic projection of the light-shielding layer on the substrate.

8. The display substrate according to claim 1, wherein, The display substrate includes a power layer and a cathode layer; the power layer includes a plurality of power lines arranged along a first direction, each power line including at least a portion extending along a second direction, the first direction intersecting the second direction; the cathode layer includes a plurality of cathode lines arranged along the first direction, each cathode line including at least a portion extending along the second direction. At least one of the second mesh portions has its orthographic projection on the substrate at least partially overlapping with the orthographic projection of the power line on the substrate; And / or, at least one of the second grid portions, when projected onto the substrate, at least partially overlaps with the orthogonal projection of the cathode line onto the substrate.

9. The display substrate according to claim 8, wherein, The display substrate includes a plurality of clock signal lines arranged along a second direction, each clock signal line including at least a portion extending along a first direction, and the pixel driving circuit is coupled to the corresponding clock signal line; the orthographic projection of the first grid portion on the substrate overlaps at least partially with the orthographic projection of the clock signal line on the substrate.

10. The display substrate according to any one of claims 1 to 9, wherein, The electrostatic discharge layer includes a plurality of second openings, the orthographic projection of the boundary of the second opening on the substrate includes a straight edge; the orthographic projection of the second opening on the substrate does not overlap with the orthographic projection of the pixel driving circuit on the substrate.

11. The display substrate according to claim 10, wherein, The orthographic projection of the boundary of the second opening onto the substrate includes at least one serrated portion.

12. The display substrate according to claim 2, wherein, The pixel driving circuit includes a driving transistor and a storage capacitor. The first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the power supply layer. The orthographic projection of the second electrode plate on the substrate overlaps with the orthographic projection of the electrostatic discharge layer on the substrate, and the second electrode plate and the electrostatic discharge layer are coupled through a via in the overlapping area.

13. The display substrate according to claim 2, wherein, The display substrate further includes a first conductive connection portion, which is coupled to a power line included in the power layer, and at least a portion of the first conductive connection portion is located on the side of the power line facing away from the substrate. The orthographic projection of the first conductive connection portion on the substrate has an overlapping area with the orthographic projection of the electrostatic discharge layer on the substrate, and the first conductive connection portion and the electrostatic discharge layer are coupled through a via in the overlapping area.

14. The display substrate according to claim 2, wherein, The display substrate further includes a first conductive connection portion and a second conductive connection portion, at least a portion of the second conductive connection portion being located on the side of the first conductive connection portion facing away from the substrate; the first conductive connection portion is coupled to the second conductive connection portion and the power layer respectively; the orthographic projection of the second conductive connection portion on the substrate has an overlapping area with the orthographic projection of the electrostatic discharge layer on the substrate, and the second conductive connection portion and the electrostatic discharge layer are coupled through a via in the overlapping area.

15. The display substrate according to claim 3, wherein, The display substrate further includes a third conductive connection portion, which is coupled to the cathode layer, and at least a portion of the third conductive connection portion is located on the side of the cathode layer facing away from the substrate. The orthographic projection of the third conductive connection portion on the substrate has an overlapping area with the orthographic projection of the electrostatic discharge layer on the substrate, and the third conductive connection portion and the electrostatic discharge layer are coupled through a via in the overlapping area.

16. The display substrate according to claim 3, wherein, The display substrate further includes a first connecting electrode and a third conductive connection portion. At least a portion of the first connecting electrode is located on the side of the third conductive connection portion facing away from the substrate. The third conductive connection portion is coupled to the first connecting electrode and the cathode layer respectively. The orthographic projection of the first connecting electrode on the substrate overlaps with the orthographic projection of the electrostatic discharge layer on the substrate. In the overlap area, the first connecting electrode and the electrostatic discharge layer are coupled through a via.

17. The display substrate according to claim 3, wherein, The orthographic projection of the cathode layer on the substrate has an overlapping area with the orthographic projection of the electrostatic discharge layer on the substrate, and the cathode layer and the electrostatic discharge layer are coupled through a via in the overlapping area.

18. The display substrate according to claim 1, wherein, The electrostatic discharge layer is made of indium tin oxide or amorphous silicon.

19. A display device comprising a display substrate as claimed in any one of claims 1 to 18.

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