Radar waveform generation method and system suitable for multiple systems

Abstract

The invention discloses a radar waveform generation system and method suitable for multiple systems, and the system comprises a CPU and an FPGA board card, and the FPGA board card is integrated with an FPGA chip and a DAC chip. Wherein the CPU generates a radar signal protocol message based on a parameter instruction sent by an upper computer, and transmits the radar signal protocol message to the FPGA chip; the FPGA chip analyzes the radar signal protocol message and caches the obtained signal waveform data and parameter instruction information respectively; generating a time sequence control signal based on the parameter instruction information, further responding to the time sequence control signal, and outputting signal waveform data; and the DAC chip performs digital-to-analog conversion on the digital waveform data according to a specified working mode and frequency, and outputs an analog signal. The PCIE high-speed interface is used as a communication bridge of the CPU and the FPGA, high-speed data transmission is ensured, the real-time performance of the system is improved, the multi-frequency band and parameterization of multi-system radar transmitting signals can be met, and the real-time switching function is achieved.

Description

Technical Field

[0001] The invention belongs to the field of radar technology, and in particular relates to a radar waveform generation method and system applicable to multiple systems. Background Art

[0002] At present, there are usually two methods for traditional radar waveform generation: one is to store the waveform data in the ROM IP core in advance, and output the data to the DAC chip in a timed manner through FPGA logic control, and then the DAC converts the digital signal into an analog signal for transmission; the other method is to generate waveform data through the DDS IP core combined with logic design, and the subsequent process is similar to the former. The limitation of the former is that the ROM data cannot be modified and the real-time switching or parameterized design of the waveform cannot be achieved. If multiple waveforms are required, a large amount of ROM resources will be occupied, increasing hardware overhead and lacking flexibility. The latter can achieve dynamic waveform generation through the DDS IP core, but the high-frequency signal output is limited by the FPGA system clock, and usually requires multiple DDS cores to work together, resulting in a significant increase in hardware resource consumption and design complexity. Especially in the high-frequency band, it may also face problems such as heavy computing burden and high response delay.

[0003] On the other hand, traditional radar systems usually only support a single waveform and a fixed working system, and lack the ability to switch and adjust multiple frequency bands and multiple modulation modes in real time. This makes the system inflexible when dealing with complex and changeable radar tasks, and unable to quickly adapt to different operational requirements. For example, many radar applications need to be able to work in different frequency bands and support waveform switching of multiple modulation modes, but traditional radar systems often cannot meet this demand. In addition, in traditional designs, hardware resources are wasted on allocating fixed storage and processing power for each waveform, resulting in low system efficiency. Especially when dealing with rapidly changing operating environments and tasks, traditional systems cannot provide sufficient flexibility and real-time response, affecting overall performance. With the advancement of radar technology and changes in application requirements, the deficiencies of traditional radar systems in multi-tasking, waveform switching, and dynamic adaptability have become key factors restricting their development. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a radar waveform generation method and system applicable to multiple systems. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] In a first aspect, the present invention provides a radar waveform generation system applicable to multiple systems, comprising: a central processing unit (CPU) and a field programmable gate array (FPGA) board, wherein the FPGA board integrates an FPGA chip and a digital-to-analog conversion (DAC) chip; wherein:

[0006] The CPU is used to generate a radar signal protocol message based on the parameter instruction sent by the host computer, and transmit the radar signal protocol message to the FPGA chip;

[0007] The FPGA chip is used to parse the radar signal protocol message and cache the obtained signal waveform data and parameter instruction information respectively; generate a timing control signal based on the parameter instruction information, and further respond to the timing control signal to output the signal waveform data;

[0008] The DAC chip is used to perform digital-to-analog conversion on the digital waveform data and output analog signals under the drive of the FPGA chip according to the specified working mode and frequency.

[0009] In one embodiment of the present invention, the CPU includes a signal generating module, a packaging module and a PCIE transmitting interface driving module, and the FPGA chip includes a PCIE receiving interface driving module; wherein,

[0010] The signal generating module is used to receive the parameter instruction sent by the host computer, parse the parameter instruction to obtain parameter instruction information, and generate signal waveform data based on the parameter instruction information;

[0011] The encapsulation module is used to package the signal waveform data and the parameter instruction information to obtain a radar signal protocol message;

[0012] The PCIE sending interface driver module is used to transmit the radar signal protocol message to the PCIE receiving interface driver module.

[0013] In one embodiment of the present invention, the FPGA chip further includes: a parsing and caching module, the parsing and caching module includes a parsing unit and a first-level cache unit, the first-level cache unit includes an instruction cache table RAM and a signal waveform data cache RAM; wherein,

[0014] The parsing unit is used to parse the radar signal protocol message, and cache the obtained parameter instruction information into the instruction cache table RAM, and cache the obtained signal waveform data into the signal waveform data cache RAM.

[0015] In one embodiment of the present invention, the FPGA chip further includes a timing control module, the parsing unit further includes a secondary cache unit, and the secondary cache unit includes a parameter instruction information secondary cache unit and a signal waveform data secondary cache unit;

[0016] The instruction cache table RAM is further used to cache the required parameter instruction information into the parameter instruction information secondary cache unit when the parameter instruction information secondary cache unit is empty;

[0017] The signal waveform data cache RAM is further used to cache the required signal waveform data into the signal waveform data secondary cache unit when the signal waveform data secondary cache unit is empty;

[0018] The timing control module is used to read the required parameter instruction information from the parameter instruction information secondary cache unit, and generate a timing control signal and a wave position parameter update signal based on the required parameter instruction information;

[0019] The parameter instruction information secondary cache unit is used to read the required parameter instruction information from the instruction cache table RAM in response to the wave position parameter update signal;

[0020] The signal waveform data secondary cache unit is used to read the required signal waveform data from the signal waveform data cache RAM in response to the waveform parameter update signal.

[0021] In one embodiment of the present invention, the FPGA chip further includes a downsampling rate module;

[0022] The signal waveform data secondary cache unit is also used to output the required signal waveform data to the downsampling rate module in response to the timing control signal.

[0023] In one embodiment of the present invention, the downsampling rate module is used to reduce the data rate of the required signal waveform data to obtain digital waveform data.

[0024] In a second aspect, the present invention further provides a radar waveform generation method applicable to multiple systems, which is applied to the radar waveform generation system described in the first aspect, and the method comprises:

[0025] Generate radar signal protocol message based on parameter instructions sent by the host computer;

[0026] Parsing the radar signal protocol message, and performing first-level caching on the obtained signal waveform data and parameter instruction information respectively;

[0027] The signal waveform data and parameter instruction information required in the first-level cache are cached in the second-level cache respectively;

[0028] Generate a timing control signal according to the parameter instruction information required in the secondary cache, output the required signal waveform data based on the timing control signal, and reduce the data rate of the required signal waveform data;

[0029] According to the specified working mode and frequency, the digital waveform data is converted into digital-to-analog form to output an analog signal.

[0030] In one embodiment of the present invention, the steps of parsing the radar signal protocol message and performing primary caching on the obtained signal waveform data and parameter instruction information respectively include:

[0031] Parsing the radar signal protocol message to obtain signal waveform data and parameter instruction information;

[0032] The parameter instruction information is cached in the instruction cache table RAM, and the obtained signal waveform data is cached in the signal waveform data cache RAM.

[0033] In one embodiment of the present invention, after the step of performing the second-level caching on the required signal waveform data and the required parameter instruction information in the first-level cache respectively, the method further includes:

[0034] Generate a wave position parameter update signal according to the parameter instruction information required in the secondary cache;

[0035] Based on the wave position parameter update signal, the required signal waveform data and the required parameter instruction information are read from the first-level cache again, and the second-level cache is performed.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] (1) With the continuous update and iteration of radar systems, the demand for parameterization and diversification of radar waveforms is increasing. The traditional radar waveform generation method relies on read-only memory (ROM) and digital direct synthesis (DDS) core, which takes up a lot of space in waveform storage and is difficult to directly output high-frequency band signals. In addition, the design complexity of the existing radar waveform generation system is also relatively high, which leads to a longer development cycle and limited system flexibility. In order to overcome the above problems, the radar waveform generation system applicable to multiple systems provided by the present invention generates waveforms in a collaborative manner between CPU and FPGA: first, the CPU is used to generate multi-band, parameterized signal waveform data. This process not only improves the flexibility of waveform generation, but also can quickly adapt to different application requirements; then the signal waveform data is transmitted to the FPGA board at high speed through a high-speed interface; on the FPGA side, the data rate is reduced through logic design, which can not only effectively reduce the burden of data transmission, but also optimize the overall performance of the system. At the same time, the FPGA chip is also responsible for real-time regulation of the data recovery rate of the DAC chip to ensure the accuracy and stability of the waveform output.

[0038] Therefore, through this collaborative working mode of CPU and FPGA, the system will be able to achieve efficient generation of multi-band arbitrary waveforms, which not only solves the storage and design complexity problems of traditional radar waveform generation methods, but also greatly improves the flexibility and real-time performance of the system, and meets the diverse needs of modern radar technology for waveform generation.

[0039] (2) In modern radar systems, due to the significant differences in information between radar waveforms of different systems and the diversity of radar working modes, how to effectively manage and schedule resources has become a key issue. In order to solve the above problems, the present invention realizes the generation of parameterized waveforms on the CPU side. The CPU generates the required instruction parameter information according to the custom protocol, which can quickly adapt to different radar working modes. In this way, the CPU can efficiently handle complex waveform generation tasks and provide necessary data support for subsequent signal processing; at the same time, on the FPGA side, it focuses on the control and timing generation of the working mode. The FPGA adjusts its working mode in real time by receiving waveform parameters from the CPU to adapt to different radar task requirements. In addition, the FPGA is also responsible for precise timing control to ensure that the generation and output of the waveform meet the predetermined time requirements. This timing control not only improves the stability of the waveform, but also enhances the overall performance of the system.

[0040] Therefore, the radar waveform generation system provided by the present invention is convenient for unified scheduling of resources, can flexibly adapt to the generation requirements of different types of radar waveforms, optimizes the communication and data exchange between the CPU and FPGA board, ensures efficient collaboration between various modules, and thus improves the response speed and reliability of the overall system.

[0041] (3) In order to meet the real-time requirements, the radar waveform generation system provided by the present invention adopts a collaborative working architecture of CPU+FPGA+PCIE. In this architecture, the CPU processor is responsible for receiving and parsing radar parameter information at the wave level. Specifically, the CPU first extracts the necessary radar parameters from the upper-level instructions or echo signals. These parameters include key information such as the current working mode, frequency band selection and modulation waveform; after receiving the radar parameter information, the CPU quickly parses and processes it. This process ensures that the system can respond to external instructions or signal changes in a timely manner and adjust the working state of the radar. The efficient processing capability of the CPU enables the system to complete complex calculations and decisions in a short time and provide accurate instructions for the FPGA; the FPGA end is responsible for executing real-time working mode switching, timing control and waveform generation. By receiving instructions from the CPU, the FPGA adjusts its working mode in real time to adapt to different radar task requirements.

[0042] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a structural schematic diagram of a radar waveform generation system applicable to multiple systems provided by an embodiment of the present invention;

[0044] Figure 2 is a schematic diagram of parameter instruction information provided by an embodiment of the present invention;

[0045] Figure 3 is a schematic diagram of the structure of the parsing and caching module provided in an embodiment of the present invention;

[0046] Figure 4 is a flow chart of a radar waveform generation method applicable to multiple systems provided by an embodiment of the present invention;

[0047] Figure 5 It is a signal parameter update timing diagram provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0049] Figure 1 FIG. 1 is a schematic diagram of a structure of a radar waveform generation system applicable to multiple systems provided by an embodiment of the present invention. Figure 1 The embodiment of the present invention provides a radar waveform generation system applicable to multiple systems, including: a central processing unit CPU and a field programmable gate array FPGA board, the FPGA board integrates an FPGA chip and a digital-to-analog conversion DAC chip; wherein,

[0050] The CPU is used to generate a radar signal protocol message based on the parameter instruction sent by the host computer, and transmit the radar signal protocol message to the FPGA chip;

[0051] The FPGA chip is used to parse the radar signal protocol message and cache the obtained signal waveform data and parameter instruction information respectively; generate a timing control signal based on the parameter instruction information, and further respond to the timing control signal to output the signal waveform data;

[0052] The DAC chip is used to perform digital-to-analog conversion on digital waveform data and output analog signals under the drive of the FPGA chip according to the specified working mode and frequency.

[0053] The radar waveform generation system applicable to multiple systems includes a central processing unit (CPU) and an FPGA board, which are connected through a PCIE (peripheral component interconnect express) high-speed interface communication. The CPU performs real-time pulse group-level modulation on radar transmission signals of different systems, and performs parameterized design of pulse width, frequency, bandwidth, pulse repetition period and pulse number on signal information, such as Figure 2 As shown, arbitrary signal waveform data is generated and sent to the FPGA board after packaging.

[0054] Specifically, the CPU includes a signal generating module, a packaging module and a PCIE transmitting interface driving module, and the FPGA chip includes a PCIE receiving interface driving module; wherein,

[0055] The signal generating module is used to receive the parameter instruction sent by the host computer, parse the parameter instruction to obtain the parameter instruction information, and generate the signal waveform data based on the parameter instruction information;

[0056] The encapsulation module is used to package the signal waveform data and the parameter instruction information to obtain the radar signal protocol message;

[0057] The PCIE sending interface driver module is used to transmit the radar signal protocol message to the PCIE receiving interface driver module.

[0058] The radar waveform generation system suitable for multiple systems uses the PCIE high-speed interface as the hardware basis for communication between the CPU and the FPGA board. It adopts the PCIE3.0*8 protocol standard, which can transmit the signal waveform data information of the next instruction to the FPGA chip at high speed for caching, and can meet the waveform switching of the data waveform at the pulse group level. Therefore, by effectively combining the CPU and the FPGA board, the real-time requirements of the system are met. The collaborative work of the two not only improves the response speed and flexibility of the system, but also ensures the stability of the system in a dynamic environment, providing reliable support for practical applications.

[0059] In this embodiment, the main function of the FPGA chip is to receive the radar signal protocol message from the CPU end, parse the radar signal protocol message to generate a corresponding timing control signal and further process the signal waveform data.

[0060] Figure 3 Schematic diagram of the structure of the parsing and caching module provided by the embodiment of the present invention. Figure 1 , Figure 3 As shown, the FPGA chip also includes: a parsing and caching module, the parsing and caching module includes a parsing unit and a first-level cache unit, the parsing unit includes an unpacking state machine, and the first-level cache unit includes an instruction cache table RAM and a signal waveform data cache RAM; wherein,

[0061] The parsing unit is used to parse the radar signal protocol message, and cache the obtained parameter instruction information into the instruction cache table RAM, and cache the obtained signal waveform data into the signal waveform data cache RAM.

[0062] The FPGA chip also includes a timing control module, and the parsing unit also includes a secondary cache unit, and the secondary cache unit includes a parameter instruction information secondary cache unit and a signal waveform data secondary cache unit;

[0063] The instruction cache table RAM is also used to cache the required parameter instruction information into the parameter instruction information secondary cache unit when the parameter instruction information secondary cache unit is empty;

[0064] The signal waveform data cache RAM is also used to cache the required signal waveform data into the signal waveform data secondary cache unit when the signal waveform data secondary cache unit is empty;

[0065] A timing control module, used for reading the required parameter instruction information from the parameter instruction information secondary cache unit, and generating a timing control signal and a wave position parameter update signal based on the required parameter instruction information;

[0066] A parameter instruction information secondary cache unit, for reading required parameter instruction information from the instruction cache table RAM in response to a wave position parameter update signal;

[0067] The signal waveform data secondary cache unit is used to read the required signal waveform data from the signal waveform data cache RAM in response to the wave position parameter update signal.

[0068] In this embodiment, the wave position parameter update signal is used to specify the update timing of mode-related instructions and parameters. Modern radar systems often have multiple operating modes, and different operating modes have different system parameters. Instruction parameter information may be sent through the host computer terminal at any time, such as frequency switching and mode switching instructions. In order not to affect the working timing and working parameters of the current and subsequent wave positions, the parsing and caching module in the FPGA board cannot execute the instruction parameter information immediately after receiving it, but needs to cache it, and wait until the current wave position is about to end before updating the instruction to the instruction register group, so that the instruction takes effect in the next wave position.

[0069] The timing control module reads the instruction parameter information in the register of the current waveform and generates the corresponding timing control signal CPI (coherent processing interval) and PRT (pulse repetition period). The timing control signal will be output to the relevant pins of the board through the serial port driver module, and the timing control signal will be input to the analysis and cache module as an enable signal for the signal waveform data to start sending.

[0070] Furthermore, the FPGA chip also includes a downsampling rate module. The signal waveform data secondary cache unit is also used to respond to the timing control signal and output the required signal waveform data to the downsampling rate module, and the downsampling rate module is used to reduce the data rate of the required signal waveform data to obtain digital waveform data.

[0071] It should be understood that due to the limitation of the operating frequency of the FPGA chip itself, it is impossible to generate a high-frequency signal clock. Therefore, this embodiment introduces a downsampling rate module to continue to reduce the data rate of the FPGA chip to the DAC chip by converting low-speed parallel to high-speed serial. When the DAC chip samples at a sampling rate of 4.8GHz, the downsampling rate module transmits the signal waveform data to the DAC chip at a rate as low as 150MHz at one end of the FPGA chip. Optionally, the specific implementation of the downsampling rate module is: design a group of 32 RAM (Random Access Memory) cores to provide 32 data link buffers; also includes a corresponding parallel-to-serial logic unit for converting low-speed parallel to high-speed serial. For example, the Serdes primitive is used to implement the 8:1 parallel-to-serial conversion function, and the DDR (Double Data Rate SDRAM) transmission mode is adopted to finally meet the data rate requirements inside the FPGA board.

[0072] In addition, the FPGA board also includes a clock chip, and the FPGA board also includes a clock chip configuration and driving module for driving the clock chip to generate a high-frequency sampling clock signal, and the sampling clock frequency is 4.8GHz.

[0073] In order to meet the requirements of various radar frequency bands, the system also integrates a DAC chip, whose maximum sampling frequency can reach 6.4GHz. By using a high-order working mode, the DAC chip can output analog signals up to 20G or more. However, the DAC chip requires a reference clock for input signal sampling, which is a clock frequency that is difficult to provide by a general FPGA chip or crystal oscillator. Therefore, in this embodiment, the clock chip integrated in the FPGA board is a broadband frequency synthesizer.

[0074] Optionally, the FPGA chip also includes a DAC interface module, which has two functions. One function is to configure relevant registers in the DAC chip through the SPI protocol so that the DAC chip works in a specified working mode. The other function is to drive multi-channel parallel signal waveform data to be transmitted to the digital-to-analog conversion module of the DAC chip through the LVDS interface.

[0075] It can be seen that the radar waveform generation system applicable to multiple systems provided by the present invention is based on the CPU+FPGA+PCIE high-speed interface architecture as the hardware basis, and realizes the flexible generation of transmission frequency band signals of various radar systems. Through parameterized design, users can quickly adjust the waveform characteristics according to specific application requirements to ensure that the system can adapt to the transmission requirements of radars of various systems. The system also has the ability to switch and adjust the output of different frequency bands and modulated signal waveforms in real time, which not only improves the flexibility and intelligence level of the radar system, but also significantly improves its work efficiency in complex environments. The radar waveform generation system will enable multi-system radars to better adapt to various application scenarios, improve overall performance, and ensure that superior detection and response capabilities are always maintained in a changing combat environment.

[0076] Figure 4 is a flow chart of a radar waveform generation method applicable to multiple systems provided by an embodiment of the present invention. Figure 4 The embodiment of the present invention further provides a radar waveform generation method applicable to multiple systems, which is applied to the above radar waveform generation system. The method includes:

[0077] S1. Generate radar signal protocol message based on parameter instructions sent by the host computer.

[0078] Specifically, the parameter instruction sent by the host computer is received, the parameter instruction is parsed to obtain the parameter instruction information, and then the signal waveform data is generated based on the parameter instruction information, and then the signal waveform data and the parameter instruction information are packaged and encapsulated to obtain the radar signal protocol message.

[0079] S2. parse the radar signal protocol message, and cache the obtained signal waveform data and parameter instruction information at the first level respectively.

[0080] Optionally, in step S2, the step of parsing the radar signal protocol message and performing a first-level cache on the obtained signal waveform data and parameter instruction information respectively includes:

[0081] Parse radar signal protocol messages to obtain signal waveform data and parameter instruction information;

[0082] The parameter instruction information is cached in the instruction cache table RAM, and the obtained signal waveform data is cached in the signal waveform data cache RAM.

[0083] S3. Perform secondary caching on the required signal waveform data and required parameter instruction information in the primary cache respectively.

[0084] Optionally, after the step of performing the second-level caching on the required signal waveform data and the required parameter instruction information in the first-level cache respectively, the method further includes:

[0085] Generate a wave position parameter update signal according to the parameter instruction information required in the secondary cache;

[0086] Based on the wave position parameter update signal, the required signal waveform data and the required parameter instruction information are read from the first-level cache again, and the second-level cache is performed.

[0087] S4. Generate a timing control signal according to the parameter instruction information required in the secondary cache, output the required signal waveform data based on the timing control signal, and reduce the data rate of the required signal waveform data.

[0088] Figure 5 is a timing diagram of signal parameter update provided by an embodiment of the present invention. Figure 5 In this embodiment, the required signal waveform data and the required parameter instruction information are read with the wave position parameter update signal as a sign. Before each wave position parameter update is generated, the signal will be pulled high, which will enable the read-write control state machine to update the current signal waveform data and instruction register group. Then, when the next wave position parameter update signal is generated, it works according to the updated instruction information and also outputs the updated signal waveform data.

[0089] S5. According to the specified working mode and frequency, the digital waveform data is converted into digital-to-analog form and an analog signal is output.

[0090] It can be seen from the above embodiments that the beneficial effects of the present invention are:

[0091] (1) With the continuous update and iteration of radar systems, the demand for parameterization and diversification of radar waveforms is increasing. The traditional radar waveform generation method relies on read-only memory (ROM) and digital direct synthesis (DDS) core, which takes up a lot of space in waveform storage and is difficult to directly output high-frequency band signals. In addition, the design complexity of the existing radar waveform generation system is also relatively high, which leads to a longer development cycle and limited system flexibility. In order to overcome the above problems, the radar waveform generation system applicable to multiple systems provided by the present invention generates waveforms in a collaborative manner between CPU and FPGA: first, the CPU is used to generate multi-band, parameterized signal waveform data. This process not only improves the flexibility of waveform generation, but also can quickly adapt to different application requirements; then the signal waveform data is transmitted to the FPGA board at high speed through a high-speed interface; on the FPGA side, the data rate is reduced through logic design, which can not only effectively reduce the burden of data transmission, but also optimize the overall performance of the system. At the same time, the FPGA chip is also responsible for real-time regulation of the data recovery rate of the DAC chip to ensure the accuracy and stability of the waveform output.

[0092] Therefore, through this collaborative working mode of CPU and FPGA, the system will be able to achieve efficient generation of multi-band arbitrary waveforms, which not only solves the storage and design complexity problems of traditional radar waveform generation methods, but also greatly improves the flexibility and real-time performance of the system, and meets the diverse needs of modern radar technology for waveform generation.

[0093] (2) In modern radar systems, due to the significant differences in information between radar waveforms of different systems and the diversity of radar working modes, how to effectively manage and schedule resources has become a key issue. In order to solve the above problems, the present invention realizes the generation of parameterized waveforms on the CPU side. The CPU generates the required instruction parameter information according to the custom protocol, which can quickly adapt to different radar working modes. In this way, the CPU can efficiently handle complex waveform generation tasks and provide necessary data support for subsequent signal processing; at the same time, on the FPGA side, it focuses on the control and timing generation of the working mode. The FPGA adjusts its working mode in real time by receiving waveform parameters from the CPU to adapt to different radar task requirements. In addition, the FPGA is also responsible for precise timing control to ensure that the generation and output of the waveform meet the predetermined time requirements. This timing control not only improves the stability of the waveform, but also enhances the overall performance of the system.

[0094] Therefore, the radar waveform generation system provided by the present invention is convenient for unified scheduling of resources, can flexibly adapt to the generation requirements of different types of radar waveforms, optimizes the communication and data exchange between the CPU and FPGA board, ensures efficient collaboration between various modules, and thus improves the response speed and reliability of the overall system.

[0095] (3) In order to meet the real-time requirements, the radar waveform generation system provided by the present invention adopts a collaborative working architecture of CPU+FPGA+PCIE. In this architecture, the CPU processor is responsible for receiving and parsing radar parameter information at the wave level. Specifically, the CPU first extracts the necessary radar parameters from the upper-level instructions or echo signals. These parameters include key information such as the current working mode, frequency band selection and modulation waveform; after receiving the radar parameter information, the CPU quickly parses and processes it. This process ensures that the system can respond to external instructions or signal changes in a timely manner and adjust the working state of the radar. The efficient processing capability of the CPU enables the system to complete complex calculations and decisions in a short time and provide accurate instructions for the FPGA; the FPGA end is responsible for executing real-time working mode switching, timing control and waveform generation. By receiving instructions from the CPU, the FPGA adjusts its working mode in real time to adapt to different radar task requirements.

[0096] In the description of the present invention, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0097] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A radar waveform generation system applicable to multiple systems, characterized in that: include: The central processing unit CPU and the field programmable gate array FPGA board card, the FPGA board card integrates the FPGA chip and the digital-to-analog conversion DAC chip; among them, The CPU is used to generate a radar signal protocol message based on the parameter instruction sent by the host computer, and transmit the radar signal protocol message to the FPGA chip; The FPGA chip is used to parse the radar signal protocol message and cache the obtained signal waveform data and parameter instruction information respectively; generate a timing control signal based on the parameter instruction information, and further respond to the timing control signal to output the signal waveform data; The DAC chip is used to perform digital-to-analog conversion on the digital waveform data and output analog signals under the drive of the FPGA chip according to the specified working mode and frequency.

2. A radar waveform generation system applicable to multiple systems according to claim 1, characterized in that: The CPU includes a signal generating module, a packaging module and a PCIE transmitting interface driving module, and the FPGA chip includes a PCIE receiving interface driving module; wherein, The signal generating module is used to receive the parameter instruction sent by the host computer, parse the parameter instruction to obtain parameter instruction information, and generate signal waveform data based on the parameter instruction information; The encapsulation module is used to package the signal waveform data and the parameter instruction information to obtain a radar signal protocol message; The PCIE sending interface driver module is used to transmit the radar signal protocol message to the PCIE receiving interface driver module.

3. The radar waveform generation system applicable to multiple systems according to claim 2, characterized in that: The FPGA chip further includes: a parsing and caching module, the parsing and caching module includes a parsing unit and a first-level cache unit, the first-level cache unit includes an instruction cache table RAM and a signal waveform data cache RAM; wherein, The parsing unit is used to parse the radar signal protocol message, and cache the obtained parameter instruction information into the instruction cache table RAM, and cache the obtained signal waveform data into the signal waveform data cache RAM.

4. The radar waveform generation system applicable to multiple systems according to claim 3, characterized in that: The FPGA chip also includes a timing control module, and the parsing unit also includes a secondary cache unit, and the secondary cache unit includes a parameter instruction information secondary cache unit and a signal waveform data secondary cache unit; The instruction cache table RAM is further used to cache the required parameter instruction information into the parameter instruction information secondary cache unit when the parameter instruction information secondary cache unit is empty; The signal waveform data cache RAM is further used to cache the required signal waveform data into the signal waveform data secondary cache unit when the signal waveform data secondary cache unit is empty; The timing control module is used to read the required parameter instruction information from the parameter instruction information secondary cache unit, and generate a timing control signal and a wave position parameter update signal based on the required parameter instruction information; The parameter instruction information secondary cache unit is used to read the required parameter instruction information from the instruction cache table RAM in response to the wave position parameter update signal; The signal waveform data secondary cache unit is used to read the required signal waveform data from the signal waveform data cache RAM in response to the waveform parameter update signal.

5. The radar waveform generation system applicable to multiple systems according to claim 4, characterized in that: The FPGA chip also includes a downsampling rate module; The signal waveform data secondary cache unit is also used to output the required signal waveform data to the downsampling rate module in response to the timing control signal.

6. The radar waveform generation system applicable to multiple systems according to claim 5, characterized in that: The downsampling rate module is used to reduce the data rate of the required signal waveform data to obtain digital waveform data.

7. A radar waveform generation method applicable to multiple systems, characterized in that: Applicable to the radar waveform generation system according to any one of claims 1 to 6, the method comprising: Generate radar signal protocol message based on parameter instructions sent by the host computer; Parsing the radar signal protocol message, and performing first-level caching on the obtained signal waveform data and parameter instruction information respectively; The signal waveform data and parameter instruction information required in the first-level cache are cached in the second-level cache respectively; Generate a timing control signal according to the parameter instruction information required in the secondary cache, output the required signal waveform data based on the timing control signal, and reduce the data rate of the required signal waveform data; According to the specified working mode and frequency, the digital waveform data is converted into digital-to-analog form to output an analog signal.

8. The radar waveform generation method applicable to multiple systems according to claim 7, characterized in that: The steps of parsing the radar signal protocol message and performing first-level caching on the obtained signal waveform data and parameter instruction information respectively include: Parsing the radar signal protocol message to obtain signal waveform data and parameter instruction information; The parameter instruction information is cached in the instruction cache table RAM, and the obtained signal waveform data is cached in the signal waveform data cache RAM.

9. The radar waveform generation method applicable to multiple systems according to claim 8, characterized in that: After the step of performing the second-level caching on the required signal waveform data and the required parameter instruction information in the first-level cache respectively, the method further includes: Generate a wave position parameter update signal according to the parameter instruction information required in the secondary cache; Based on the wave position parameter update signal, the required signal waveform data and the required parameter instruction information are read from the first-level cache again, and the second-level cache is performed.

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