Memory scheduling system and method, electronic equipment, storage medium and program

Abstract

The invention discloses a memory scheduling system and method, an electronic device, a storage medium and a program, and relates to the technical field of servers, the memory scheduling system comprises a plurality of servers, a switching device and a plurality of memory devices, the switching device comprises a plurality of uplink memory interfaces, a plurality of downlink memory interfaces, a processor and a connector, the switching device is connected with a plurality of servers through a plurality of uplink memory interfaces, the switching device is connected with a plurality of memory devices through a plurality of downlink memory interfaces, and each memory device comprises at least one memory logic segment; and the processor is used for recording the scheduling times corresponding to each memory logic segment, and determining a target memory segment corresponding to at least one server in the plurality of memory logic segments corresponding to the plurality of memory devices according to the scheduling times corresponding to each memory logic segment. The utilization rate of memory resources can be improved.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to a memory scheduling system, method, electronic device, storage medium and program. Background Art

[0002] A data center may include multiple servers and a memory device corresponding to each server. When the server processes data through a central processing unit (CPU), the memory device corresponding to the server may provide memory resources for the CPU.

[0003] In related technologies, memory pooling can be performed through high-speed interconnect (Compute Express Link, CXL) switching technology to integrate memory resources scattered in different servers into a resource pool, and each server can obtain memory resources from the memory pool. However, each memory device in the resource pool can only be allocated to one server for use, and the memory resources used by the server for work are far less than the memory resources of the allocated memory devices, resulting in low memory resource utilization. Summary of the invention

[0004] The present application provides a memory scheduling system, method, electronic device, storage medium and program to at least solve the problem of low memory resource utilization in related technologies.

[0005] The present application provides a memory scheduling system, which includes multiple servers, a switching device and multiple memory devices. The switching device includes multiple upstream memory interfaces, multiple downstream memory interfaces, a processor and a connector. The processor and the connector are connected, wherein:

[0006] The switching device is connected to the multiple servers via multiple upstream memory interfaces, the switching device is connected to the multiple memory devices via multiple downstream memory interfaces, and the memory device includes at least one memory logic segment;

[0007] The plurality of memory devices are used to provide memory resources to the plurality of servers, and the connector is used to connect each upstream memory interface with a downstream memory interface corresponding to a target memory segment;

[0008] The processor is used to record the scheduling number corresponding to each memory logical segment, and according to the scheduling number corresponding to each memory logical segment, determine a target memory segment corresponding to at least one server among multiple memory logical segments corresponding to multiple memory devices, and the target memory segment is used to provide memory resources for its corresponding server.

[0009] The present application provides a memory scheduling method, including:

[0010] Get the resource requirements of the target server;

[0011] According to the resource demand, a target memory segment corresponding to the target server is determined among multiple memory logical segments. The target memory segment is used to provide memory resources for the target server. The multiple memory logical segments are determined by dividing the memory of multiple memory devices, and each memory device corresponds to at least one memory logical segment.

[0012] The present application provides a memory scheduling device, comprising: a first acquisition module, a second acquisition module, a first determination module and a second determination module, wherein:

[0013] The first acquisition module is used to obtain the resource demand of the target server;

[0014] The second acquisition module is used to acquire a first memory capacity corresponding to each memory logical segment in a plurality of memory logical segments, where the plurality of memory logical segments are determined by performing memory division on a plurality of memory devices, and each memory device corresponds to at least one memory logical segment;

[0015] The first determination module is used to determine a plurality of intermediate memory segments from a plurality of memory logical segments according to the number of scheduling times corresponding to each memory logical segment;

[0016] The second determination module is used to determine a target memory segment according to the first memory capacity and resource demand corresponding to each intermediate memory segment, and the target memory segment is used to provide memory resources for the target server.

[0017] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any one of the above-mentioned memory scheduling methods when executing the computer program.

[0018] The present application also provides a computer-readable storage medium, in which a computer program is stored, wherein when the computer program is executed by a processor, the steps of any of the above-mentioned memory scheduling methods are implemented.

[0019] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned memory scheduling methods when executed by a processor.

[0020] Through the memory scheduling system, method, electronic device, storage medium and program provided by the present application, the memory scheduling system may include multiple servers, switching devices and multiple memory devices. The switching device may include multiple upstream memory interfaces, multiple downstream memory interfaces, processors and connectors. The processor may be used to determine the target memory segment corresponding to each server in the multiple memory logical segments corresponding to the multiple memory devices. The memory device may be divided into at least one memory logical segment. The processor may determine the target logical segment corresponding to each upstream memory interface in the multiple memory logical segments corresponding to the multiple memory devices according to the number of scheduling times corresponding to each memory logical segment. The memory capacity of the memory logical segment is relatively small. After being allocated to the server corresponding to the upstream memory interface, the difference between the memory resources used by the server for work and the memory resources corresponding to the allocated target logical segment may be reduced, thereby improving the utilization rate of the memory resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A schematic diagram of an application scenario provided in an embodiment of the present application;

[0023] Figure 2 A schematic diagram of the structure of a memory scheduling system provided in an embodiment of the present application;

[0024] Figure 3 A schematic diagram of the structure of another memory scheduling system provided in an embodiment of the present application;

[0025] Figure 4 A schematic diagram of a memory resource scheduling structure provided in an embodiment of the present application;

[0026] Figure 5 A flowchart of a memory scheduling method provided in an embodiment of the present application;

[0027] Figure 6 A schematic diagram of another memory scheduling method provided in an embodiment of the present application;

[0028] Figure 7 A schematic diagram of the structure of a memory scheduling device provided in an embodiment of the present application;

[0029] Figure 8 A schematic diagram of the structure of an electronic device provided in this application. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] It should be noted that, in the description of this application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0032] Figure 1 A schematic diagram of an application scenario provided by an embodiment of the present application. Figure 1 The memory scheduling system 100 includes a host box (Host Box, HB), a high-speed interconnect technology (Compute Express Link, CXL) switch box (CXLSwitch Box, CSB) and a CXL memory box (CXL Memory Box, CMB), wherein the host box may include multiple servers 101, the switch box may include a switching device 102, and the memory box may include multiple memory devices 103.

[0033] The switching device 102 may include multiple upstream memory interfaces, multiple downstream memory interfaces, processors, and connectors. The CPU of the server 101 may be connected to an upstream memory interface of the switching device 102 via CXL. The downstream memory interface of the switching device 102 may be connected to a memory device 103 via CXL. CXL is a cache consistency protocol that can release memory resources based on the PCIe physical bus, and can achieve an increase in memory capacity across multiple CPUs.

[0034] The switching device 102 can perform memory pooling through the CXL switch technology, and integrate the memory resources of multiple memory devices 103 into a resource pool. Each server 101 can determine its corresponding memory device 103 in the resource pool.

[0035] However, each memory device in the resource pool can only be allocated to one server, and the memory resources used by the server for work are far less than the memory resources of the allocated memory device (for example, the capacity of the memory device allocated to the server is 64GB, 20GB is actually occupied, and the remaining 44GB is idle), resulting in low memory resource utilization.

[0036] In an embodiment of the present application, the memory device can be divided into at least one memory logical segment. The processor can determine the target logical segment corresponding to each upstream memory interface among the multiple memory logical segments corresponding to the multiple memory devices based on the scheduling number corresponding to each memory logical segment. The memory capacity of the memory logical segment is relatively small. After being allocated to the server corresponding to the upstream memory interface, the difference between the memory resources used for work by the server and the memory resources corresponding to the allocated target logical segment can be reduced, thereby improving the utilization rate of the memory resources.

[0037] Figure 2 A schematic diagram of the structure of a memory scheduling system provided in an embodiment of the present application. Figure 2 The memory scheduling system 100 may include multiple servers, switching devices, and multiple memory devices. The switching device may be connected to multiple servers via multiple upstream memory interfaces, and the switching device may be connected to multiple memory devices via multiple downstream memory interfaces.

[0038] Specifically, the server may be a dual-core server, which may include two CPUs, and the two CPUs may be connected to each other through a hyperlink interconnect (UPI), wherein the UPI may be used to implement high-speed communication between CPUs in a multi-processor system. The upstream memory interface may be connected to each of the two CPUs through CXL.

[0039] See also Figure 2 There are three servers in total. The servers include two CPUs. The switching device has three uplink memory interfaces in total. The first uplink memory interface is connected to the two CPUs of the first server through CXL, the second uplink memory interface is connected to the two CPUs of the second server through CXL, and the third uplink memory interface is connected to the two CPUs of the third server through CXL.

[0040] It is worth noting that the embodiments of the present application only illustrate the connection between a dual-way server and an upstream memory interface, and do not limit the server. For example, the server may also be a single-way server, a four-way server, etc.

[0041] Multiple memory devices can be used to provide memory resources to multiple servers. The memory devices may include a memory expansion controller (Memory Expander Controller, MXC), a flash chip (flash) and at least one storage module. The downstream memory interface is connected to the memory expansion controller, and the memory expansion controller is respectively connected to the flash chip and at least one storage module. The memory device may be a memory stick.

[0042] The processor can obtain the memory capacity of at least one memory module in the memory expansion controller through the downstream memory interface; the flash memory chip is used to store the configuration parameters of the at least one memory module.

[0043] The memory module can be a dual-inline memory module (DIMM), MXC is connected to DIMM, and MXC is connected to Flash through a serial peripheral interface (SPI) bus. The SPI bus is a synchronous serial communication protocol, which is mainly used for short-distance, high-speed chip-to-chip communication.

[0044] Among them, MXC can be responsible for managing memory expansion and access optimization, for example, coordinating the work of multiple DIMMs, controlling the bandwidth allocation of memory channels, and optimizing the efficiency of data flow. Flash can be used to store Serial Presence Detect (SPD) information. SPD records the configuration parameters of DIMMs (for example, timing, capacity, voltage, manufacturer information, etc.) for automatic identification and configuration of memory when the system starts. DIMMs can integrate multiple Dynamic Random Access Memory (DRAM) chips to provide temporary data storage for the CPU and support high-speed reading and writing.

[0045] The DIMM may be a fourth generation double data rate 4 (DDR4) synchronous dynamic random access memory or a fifth generation double data rate 5 (DDR5) synchronous dynamic random access memory.

[0046] The downstream memory interface can be connected to the MXC of the memory device through a high-speed interconnect bus (i.e., CXL), see Figure 2 There are 3 downstream memory interfaces and 3 memory devices in total. The first downstream memory interface is connected to the MXC of the first memory device through CXL, the second downstream memory interface is connected to the MXC of the second memory device through a high-speed interconnect bus (ie, CXL), and the third downstream memory interface is connected to the MXC of the third memory device through CXL.

[0047] See also Figure 2 ,The switching device may include a plurality of upstream memory interfaces, a plurality of downstream memory interfaces, a processor and a connector, the processor and the connector are connected, and the connector connects each upstream memory interface with a downstream memory interface corresponding to the target memory segment.

[0048] The processor can divide the memory device into at least one memory logical segment. The processor can record the scheduling number corresponding to each memory logical segment. The processor can determine a target memory segment corresponding to at least one server among multiple memory logical segments corresponding to multiple memory devices according to the scheduling number corresponding to each memory logical segment. The target memory segment can be used to provide memory resources for its corresponding server.

[0049] After the processor determines the target memory segment, the connector can be used to connect each upstream memory interface to the downstream memory interface corresponding to the target memory segment, and the downstream memory interface can include at least one second sub-interface, and the second sub-interface can be used to store a logical address corresponding to a memory logical segment. The number of second sub-interfaces corresponding to each downstream memory interface is the same as the number of memory logical segments of the memory device corresponding to the downstream memory interface.

[0050] See also Figure 2 , each downstream memory interface includes M second sub-interfaces, that is, the memory device is divided into M memory logical segments, M is an integer greater than or equal to 1, and each downstream memory interface can store the logical address of its corresponding memory logical segment.

[0051] The connector can connect the first upstream memory interface with the two second sub-interfaces of the first downstream memory interface, that is, the two memory logic segments of the first memory device provide memory resources for the first server; the second upstream memory node can be connected with a second sub-interface of the second downstream memory interface and a second sub-interface of the third downstream memory interface, that is, a memory logic segment of the second memory device and a memory logic segment of the third memory device provide memory resources for the second server; the third upstream memory interface can be connected with a second sub-interface of the third downstream memory interface, that is, a memory logic segment of the third memory device provides memory resources for the third server.

[0052] In an embodiment of the present application, a memory device may include at least one memory logic segment, and a processing device may determine a target logic segment corresponding to each upstream memory interface from multiple memory logic segments corresponding to multiple memory devices according to the number of scheduling times corresponding to each memory logic segment. The memory capacity of the memory logic segment is relatively small. After being allocated to a server corresponding to the upstream memory interface, the difference between the memory resources used by the server for work and the memory resources corresponding to the allocated target logic segment may be reduced, thereby improving the utilization of memory resources. In addition, through the number of scheduling times corresponding to each memory logic segment, a memory logic segment with a smaller number of scheduling times may be determined as a target logic segment, the number of scheduling times of each memory logic segment may be balanced, the service life of the memory device may be improved, and the stability of the system may be improved.

[0053] Figure 3 This is a schematic diagram of another memory scheduling system provided in an embodiment of the present application. Figure 3 ,exist Figure 2 Based on the memory scheduling system 100 shown, in the memory scheduling system 100, the processor and the connector are communicatively connected via a UART bus, wherein the UART bus (Universal Asynchronous Receiver / Transmitter) is an asynchronous serial communication protocol widely used for low-speed, reliable data transmission between devices (such as microcontrollers and sensors, processors and connectors, etc.).

[0054] The processor may obtain the resource requirement of the target server, and determine a target memory segment corresponding to the target server in a plurality of memory logical segments according to the resource requirement and the resource demand.

[0055] In the present application, the target memory segment corresponding to the target server can be determined by the resource demand of the target server, so that the memory resources allocated to the target server can be just suitable for the use of the target server, and then more memory resources can be released for use by servers with larger resource demands, which can improve the effectiveness of memory resource allocation. In addition, it can also reduce the idleness of memory resources in the target server and improve the utilization rate of memory resources.

[0056] In this application, the memory logical segments with lower usage times can be scheduled to the target server preferentially through the scheduling times, so as to balance the usage rate of each memory logical segment and avoid high usage rate of some memory logical segments, thereby increasing the service life of the corresponding memory device and improving the reliability of the system.

[0057] In some possible embodiments, the processor further includes an expander, and the processor can be connected to a plurality of downstream memory interfaces via the expander.

[0058] Specifically, the expander and the processor are communicatively connected via an Inter-Integrated Circuit (I2C) bus, wherein the expander may be an I2C expander, which is an electronic device for enhancing or expanding the function of the I2C bus, and can solve the problem of insufficient number of General Purpose Input / Output (GPIO) pins in system design, and simplify circuit design through flexible serial communication.

[0059] The processor may also be configured to perform memory partitioning processing on the memory device corresponding to each downstream memory interface, and determine at least one memory logical segment corresponding to each memory device.

[0060] In the present application, the memory device can be divided into at least one memory logical segment, and the memory capacity of each memory logical segment is smaller than the memory capacity of the memory device. When the memory logical segment is allocated to the target server, the idle memory capacity can be reduced and the utilization rate of memory resources can be improved.

[0061] The connector can be used to connect each upstream memory interface to a downstream memory interface corresponding to a target memory segment.

[0062] The connector can receive instructions from the processor and dispatch memory resources of different downstream memory interfaces to the specified upstream memory interface.

[0063] In some possible embodiments, the upstream memory interface may include at least one first sub-interface, the downstream memory interface may include at least one second sub-interface, the connector is connected to at least one first sub-interface corresponding to each upstream memory interface, and the connector is connected to at least one second sub-interface corresponding to each downstream memory interface, wherein:

[0064] The first sub-interface can be used to store the logical address of the target memory segment corresponding to the target memory interface, and the target memory interface is the uplink memory interface corresponding to the first sub-interface; the second sub-interface can be used to store the logical address corresponding to any memory logical segment.

[0065] For example, assuming that the first memory device is divided into 16 memory logical segments, and the first memory device corresponds to the first downstream memory interface, then the first downstream memory interface includes 16 second sub-interfaces, and each second sub-interface can store a logical address corresponding to a memory logical segment.

[0066] It is worth noting that the number of memory logical segments corresponding to each memory device may be the same or different. For example, the first memory device may include 16 memory logical segments, the second memory device may include 8 memory logical segments, and the third memory device may include 16 memory logical segments.

[0067] The processor may store the logical address of the target memory segment in the first sub-interface of the target memory interface. For example, see Figure 3 , the first server corresponds to the first upstream memory interface. Assuming that the target memory segments corresponding to the first server are the first memory logical segment and the second memory logical segment of the first memory device, then the logical address of the first memory logical segment of the first memory device can be stored in the first first sub-interface of the first upload memory interface, and the logical address of the second memory logical segment of the first memory device can be stored in the second first sub-interface of the first upstream memory interface.

[0068] In the present application, the logical address of the target memory segment can be stored through the first sub-interface, and the server can utilize the memory resources through the logical address, which can improve the efficiency of the server's memory access.

[0069] It is worth noting that the maximum number of first sub-interfaces corresponding to the upstream memory interface is the number of multiple memory logical segments. For example, there are 3 memory devices, each memory device includes 16 memory logical segments, and there are 48 memory logical segments in total. Then, the maximum number of first sub-interfaces corresponding to the upstream memory interface is 48.

[0070] Normally, not all memory logical segments are allocated to the same server. The number of first sub-interfaces corresponding to the upstream memory interface may be the number of memory logical segments corresponding to a memory device. For example, the number of first sub-interfaces corresponding to the upstream memory interface may be 16 or 8.

[0071] Figure 4 A schematic diagram of a memory resource scheduling structure provided by an embodiment of the present application. Figure 4 For any memory device, the memory device may include 16 memory logic segments, where the full name of the memory logic segment is Memory Logic Segment, abbreviated as MLS. Figure 4 16 memory logical segments are indicated by MLS0-MLS15 respectively. The switching device includes a processor and a connector, and the processor and the connector are connected to each other through UART. The memory logical segments of the memory device can be dispatched to the four servers through the switching device. Figure 4In the example, four servers are indicated by HOST0, HOST1, HOST2 and HOST3 respectively. The target memory segments corresponding to HOST0 are MLS0 and MLS3, the target memory segments corresponding to HOST1 are MLS5 and MLS8, the target memory segments corresponding to HOST2 are MLS7 and MLS9, and the target memory segments corresponding to HOST3 are MLS12 and MLS15.

[0072] After dividing the memory device into multiple memory logical segments, the memory logical segments can be allocated to different servers for use, which can greatly improve the memory utilization rate.

[0073] In some possible embodiments, memory logical segments of different memory devices may be allocated to the same target server, for example, the memory logical segment of the first memory device and the memory logical segment of the second memory device are allocated to the first server.

[0074] Based on the above memory scheduling system, the following Figure 5 and Figure 6 The memory scheduling method provided in the embodiment of the present application is described.

[0075] Figure 5 A flowchart of a memory scheduling method provided in an embodiment of the present application. Figure 5 , the method may include:

[0076] S501: Obtain resource requirements of a target server.

[0077] The target server is any one of the multiple servers.

[0078] S502: Obtain a first memory capacity corresponding to each memory logical segment in a plurality of memory logical segments.

[0079] Before determining the target memory segment corresponding to the target server, it also includes performing memory partitioning processing on each memory device. The specific execution process can be seen in the following steps: the memory capacity corresponding to each memory device can be obtained through multiple downstream memory interfaces, and for any memory device, memory partitioning processing is performed according to the second memory capacity of the memory device to obtain at least one memory logical segment corresponding to the memory device, and each memory logical segment is stored in the second sub-interface.

[0080] The multiple memory logical segments may include at least one memory logical segment corresponding to each memory device. For example, assuming there are three memory devices, the first memory device includes memory logical segment 11 and memory logical segment 12, the second memory device includes memory logical segment 21, and the third memory device includes memory logical segment 31 and memory logical segment 32. Then, the multiple memory logical segments include memory logical segment 11, memory logical segment 12, memory logical segment 21, memory logical segment 31, and memory logical segment 32.

[0081] It is worth noting that after the memory chassis corresponding to multiple memory devices are powered on, MXC can read the Flash to complete initialization for any memory device, and MXC can obtain the memory resources of each DIMM. The processor can obtain the second memory capacity of each memory device through MXC.

[0082] S503: Determine a plurality of intermediate memory segments from the plurality of memory logical segments according to the number of scheduling times corresponding to each memory logical segment.

[0083] The multiple intermediate memory segments are memory logical segments with fewer call times among the multiple memory logical segments.

[0084] After scheduling the memory logic segment, the processor can update the scheduling times corresponding to the memory logic segment. Each time the target memory segment is allocated to the target server, the memory logic segment with a low call count can be allocated first, which can increase the service life of the memory device and at the same time improve the reliability of the system.

[0085] S504: Determine a target memory segment according to the first memory capacity and resource requirement corresponding to each intermediate memory segment.

[0086] The target memory segment can be used to provide memory resources for the target server. The multiple memory logical segments are determined by dividing the memory of the multiple memory devices, and each memory device corresponds to at least one memory logical segment.

[0087] The memory scheduling method provided in the present application can determine multiple intermediate memory segments according to the resource demand of the target server and the number of calls corresponding to each memory logic segment. The intermediate memory segment is a memory logic segment with fewer calls, and then the target logic segment corresponding to each upstream memory interface is determined in the multiple intermediate memory segments. Multiple intermediate memory segments can be determined by the number of calls, and the memory logic segments with fewer uses can be allocated first, which can improve the reliability of the system. In addition, the first memory capacity of the memory logic segment is relatively small. After being allocated to the server corresponding to the upstream memory interface, the difference between the memory resources used by the server for work and the memory resources corresponding to the allocated target logic segment can be reduced, thereby improving the utilization of memory resources.

[0088] Figure 6A schematic diagram of another memory scheduling method provided in an embodiment of the present application. Figure 6 , the method may include:

[0089] S601: Obtain resource requirements of a target server.

[0090] The execution process of S601 may refer to the execution process of S501 described above, and will not be described in detail here.

[0091] S602: Obtain a first memory capacity corresponding to each memory logical segment in a plurality of memory logical segments.

[0092] The first memory capacity corresponding to each memory logic may be obtained through the plurality of second sub-interfaces.

[0093] In some possible embodiments, the first memory capacity corresponding to each memory logical segment may be the same. For example, the second memory capacity of the memory device is 64G, and the memory device is divided into 8 memory logical segments, then the first memory capacity corresponding to each memory logical segment is 8G.

[0094] In some possible embodiments, the first memory capacity corresponding to each memory logic may be the same or different. For example, the second memory capacity of the memory device is 64G, and the memory device is divided into 12 memory logic segments, then the first memory capacity of 8 memory logic segments is 5G, and the first memory capacity of 4 memory logic segments is 6G.

[0095] S603: Determine a plurality of intermediate memory segments from the plurality of memory logical segments according to the number of scheduling times corresponding to each memory logical segment.

[0096] In some possible embodiments, multiple memory logical segments are sorted in order from small to large according to the number of scheduling times to obtain a sorted memory segment set, and a preset number N is obtained, and the first N memory logical segments in the memory segment set are determined as multiple intermediate memory segments, where N is an integer greater than or equal to 1.

[0097] For example, assuming that there are 8 memory logical segments, namely memory logical segments 1-8, the scheduling times corresponding to each memory logical segment can be seen below, the memory segment set is {memory logical segment 3, memory logical segment 2, memory logical segment 4, memory logical segment 8, memory logical segment 1, memory logical segment 7, memory logical segment 6, memory logical segment 5}, assuming that the preset number N is 4, then the multiple intermediate memory segments are determined as: memory logical segment 3, memory logical segment 2, memory logical segment 4, memory logical segment 8.

[0098] Table 1

[0099] Memory logical segment Scheduling times Dispatch ratio Memory capacity Memory logical segment 1 13 13% 1G Memory logical segment 2 7 7% 1G Memory logical segment 3 6 6% 2G Memory logical segment 4 9 9% 4G Memory logical segment 5 20 20% 6G Memory logical segment 6 18 18% 6G Memory logical segment 7 16 16% 8G Memory logical segment 8 11 11% 8G

[0100] In some possible embodiments, the scheduling ratio corresponding to each memory logic segment is determined according to the scheduling number corresponding to each memory logic segment, a preset ratio is obtained, and the memory logic segment with a scheduling ratio less than or equal to the preset ratio is determined as an intermediate memory segment to determine multiple intermediate memory segments.

[0101] Specifically, for any memory logical segment, a ratio of the number of scheduling times corresponding to the memory logical segment to the total number of scheduling times corresponding to multiple memory logical segments is determined as the scheduling ratio.

[0102] For example, there are 8 memory logical segments, namely memory logical segments 1-8. The number of scheduling times for each memory logical segment and the scheduling ratio corresponding to each memory logical segment are shown in Table 1. Assuming that the preset ratio is 10%, memory logical segment 2, memory logical segment 3 and memory logical segment 4 are middle memory segments.

[0103] S604: Determine whether there is an intermediate memory segment in the first memory capacity corresponding to each intermediate memory segment that is greater than the resource demand.

[0104] If yes, execute step S605;

[0105] If not, execute step S607.

[0106] S605: Determine at least one first memory segment and multiple second memory segments according to the first memory capacity and resource requirement corresponding to each intermediate memory segment.

[0107] The first memory segment is an intermediate memory segment whose first memory capacity is greater than or equal to the resource requirement, and the second memory segment is an intermediate memory segment whose first memory capacity is less than the resource requirement.

[0108] S606: Determine a target memory segment according to at least one first memory segment, multiple second memory segments, and resource requirements.

[0109] The target memory segment can be one or more.

[0110] In some possible embodiments, the difference between the first memory capacity corresponding to each first memory segment in at least one first memory segment and the resource demand can be determined as the capacity difference; determine whether there is a first memory segment whose capacity difference is less than or equal to a preset difference; if so, determine the first memory segment whose capacity difference is less than or equal to the preset difference as the target memory segment, and there is one target memory segment; if not, determine the target memory segment according to the first memory capacity corresponding to the second memory segment, and there are multiple target memory segments.

[0111] The capacity difference value is used to indicate the extent to which the first memory capacity corresponding to the first memory segment is greater than the resource requirement of the server.

[0112] If the first memory capacity of the first memory segment is smaller than the resource requirement, the first memory segment may be determined as the target memory segment. In this case, there is one target memory segment.

[0113] If there is a first memory segment whose capacity difference is less than or equal to the preset difference, that is, the first memory segment meets the memory requirement of the target server and does not leave too many memory resources idle, the first memory segment can be determined as the target memory segment.

[0114] In some possible embodiments, there may be multiple first memory segments whose capacity difference is less than or equal to a preset difference, and the first memory segment with the least number of scheduling times may be determined as the target memory segment.

[0115] If the first memory capacity of the first memory segment is larger than the resource demand, that is, the capacity difference is larger than the preset difference, the first memory segment cannot be determined as the target memory segment of the target server. If a memory logical segment with more memory resources is allocated to the target server, more memory resources will be idle, which will reduce the utilization rate of memory resources. At this time, the target memory segment can be determined according to the first memory capacity corresponding to each second memory segment, and there are multiple target memory segments.

[0116] For example, there are 8 memory logical segments in total, and the scheduling times, scheduling ratio, and memory capacity corresponding to each memory logical segment can be seen in Table 1. Assuming that the resource demand is 5G, memory logical segment 3, memory logical segment 2, memory logical segment 4, and memory logical segment 8 are intermediate memory segments, where memory logical segment 8 is the first memory segment, and memory logical segment 3, memory logical segment 2, and memory logical segment 4 are the second memory segment. Assuming that the preset difference is 1G, the capacity difference of memory logical segment 8 is greater than the preset difference, and the target memory segment can be determined from memory logical segment 3, memory logical segment 2, and memory logical segment 4.

[0117] If the first memory capacity of the second memory segment is less than the resource requirement, then multiple target memory segments are determined from the multiple second memory segments. If the memory capacity corresponding to the multiple target memory segments is greater than the resource requirement, multiple memory segment combinations can be determined from the multiple second memory segments to select a target memory segment suitable as the target server from the multiple memory segment combinations.

[0118] Specifically, multiple memory segment combinations can be determined based on multiple second memory segments, and the memory segment combination can include at least two second memory segments; the third memory capacity corresponding to each memory segment combination is determined; the memory segment combination whose third memory capacity is greater than the resource demand is determined as an intermediate combination to obtain at least one intermediate combination; the intermediate combination with the smallest third memory capacity is determined as the target combination, and the second memory segment corresponding to the target combination is determined as the target memory segment.

[0119] For example, assuming that the second memory segment is memory logical segment 3, memory logical segment 2 and memory logical segment 4, four memory segment combinations can be determined, namely memory segment combinations 1-4. Assuming that the first memory capacity corresponding to each memory logical segment can be seen in Table 1, the second memory segment and the third memory capacity corresponding to each memory segment combination can be seen in Table 2, then the intermediate combination can be determined to be memory segment combination 3 and memory segment combination 4. Since the third memory capacity of memory segment combination 3 is smaller than the third memory capacity of memory segment combination 4, the memory logical segment 3 and memory logical segment 4 corresponding to memory segment combination 3 can be determined as the target memory segments.

[0120] Table 2

[0121] Memory segment combination Memory Segments Memory capacity Memory segment combination 1 Memory logical segment 2 and memory logical segment 3 3G Memory segment combination 2 Memory logical segment 2 and memory logical segment 4 5G Memory segment combination 3 Memory logical segment 3 and memory logical segment 4 6G Memory segment combination 4 Memory logical segment 3, memory logical segment 2, and memory logical segment 4 7G

[0122] In the present application, it can be determined whether there is a first memory segment whose capacity difference is less than or equal to a preset difference. If so, the first memory segment whose capacity difference is less than or equal to the preset difference is determined as the target memory segment; if not, the target memory segment is determined based on the first memory capacity corresponding to the second memory segment. This can ensure that the memory logical segment allocated to the target server will not be much larger than the resource demand, thereby reducing the waste of memory resources and increasing the utilization of memory resources.

[0123] S607: Determine a target memory segment according to the first memory capacity corresponding to each intermediate memory segment.

[0124] In some possible embodiments, referring to step S606, the execution process of determining the target memory segment according to the first memory capacity corresponding to each second memory segment is not described in detail here.

[0125] In some other possible embodiments, multiple intermediate memory segments may be sorted according to the first memory capacity corresponding to each intermediate memory segment to obtain a memory segment queue; and a target memory segment may be determined in the memory segment queue according to resource demand.

[0126] Specifically, the plurality of intermediate memory segments may be sorted from largest to smallest according to the first memory capacity to obtain a memory segment queue.

[0127] There are Q intermediate memory segments in the memory segment queue. The i-th first candidate memory segment is determined in the memory segment queue, and the j-th second candidate memory segment is determined except the i-th first candidate memory segment, until the sum of the i-th first candidate memory segment and the j-th second candidate memory segment is greater than the resource demand, and the i-th first candidate memory segment and the j-th second candidate memory segment are determined as the target memory segment. Wherein, Q is an integer greater than or equal to 1, i is 1, 2, ..., Q, and j is 1, 2, ..., Q-1.

[0128] For example, assuming that memory logical segment 3, memory logical segment 2, memory logical segment 4, and memory logical segment 8 are intermediate memory segments, the memory capacity corresponding to each memory logical segment can be seen in Table 1, assuming that the memory segment queue is {memory logical segment 4, memory logical segment 3, and memory logical segment 2}, assuming that the resource demand is 5G, and assuming that the preset difference is 1G. The first first memory segment to be selected is memory logical segment 4, and the first second memory segment to be selected is memory logical segment 3. The sum of memory logical segment 4 and memory logical segment 3 is greater than the resource demand, then memory logical segment 4 and memory logical segment 3 can be determined as the target memory segments.

[0129] The memory scheduling method provided in the embodiment of the present application can obtain the first memory capacity corresponding to each memory logic segment in multiple memory logic segments, determine multiple intermediate memory segments in multiple memory logic segments according to the number of scheduling times corresponding to each memory logic segment, and determine the target memory segment according to the first memory capacity and resource demand corresponding to each intermediate memory segment. The memory logic segment with a smaller number of scheduling times can be selected as the target memory segment according to the number of scheduling times, which can improve the service life of the memory device and thus improve the reliability of the system. In addition, after selecting multiple intermediate memory segments, a target memory segment or multiple target memory segments can be selected according to the first memory capacity corresponding to each intermediate memory segment, so that the memory resources provided by the target memory segment are suitable for the resource demand, and too many memory resources will not be idle, which can improve the utilization rate of memory resources.

[0130] Figure 7 This is a schematic diagram of the structure of a memory scheduling device provided in an embodiment of the present application. Figure 7 The memory scheduling device 700 includes a first acquisition module 701, a second acquisition module 702, a first determination module 703 and a second determination module 704, wherein:

[0131] The first acquisition module 701 is used to obtain the resource demand of the target server;

[0132] The second acquisition module 702 is used to acquire a first memory capacity corresponding to each memory logical segment in a plurality of memory logical segments, where the plurality of memory logical segments are determined by performing memory division on a plurality of memory devices, and each memory device corresponds to at least one memory logical segment;

[0133] The first determination module 703 is used to determine a plurality of intermediate memory segments from a plurality of memory logical segments according to the number of scheduling times corresponding to each memory logical segment;

[0134] The second determination module 704 is used to determine a target memory segment according to the first memory capacity and resource requirement corresponding to each intermediate memory segment, and the target memory segment is used to provide memory resources for the target server.

[0135] In a possible embodiment, the second determining module 704 is specifically configured to:

[0136] Determine whether there is an intermediate memory segment greater than the resource requirement in the first memory capacity corresponding to each intermediate memory segment;

[0137] If so, at least one first memory segment and multiple second memory segments are determined according to the first memory capacity and resource requirement corresponding to each intermediate memory segment, and a target memory segment is determined according to the at least one first memory segment, the multiple second memory segments and the resource requirement, wherein the first memory segment is an intermediate memory segment whose first memory capacity is greater than or equal to the resource requirement, and the second memory segment is an intermediate memory segment whose first memory capacity is less than the resource requirement;

[0138] If not, the target memory segment is determined according to the first memory capacity corresponding to each intermediate memory segment.

[0139] In a possible embodiment, the second determining module 704 is specifically configured to:

[0140] Determine a difference between a first memory capacity corresponding to each first memory segment in at least one first memory segment and a resource requirement as a capacity difference;

[0141] Determine whether there is a first memory segment whose capacity difference is less than or equal to a preset difference;

[0142] If so, the first memory segment whose capacity difference is less than or equal to the preset difference is determined as the target memory segment, and there is one target memory segment;

[0143] If not, a target memory segment is determined according to the first memory capacity corresponding to the second memory segment, and there are multiple target memory segments.

[0144] In a possible embodiment, the second determining module 704 is specifically configured to:

[0145] According to the first memory capacity corresponding to each intermediate memory segment, the plurality of intermediate memory segments are sorted to obtain a memory segment queue;

[0146] According to the resource demand, the target memory segment is determined in the memory segment queue.

[0147] In a possible embodiment, the second determining module 704 is specifically configured to:

[0148] Determine a plurality of memory segment combinations according to the plurality of second memory segments, wherein the memory segment combinations include at least two second memory segments;

[0149] Determine the third memory capacity corresponding to each memory segment combination;

[0150] Determine the memory segment combination whose third memory capacity is greater than the resource requirement as an intermediate combination, so as to obtain at least one intermediate combination;

[0151] The intermediate combination with the smallest third memory capacity is determined as the target combination, and the second memory segment corresponding to the target combination is determined as the target memory segment.

[0152] In a possible embodiment, the second determining module 704 is specifically configured to:

[0153] Sorting the multiple memory logical segments in ascending order of the scheduling times to obtain a sorted memory segment set, obtaining a preset number N, and determining the first N memory logical segments in the memory segment set as multiple intermediate memory segments, where N is an integer greater than or equal to 1;

[0154] Alternatively, according to the scheduling times corresponding to each memory logic segment, the scheduling ratio corresponding to each memory logic segment is determined, a preset ratio is obtained, and the memory logic segment with a scheduling ratio less than or equal to the preset ratio is determined as an intermediate memory segment to determine multiple intermediate memory segments.

[0155] The description of the features in the embodiment corresponding to the memory scheduling device can refer to the relevant description of the embodiment corresponding to the memory scheduling method, which will not be repeated here.

[0156] Figure 8 This is a schematic diagram of the structure of an electronic device provided in this application. Figure 8 As shown, the electronic device 800 provided in this embodiment includes: at least one processor 801 and a memory 802. Optionally, the electronic device 800 further includes a communication component 803. The processor 801, the memory 802 and the communication component 803 are connected via a bus.

[0157] In the specific implementation process, at least one processor 801 executes the computer execution instructions stored in the memory 802, so that at least one processor 801 executes the above-mentioned inland scheduling method embodiment.

[0158] The specific implementation process of the processor 801 can be found in the above method embodiment, and its implementation principle and technical effect are similar, so this embodiment will not be repeated here.

[0159] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the application may be directly implemented as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.

[0160] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (NVM), such as at least one disk storage.

[0161] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of this application is not limited to only one bus or one type of bus.

[0162] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned memory scheduling method embodiments when running.

[0163] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0164] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above-mentioned memory scheduling method embodiments are implemented.

[0165] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned memory scheduling method embodiments are implemented.

[0166] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0167] The above is a detailed introduction to a memory scheduling method provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A memory scheduling system, characterized in that: The memory scheduling system includes multiple servers, a switching device and multiple memory devices, wherein the switching device includes multiple upstream memory interfaces, multiple downstream memory interfaces, a processor and a connector, wherein the processor is connected to the connector, The switching device is connected to the multiple servers via the multiple upstream memory interfaces, the switching device is connected to the multiple memory devices via the multiple downstream memory interfaces, and the memory device includes at least one memory logic segment; The multiple memory devices are used to provide memory resources to the multiple servers, and the connector is used to connect each upstream memory interface to a downstream memory interface corresponding to a target memory segment; The processor is used to record the scheduling number corresponding to each memory logical segment, and determine a target memory segment corresponding to at least one server among the multiple memory logical segments corresponding to the multiple memory devices based on the scheduling number corresponding to each memory logical segment, and the target memory segment is used to provide memory resources for its corresponding server.

2. The memory scheduling system according to claim 1, characterized in that: The processor is specifically used for: Get the resource requirements of the target server; According to the resource demand and the number of scheduling times corresponding to each memory logical segment, a target memory segment corresponding to the target server is determined from the multiple memory logical segments.

3. The memory scheduling system according to claim 2, characterized in that: The processor further includes an expander, and the processor is connected to the multiple downstream memory interfaces via the expander, wherein: The processor is further configured to perform memory partitioning processing on the memory device corresponding to each downstream memory interface, and determine at least one memory logical segment corresponding to each memory device.

4. The memory scheduling system according to claim 3, characterized in that: The memory device includes a memory expansion controller, a flash memory chip and at least one storage module, the downstream memory interface is connected to the memory expansion controller, and the memory expansion controller is respectively connected to the flash memory chip and the at least one storage module, wherein: The processor obtains the memory capacity of the at least one memory module in the memory expansion controller through the downstream memory interface; The flash memory chip is used to store configuration parameters of the at least one memory module.

5. The memory scheduling system according to claim 1, characterized in that: The upstream memory interface includes at least one first sub-interface, the downstream memory interface includes at least one second sub-interface, the connector is connected to at least one first sub-interface corresponding to each upstream memory interface, and the connector is connected to at least one second sub-interface corresponding to each downstream memory interface, wherein: The first sub-interface is used to store a logical address of a target memory segment corresponding to a target memory interface, and the target memory interface is an uplink memory interface corresponding to the first sub-interface; The second sub-interface is used to store the logical address corresponding to any memory logical segment.

6. The memory scheduling system according to claim 4, characterized in that: The multiple upstream memory interfaces are communicatively connected to the multiple servers via a high-speed interconnection bus, and the multiple downstream memory interfaces are communicatively connected to the multiple memory devices via a high-speed interconnection bus.

7. A memory scheduling method, characterized in that: include: Get the resource requirements of the target server; Obtaining a first memory capacity corresponding to each memory logical segment of a plurality of memory logical segments, wherein the plurality of memory logical segments are determined by performing memory division on a plurality of memory devices, and each memory device corresponds to at least one memory logical segment; According to the scheduling number corresponding to each memory logical segment, determining a plurality of intermediate memory segments among the plurality of memory logical segments; A target memory segment is determined according to the first memory capacity corresponding to each intermediate memory segment and the resource demand, and the target memory segment is used to provide memory resources for the target server.

8. The method according to claim 7, characterized in that Determining the target memory segment according to the first memory capacity corresponding to each intermediate memory segment and the resource requirement includes: Determine whether there is an intermediate memory segment greater than the resource requirement in the first memory capacity corresponding to each intermediate memory segment; If so, determining at least one first memory segment and multiple second memory segments according to the first memory capacity corresponding to each intermediate memory segment and the resource requirement, and determining the target memory segment according to the at least one first memory segment, the multiple second memory segments and the resource requirement, wherein the first memory segment is an intermediate memory segment whose first memory capacity is greater than or equal to the resource requirement, and the second memory segment is an intermediate memory segment whose first memory capacity is less than the resource requirement; If not, the target memory segment is determined according to the first memory capacity corresponding to each intermediate memory segment.

9. The method according to claim 8, characterized in that Determining the target memory segment according to the at least one first memory segment, the plurality of second memory segments, and the resource requirement includes: Determine a difference between a first memory capacity corresponding to each first memory segment in the at least one first memory segment and the resource requirement as a capacity difference; Determine whether there is a first memory segment whose capacity difference is less than or equal to a preset difference; If so, the first memory segment whose capacity difference is less than or equal to the preset difference is determined as the target memory segment, and there is one target memory segment; If not, the target memory segment is determined according to the first memory capacity corresponding to the second memory segment, and there are multiple target memory segments.

10. The method according to claim 9, characterized in that Determining the target memory segment according to the first memory capacity corresponding to the second memory segment includes: Determine a plurality of memory segment combinations according to the plurality of second memory segments, wherein the memory segment combinations include at least two second memory segments; Determine the third memory capacity corresponding to each memory segment combination; Determine the memory segment combination whose third memory capacity is greater than the resource requirement as an intermediate combination, so as to obtain at least one intermediate combination; The intermediate combination with the smallest third memory capacity is determined as the target combination, and the second memory segment corresponding to the target combination is determined as the target memory segment.

11. The method according to claim 8, characterized in that Determining the target memory segment according to the first memory capacity corresponding to each intermediate memory segment includes: According to the first memory capacity corresponding to each intermediate memory segment, the plurality of intermediate memory segments are sorted to obtain a memory segment queue; According to the resource demand, the target memory segment is determined in the memory segment queue.

12. The method according to claim 8, characterized in that According to the scheduling times corresponding to each memory logic segment, a plurality of intermediate memory segments are determined in the plurality of memory logic segments, including: Sorting the plurality of memory logical segments according to the order of the scheduling times from small to large to obtain a sorted memory segment set, obtaining a preset number N, and determining the first N memory logical segments in the memory segment set as the plurality of intermediate memory segments, where N is an integer greater than or equal to 1; Alternatively, according to the scheduling number corresponding to each memory logic segment, the scheduling ratio corresponding to each memory logic segment is determined, a preset ratio is obtained, and the memory logic segment whose scheduling ratio is less than or equal to the preset ratio is determined as the intermediate memory segment, so as to determine the multiple intermediate memory segments.

13. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the memory scheduling method as claimed in any one of claims 7 to 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the memory scheduling method according to any one of claims 7 to 12.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the memory scheduling method according to any one of claims 7 to 12 are implemented.

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