Method and device for determining target test scheme and medium

Abstract

The invention relates to the technical field of semiconductor testing. In particular to a method and equipment for determining a target test scheme and a medium. The method comprises the steps that chip distribution information and target test conditions of a to-be-tested wafer are acquired, and the chip distribution information comprises a plurality of chips arranged in a matrix and test demand information of each chip; according to the test capability of the probe card and the position coordinate information of the plurality of chips, candidate test steps corresponding to the wafer to be tested are generated, and the candidate test steps comprise the position coordinate information of the chips covered by the probe card for a single time; and according to the candidate test steps, determining a target test scheme of the to-be-tested wafer, the target test scheme including a plurality of target test steps, and the target test scheme satisfying the target test condition. The purpose of automatically and intelligently determining the target test scheme meeting the target test condition is achieved. The intelligent determination of the test path is realized, and the efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and in particular to a method, device and medium for determining a target testing scheme. Background Art

[0002] In the semiconductor manufacturing process, the chip (DUT, Device Under Test) is made on the wafer. The probe card test involves using the probe card to touch the solder joints of the chip to test whether the chip functions normally. Probe card testing is a key link in ensuring chip quality. Traditional testing methods rely on manual experience to determine the test path and are not intelligent; they test chips that do not need to be tested, resulting in a waste of time and resources. Therefore, there is an urgent need in the prior art for a method that can automatically determine the target test plan. Summary of the invention

[0003] In order to solve the above problems, the present application provides a method, device and medium for determining a target test scheme.

[0004] According to one aspect of the present application, a method for determining a target test scheme is provided, the method comprising: Obtain chip distribution information and target test conditions of the wafer to be tested, wherein the chip distribution information includes multiple chips arranged in a matrix and test requirement information of each chip; Generate candidate test steps corresponding to the wafer to be tested according to the test capability of the probe card and the position coordinate information of the plurality of chips, wherein the candidate test steps include the position coordinate information of the chips covered by the probe card in a single time; A target test scheme for the wafer to be tested is determined according to the candidate test steps, wherein the target test scheme includes a plurality of target test steps and the target test scheme satisfies the target test conditions.

[0005] According to one aspect of the present application, a computer device is provided, the device comprising: Processor; and A memory arranged to store computer executable instructions which, when executed, cause the processor to perform the operations of any of the methods described above.

[0006] According to one aspect of the present application, a computer-readable medium storing instructions is provided, wherein when the instructions are executed, the system performs the operation of any of the methods described above.

[0007] Compared with the prior art, this application obtains the chip distribution information and target test conditions of the wafer to be tested, generates candidate test steps corresponding to the wafer to be tested according to the test capability of the probe card and the position coordinate information of multiple chips; and determines the target test plan of the wafer to be tested according to the candidate test steps. The purpose of automatically and intelligently determining the target test plan that meets the target test conditions is achieved. The intelligent determination of the test path is realized, and the efficiency is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings: Figure 1 A flow chart of a method for determining a target test scheme according to an embodiment of the present application is shown; Figure 2 Shows chip distribution information according to an embodiment of the present application; Figure 3 shows chip distribution information according to another embodiment of the present application; Figure 4 A schematic diagram of a device structure for determining a target test scheme according to an embodiment of the present application is shown; Figure 5 An exemplary system is shown that can be used to implement the various embodiments described in this application. DETAILED DESCRIPTION

[0009] The present application is described in further detail below in conjunction with the accompanying drawings.

[0010] In a typical configuration of the present application, the terminal, the device of the service network and the trusted party all include one or more processors (eg, a central processing unit (CPU)), an input / output interface, a network interface and a memory.

[0011] Memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash memory. Memory is an example of a computer-readable medium.

[0012] Computer readable media include permanent and non-permanent, removable and non-removable media that can be used to store information by any method or technology. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, Phase-Change Memory (PCM), Programmable Random Access Memory (PRAM), Static Random-Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of random access memory (RAM), Read-Only Memory (ROM), Electrically-Erasable Programmable Read-Only Memory (EEPROM), Flash memory or other memory technology, Compact Disc Read-Only Memory (CD-ROM), Digital Versatile Disc (DVD) or other optical storage, magnetic cassettes, tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.

[0013] The devices referred to in this application include but are not limited to terminals, network devices, or devices formed by integrating terminals and network devices through a network. The terminal includes but is not limited to any mobile electronic product that can interact with a user (for example, interact with a user through a touchpad), such as a smart phone, a tablet computer, etc. The mobile electronic product can use any operating system, such as an Android operating system, an iOS operating system, etc. Among them, the network device includes an electronic device that can automatically perform numerical calculations and information processing according to pre-set or stored instructions, and its hardware includes but is not limited to a microprocessor, an application specific integrated circuit (ASIC), a programmable logic device (PLD), a field programmable gate array (FPGA), a digital signal processor (DSP), an embedded device, etc. The network device includes but is not limited to a computer, a network host, a single network server, a plurality of network server sets or a cloud composed of multiple servers; here, the cloud is composed of a large number of computers or network servers based on cloud computing (Cloud Computing), wherein cloud computing is a type of distributed computing, a virtual supercomputer composed of a group of loosely coupled computer sets. The network includes but is not limited to the Internet, wide area network, metropolitan area network, local area network, VPN network, wireless self-organizing network (Ad Hoc network), etc. Preferably, the device may also be a program running on the terminal, network device, or a device formed by integrating the terminal and network device, network device, touch terminal, or network device and touch terminal through a network.

[0014] Of course, those skilled in the art should understand that the above-mentioned devices are only examples, and other existing or future devices that are applicable to the present application should also be included in the scope of protection of the present application and are included here by reference.

[0015] In the description of the present application, “plurality” means two or more, unless otherwise clearly and specifically defined.

[0016] Figure 1A flow chart of a method for optimizing the number of probe card contacts according to an embodiment of the present application is shown, and the method includes step S11, step S12, and step S13. In step S11, the chip distribution information and target test conditions of the wafer to be tested are obtained, wherein the chip distribution information includes multiple chips arranged in a matrix and the test requirement information of each chip; in step S12, candidate test steps corresponding to the wafer to be tested are generated according to the test capability of the probe card and the position coordinate information of the multiple chips, wherein the candidate test steps include the position coordinate information of the chip covered by the probe card at a single time; in step S13, the target test scheme of the wafer to be tested is determined according to the candidate test steps, wherein the target test scheme includes multiple target test steps, and the target test scheme meets the target test conditions.

[0017] Specifically, in step S11, the chip distribution information and target test conditions of the wafer to be tested are obtained, wherein the chip distribution information includes a plurality of chips arranged in a matrix and test requirement information for each chip. In some embodiments, the test requirement information includes whether it needs to be tested or not. In some embodiments, reference Figure 2 The multiple chips arranged in a matrix as shown and the test requirement information of each chip. The system uses 1 to represent the chip that needs to be tested and 0 to represent the chip that does not need to be tested. By marking the test requirements of the chip, unnecessary testing is avoided. In some embodiments, the method of this solution can be implemented by a corresponding software APP. For example, an input window is set in the system interface, and the user can enter information such as the target test conditions through the input window (for example, the user name and other information can also be entered). In some embodiments, the target test conditions include but are not limited to test coverage and the number of multiple contact chips. For example, the test coverage needs to reach the target test coverage, and the number of multiple contact chips needs to be less than the target number of multiple contact chips. In some embodiments, the test coverage includes the ratio between the number of new chips that the test scheme can test and the total number of new chips, wherein the new chips include the chips that need to be tested. For example, the test scheme includes multiple test steps, each test step can test one or more new chips, and the test coverage includes the ratio between the number of new chips that the test scheme can test and the total number of new chips that need to be tested. The number of multiple contact chips includes the number of chips that are contacted multiple times by the probe card during the test process. For example, if test step A contacts new chip A, and test step B also contacts new chip A, then the new chip A is a multi-contact chip.

[0018] In step S12, candidate test steps corresponding to the wafer to be tested are generated based on the test capability of the probe card and the position coordinate information of multiple chips, wherein the candidate test steps include the position coordinate information of the chips covered by the probe card in a single test. Here, those skilled in the art will understand that the test capability of the probe card includes the number and range of chips (DUT) that the probe card can cover in one test operation. Specifically, the number of needles on the probe card determines the number of chips that can be tested simultaneously in each test (for example, a four-needle probe card can test four chips at the same time). The needle layout of the probe card determines the range of chips covered in each test (for example, a 2x2 area). In some embodiments, the system traverses multiple chips arranged in a matrix according to the test capability of the probe card, and generates candidate test steps corresponding to the wafer to be tested, so that all candidate test steps can cover multiple chips arranged in the matrix. For example, refer to Figure 2 , the position coordinate information of the chip located in the upper left corner includes (1,1), and so on, the position coordinate information of the chip located in the lower right corner includes (5,6). The system traverses the multiple chips arranged in the entire matrix and generates candidate test steps that can cover the multiple chips arranged in the entire matrix. For example, the test capability of the probe card includes testing 4 chips at a time, and the test range is 2x2 area. Figure 2 The candidate test steps corresponding to the multiple chips arranged in the matrix shown include candidate test step A: (1,1), (1,2), (2,1), (2,2); candidate test step B: (1,2), (1,3), (2,2), (2,3); candidate test step C: (1,3), (1,4), (2,3), (2,4); candidate test step D: (1,4), (1,5), (2,4), (2,5); candidate test step E: (2,1), (2,2), (3,1), (3,2); candidate test step F: (2,2), (2,3), (3,2), (3,3)...Candidate test step P: (4,4), (4,5), (5,4), (5,5).

[0019] In step S13, a target test scheme for the wafer to be tested is determined according to the candidate test steps, wherein the target test scheme includes multiple target test steps, and the target test scheme meets the target test conditions. In some embodiments, an initial test scheme can be generated according to the candidate test steps, and then the target test scheme can be obtained by optimizing the initial test scheme. For the specific description of this part, please refer to the corresponding embodiment below, which will not be repeated here. In some embodiments, the test scheme includes multiple test steps, and whether the test scheme meets the target test conditions can be determined by calculating the test coverage of the test scheme and the number of multiple contact chips. For example, the test scheme includes test step A: (1,1), (1,2), (2,1), (2,2); test step C: (1,3), (1,4), (2,3), (2,4). The chips to be tested include (1,1), (1,2), (1,3), (2,1), (2,2), (2,3), (1,5), (2,5). Then the test coverage of the test scheme is 75%, and the number of multiple contact chips is 0.

[0020] In some embodiments, the method further includes step S14 (not shown) before step S13. In step S14, if the candidate test step meets the exclusion condition, the candidate test step is excluded to obtain the candidate test step after exclusion screening. In some embodiments, in order to improve the analysis speed and accuracy, the test steps that will definitely not be used as the target test scheme are excluded. In some embodiments, the exclusion conditions include but are not limited to the candidate test steps not including the chips that need to be tested and the candidate test steps including the chips outside the effective area. For example, if there is a candidate test step, and the test requirement information of the chip included in the candidate test step does not need to be tested, then the candidate test step can be directly excluded. Of course, those skilled in the art will understand that the exclusion conditions described above are only examples, and other or existing possible exclusion conditions that can be applied to the present application are also within the scope of protection of the present application.

[0021] In some embodiments, the exclusion condition includes a chip outside the effective area in the candidate test step, and the method further includes step S15 (not shown). In step S15, the diameter of the effective area of ​​the wafer to be tested is determined according to a wafer effective area calculation algorithm, wherein the calculation algorithm includes , where r includes the diameter of the effective area, R includes the wafer diameter, and L includes the edge width of the wafer to be tested; if there is a target candidate test step in the candidate test step, the target candidate test step is deleted, wherein the target candidate test step includes chips outside the effective area. In some embodiments, the edge area of ​​the wafer is generally not suitable for testing because the chips at the edge may be incomplete or defective. The effective area includes areas other than the edge area. If the chips included in the candidate test step exceed the effective area, it may cause test failure or waste of resources. In some embodiments, if a candidate test step includes chips outside the effective area, the candidate test step is deleted as a target candidate test step. In some embodiments, the system can detect chips outside the effective area by calculating the distance of each chip from the center of the wafer according to the position coordinate information of each chip. For example, if there is a target candidate test step, the candidate test step includes chips (6,1), (6,2), (7,1), (7,2), wherein the distance of (7,1) from the center of the wafer is greater than the radius r of the effective area, the candidate test step is deleted as a target candidate test step.

[0022] In some embodiments, step S13 includes step S131 (not shown) and step S132 (not shown). In step S131, an initial test plan for the wafer to be tested is generated according to the candidate test steps; in step S132, the initial test plan is optimized by an optimization algorithm to generate a target test plan for the wafer to be tested, wherein the target test plan satisfies the target test conditions. In some embodiments, multiple candidate test steps can be randomly selected as the initial test plan. In other embodiments, the initial test plan can be determined based on the number of new chips included in the candidate test steps. For the specific description of this part, please refer to the corresponding embodiment below, which will not be repeated here. After determining the initial test plan, the initial test plan is optimized by an optimization algorithm to obtain a target test plan that meets the target test conditions.

[0023] In some embodiments, step S131 includes: initializing a chip set, wherein the chip set includes chips that need to be tested from multiple chips; preferably including the candidate test step with the largest number of chips in the chip set as the initial test step in the initial test plan; deleting the chip included in the initial test step from the chip set to update the chip set; preferably including the candidate test step with the largest number of chips in the updated chip set from the remaining candidate test steps as the initial test step in the initial test plan; repeating the above steps until the number of chips in the chip set is zero to obtain the initial test plan. For example, the system initializes the chip set that needs to be tested. For example, the chip set that needs to be tested includes (1,1), (1,2), (1,3), (1,5), (2,1), (2,2), (2,3), (2,5). The candidate test steps include candidate test step A: (1,1), (1,2), (2,1), (2,2); candidate test step B: (1,2), (1,3), (2,2), (2,3); candidate test step C: (1,3), (1,4), (2,3), (2,4); candidate test step D: (1,4), (1,5), (2,4), (2,5). Among them, the number of chips required to be tested included in candidate test step A is 4, the number of chips required to be tested included in candidate test step B is 4, the number of chips required to be tested included in candidate test step C is 2, and the number of chips required to be tested included in candidate test step D is 2. According to the number of chips required to be tested, the candidate test step with the largest number is preferentially selected. For example, it is preferentially selected from candidate test steps A and B, and it can be randomly selected from candidate test steps A and B. For example, candidate test step A is selected as a test step in the initial test plan. The chip set required to be tested is updated to (1,3), (1,5), (2,3), (2,5). In some embodiments, each time a candidate test step is selected, the chip included in the selected candidate test step is deleted from the chip set that needs to be tested to update the chip set in real time. Then, based on the updated chip set, the candidate test step that includes the largest number of chips in the chip set is selected from the remaining candidate test steps as the test step in the initial test plan. For example, candidate test step B, candidate test step C, and candidate test step D all include chips from 2 chip sets, then candidate test step B is randomly determined as the test step in the initial test plan. The updated chip set is (1,5), (2,5). The number of chips included in candidate test step C in the updated chip set is 0, and the number of chips included in candidate test step D in the updated chip set is 2, then candidate test step D is selected as the test step in the initial test plan. The initial test plan includes candidate test step A, candidate test step B, and candidate test step D.

[0024] In some embodiments, step S132 includes: calculating the fitness of each initial test solution, where: , where f includes fitness, a includes test coverage, b includes the number of test steps, and x includes weight; the initial test scheme with fitness equal to or greater than the first fitness threshold is subjected to crossover and mutation processing to obtain a target test scheme that meets the target test condition, wherein the fitness of the target test condition is equal to or greater than the second fitness threshold. In some embodiments, multiple initial test schemes may be included, including but not limited to the initial test scheme determined by the chip set mentioned in the above embodiments, the initial test scheme determined randomly, or the initial test scheme specified by the user (for example, the user specifies the initial test scheme through the input window on the system interface). After obtaining the initial test scheme, the system calculates the fitness of each initial test scheme. In some embodiments, the test coverage includes the ratio of the number of chips that can be tested by the initial test scheme to the total number of chips that need to be tested. For example, the above initial test scheme includes candidate test step A, candidate test step B, candidate test step D, the number of steps is 3, the test coverage is 100%, and the weight is 0.1, then the fitness f=1-3*0.3=0.7. The system presets a first fitness threshold, and selects an initial test scheme with a fitness equal to or greater than the first fitness threshold for optimization. The optimization algorithm includes but is not limited to crossover and mutation processing in the genetic algorithm. For example, the initial test scheme X includes step B, step E, and step D, and the crossover point is 1, then the new initial test scheme obtained after the crossover is: step B, step D, step E. For another example, the initial test scheme X includes step B, step E, and step D, and the mutation point (such as step D) is randomly determined to obtain step C, and then step D is replaced with step C. The initial test scheme is iteratively processed by the optimization algorithm until a target test scheme that meets the target test conditions is obtained, and the target test scheme is saved to be presented to the user. In some embodiments, the target test scheme includes multiple target test schemes, and the multiple target test schemes can be ranked according to the fitness, and the top N target test schemes are presented to the user through the system interface. In some embodiments, there is also a backtracking mechanism. For example, if the fitness of the test scheme obtained by optimization is smaller than that before optimization, then backtrack to the test scheme before optimization. For example, if the fitness of steps B, D, and E obtained by the initial test scheme X after the cross processing is less than that of steps B, E, and D before the cross processing, then backtrack to steps B, E, and D before the cross processing.

[0025] In some embodiments, step S12 includes: dividing the wafer to be tested into multiple areas; for each area, generating candidate test steps corresponding to the area according to the test capability of the probe card, the position coordinate information of multiple chips, and the test requirement information of each chip, wherein the candidate test steps include the coordinate information of the chips covered by the probe card at a single time; for each area, determining the target test scheme of the area according to the candidate test steps corresponding to the area, and each time the target test scheme of an area is determined, querying whether there is the same area from the area where the target test scheme has not been determined according to the chip layout of the area, and the same area is the same as the chip layout of the area; if there is the same area, directly determining the target test scheme of the area as the target test scheme of the same area; after determining the target test scheme of each area, merging the target test schemes of multiple areas into the target test scheme of the wafer to be tested. In some embodiments, in order to improve computing power and reduce overall computing pressure. The wafer to be tested is divided into multiple areas (for example, the wafer to be tested is evenly divided into four areas), and for each area, the target test scheme of each area is determined by the above method. After determining the target test scheme for each area, based on the chip layout of the area, it is queried whether there is an identical area with the same chip layout from the area where the target test scheme has not been determined. If there is an identical area in the area, the target test scheme of the area is directly determined as the target test scheme of the same area. In some embodiments, the chip layout includes the arrangement of the chips of the test requirement information and the test requirement information. For example, referring to Figure 3, the wafer is evenly divided into four areas, namely the upper left area, the upper right area, the lower left area, and the lower right area. Among them, the chip layouts of the lower left area and the lower right area are the same. For example, the chip arrangement and test requirement information of the lower left area and the lower right area are the same. If it is determined that the target test scheme for the lower left area includes target test steps (3,2), (3,3), (4,2), (4,3), target test steps (3,1), (3,2), (4,1), (4,2), then the target test scheme for the lower right area is directly determined according to the target test scheme for the lower left area (for example, (3,5), (3,6), (4,5), (4,6), target test steps (3,4), (3,5), (4,4), (4,5). In some embodiments, the system uses 1 to indicate a chip that needs to be tested and 0 to indicate a chip that does not need to be tested, and determines whether the chip layouts of the two areas are overlapped by comparing the chip layouts of the areas, for example, by comparing whether the chip layouts of 0 and 1 of the two areas overlap. Are they the same? Therefore, the target test steps of the target test scheme for the lower right area are determined according to the target test steps of the target test scheme for the lower left area. Specifically, the target test scheme for the lower right area can be determined according to the order between the target test steps in the lower left area. For example, the target test steps included in the target test scheme for the lower left area are sequentially distributed throughout the lower left area from right to left, and the target test scheme for the lower right area is also sequentially distributed throughout the lower right area from right to left. Of course, those skilled in the art will appreciate that the specific process of determining the target test scheme for the same area as the chip layout in the area according to the target test scheme for the area described above is only an example, and other existing or future specific processes that may appear are also within the scope of protection of the present application if they are applicable to the present application.

[0026] Figure 4 A schematic diagram of the structure of a device for determining a target test scheme according to an embodiment of the present application is shown, the device includes module 11, module 12, and module 13, module 11 is used to obtain chip distribution information and target test conditions of a wafer to be tested, wherein the chip distribution information includes multiple chips arranged in a matrix and test requirement information for each chip; module 12 is used to generate candidate test steps corresponding to the wafer to be tested according to the test capability of a probe card and position coordinate information of multiple chips, wherein the candidate test steps include position coordinate information of chips covered by the probe card at a single time; module 13 is used to determine a target test scheme for the wafer to be tested according to the candidate test steps, wherein the target test scheme includes multiple target test steps, and the target test scheme meets the target test conditions.

[0027] Here, the specific implementations of module 11, module 12, module 13 and the corresponding specific implementations are the same as or similar to the specific implementations of step S11, step S12 and step S13, and thus are not described in detail and are included herein by reference.

[0028] In addition to the methods and devices described in the above embodiments, the present application also provides a computer-readable storage medium, which stores computer code. When the computer code is executed, the method described in any of the preceding items is executed.

[0029] The present application also provides a computer program product. When the computer program product is executed by a computer device, the method described in any of the preceding items is executed.

[0030] The present application also provides a computer device, the computer device comprising: one or more processors; a memory for storing one or more computer programs; When the one or more computer programs are executed by the one or more processors, the one or more processors are caused to implement the method as described in any of the preceding items.

[0031] Figure 5 An exemplary system that can be used to implement various embodiments described in this application is shown; like Figure 5 In some embodiments shown, the system 300 can be used as any of the devices in the various described embodiments. In some embodiments, the system 300 may include one or more computer-readable media (e.g., system memory or NVM / storage device 320) with instructions and one or more processors (e.g., (one or more) processors 305) coupled to the one or more computer-readable media and configured to execute instructions to implement modules to perform the actions described in this application.

[0032] For one embodiment, system control module 310 may include any suitable interface controller to provide any suitable interface to at least one of processor(s) 305 and / or any suitable device or component in communication with system control module 310 .

[0033] The system control module 310 may include a memory controller module 330 to provide an interface to the system memory 315. The memory controller module 330 may be a hardware module, a software module, and / or a firmware module.

[0034] The system memory 315 may be used, for example, to load and store data and / or instructions for the system 300. For one embodiment, the system memory 315 may include any suitable volatile memory, such as a suitable DRAM. In some embodiments, the system memory 315 may include double data rate type four synchronous dynamic random access memory (DDR4 SDRAM).

[0035] For one embodiment, system control module 310 may include one or more input / output (I / O) controllers to provide interfaces to NVM / storage device 320 and communication interface(s) 325 .

[0036] For example, NVM / storage device 320 may be used to store data and / or instructions. NVM / storage device 320 may include any suitable non-volatile memory (e.g., flash memory) and / or may include any suitable non-volatile storage device(s) (e.g., one or more hard disk drives (HDDs), one or more compact disk (CD) drives, and / or one or more digital versatile disk (DVD) drives).

[0037] NVM / storage device 320 may include storage resources that are physically part of the device on which system 300 is installed, or it may be accessible to the device without being part of the device. For example, NVM / storage device 320 may be accessed over a network via communication interface(s) 325.

[0038] Communication interface(s) 325 may provide an interface for system 300 to communicate over one or more networks and / or with any other suitable devices. System 300 may wirelessly communicate with one or more components of a wireless network in accordance with any of one or more wireless network standards and / or protocols.

[0039] For one embodiment, at least one of the processor(s) 305 may be packaged together with the logic of one or more controllers of the system control module 310 (e.g., the memory controller module 330). For one embodiment, at least one of the processor(s) 305 may be packaged together with the logic of one or more controllers of the system control module 310 to form a system-in-package (SiP). For one embodiment, at least one of the processor(s) 305 may be integrated on the same die with the logic of one or more controllers of the system control module 310. For one embodiment, at least one of the processor(s) 305 may be integrated on the same die with the logic of one or more controllers of the system control module 310 to form a system on chip (SoC).

[0040] In various embodiments, the system 300 may be, but is not limited to: a server, a workstation, a desktop computing device, or a mobile computing device (e.g., a laptop computing device, a handheld computing device, a tablet computer, a netbook, etc.). In various embodiments, the system 300 may have more or fewer components and / or a different architecture. For example, in some embodiments, the system 300 includes one or more cameras, a keyboard, a liquid crystal display (LCD) screen (including a touch screen display), a non-volatile memory port, multiple antennas, a graphics chip, an application specific integrated circuit (ASIC), and a speaker.

[0041] It should be noted that the present application can be implemented in software and / or a combination of software and hardware, for example, it can be implemented using an application-specific integrated circuit (ASIC), a general-purpose computer or any other similar hardware device. In one embodiment, the software program of the present application can be executed by a processor to implement the steps or functions described above. Similarly, the software program of the present application (including related data structures) can be stored in a computer-readable recording medium, for example, a RAM memory, a magnetic or optical drive or a floppy disk and the like. In addition, some steps or functions of the present application can be implemented using hardware, for example, as a circuit that cooperates with a processor to perform various steps or functions.

[0042] In addition, a part of the present application may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present application through the operation of the computer. Those skilled in the art should understand that the existence of computer program instructions in computer-readable media includes but is not limited to source files, executable files, installation package files, etc., and accordingly, the way in which computer program instructions are executed by a computer includes but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to the computer.

[0043] Communication media include media by which communication signals containing, for example, computer readable instructions, data structures, program modules, or other data are transmitted from one system to another. Communication media may include guided transmission media such as cables and wires (e.g., fiber optic, coaxial, etc.) and wireless (unguided transmission) media that can propagate energy waves, such as acoustic, electromagnetic, RF, microwave, and infrared. Computer readable instructions, data structures, program modules, or other data may be embodied as a modulated data signal in, for example, a wireless medium such as a carrier wave or similar mechanism such as embodied as part of spread spectrum technology. The term "modulated data signal" refers to a signal whose one or more characteristics are changed or set in such a manner as to encode information in the signal. Modulation may be analog, digital, or a hybrid modulation technique.

[0044] By way of example and not limitation, computer-readable storage media may include volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules or other data. For example, computer-readable storage media include, but are not limited to, volatile memory, such as random access memory (RAM, DRAM, SRAM); and non-volatile memory, such as flash memory, various read-only memories (ROM, PROM, EPROM, EEPROM), magnetic and ferromagnetic / ferroelectric memories (MRAM, FeRAM); and magnetic and optical storage devices (hard disks, magnetic tapes, CDs, DVDs); or other media now known or later developed that can store computer-readable information / data for use with a computer system.

[0045] Here, according to an embodiment of the present application, a device is included, which includes a memory for storing computer program instructions and a processor for executing the program instructions, wherein, when the computer program instructions are executed by the processor, the device is triggered to run the methods and / or technical solutions based on the aforementioned multiple embodiments of the present application.

[0046] It is obvious to those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application.

Claims

1. A method for determining a target test scheme, characterized in that: The method comprises: Obtain chip distribution information and target test conditions of a wafer to be tested, wherein the chip distribution information includes a plurality of chips arranged in a matrix and test requirement information of each chip; Generating candidate test steps corresponding to the wafer to be tested according to the test capability of the probe card and the position coordinate information of the plurality of chips, wherein the candidate test steps include the position coordinate information of the chips covered by the probe card at a single time; A target test scheme for the wafer to be tested is determined according to the candidate test steps, wherein the target test scheme includes a plurality of target test steps and the target test scheme satisfies the target test condition.

2. The method according to claim 1, characterized in that: The step of generating candidate tests corresponding to the wafer to be tested according to the test capability of the probe card and the position coordinate information of the plurality of chips includes: According to the test capability of the probe card, the multiple chips arranged in the matrix are traversed to generate candidate test steps corresponding to the wafer to be tested, so that all the candidate test steps can cover the multiple chips arranged in the matrix.

3. The method according to claim 1, characterized in that The method further comprises, before determining the target test scheme of the wafer to be tested according to the candidate test steps: If the candidate test step meets the exclusion condition, the candidate test step is excluded.

4. The method according to claim 3, characterized in that The exclusion condition includes that the candidate test step includes chips outside the effective area, and the method further includes: The diameter of the effective area of ​​the wafer to be tested is determined according to a wafer effective area calculation algorithm, wherein the calculation algorithm includes , here, the r includes the diameter of the effective area, the R includes the wafer diameter, and the L includes the edge width of the wafer to be tested; If there is a target candidate test step in the candidate test steps, the target candidate test step is deleted, wherein the target candidate test step includes chips outside the effective area.

5. The method according to claim 1, characterized in that Determining a target test scheme for the wafer to be tested according to the candidate test steps includes: Generate an initial test plan for the wafer to be tested according to the candidate test steps; The initial test plan is optimized by an optimization algorithm to generate a target test plan for the wafer to be tested, wherein the target test plan satisfies the target test condition.

6. The method according to claim 5, characterized in that Generating an initial test plan for the wafer to be tested according to the candidate test steps includes: Initializing a chip set, wherein the chip set includes chips that need to be tested among the multiple chips; Preferably, the candidate test step including the largest number of chips in the chip set is used as the initial test step in the initial test scheme; Deleting the chips included in the initial testing step from the chip set to update the chip set; Preferentially including the candidate test step with the largest number of chips in the updated chip set from the remaining candidate test steps as the initial test step in the initial test scheme; The above steps are repeated until the number of chips in the chip set is zero, so as to obtain the initial test plan.

7. The method according to claim 5, characterized in that The optimizing the initial test plan by using an optimization algorithm to generate a target test plan for the wafer to be tested includes: Calculate the fitness of each initial test solution, where , where f includes the fitness, a includes the test coverage, b includes the number of test steps, and x includes the weight; An initial test scheme whose fitness is equal to or greater than a first fitness threshold is subjected to crossover and mutation processing to obtain a target test scheme that meets the target test condition, wherein the fitness of the target test condition is equal to or greater than a second fitness threshold.

8. The method according to claim 1, characterized in that The step of generating candidate tests corresponding to the wafer to be tested according to the test capability of the probe card and the position coordinate information of the plurality of chips includes: Dividing the wafer to be tested into a plurality of areas; For each area, generating candidate test steps corresponding to the area according to the test capability of the probe card, the position coordinate information of multiple chips in the area, and the test requirement information of each chip, wherein the candidate test steps include the coordinate information of the chips covered by the probe card at a single time; For each region, a target test scheme for the region is determined according to the candidate test steps corresponding to the region. After a target test scheme for a region is determined, a query is made based on the chip layout of the region to determine whether there is an identical region in the region where the target test scheme has not been determined. The identical region has the same chip layout as the region. If the same area exists in the area, the target test scheme directly based on the area is determined as the target test scheme for the same area; After determining the target test scheme for each area, the target test schemes for multiple areas are merged into the target test scheme for the wafer to be tested.

9. A computer device for determining a target test scheme, comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program / instruction stored thereon, characterized in that: When the computer program / instructions are executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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