Preparation method of wafer

Abstract

The invention belongs to the technical field of semiconductors, and discloses a wafer preparation method which comprises the following steps: preparing a wafer transition structure, and performing graphical etching on a transition layer of the wafer transition structure to form a drain electrode and a third electrode; a gate electrode window and a source electrode window are etched downwards from the second dielectric layer of the wafer transition structure, or a gate electrode window, a source electrode window and a drain electrode window are etched, and a wafer is obtained; the transition layer of the wafer transition structure covers part of the front surface of the wafer transition structure, the front surface of the wafer transition structure is short-circuited to serve as an upper electrode of the wafer transition structure, and the back surface of the wafer transition structure is short-circuited to serve as a lower electrode of the wafer transition structure; each of the wafer transition structure and the wafer comprises a plurality of chips, three ends of a first resistance electrode of each chip are connected, a second resistance electrode of each chip penetrates through the laminated structure and the first dielectric layer, one end of the second resistance electrode of each chip is located in the substrate, and the other end of the second resistance electrode of each chip is located in the second dielectric layer.

Description

[0001] This application is a divisional application of the invention patent application with the application date of September 24, 2024, application number 2024113283074, and invention name "Wafer transition structure, wafer and preparation method thereof, aging test device and aging test method". Technical Field

[0002] The invention belongs to the technical field of wafer testing, and in particular relates to a method for preparing a wafer. Background Art

[0003] The curve of the failure rate of power devices changing with time conforms to the law of the "bathtub curve", which is divided into early failure period, accidental failure period, and wear-out failure period. The failure rate is high in the early failure stage, but it decreases rapidly with time. The failure causes in this stage are mainly caused by defects in design, raw materials, and manufacturing processes. In the accidental failure stage, the failure rate is reduced to a relatively low level, reflecting a stable state, and the failure rate is approximately constant. The failures in this stage are mainly caused by accidental factors. The accidental failure stage is the main working period of the product. In the wear-out failure stage, the failure rate rises rapidly with time, and product failures soon increase in large numbers until they are finally scrapped, which is related to the design life of the device. One of the ultimate goals of reliability work is to take measures such as environmental stress to screen devices, reduce the early failure rate, and ensure that the product is in the accidental failure period when it reaches the user. Especially for GaN third-generation semiconductors and wide bandgap compound semiconductors, there is lattice mismatch in epitaxial materials, which causes various epitaxial defects, and there are also problems such as immaturity and many defects in the process. It is easy to cause a high early failure rate, which is difficult to meet the needs of industrial control and automotive regulations. Therefore, how to effectively screen out early failures of power devices is an urgent problem to be solved in the field of manufacturing and application of third-generation semiconductor power devices.

[0004] In this regard, the prior art has tested the devices through a wafer-level test (Burn-in), which uses a needle card with hundreds to thousands of pins to pin and fix the multiple electrodes of each chip on the wafer one by one, put it into an oven, and connect it to the outside through the needle card to form a separate circuit for each device, which is connected to hundreds to thousands of external fuses or fast-fuse resistors and finally connected to the main power supply. The main problems with this method in the industry are as follows:

[0005] (1) The equipment cost is extremely high. Even the steps of needle card and wafer needle insertion require large equipment. The cost of needle card consumables is extremely high. Any chip failure may cause the probe in contact with it to burn, thus causing damage to the entire needle card.

[0006] (2) The external loop is extremely complex. Each chip corresponds to an external loop, with hundreds of loops. The operation of replacing fuses or fast-fuse resistors is cumbersome and complicated.

[0007] (3) Especially heteroepitaxial growth or thick metal in the wafer will cause wafer warping, which will lead to uncontrollable needle penetration of the entire wafer, and it is very likely to cause local false connection problems, causing chip failure or failure to be tested. Summary of the invention

[0008] In view of this, in order to overcome the defects of the prior art, the purpose of the present invention is to provide a method for preparing a wafer, wherein the wafer transition structure can be used for wafer-level assessment, and even if individual chips fail, the assessment of the entire wafer can still continue.

[0009] In order to achieve the above object, the present invention adopts the following technical solutions:

[0010] The present invention provides a wafer transition structure, comprising a plurality of chips, wherein one side of the wafer transition structure has a transition layer, and each of the chips comprises a source electrode, a drain electrode, a gate electrode, a first resistor, a second resistor, a first resistor electrode, a second resistor electrode, a field plate, a connecting section, and a substrate, a stacked structure, a first dielectric layer, and a second dielectric layer arranged in sequence from bottom to top, wherein the second dielectric layer is close to the transition layer, the source electrode is located in the stacked structure and the first dielectric layer, the drain electrode is located in the stacked structure, the first dielectric layer, and the second dielectric layer, and the gate electrode is located in the first dielectric layer; the connecting section is used to connect the gate electrode and the first resistor electrode, and the drain electrode is also connected to the transition layer; the field plate is connected to the gate electrode and the connecting section, the first resistor electrode is connected to the gate electrode and the first resistor, and the first resistor electrode is also connected to the second resistor or the substrate, and the resistance value of the first resistor is greater than the resistance value of the second resistor;

[0011] The source electrodes of all the chips of the wafer transition structure are connected in parallel to the substrate, and the transition layer is used to connect the drain electrodes of all the chips of the wafer transition structure in parallel.

[0012] In some embodiments of the present invention, the first resistor is a cascade resistor, the second resistor is a protection resistor, the resistance of the first resistor is 100Ω~100MΩ, preferably 1~20MΩ, and the resistance of the second resistor is 1Ω~1MΩ, preferably 1~100kΩ.

[0013] The present invention temporarily connects the three-terminal normally-on chip to a normally-off chip with two ends (high-level connection end and low-level connection end) through chip design, and after all chips are connected in series with protection resistors, the high-level connection end (the front of the wafer transition structure) is short-circuited as the upper electrode of the wafer transition structure, and the low-level connection end (the back of the wafer transition structure) is short-circuited as the lower electrode of the wafer transition structure. Finally, the whole wafer transition structure outputs only two electrodes, which greatly simplifies the difficulty of wafer-level assessment. And the wafer transition structure realizes that all chips are connected in series with protection resistors respectively. When the chip under test breaks down, the branch protection resistor is fused, so that other branch assessments can still continue.

[0014] Specifically, in some embodiments of the present invention, the source electrode of the chip is connected in series to a cascade resistor (first resistor), the other end of the cascade resistor is connected to the gate electrode of the chip, and only the drain electrode is used as a high-level connection terminal. The gate electrode is connected in series with a protective resistor (second resistor), and the other end of the protective resistor is used as a low-level connection terminal. The high and low levels are short-circuited respectively to serve as the upper and lower electrodes of the entire wafer transition structure.

[0015] Specifically, in some other embodiments of the present invention, the source electrode of the chip is connected in series to a cascade resistor (first resistor), the other end of the cascade resistor is connected to the gate electrode of the chip, and one end of the gate electrode is used as a low-level connection terminal; the protection resistor (second resistor) is located between the drain electrode and the high-level connection terminal. The high and low levels are short-circuited respectively to serve as the upper and lower electrodes of the entire wafer transition structure.

[0016] According to some preferred embodiments of the present invention, the drain electrode includes a drain electrode body electrode and a drain electrode first electrode, the drain electrode body electrode is located below the drain electrode first electrode, a portion of the drain electrode body electrode is located in the stacked structure, another portion of the drain electrode body electrode is located in the first dielectric layer, a portion of the drain electrode first electrode is located in the first dielectric layer, and another portion of the drain electrode first electrode is located in the second dielectric layer.

[0017] According to some preferred implementation aspects of the present invention, one end of the drain electrode first electrode is connected to the transition layer, and the other end of the drain electrode first electrode is connected to the drain electrode body electrode.

[0018] According to some preferred embodiments of the present invention, the drain electrode also includes a drain electrode second electrode, the drain electrode second electrode is located between the drain electrode body electrode and the drain electrode first electrode, one end of the drain electrode second electrode is connected to one end of the second resistor, the other end of the drain electrode second electrode is connected to the drain electrode body electrode, and the other end of the second resistor is connected to one end of the drain electrode first electrode.

[0019] According to some preferred embodiments of the present invention, one end of the second resistor electrode is connected to the substrate, the other end of the second resistor electrode is connected to the second resistor, and one end of the second resistor away from the second resistor electrode is connected to the first resistor electrode.

[0020] Preferably, the upper surface (front side) of one of the wafer transition structures provided by the present invention is the drain electrodes of all chips connected in parallel, and the lower surface (back side) is the source electrodes of all chips connected to their respective cascade resistors and then to their respective gate electrodes. Furthermore, the respective gate electrodes are connected to their respective protection resistors and then uniformly connected in parallel to the substrate.

[0021] According to some preferred implementation aspects of the present invention, one end of the second resistor electrode is connected to the substrate, and the other end of the second resistor electrode is connected to the first resistor electrode, so that the first resistor electrode is also connected to the substrate.

[0022] Preferably, the upper surface (front side) of another wafer transition structure provided by the present invention is connected in parallel to one end of the protection resistor of each chip, and the other end of the protection resistor is respectively connected to the drain electrode of each chip, and the lower surface (back side) is connected to the source electrodes of all chips, which are respectively connected to their respective cascade resistors and then to their respective gate electrodes, and then uniformly connected in parallel to the substrate.

[0023] According to some preferred implementation aspects of the present invention, the thickness of the transition layer is 0.5 to 8 μm. Preferably, the thickness of the transition layer is 4 to 6 μm.

[0024] The present invention also provides a method for preparing the above-mentioned wafer transition structure, comprising the following steps:

[0025] Selecting a conductive material as a substrate, performing epitaxial growth of nitride on the substrate, and sequentially forming a nucleation layer, a buffer layer, a channel layer, a barrier layer and a cap layer, wherein the nucleation layer, the buffer layer, the channel layer, the barrier layer and the cap layer constitute a stacked structure;

[0026] On the capping layer of the stacked structure, a patterning process is performed and ion materials are injected to form an electrical isolation region, and the structure of the first resistor is realized during isolation;

[0027] On the cap layer of the stacked structure, a source electrode hole, a drain electrode body electrode hole and a first resistor electrode hole are formed by etching;

[0028] Filling metal into the source electrode hole, the drain electrode body electrode hole and the first resistor electrode hole, performing annealing to form ohmic contacts, and forming a source electrode, a drain electrode body electrode and a first resistor electrode respectively;

[0029] Depositing a first dielectric layer on the source electrode, the drain electrode, the body electrode and the first resistor electrode, and etching a gate electrode hole, a through hole and a second resistor electrode hole, or etching a gate electrode hole, a through hole, a drain electrode second electrode hole and a second resistor electrode hole;

[0030] Filling metal on the first dielectric layer and etching away excess metal to form a gate electrode and a field plate, a connecting segment, a second resistor and a second resistor electrode, or forming a gate electrode and a field plate, a connecting segment, a second resistor, a second resistor electrode and a drain electrode second electrode;

[0031] Depositing a second dielectric layer on the gate electrode, the field plate and the connecting section, and etching a first electrode hole for the drain electrode;

[0032] Metal is filled on the second dielectric layer to form a drain electrode, a first electrode and a transition layer to obtain the wafer transition structure.

[0033] The electrode connection of the chip of the present invention is achieved through metal connection, and there is no virtual connection problem, which is beneficial to improving the reliability of the assessment process.

[0034] The present invention further provides a method for preparing a wafer, comprising the following steps:

[0035] The wafer transition structure is prepared by the above-mentioned method for preparing the wafer transition structure, and then the transition layer is patterned and etched to form a drain electrode and a third electrode;

[0036] A gate electrode opening window and a source electrode opening window are etched downward from the second dielectric layer, or a gate electrode opening window, a source electrode opening window and a drain electrode opening window are etched downward to obtain the wafer.

[0037] The wafer transition structure of the present invention can be directly used for wafer-level assessment. After the assessment is completed, the wafer transition structure can be used to remove the transition layer through graphic etching and etch out the opening windows corresponding to each electrode, so that each chip can restore each functional electrode, complete the complete wafer process to obtain a wafer, which can be used for subsequent testing, screening, cutting, and packaging devices.

[0038] The present invention also provides a wafer, which is prepared by the wafer preparation method as described above, and the wafer includes multiple chips, each of which includes a source electrode, a drain electrode, a gate electrode, a first resistor, a second resistor, a first resistor electrode, a second resistor electrode, a field plate, a connecting section, and a substrate, a stacked structure, a first dielectric layer, and a second dielectric layer arranged in sequence from bottom to top, the source electrode is located in the stacked structure and the first dielectric layer, the drain electrode is located in the stacked structure, the first dielectric layer and the second dielectric layer, and the gate electrode is located in the first dielectric layer; the connecting section is used to connect the gate electrode and the first resistor electrode; the field plate is connected to the gate electrode and the connecting section, the first resistor electrode is connected to the gate electrode and the first resistor, and the first resistor electrode is also connected to the second resistor or the substrate.

[0039] According to some preferred embodiments of the present invention, the drain electrode includes a drain electrode body electrode, a drain electrode first electrode and a drain electrode third electrode, the drain electrode body electrode is located below the drain electrode first electrode, a portion of the drain electrode body electrode is located in the stacked structure, another portion of the drain electrode body electrode is located in the first dielectric layer, a portion of the drain electrode first electrode is located in the first dielectric layer, another portion of the drain electrode first electrode is located in the second dielectric layer, the drain electrode third electrode is located above the second dielectric layer, and the drain electrode third electrode is connected to the drain electrode first electrode.

[0040] According to some preferred implementation aspects of the present invention, it further includes a gate electrode opening and a source electrode opening, wherein the gate electrode opening is located above the gate electrode, and the source electrode opening is located above the source electrode.

[0041] According to some preferred implementation aspects of the present invention, it further includes a drain electrode opening, wherein the drain electrode opening is located above the drain electrode body electrode.

[0042] The present invention also provides an aging test device for performing an aging test on the wafer transition structure as described above.

[0043] Preferably, the aging test device of the present invention includes a sheet rack, the interior of the sheet rack has a cavity, and a plurality of slot units arranged at intervals are provided on two opposite side walls of the cavity, and each slot unit includes two oppositely arranged slots, which are used to place the wafer transition structure and also limit the position of the wafer transition structure to prevent it from falling. In addition, a first electrode and a second electrode are fixedly provided in one of the slots of a slot unit, and a wafer transition structure is located between the first electrode and the second electrode of a slot, the first electrode contacts the front side of the wafer transition structure, and the second electrode contacts the back side of the wafer transition structure. There is also a certain elastic pressure between the first electrode and the second electrode to ensure that they can form good electrical contact with the front and back sides of the wafer transition structure.

[0044] Preferably, the first electrode in each slot is short-connected to the first wire, the second electrode in each slot is short-connected to the second wire, and finally the first wire and the second wire are centrally led out and connected to the power supply. During the test, the entire aging test device can be placed in an oven, and the wafer-level assessment of the transition structure of the entire wafer can be achieved through centralized power supply.

[0045] Preferably, the card slots in each card slot unit are suitable for all types of chips without compatibility issues.

[0046] The present invention also provides an aging test method, which uses the aging test device as described above to perform an aging test on the wafer transition structure.

[0047] During the test, the wafer transition structure to be assessed is directly inserted into the corresponding card slot in the aging test device, the front and back of each wafer transition structure are respectively connected to the first electrode and the second electrode in the corresponding card slot, the entire aging test device is placed in an oven, the oven temperature is adjusted to -60 to 300°C, the voltage of the power supply is adjusted to 1 to 3000V, and the wafer-level assessment is performed on the entire wafer transition structure, and the assessment time is 0.01 to 1000 hours. The aging test method of the present invention greatly simplifies the operation difficulty and improves production efficiency.

[0048] Due to the adoption of the above technical solution, compared with the prior art, the present invention is beneficial in that:

[0049] (1) Each wafer transition structure has only two electrodes and contains a protection resistor, which greatly simplifies the difficulty of wafer-level testing and significantly increases the density of wafer-level testing;

[0050] (2) Each chip in the wafer transition structure has its own protection resistor, so there is no need to add a fuse or fast-fuse resistor to each chip externally, which greatly simplifies the assessment loop and improves the reliability of the assessment. In addition, the resistance value and fusing capacity of the protection resistor can actually be adjusted through the wafer process, achieving good protection capabilities, so that the power supply of the entire system will not be clamped and pulled down due to failed components, thereby improving the reliability of the assessment system itself.

[0051] (3) The wafer transition structure of the present invention is set so that during the wafer-level assessment process, when a single chip fails, the chip is short-circuited and has a low resistance, and the voltage originally applied to it is applied to the protection resistor connected in series in the chip, causing the power of the protection resistor to be too high and instantly melt, thereby avoiding power supply current protection, so that even if a single chip fails, the assessment of the entire wafer can continue;

[0052] (4) The aging test device of the present invention has a simple structure, and one device can simultaneously test the transition structures of hundreds of wafers, which can effectively reduce the cost of the test equipment and improve the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0054] Figure 1 It is a cross-sectional schematic diagram of the wafer preparation method of Example 5 and Example 6 of the present invention after the stacked structure is formed in step 1;

[0055] Figure 2 It is a cross-sectional schematic diagram after forming the first resistor in step 2 of the method for preparing a wafer according to embodiment 5 of the present invention;

[0056] Figure 3 It is a cross-sectional schematic diagram after forming a source electrode hole, a drain electrode body electrode hole and a first resistor electrode hole in step 3 of the method for preparing a wafer of embodiment 5 of the present invention;

[0057] Figure 4 It is a cross-sectional schematic diagram after forming a source electrode, a drain electrode, a body electrode and a first resistor electrode in step 3 of the method for preparing a wafer according to embodiment 5 of the present invention;

[0058] Figure 5 It is a cross-sectional schematic diagram after forming a first dielectric layer, a gate electrode hole, a through hole, and a second resistor electrode hole in step 4 of the method for preparing a wafer according to embodiment 5 of the present invention;

[0059] Figure 6 It is a cross-sectional schematic diagram after forming a gate electrode and a field plate, a connecting section, a second resistor and a second resistor electrode in step 5 of the method for preparing a wafer according to embodiment 5 of the present invention;

[0060] Figure 7 It is a cross-sectional schematic diagram after forming a second dielectric layer and a first electrode hole for a drain electrode in step 6 of the method for preparing a wafer according to embodiment 5 of the present invention;

[0061] Figure 8 It is a cross-sectional schematic diagram after forming the drain electrode, the first electrode and the transition layer in step 7 of the method for preparing a wafer according to embodiment 5 of the present invention;

[0062] Fig. 9 It is a cross-sectional schematic diagram after forming the drain electrode and the third electrode in step 8 of the method for preparing a wafer according to embodiment 5 of the present invention;

[0063] Fig.10 It is a cross-sectional schematic diagram after forming a gate electrode opening window and a source electrode opening window in step 8 of the method for preparing a wafer according to embodiment 5 of the present invention;

[0064] Fig.11 Schematic diagram of the top view of the wafer in Embodiment 3 and Embodiment 5 of the present invention;

[0065] Fig.12 is an equivalent circuit diagram of the wafer transition structure in Embodiment 1 and Embodiment 5 of the present invention;

[0066] Fig.13 It is a cross-sectional schematic diagram after forming the first resistor in step 2 of the wafer preparation method of embodiment 6 of the present invention;

[0067] Fig.14 It is a cross-sectional schematic diagram after forming a source electrode hole, a drain electrode body electrode hole and a first resistor electrode hole in step 3 of the method for preparing a wafer according to embodiment 6 of the present invention;

[0068] Fig.15 It is a cross-sectional schematic diagram after forming a source electrode, a drain electrode, a body electrode and a first resistor electrode in step 3 of the method for preparing a wafer according to embodiment 6 of the present invention;

[0069] Fig.16 It is a cross-sectional schematic diagram after forming a first dielectric layer, a gate electrode hole, a through hole, and a second resistor electrode hole in step 4 of the method for preparing a wafer according to embodiment 6 of the present invention;

[0070] Fig.17 It is a cross-sectional schematic diagram after forming a gate electrode and a field plate, a connecting section, a second resistor and a second resistor electrode in step 5 of the method for preparing a wafer according to embodiment 6 of the present invention;

[0071] Fig.18 It is a cross-sectional schematic diagram after forming a second dielectric layer and a drain electrode first electrode hole in step 6 of the method for preparing a wafer according to embodiment 6 of the present invention;

[0072] Fig.19 It is a cross-sectional schematic diagram after forming the drain electrode, the first electrode and the transition layer in step 7 of the method for preparing a wafer according to embodiment 6 of the present invention;

[0073] Fig. 20 It is a cross-sectional schematic diagram after forming the drain electrode and the third electrode in step 8 of the method for preparing a wafer according to embodiment 6 of the present invention;

[0074] Fig.21 It is a cross-sectional schematic diagram after forming a gate electrode opening window, a source electrode opening window and a drain electrode opening window in step 8 of the method for preparing a wafer according to embodiment 6 of the present invention;

[0075] Fig. 22 Schematic diagram of the top view of the wafer in Embodiment 4 and Embodiment 6 of the present invention;

[0076] Fig.23 is an equivalent circuit diagram of the wafer transition structure in Embodiment 2 and Embodiment 6 of the present invention;

[0077] Fig.24 It is a schematic diagram of the three-dimensional structure of the aging test device in Example 7 of the present invention;

[0078] It should be noted that, for Example 1, the above Figures 1 to 9 It is a schematic cross-sectional view along the dotted line A. Fig.10 is a schematic cross-sectional view along the dotted line B; for Example 2, the above Figure 1 , Figures 13 to 20 It is a cross-sectional schematic diagram along the dotted line C. Fig.21 It is a schematic cross-sectional view along the dotted line D;

[0079] Wherein, the accompanying drawings are marked as follows:

[0080] Substrate-1, nucleation layer-20, buffer layer-21, channel layer-22, first resistor-221, barrier layer-23, cap layer-24, source electrode hole-241, drain electrode body electrode hole-242, first resistor electrode hole-243, second resistor electrode hole-244, source electrode-3, drain electrode body electrode-41, drain electrode first electrode-42, drain electrode second electrode-43, drain electrode third electrode-44, first dielectric layer-5, second dielectric layer-6, gate electrode hole-61, through hole-62, second resistor-63, drain electrode first electrode hole-64, drain electrode second electrode hole-65, source electrode opening window-66, gate electrode opening window-67, drain electrode opening window-68, gate electrode-71, field plate-72, connecting segment-73, transition layer-8, first resistor electrode-91, second resistor electrode-92;

[0081] Sheet frame 101, cavity 102, card slot 103, first electrode 104, second electrode 105, first wire 106, second wire 107. DETAILED DESCRIPTION

[0082] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0083] The wafer transition structure of the present invention comprises a plurality of chips, and the front side of the wafer transition structure has a transition layer 8, each chip comprises a source electrode 3, a drain electrode, a gate electrode 71, a first resistor 221, a second resistor 63, a first resistor electrode 91, a second resistor electrode 92, a field plate 72, a connecting section 73, and a substrate 1, a stacked structure, a first dielectric layer 5, and a second dielectric layer 6 arranged in sequence from bottom to top, the second dielectric layer 6 is close to the transition layer 8, and the transition layer 8 is used to connect the drain electrodes of all chips of the wafer transition structure in parallel; the thickness of the transition layer 8 is 0.5 to 8 μm, preferably 4 to 6 μm. The first resistor 221 of the present invention is a cascade resistor, and the second resistor 63 is a protective resistor. The resistance of the first resistor 221 is greater than the resistance of the second resistor 63. The resistance of the first resistor 221 is 100Ω to 100MΩ, preferably 1 to 20MΩ, and the resistance of the second resistor 63 is 1Ω to 1MΩ, preferably 1 to 100kΩ.

[0084] Specifically, the stacked structure includes a nucleation layer 20, a buffer layer 21, a channel layer 22, a barrier layer 23 and a cap layer 24 arranged in sequence from bottom to top. The source electrode 3 is located in the barrier layer 23, the cap layer 24 and the first dielectric layer 5, the drain electrode is located in the barrier layer 23, the cap layer 24, the first dielectric layer 5 and the second dielectric layer 6, and the gate electrode 71 is located in the first dielectric layer 5. The field plate 72 is connected to the gate electrode 71 and the connecting section 73, wherein the connecting section 73 is used to connect the gate electrode 71 and the first resistor electrode 91, and the drain electrode is also connected to the transition layer 8.

[0085] Furthermore, the first resistor electrode 91 is three-terminal connected, two ends of which are respectively connected to the gate electrode 71 and the first resistor 221 , and the first resistor electrode 91 is also connected to the second resistor 63 or the substrate 1 .

[0086] The second resistance electrode 92 runs through the entire stacked structure and the first dielectric layer 5 , one end of the second resistance electrode 92 is located in the substrate 1 , and the other end of the second resistance electrode 92 is located in the second dielectric layer 6 .

[0087] Furthermore, the drain electrode includes a drain electrode body electrode 41 and a drain electrode first electrode 42, the drain electrode body electrode 41 is located below the drain electrode first electrode 42, the drain electrode body electrode 41 is located in the barrier layer 23, the cap layer 24 and the first dielectric layer 5, and the drain electrode first electrode 42 is located in the first dielectric layer 5 and the second dielectric layer 6.

[0088] When the first resistor electrode 91 is connected to the gate electrode 71, the first resistor 221 and the second resistor 63 respectively, one end of the drain electrode first electrode 42 is connected to the transition layer 8, and the other end of the drain electrode first electrode 42 is connected to the drain electrode body electrode 41. One end of the second resistor electrode 92 is connected to the substrate 1, and the other end of the second resistor electrode 92 is connected to the second resistor 63, and the end of the second resistor 63 away from the second resistor electrode 92 is connected to the first resistor electrode 91. The front side of the wafer transition structure is the drain electrodes of all chips connected in parallel, and the back side is the source electrodes 3 of all chips connected to their respective first resistors 221 and then connected to their respective gate electrodes 71, and further, after the respective gate electrodes 71 are connected to their respective second resistors 63, they are uniformly connected in parallel to the substrate 1.

[0089] When the first resistor electrode 91 is connected to the gate electrode 71, the first resistor 221 and the substrate 1 respectively, the drain electrode also includes a drain electrode second electrode 43, the drain electrode second electrode 43 is located between the drain electrode body electrode 41 and the drain electrode first electrode 42, one end of the drain electrode second electrode 43 is connected to one end of the second resistor 63, the other end of the drain electrode second electrode 43 is connected to the drain electrode body electrode 41, and the other end of the second resistor 63 is connected to one end of the drain electrode first electrode 42. At this time, one end of the second resistor electrode 92 is connected to the substrate 1, and the other end of the second resistor electrode 92 is connected to the first resistor electrode 91. The front side of the wafer transition structure is that one end of the second resistor 63 of each chip is connected in parallel, and the other end of the second resistor 63 is connected to the drain electrode of each chip respectively, and the back side is that the source electrodes 3 of all chips are connected to their respective first resistors 221 and then connected to their respective gate electrodes 71, and then connected in parallel to the substrate 1.

[0090] The design of the wafer transition structure of the present invention realizes that the high-voltage end (front side of the wafer transition structure) of all chips is short-circuited as the upper electrode of the wafer transition structure, and the low-voltage end (back side of the wafer transition structure) of all chips is short-circuited as the lower electrode of the wafer transition structure, and finally the whole wafer transition structure outputs only two electrodes, thereby realizing the temporary connection of the three-terminal normally-on chip to the two-terminal normally-off chip, which greatly simplifies the difficulty of wafer-level assessment. The wafer transition structure of the present invention can be directly used for wafer-level assessment, and even if individual chips fail, the assessment of the whole wafer transition structure can still continue.

[0091] The present invention also provides a wafer structure, which is obtained by patterning the transition layer 8 on the basis of the above-mentioned wafer transition structure, and then etching the gate electrode opening window 67 and the source electrode opening window 66 on the second dielectric layer 6, or etching the gate electrode opening window 67, the source electrode opening window 66 and the drain electrode opening window 68 on the second dielectric layer 6. After the wafer-level assessment is completed, the wafer transition structure can restore the functional electrodes of each chip through the above-mentioned simple process, complete the complete wafer process to obtain the wafer, and can continue to be used for subsequent testing, screening, cutting, packaging devices and other processes, which not only realizes a simple and easy-to-operate wafer-level assessment, but also helps to screen the early failures of power devices, and does not affect the subsequent processes of the wafer.

[0092] Example 1 Wafer transition structure

[0093] like Figure 8As shown, the wafer transition structure in this embodiment includes multiple chips, and the front side of the wafer transition structure has a transition layer 8, and the material of the transition layer 8 is metal. Each chip includes a source electrode 3, a drain electrode, a gate electrode 71, a first resistor 221, a second resistor 63, a first resistor electrode 91, a second resistor electrode 92, a field plate 72, a connecting section 73, and a substrate 1, a stacked structure, a first dielectric layer 5 and a second dielectric layer 6 arranged from bottom to top. The second dielectric layer 6 is close to the transition layer 8. The transition layer 8 is used to connect the drain electrodes of all chips of the wafer transition structure in parallel; the thickness of the transition layer 8 is preferably 4 to 6 μm. The stacked structure includes a nucleation layer 20, a buffer layer 21, a channel layer 22, a barrier layer 23 and a cap layer 24 arranged from bottom to top.

[0094] In this embodiment, the first resistor 221 is a cascade resistor, and the second resistor 63 is a protection resistor. The resistance of the first resistor 221 is 1-20 MΩ, and the resistance of the second resistor 63 is 1-100 kΩ. The resistance of the first resistor 221 is greater than that of the second resistor 63.

[0095] Specifically, the source electrode 3 is located in the barrier layer 23, the cap layer 24 and the first dielectric layer 5, and the gate electrode 71 is located in the first dielectric layer 5. The drain electrode includes a drain electrode body electrode 41 and a drain electrode first electrode 42, the drain electrode body electrode 41 is located below the drain electrode first electrode 42, the drain electrode body electrode 41 is located in the barrier layer 23, the cap layer 24 and the first dielectric layer 5, and the drain electrode first electrode 42 is located in the first dielectric layer 5 and the second dielectric layer 6. One end of the drain electrode first electrode 42 is connected to the transition layer 8, and the other end thereof is connected to the drain electrode body electrode 41. The field plate 72 is connected to both the gate electrode 71 and the connecting section 73, the field plate 72 is located in the second dielectric layer 6, the connecting section 73 is located in the first dielectric layer 5 and the second dielectric layer 6, wherein the connecting section 73 is made of metal, and the connecting section 73 is used to connect the gate electrode 71 to the first resistor electrode 91.

[0096] Furthermore, the first resistor electrode 91 is located in the barrier layer 23 , the cap layer 24 and the first dielectric layer 5 . The first resistor electrode 91 is three-terminal connected, and is respectively connected to the gate electrode 71 , the first resistor 221 and the second resistor 63 .

[0097] Furthermore, the second resistor electrode 92 runs through the entire stacked structure and the first dielectric layer 5, one end of the second resistor electrode 92 is located in the substrate 1, and the other end of the second resistor electrode 92 is located in the second dielectric layer 6. In this embodiment, one end of the second resistor electrode 92 is connected to the substrate 1, the other end of the second resistor electrode 92 is connected to the second resistor 63, and one end of the second resistor 63 away from the second resistor electrode 92 is connected to the first resistor electrode 91.

[0098] Through the arrangement of the wafer transition structure in this embodiment, the front side of the wafer transition structure is connected in parallel to the drain electrodes of all chips, and the back side is connected to the source electrodes 3 of all chips, which are respectively connected to the respective first resistors 221 and then to the respective gate electrodes 71. Furthermore, the respective gate electrodes 71 are connected to the respective second resistors 63 and then connected in parallel to the substrate 1. The equivalent circuit diagram of the wafer transition structure in this embodiment is shown in FIG. Fig.12 As shown, the source electrode 3 of the chip is connected in series to the first resistor 221, the other end of the first resistor 221 is connected to the gate electrode 71 of the chip, and the drain electrode serves as a high-level connection terminal; the gate electrode 71 is connected in series to the second resistor 63, and the other end of the second resistor 63 serves as a low-level connection terminal.

[0099] When the high level connection terminal is connected to the voltage V 0 When the low-level connection terminal is connected to a low voltage of 0V, since the leakage currents of the G terminal (gate electrode 71) and the D terminal (drain electrode) and the G terminal and the S terminal (source electrode 3) of the chip are extremely low, the circuit is equivalent to R DS Connected in series with the first resistor 221 and the second resistor 63, V SG =V 第一电阻 , when the voltage V 0 Low leads to V SG When the voltage divided by is lower than the absolute value of the chip threshold, the chip is in the on state, R DS Small and low voltage division. When the voltage V 0 The increase causes V SG When the voltage divider is higher than the absolute value of the chip threshold, the chip is in the off state. DS Very large, and R DS is greater than the resistance of the first resistor 221 and the second resistor 63, so V 第一电阻 is approximately equal to the absolute value of the chip's threshold, while V DS In this way, high voltage is applied to both ends of the drain electrode and the source electrode 3 of the chip, and a voltage approximately equal to the absolute value of the threshold voltage is applied to both ends of the source electrode 3 and the gate electrode 71, thereby realizing high voltage reverse bias of the chip (high voltage is applied when the device is turned off), so that the wafer transition structure can complete the wafer level assessment.

[0100] Example 2 Wafer transition structure

[0101] like Fig.19As shown, the wafer transition structure in this embodiment includes multiple chips, and the front side of the wafer transition structure has a transition layer 8, and the material of the transition layer 8 is metal. Each chip includes a source electrode 3, a drain electrode, a gate electrode 71, a first resistor 221, a second resistor 63, a first resistor electrode 91, a second resistor electrode 92, a field plate 72, a connecting section 73, and a substrate 1, a stacked structure, a first dielectric layer 5 and a second dielectric layer 6 arranged from bottom to top. The second dielectric layer 6 is close to the transition layer 8. The transition layer 8 is used to connect the drain electrodes of all chips of the wafer transition structure in parallel; the thickness of the transition layer 8 is preferably 4 to 6 μm. The stacked structure includes a nucleation layer 20, a buffer layer 21, a channel layer 22, a barrier layer 23 and a cap layer 24 arranged from bottom to top.

[0102] In this embodiment, the first resistor 221 is a cascade resistor, and the second resistor 63 is a protection resistor. The resistance of the first resistor 221 is 1-20 MΩ, and the resistance of the second resistor 63 is 1-100 kΩ. The resistance of the first resistor 221 is greater than that of the second resistor 63.

[0103] Specifically, the source electrode 3 is located in the barrier layer 23, the cap layer 24 and the first dielectric layer 5, and the gate electrode 71 is located in the first dielectric layer 5. The drain electrode includes a drain electrode body electrode 41, a drain electrode first electrode 42 and a drain electrode second electrode 43, the drain electrode second electrode 43 is located between the drain electrode body electrode 41 and the drain electrode first electrode 42, the drain electrode body electrode 41 is located in the barrier layer 23, the cap layer 24 and the first dielectric layer 5, the drain electrode first electrode 42 is located in the second dielectric layer 6, and the drain electrode second electrode 43 is located in the first dielectric layer 5 and the second dielectric layer 6; one end of the drain electrode second electrode 43 is connected to one end of the second resistor 63, the other end of the drain electrode second electrode 43 is connected to the drain electrode body electrode 41, one end of the drain electrode first electrode 42 is connected to the transition layer 8, and the other end of the drain electrode first electrode 42 is connected to the other end of the second resistor 63. The field plate 72 is connected to the gate electrode 71 and the connecting section 73. The field plate 72 is located in the second dielectric layer 6. The connecting section 73 is located in the first dielectric layer 5 and the second dielectric layer 6. The connecting section 73 is made of metal and is used to connect the gate electrode 71 and the first resistor electrode 91.

[0104] Furthermore, the first resistor electrode 91 is located in the barrier layer 23 , the cap layer 24 and the first dielectric layer 5 . The first resistor electrode 91 is three-terminal connected, and is respectively connected to the gate electrode 71 , the first resistor 221 and the substrate 1 .

[0105] Further, the second resistor electrode 92 runs through the entire stacked structure and the first dielectric layer 5, one end of the second resistor electrode 92 is located in the substrate 1, and the other end of the second resistor electrode 92 is located in the second dielectric layer 6. In this embodiment, one end of the second resistor electrode 92 is connected to the substrate 1, and the other end of the second resistor electrode 92 is connected to the first resistor electrode 91, so that one end of the first resistor electrode 91 can be connected to the substrate 1.

[0106] Through the arrangement of the wafer transition structure in this embodiment, the front side of the wafer transition structure is connected in parallel with one end of the second resistor 63 of each chip, and the other end of the second resistor 63 is connected to the drain electrode of each chip respectively, and the back side is connected to the source electrodes 3 of all chips respectively connected to the first resistor 221 and then connected to the gate electrode 71 respectively, and then connected in parallel to the substrate 1. The equivalent circuit diagram of the wafer transition structure in this embodiment is shown in FIG. Fig.23 As shown, the source electrode 3 of the chip is connected in series to the first resistor 221, and the other end of the first resistor 221 is connected to the gate electrode 71 of the chip, and the gate electrode 71 serves as a low-level connection terminal; the second resistor 63 of this embodiment is located between the drain electrode and the high-level connection terminal.

[0107] When the high level connection terminal is connected to the voltage V 0 When the low-level connection terminal is connected to a low voltage of 0V, since the leakage currents of the G terminal (gate electrode 71) and the D terminal (drain electrode) and the G terminal and the S terminal (source electrode 3) of the chip are extremely low, the circuit is equivalent to R DS Connected in series with the first resistor 221 and the second resistor 63, V SG =V 第一电阻 , when the voltage V 0 Low leads to V SG When the voltage divided by is lower than the absolute value of the chip threshold, the chip is in the on state, R DS Small and low voltage division. When the voltage V 0 The increase causes V SG When the voltage divider is higher than the absolute value of the chip threshold, the chip is in the off state. DS Very large, and R DS is greater than the resistance of the first resistor 221 and the second resistor 63, so V 第一电阻 is approximately equal to the absolute value of the chip's threshold, while V DS In this way, high voltage is applied to both ends of the drain electrode and the source electrode 3 of the chip, and a voltage approximately equal to the absolute value of the threshold voltage is applied to both ends of the source electrode 3 and the gate electrode 71, thereby realizing high voltage reverse bias of the chip (high voltage is applied when the device is turned off), so that the wafer transition structure can complete the wafer level assessment.

[0108] Example 3 Wafer structure

[0109] like Fig.10 and Fig.11 (gate electrode opening window 67 and source electrode opening window 66 are not shown), the wafer in this embodiment is obtained by patterning and etching the transition layer 8 on the basis of the wafer transition structure in embodiment 1, and then etching the gate electrode opening window 67 and the source electrode opening window 66 on the second dielectric layer 6. The wafer in this embodiment includes multiple chips, each chip includes a source electrode 3, a drain electrode, a gate electrode 71, a first resistor 221, a second resistor 63, a first resistor electrode 91, a second resistor electrode 92, a field plate 72, a connecting section 73, and a substrate 1, a stacked structure, a first dielectric layer 5 and a second dielectric layer 6 arranged in sequence from bottom to top; the stacked structure includes a nucleation layer 20, a buffer layer 21, a channel layer 22, a barrier layer 23 and a cap layer 24 arranged in sequence from bottom to top.

[0110] In this embodiment, the first resistor 221 is a cascade resistor, and the second resistor 63 is a protection resistor. The resistance of the first resistor 221 is 1-20 MΩ, and the resistance of the second resistor 63 is 1-100 kΩ. The resistance of the first resistor 221 is greater than that of the second resistor 63.

[0111] Specifically, the source electrode 3 is located in the barrier layer 23, the cap layer 24 and the first dielectric layer 5, and the gate electrode 71 is located in the first dielectric layer 5. The drain electrode includes a drain electrode body electrode 41, a drain electrode first electrode 42 and a drain electrode third electrode 44, the drain electrode body electrode 41 is located below the drain electrode first electrode 42, the drain electrode body electrode 41 is located in the barrier layer 23, the cap layer 24 and the first dielectric layer 5, the drain electrode first electrode 42 is located in the first dielectric layer 5 and the second dielectric layer 6, and the drain electrode third electrode 44 is located above the second dielectric layer 6. One end of the drain electrode first electrode 42 is connected to the drain electrode third electrode 44, and the other end of the drain electrode first electrode 42 is connected to the drain electrode body electrode 41. The field plate 72 is connected to the gate electrode 71 and the connecting section 73. The field plate 72 is located in the second dielectric layer 6. The connecting section 73 is located in the first dielectric layer 5 and the second dielectric layer 6. The connecting section 73 is made of metal and is used to connect the gate electrode 71 and the first resistor electrode 91.

[0112] Furthermore, the wafer structure also includes a gate electrode opening window 67 and a source electrode opening window 66, the gate electrode opening window 67 is located above the field plate 72 connected to the gate electrode 71, and the source electrode opening window 66 is located above the source electrode 3. The arrangement of the drain electrode third electrode 44, the gate electrode opening window 67 and the source electrode opening window 66 enables the drain electrode, the gate electrode 71 and the source electrode 3 of the chip to restore their respective functions, and can be used for subsequent testing, screening, cutting and packaging of devices.

[0113] Furthermore, the first resistor electrode 91 is located in the barrier layer 23 , the cap layer 24 and the first dielectric layer 5 . The first resistor electrode 91 is three-terminal connected, and is respectively connected to the gate electrode 71 , the first resistor 221 and the second resistor 63 .

[0114] Furthermore, the second resistor electrode 92 runs through the entire stacked structure and the first dielectric layer 5, one end of the second resistor electrode 92 is located in the substrate 1, and the other end of the second resistor electrode 92 is located in the second dielectric layer 6. In this embodiment, one end of the second resistor electrode 92 is connected to the substrate 1, the other end of the second resistor electrode 92 is connected to the second resistor 63, and one end of the second resistor 63 away from the second resistor electrode 92 is connected to the first resistor electrode 91.

[0115] Example 4 Wafer structure

[0116] like Fig.21 and Fig. 22 (source electrode opening window 66, gate electrode opening window 67 and drain electrode opening window 68 are not shown), the wafer in this embodiment is obtained by patterning the transition layer 8 on the basis of the wafer transition structure in embodiment 2, and then etching the gate electrode opening window 67, source electrode opening window 66 and drain electrode opening window 68 on the second dielectric layer 6. The wafer in this embodiment includes a plurality of chips, each chip includes a source electrode 3, a drain electrode, a gate electrode 71, a first resistor 221, a second resistor 63, a first resistor electrode 91, a second resistor electrode 92, a field plate 72, a connecting section 73, and a substrate 1, a stacked structure, a first dielectric layer 5 and a second dielectric layer 6 arranged in sequence from bottom to top; the stacked structure includes a nucleation layer 20, a buffer layer 21, a channel layer 22, a barrier layer 23 and a cap layer 24 arranged in sequence from bottom to top.

[0117] In this embodiment, the first resistor 221 is a cascade resistor, and the second resistor 63 is a protection resistor. The resistance of the first resistor 221 is 1-20 MΩ, and the resistance of the second resistor 63 is 1-100 kΩ. The resistance of the first resistor 221 is greater than that of the second resistor 63.

[0118] Specifically, the source electrode 3 is located in the barrier layer 23, the cap layer 24 and the first dielectric layer 5, and the gate electrode 71 is located in the first dielectric layer 5. The drain electrode includes a drain electrode body electrode 41, a drain electrode first electrode 42, a drain electrode second electrode 43 and a drain electrode third electrode 44, the drain electrode second electrode 43 is located between the drain electrode body electrode 41 and the drain electrode first electrode 42, the drain electrode body electrode 41 is located in the barrier layer 23, the cap layer 24 and the first dielectric layer 5, the drain electrode first electrode 42 is located in the second dielectric layer 6, the drain electrode second electrode 43 is located in the first dielectric layer 5 and the second dielectric layer 6, and the drain electrode third electrode 44 is located above the second dielectric layer 6. One end of the drain electrode second electrode 43 is connected to one end of the second resistor 63, the other end of the drain electrode second electrode 43 is connected to the drain electrode body electrode 41, one end of the drain electrode first electrode 42 is connected to the drain electrode third electrode 44, and the other end of the drain electrode first electrode 42 is connected to the other end of the second resistor 63. The field plate 72 is connected to the gate electrode 71 and the connecting section 73. The field plate 72 is located in the second dielectric layer 6. The connecting section 73 is located in the first dielectric layer 5 and the second dielectric layer 6. The connecting section 73 is made of metal and is used to connect the gate electrode 71 and the first resistor electrode 91. The drain electrode third electrode 44 of this embodiment is not provided for connecting the wire, but for protecting the drain electrode first electrode 42 and the drain electrode body electrode 41 thereunder from being damaged.

[0119] Furthermore, the wafer structure of this embodiment further includes a gate electrode opening window 67, a source electrode opening window 66 and a drain electrode opening window 68, the gate electrode opening window 67 is located above the field plate 72 connected to the gate electrode 71, the source electrode opening window 66 is located above the source electrode 3, and the drain electrode opening window 68 is located above the drain electrode body electrode 41. The arrangement of the drain electrode opening window 68, the gate electrode opening window 67 and the source electrode opening window 66 enables the drain electrode, the gate electrode 71 and the source electrode 3 of the chip to restore their respective functions, and can be used for subsequent testing, screening, cutting and packaging of devices.

[0120] Furthermore, the first resistor electrode 91 is located in the barrier layer 23 , the cap layer 24 and the first dielectric layer 5 . The first resistor electrode 91 is three-terminal connected, and is respectively connected to the gate electrode 71 , the first resistor 221 and the substrate 1 .

[0121] Further, the second resistor electrode 92 runs through the entire stacked structure and the first dielectric layer 5, one end of the second resistor electrode 92 is located in the substrate 1, and the other end of the second resistor electrode 92 is located in the second dielectric layer 6. In this embodiment, one end of the second resistor electrode 92 is connected to the substrate 1, and the other end of the second resistor electrode 92 is connected to the first resistor electrode 91, so that one end of the first resistor electrode 91 can be connected to the substrate 1.

[0122] Example 5 Wafer Preparation Method

[0123] This embodiment provides a method for preparing the wafer in the above embodiment 3, which specifically includes the following steps:

[0124] Step 1: Select a conductive material as substrate 1, such as Figure 1 As shown, nitride epitaxial growth is performed on the substrate 1 to sequentially form a nucleation layer 20, a buffer layer 21, a channel layer 22, a barrier layer 23 and a cap layer 24, wherein the nitride comprises a III-group nitride material such as GaN, AlGaN, AlN, AlGaNInN, SiN, etc. The nucleation layer 20, the buffer layer 21, the channel layer 22, the barrier layer 23 and the cap layer 24 form a stacked structure, thereby forming a complete semiconductor epitaxial layer structure, and can form a high-concentration two-dimensional electron gas at the heterojunction interface between the channel layer 22 and the barrier layer 23 to generate a conductive channel.

[0125] The substrate 1 is made of one or more combinations of silicon, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, silicon carbide, germanium or any other material capable of growing group III nitride materials after being doped.

[0126] Step 2: If Figure 2 As shown, a patterning process is performed on the cap layer 24 and ion materials are implanted to destroy the two-dimensional electron gas in the implanted area to form an electrical isolation area. During the isolation, a first resistor 221 structure is formed.

[0127] Step 3: If Figure 3 As shown, patterned etching is performed on the cap layer 24 to form a source electrode hole 241, a drain electrode body electrode hole 242 and a first resistor electrode hole 243, and metal is filled in the source electrode hole 241, the drain electrode body electrode hole 242 and the first resistor electrode hole 243. The metal includes one or more combinations of Ti, Al, TiN, Au, AlCu, AlSiCu, and W. The filling method includes evaporation, sputtering, etc., and patterned stripping or etching is used to form a specific structure, and annealing is performed to form an ohmic contact, so as to form a source electrode 3, a drain electrode body electrode 41 and a first resistor electrode 91, respectively, as shown in FIG. Figure 4 shown.

[0128] Step 4: Deposit SiN, SiO on the source electrode 3, the drain electrode body electrode 41 and the first resistor electrode 91. 2 、SiON、Al 2 O 3 One or more combinations thereof form the first dielectric layer 5, such as Figure 5 As shown, a gate electrode hole 61, a through hole 62 and a second resistor electrode hole 244 are etched out.

[0129] Step 5: Fill the first dielectric layer 5 with metal, the metal includes one or more combinations of Cu, Ag, Sn, Pb, PbSn, Ti, Al, AlCu, AlSiCu, TiN, and the filling method includes evaporation, sputtering, etc. Cooperate with patterned stripping or etching to form a specific structure, etch away excess metal, and form the gate electrode 71 and the field plate 72, the connecting section 73, the second resistor 63 and the second resistor electrode 92, such as Figure 6 shown.

[0130] Step 6: Figure 7 As shown, SiN, SiO 2 、SiON、Al 2 O 3 One or more combinations thereof are used to form a second dielectric layer 6, and a drain electrode first electrode hole 64 is etched.

[0131] Step 7: Figure 8 As shown, metal is filled on the second dielectric layer 6 to form a drain electrode first electrode 42 and a transition layer 8, thereby obtaining the wafer transition structure in Embodiment 1. The metal includes one or more combinations of Ti, Al, TiN, Au, AlCu, AlSiCu, and W, and the transition layer 8 covers the front side of the entire wafer transition structure.

[0132] Step 8: Fig. 9 As shown, the transition layer 8 is patterned and etched to form the drain electrode and the third electrode 44; and then the gate electrode opening window 67 and the source electrode opening window 66 are etched downward from the second dielectric layer 6, as shown in FIG. Fig.10 As shown, the final structure obtained is a wafer as in Example 3.

[0133] Example 6 Wafer Preparation Method

[0134] This embodiment provides a method for preparing the wafer in the above-mentioned embodiment 4, which specifically includes the following steps:

[0135] Step 1: Select a conductive material as substrate 1, such as Figure 1 As shown, nitride epitaxial growth is performed on a substrate 1 to sequentially form a nucleation layer 20, a buffer layer 21, a channel layer 22, a barrier layer 23 and a cap layer 24, and the materials include group III nitride materials such as GaN, AlGaN, AlN, AlGaNInN, SiN, etc. The nucleation layer 20, the buffer layer 21, the channel layer 22, the barrier layer 23 and the cap layer 24 form a stacked structure, thereby forming a complete semiconductor epitaxial layer structure, and can form a high-concentration two-dimensional electron gas at the heterojunction interface between the channel layer 22 and the barrier layer 23 to generate a conductive channel.

[0136] The substrate 1 is made of one or more combinations of silicon, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, silicon carbide, germanium or any other material capable of growing group III nitride materials after being doped.

[0137] Step 2: If Fig.13 As shown, a patterning process is performed on the cap layer 24 and ion materials are implanted to destroy the two-dimensional electron gas in the implanted area to form an electrical isolation area. During the isolation, a first resistor 221 structure is formed.

[0138] Step 3: If Fig.14 As shown, patterned etching is performed on the cap layer 24 to form a source electrode hole 241, a drain electrode body electrode hole 242 and a first resistor electrode hole 243; and metal is filled in the source electrode hole 241, the drain electrode body electrode hole 242 and the first resistor electrode hole 243, and the metal includes one or more combinations of Ti, Al, TiN, Au, AlCu, AlSiCu, W, and the filling method includes evaporation, sputtering, etc., combined with patterned stripping or etching to form a specific structure, and annealing is performed to form an ohmic contact, respectively forming a source electrode 3, a drain electrode body electrode 41 and a first resistor electrode 91, as shown in FIG. Fig.15 shown.

[0139] Step 4: Fig.16 As shown, SiN, SiO are deposited on the source electrode 3, the drain electrode body electrode 41 and the first resistor electrode 91. 2 、SiON、Al 2 O 3 One or more combinations thereof are used to form a first dielectric layer 5; and a gate electrode hole 61, a through hole 62, a drain electrode second electrode hole 65 and a second resistor electrode hole 244 are etched.

[0140] Step 5: Fill the first dielectric layer 5 with metal, the metal includes one or more combinations of Cu, Ag, Sn, Pb, PbSn, Ti, Al, AlCu, AlSiCu, TiN, and the filling method includes evaporation, sputtering, etc. Cooperate with patterned stripping or etching to form a specific structure, etch away excess metal, and form the gate electrode 71 and the field plate 72, the connecting section 73, the second resistor 63 and the second resistor electrode 92 and the drain electrode second electrode 43, such as Fig.17 shown.

[0141] Step 6: Fig.18 As shown, SiN, SiO 2 、SiON、Al 2 O 3 One or more combinations thereof are used to form a second dielectric layer 6, and a drain electrode first electrode hole 64 is etched.

[0142] Step 7: Fig.19 As shown, metal is filled on the second dielectric layer 6 to form a drain electrode first electrode 42 and a transition layer 8, thereby obtaining the wafer transition structure in Embodiment 2. The metal includes one or more combinations of Ti, Al, TiN, Au, AlCu, AlSiCu, and W, and the transition layer 8 covers the front side of the entire wafer transition structure.

[0143] Step 8: Fig. 20 As shown, the transition layer 8 is patterned and etched to form the drain electrode and the third electrode 44; and then the gate electrode opening window 67, the source electrode opening window 66 and the drain electrode opening window 68 are etched downward from the second dielectric layer 6, as shown in FIG. Fig.21 The position of the drain electrode opening window 68 in this embodiment avoids the position of the second resistor 63 when opening, and finally a wafer with the structure as in Embodiment 4 is obtained.

[0144] Embodiment 7 Aging test device

[0145] like Fig.24 As shown, this embodiment provides an aging test device for performing aging tests on the wafer transition structures in Embodiments 1 and 2, which includes a wafer rack 101, the wafer rack 101 has a cavity 102 inside, and a plurality of slot units are evenly spaced on two opposite side walls of the cavity 102, each slot unit includes two oppositely arranged slots 103, in this embodiment, the two slots 103 of each slot unit are located on the same horizontal line; and the distance between the sides of the two slots 103 of each slot unit that are close to each other is smaller than the diameter of the wafer transition structure, and the distance between the sides of the two slots 103 of each slot unit that are far away from each other is larger than the diameter of the wafer transition structure, so that the slots 103 can be used to place the edge part of the wafer transition structure, and can also limit the position of the wafer transition structure to prevent it from falling.

[0146] Furthermore, a first electrode 104 and a second electrode 105 are fixedly disposed in one of the slots 103 of each slot unit, and the first electrode 104 and the second electrode 105 are used together to clamp a wafer transition structure. The first electrode 104 contacts the front side of the wafer transition structure, and the second electrode 105 contacts the back side of the wafer transition structure; and there is a certain elastic pressure between the first electrode 104 and the second electrode 105, ensuring that they can form good electrical contact with the front side and the back side of the wafer transition structure.

[0147] Furthermore, the first electrode 104 in each slot 103 is shorted to the first wire 106, and the second electrode 105 in each slot 103 is shorted to the second wire 107. Finally, the first wire 106 and the second wire 107 are centrally led out and connected to the power supply, wherein the first wire 106 is a high-voltage connection and the second wire 107 is used for grounding. During the test, the entire aging test device can be placed in an oven, and the wafer-level assessment of the transition structure of the entire wafer can be achieved through centralized power supply.

[0148] Example 8 Aging Test Method

[0149] This embodiment provides a method for performing an aging test on the wafer transition structures of Embodiments 1 and 2 using the aging test device of Embodiment 7.

[0150] Specifically, during the test, the wafer transition structure to be assessed is directly inserted into the corresponding card slot 103 in the aging test device, and the front and back of each wafer transition structure are respectively connected to the first electrode 104 and the second electrode 105 in the corresponding card slot 103, and then the entire aging test device is placed in an oven, and the oven temperature is adjusted to -60 to 300°C, and the voltage of the power supply is adjusted to 1 to 3000V, so that the wafer-level assessment of the entire wafer transition structure can be performed, and the assessment time is 0.01 to 1000h. The aging test method of the present invention greatly simplifies the operational difficulty of wafer-level assessment and effectively improves work efficiency.

[0151] The above embodiments of the present invention are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a wafer, characterized in that: The steps include: Prepare a wafer transition structure, then perform patterned etching on the transition layer of the wafer transition structure to form a drain electrode and a third electrode; then etch downward from the second dielectric layer of the wafer transition structure to form a gate electrode opening window and a source electrode opening window, or etch downward to form a gate electrode opening window, a source electrode opening window and a drain electrode opening window to obtain the wafer; The transition layer of the wafer transition structure covers a portion of the front side of the wafer transition structure, the front side of the wafer transition structure is short-circuited to serve as an upper electrode of the wafer transition structure, and the back side of the wafer transition structure is short-circuited to serve as a lower electrode of the wafer transition structure; The wafer transition structure and the wafer both include multiple chips, each of which includes a source electrode, a drain electrode, a gate electrode, a first resistor, a second resistor, a first resistor electrode, a second resistor electrode, and a substrate, a stacked structure, a first dielectric layer, and a second dielectric layer arranged in sequence from bottom to top. The first resistor electrode is three-terminal connected, the second resistor electrode runs through the stacked structure and the first dielectric layer, one end of the second resistor electrode is located in the substrate, and the other end of the second resistor electrode is located in the second dielectric layer.

2. The preparation method according to claim 1, characterized in that: The first resistor is formed by performing patterning and implantation on the stacked structure, and the second resistor is formed by filling metal on the first dielectric layer and etching away excess metal.

3. The preparation method according to claim 2, characterized in that: The first resistor is a cascade resistor, and the resistance value of the first resistor is 1 to 20 MΩ; the second resistor is a protection resistor, and the resistance value of the second resistor is 1 to 100 kΩ.

4. The preparation method according to claim 1, characterized in that: The thickness of the transition layer is 4-6 μm.

5. The preparation method according to claim 3, characterized in that: A portion of the first resistance electrode is located in the stacked structure, and another portion of the first resistance electrode is located in the first dielectric layer.

6. The preparation method according to claim 5, characterized in that: The three ends of the first resistor electrode are respectively connected to the gate electrode, the first resistor and the second resistor.

7. The preparation method according to claim 6, characterized in that: The source electrode of the chip of the wafer transition structure is connected in series with the first resistor, the other end of the cascade resistor is connected to the gate electrode of the chip, the gate electrode is connected in series with the second resistor, the other end of the second resistor serves as a low-level connection end, and the drain electrode serves as a high-level connection end.

8. The preparation method according to claim 6, characterized in that: The three ends of the first resistor electrode are respectively connected to the gate electrode, the first resistor and the substrate.

9. The preparation method according to claim 8, characterized in that: The source electrode of the chip of the wafer transition structure is connected in series with the first resistor, the other end of the first resistor is connected to the gate electrode of the chip, one end of the gate electrode serves as a low-level connection end, and the second resistor is located between the drain electrode and the high-level connection end.

10. The preparation method according to claim 1, characterized in that: The second dielectric layer is close to the transition layer, and a material of the transition layer is a combination of one or more of Ti, Al, TiN, Au, AlCu, AlSiCu or W.

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