Three-level power factor rectifier and operation method thereof

Abstract

The invention discloses a three-level power factor rectifier and an operation method thereof, the three-level power factor rectifier comprises a diode bridge arm, a bridge arm group, an input inductor, a capacitor group and a controller, and the bridge arm group comprises a first switch, a second switch, a third switch and a fourth switch which are sequentially connected in series. When the controller judges that the load of the three-level power factor rectifier is lower than a load threshold value, the controller enters a burst mode, and the burst mode comprises a burst time period and a burst sleep time period. In the sudden sleep period, when the voltage value of the alternating current power supply is higher than a first threshold value, the first switch and the second switch are turned on, and when the voltage value of the alternating current power supply is lower than a second threshold value, the third switch and the fourth switch are turned on. When the burst sleep period enters the burst period, the controller turns on the second switch and the third switch for a specific period.

Description

Technical Field

[0001] The present invention relates to a three-level power factor rectifier and an operating method thereof, and in particular to a three-level power factor rectifier with reduced voltage stress and an operating method thereof. Background Art

[0002] As the information industry has developed rapidly in recent years, power supplies have played an important role. Information or home appliances are gradually required to reduce power consumption to a certain value when working at no load or light load. On the other hand, since harmonic suppression has been classified and limited in the international standard IEC61000-3-2, and the maximum rated harmonic current has been specified, information or home appliances must be equipped with power factor correction to improve the power factor at the AC power supply end.

[0003] With the advancement of distributed renewable energy generation technology and the increasing number of DC power devices, the demand for low-voltage DC power distribution is increasing. Traditional solutions usually use transformers to convert medium-voltage AC power (MVAC) into low-voltage AC power, and then use AC / DC converters to convert low-voltage AC power into low-voltage DC power. Later, devices such as Power Electronic Transformer (PET) were developed, which use high-frequency isolation circuits to achieve power conversion devices from medium-voltage AC to low-voltage DC.

[0004] However, the existing power electronic transformer still uses two-stage circuits. The front stage circuit uses a series AC / DC converter to convert the input medium-voltage AC power into multiple intermediate DC power supplies. The rear stage circuit uses a DC / DC converter to convert the intermediate DC power into a low-voltage DC power supply. However, each converter needs to be equipped with a corresponding medium-voltage isolation transformer, insulation parts, mechanical parts, optical fiber connectors, etc. The more units there are, the higher the complexity and cost of the system. Due to the low withstand voltage level of commercial semiconductor devices, power electronic transformers can use a three-level converter to increase the intermediate DC power level (>1.5kV), thereby reducing the number of cascaded circuits. In addition, the three-level converter can be operated by the controller to have a power factor correction function (i.e., a three-level power factor rectifier) ​​to reduce power loss and improve the conversion efficiency of the three-level converter during AC / DC conversion.

[0005] However, in the application of three-level power factor rectifiers, when the load is light or no load, the power switch elements of the three-level power factor rectifier need to withstand high voltage stress. The main reason is that the power switch element is affected by parasitic capacitance at the moment of conduction, and the medium-voltage AC power supply is easily attached to the two ends of the power switch element, resulting in the generation of instantaneous high voltage. To solve this problem, the current solution is usually to use higher-specification power switch elements. However, this will make the circuit volume of the three-level power factor rectifier larger and force the circuit cost to increase.

[0006] Therefore, how to design a three-level power factor rectifier and its operating method to reduce the voltage stress on the power switch element of the three-level power factor rectifier when the load is light load or no load is a major research topic that the creator of this case wants to conduct. Summary of the invention

[0007] In order to solve the above problems, the present disclosure provides a three-level power factor rectifier with reduced voltage stress to overcome the problems of the prior art. Therefore, the three-level power factor rectifier of the present disclosure includes a diode bridge arm, a bridge arm group, an input inductor, a capacitor group and a controller, and the bridge arm group includes a first bridge arm and a second bridge arm. The diode bridge arm includes a first diode and a second diode connected in series, and the bridge arm group is connected in parallel with the diode bridge arm. The first bridge arm includes a first switch, a second switch, a third switch and a fourth switch connected in series in sequence, and the second bridge arm is connected in parallel with the second switch and the third switch, and includes a first freewheeling element and a second freewheeling element connected in series in sequence. The input inductor is coupled between a first node between the second switch and the third switch, a second node between the first diode and the second diode, and an input end receiving an AC power supply. The capacitor group is connected in parallel with the bridge arm group, and includes a first capacitor and a second capacitor connected in series in sequence, and the midpoint between the first capacitor and the second capacitor is coupled to the first freewheeling element and the second freewheeling element. The controller operates the first bridge arm in a burst mode, and the burst mode includes a burst period and a burst sleep period. When the burst sleep period enters the burst period, the controller turns on the second switch and the third switch for a specific period of time.

[0008] In order to solve the above problems, the present disclosure provides a three-level power factor rectifier with reduced voltage stress to overcome the problems of the prior art. Therefore, the three-level power factor rectifier of the present disclosure includes a diode bridge arm, a bridge arm group, an input inductor, a capacitor group and a controller, and the bridge arm group includes a first bridge arm and a second bridge arm. The diode bridge arm includes a first diode and a second diode connected in series, and the bridge arm group is connected in parallel with the diode bridge arm. The first bridge arm includes a first switch, a second switch, a third switch and a fourth switch connected in series in sequence, and the second bridge arm is connected in parallel with the second switch and the third switch, and includes a first freewheeling element and a second freewheeling element connected in series in sequence. The input inductor is coupled between a first node between the second switch and the third switch, a second node between the first diode and the second diode, and an input end receiving an AC power supply. The capacitor group is connected in parallel with the bridge arm group, and includes a first capacitor and a second capacitor connected in series in sequence, and the midpoint between the first capacitor and the second capacitor is coupled to the first freewheeling element and the second freewheeling element. The controller operates the first bridge arm in a light-load burst mode, and the burst mode includes a burst period and a burst sleep period. When the controller operates the first bridge arm in the burst sleep period, the AC power supply is in the positive half cycle, and the voltage value of the AC power supply is higher than the first threshold, the controller turns on the first switch and the second switch; when the controller operates the first bridge arm in the burst sleep period, the AC power supply is in the negative half cycle, and the voltage value of the AC power supply is lower than the second threshold, the controller turns on the third switch and the fourth switch.

[0009] In order to solve the above problems, the present disclosure provides an operation method of a three-level power factor rectifier to overcome the problems of the prior art. Therefore, the three-level power factor rectifier of the present disclosure includes a diode bridge arm, a bridge arm group and a capacitor group, and the bridge arm group includes a first switch, a second switch, a third switch and a fourth switch connected in series in sequence to form a discharge path from the input inductor of the three-level power factor rectifier to the capacitor group. The operation method of the three-level power factor rectifier includes the following steps: (a) converting the AC power supply to the DC power supply by controlling the on / off of the first switch, the second switch, the third switch and the fourth switch. (b) determining that the three-level power factor rectifier is in a light load and entering a burst mode, and the burst mode includes a burst period and a burst sleep period. (c) when the AC power supply is in a positive half cycle and the voltage value of the AC power supply is higher than a first threshold value during the burst sleep period, turning on the first switch and the second switch. (d) when the AC power supply is in a negative half cycle and the voltage value of the AC power supply is lower than a second threshold value during the burst sleep period, turning on the third switch and the fourth switch. (e) When the burst period is entered from the burst sleep period, the second switch and the third switch are turned on for a specific period of time.

[0010] The main purpose and effect of the present disclosure is that when the three-level power factor rectifier operates in the burst mode, the input inductor is kept in the demagnetized state in the burst mode through the specific switch operation method of the present disclosure, so as to prevent the voltage at the two ends of the switch from exceeding the upper limit of the preset specification when the three-level power factor rectifier operates in the burst mode. In this way, the switch can select a switch element with a suitable rated specification, thereby achieving the effect of reducing the construction cost of the three-level power factor rectifier.

[0011] In order to further understand the technology, means and effects adopted by the present invention to achieve the predetermined purpose, please refer to the following detailed description and drawings of the present invention. It is believed that the purpose, characteristics and features of the present invention can be understood in depth and in detail. However, the attached drawings are only provided for reference and explanation and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A circuit block diagram of a three-level power factor rectifier with reduced voltage stress disclosed in the present invention;

[0013] Figure 2A to Figure 2F Schematic diagram of various operating modes of the three-level power factor rectifier disclosed in the present invention;

[0014] Figure 3A It is a waveform diagram of the three-level power factor rectifier of the present disclosure operating in the first embodiment of the general mode;

[0015] Figure 3B It is a waveform diagram of the third-level power factor rectifier of the present disclosure operating in the general mode of the second embodiment;

[0016] Figure 4 The switching timing diagram of the three-level power factor rectifier disclosed in the present invention operating in a general mode within a switching cycle;

[0017] Figure 5 A switching waveform diagram of the three-level power factor rectifier disclosed herein operating in a burst mode without using a specific switching operation method;

[0018] Fig. 6A The switching timing diagram of the three-level power factor rectifier of the present disclosure operating in the burst mode and entering the burst period from the burst sleep period;

[0019] Figure 6B The switching timing diagram of the three-level power factor rectifier of the present invention operating in the burst mode and in the burst sleep period;

[0020] Figure 6C A switching timing diagram of the three-level power factor rectifier of the present disclosure operating in a burst mode; and

[0021] Figure 7The invention discloses a method flow chart of an operation method of a three-level power factor rectifier.

[0022] Description of Reference Numerals

[0023] 100…Three-stage power factor rectifier

[0024] 100-1…Input

[0025] 1…Diode bridge arm

[0026] D1…First diode

[0027] D2…Second diode

[0028] 2…Bridge arm group

[0029] 22…First bridge arm

[0030] S1…First switch

[0031] S2…Second switch

[0032] S3…The third switch

[0033] S4…Fourth switch

[0034] A…First Node

[0035] B…Second Node

[0036] Cp…parasitic capacitance

[0037] 24…Second bridge arm

[0038] 242…First freewheeling element

[0039] 244…Second freewheeling element

[0040] 3…Input inductance

[0041] L1…First inductor

[0042] L2…Second inductor

[0043] 4…Capacitor Bank

[0044] C1…First capacitor

[0045] C2…Second capacitor

[0046] N…midpoint

[0047] 5…Controller

[0048] 200…Load

[0049] Vac…AC power supply

[0050] Vm…voltage value

[0051] VH…First Threshold

[0052] VL…Second threshold

[0053] Vdc…DC power supply

[0054] Vab…voltage

[0055] Vc1…first capacitor voltage

[0056] Vc2…Second capacitor voltage

[0057] Vds1~Vds4…voltage

[0058] Sc1~Sc4…control signal

[0059] Ds…Switching cycle

[0060] Td1…First dead time

[0061] Td2…Second dead time

[0062] Tx…Time

[0063] BM…Burst Mode

[0064] B_on…Emergency period

[0065] B_off…burst sleep period

[0066] TA…specific period

[0067] Thl…Crossover period

[0068] I, II...virtual frame

[0069] SP…Preset Specifications

[0070] (S100) to (S500) ... steps DETAILED DESCRIPTION

[0071] The technical content and detailed description of the present invention are described as follows with reference to the accompanying drawings:

[0072] See also Figure 1The circuit block diagram of the three-level power factor rectifier with reduced voltage stress disclosed in the present invention. The three-level power factor rectifier 100 receives an AC power source Vac and is coupled to a load or a subsequent conversion circuit (hereinafter collectively referred to as a load 200) to provide a DC power source Vdc to power the load 200. The three-level power factor rectifier 100 includes a diode bridge arm 1, a bridge arm group 2, an input inductor 3, a capacitor group 4 and a controller 5, and the bridge arm group 2 includes a first bridge arm 22 and a second bridge arm 24. The diode bridge arm 1 is connected in parallel to the first bridge arm 22 of the bridge arm group 2 and the capacitor group 4, and the diode bridge arm 1 includes a first diode D1 and a second diode D2 connected in series. The first diode D1 and the second diode D2 can be replaced by active switches (such as but not limited to transistors), and their conduction / disconnection is controlled by the controller 5.

[0073] The first bridge arm 22 includes a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4 connected in series in sequence, and the second bridge arm 24 includes a first freewheeling element 242 and a second freewheeling element 244 connected in series in sequence. The first end of the first freewheeling element 242 is coupled to the node between the first switch S1 and the second switch S2, the second end of the first freewheeling element 242 is coupled to the first end of the second freewheeling element 244, and the second end of the second freewheeling element 244 is coupled to the node between the third switch S3 and the fourth switch S4, so as to form a circuit structure in which the second bridge arm 24 is connected in parallel to the second switch S2 and the third switch S3. The first freewheeling element 242 and the second freewheeling element 244 can be passive diodes, or can be active switches (such as but not limited to transistors) whose on / off is controlled by the controller 5.

[0074] The first end of the input inductor 3 is coupled to the input end 100-1 of the three-stage power factor rectifier 100, and receives the AC power source Vac through the input end 100-1. The second end of the input inductor 3 is coupled to the first node A between the second switch S2 and the third switch S3, and the third end of the input inductor 3 is coupled to the second node B between the first diode D1 and the second diode D2. Specifically, the input inductor 3 may include a first inductor L1 and a second inductor L2. The first inductor L1 is coupled between the input end 100-1 and the first node A, and the second inductor L2 is coupled between the input end 100-1 and the second node B. Among them, the input inductor 3 may only include any one of the first inductor L1 and the second inductor L2, and not the first inductor L1 or the second inductor L2. Figure 1 The number of items presented is limited to 2.

[0075] The capacitor group 4 can be coupled to the load 200 via a DC bus (DC-link), and the capacitor group 4 includes a first capacitor C1 and a second capacitor C2 connected in series. The midpoint N between the first capacitor C1 and the second capacitor C2 is coupled to the node between the first freewheeling element 242 and the second freewheeling element 244, so that the midpoint N forms the midpoint potential end of the capacitor group 4. The controller 5 is coupled to the first bridge arm 22, and provides control signals Sc1-Sc4 to the switches S1-S4 respectively, so as to control the three-level power factor rectifier 100 to convert the AC power Vac into the DC power Vdc by controlling the first bridge arm 22. Among them, the controller 5 has at least two operation modes. When the load 200 is higher than a load threshold (for example, more than 3.5% of the rated full load value), the controller 5 can operate the three-level power factor rectifier 100 in the normal mode, and when the load 200 is lower than the load threshold (for example, less than 3.5% of the rated full load value, i.e., light load or no load), the controller 5 can operate the three-level power factor rectifier 100 in the burst mode. In the burst mode, there are generally a burst period and a burst sleep period. In the burst period, the controller 5 provides control signals Sc1-Sc4 to control switches S1-S4 to maintain the energy of the first capacitor C1 and the second capacitor C2 to maintain and stabilize the voltage of the DC power source Vdc. Conversely, in the burst sleep period, the controller 5 may not provide control signals Sc1-Sc4 to control switches S1-S4 to reduce the power consumption of the three-level power factor rectifier 100 by sleeping (or standby).

[0076] See also Figure 2A to Figure 2F Schematic diagram of each operating mode of the three-level power factor rectifier disclosed in the present invention, and refer to Figure 1 The operation mode of the three-level power factor rectifier 100 consists of 6 modes, and the controller 5 controls the on and off of switches S1 to S4 to form the following modes: Figure 2A to Figure 2F When the AC power source Vac is in the positive half cycle, the input current flows into the first node A of the three-stage power factor rectifier 100 and flows out from the second node B. At this time, the second diode D2 is forward biased, and the input current is in the positive direction. Figure 2A As shown, the three-level power factor rectifier 100 operates in the +2 mode. At this time, the input current flows through the first switch S1, the second switch S2, the first capacitor C1 and the second capacitor C2 of the capacitor group 4 and the second diode D2, and the voltage Vab between the first node A and the second node B of the three-level power factor rectifier 100 is the first capacitor voltage Vc1 of the first capacitor C1 plus the second capacitor voltage Vc2 of the second capacitor C2. Figure 2BAs shown, the three-stage power factor rectifier 100 operates in the +1 mode. At this time, the input current flows through the third switch S3, the second freewheeling element 244, the second capacitor C2 and the second diode D2, and the voltage Vab between the first node A and the second node B is the second capacitor voltage Vc2. Figure 2C As shown, the three-level power factor rectifier 100 operates in the +0 mode. At this time, the input current only flows through the third switch S3, the fourth switch S4 and the second diode D2, and the voltage Vab between the first node A and the second node B is 0, and the current direction is forward.

[0077] When the AC power source Vac is in the negative half cycle, the input current flows in from the second node B and flows out from the first node A. At this time, the first diode D1 is forward biased, and the input current is in the negative direction. Figure 2D As shown, the three-level power factor rectifier 100 operates in the -2 mode. At this time, the input current flows through the first diode D1, the first capacitor C1, the second capacitor C2, the third switch S3 and the fourth switch S4, and the voltage Vab between the first node A and the second node B is the negative first capacitor voltage Vc1 minus the second capacitor voltage Vc2. Figure 2E As shown, the three-level power factor rectifier 100 operates in the -1 mode, the current flows through the first diode D1, the first capacitor C1, the first freewheeling element 242 and the second switch S2, and the voltage Vab between the first node A and the second node B is the negative first capacitor voltage Vc1. Figure 2F As shown, the three-level power factor rectifier 100 operates in a -0 mode, the current flows through the first diode D1, the first switch S1 and the second switch S2, and the voltage Vab between the first node A and the second node B is 0, and the current direction is negative.

[0078] See also Figure 3A The waveform diagram of the three-level power factor rectifier of the present disclosure operating in the first embodiment of the general mode, Figure 3B This is a waveform diagram of the third-level power factor rectifier of the present disclosure operating in the general mode of the second embodiment, with reference to Figure 1 to Figure 2F .exist Figure 3A and Figure 3B In combination Figure 2A to Figure 2F The various modes described above make the voltage Vab between the first node A and the second node B fit the sinusoidal curve of the input power source Vac by controlling the duration of the three-level power factor rectifier 100 in each mode. Figure 3AIn the figure, it is assumed that the first capacitor voltage Vc1 is equal to the second capacitor voltage Vc2, both of which are 0.5Vdc (Vdc is the output power supply). When the input power supply Vac is in the positive half cycle and the voltage Vab is between 0.5Vdc and Vdc, the controller 5 controls the three-level power factor rectifier 100 to switch back and forth between the +1 mode and the +2 mode according to the voltage value Vm of the AC power supply Vac, and in the +1 mode and +2 mode, the modulation is performed by adjusting the duty cycle of the control signals Sc1~Sc4. When the input power supply Vac is in the positive half cycle and the voltage Vab is between 0 and 0.5Vdc, the controller 5 controls the three-level power factor rectifier 100 to switch back and forth between the +1 mode and the +0 mode according to the voltage value Vm of the AC power supply Vac, and in the +1 mode and +0 mode, the modulation is performed by adjusting the duty cycle of the control signals Sc1~Sc4. The operation from the +2 mode to the +0 mode is performed when the input power source Vac is in the positive half cycle.

[0079] On the contrary, when the input power Vac is in the negative half cycle and the voltage Vab is between -0.5Vdc and -Vdc, the controller 5 controls the three-level power factor rectifier 100 to switch back and forth between the -1 mode and the -2 mode according to the voltage value Vm of the AC power Vac, and modulates by adjusting the duty ratio of the control signals Sc1 to Sc4 in the -1 mode and -2 mode. When the input power Vac is in the negative half cycle and the voltage Vab is between 0 and -0.5Vdc, the controller 5 controls the three-level power factor rectifier 100 to switch back and forth between the -1 mode and the -0 mode according to the voltage value Vm of the AC power Vac, and modulates by adjusting the duty ratio of the control signals Sc1 to Sc4 in the -1 mode and -0 mode. The above-mentioned operation from the -2 mode to the -0 mode is the operation when the input power Vac is in the negative half cycle.

[0080] exist Figure 3A In the embodiment, the voltage Vab is boosted from -Vdc to -0 and from 0 to Vdc, which is called the boosting step, and the voltage is reduced from Vdc to 0 and from 0 to -Vdc, which is called the reducing step. When the voltage value Vm of the AC power source Vac is in the positive half cycle or the negative half cycle, the controller 5 operates the switches S1 to S4 according to the changes of each mode, so that the voltage Vab is repeatedly boosted and reduced, thereby controlling the three-level power factor rectifier 100 to convert the AC power source Vac into the DC power source Vdc and correct its power factor.

[0081] Figure 3B Similar to Figure 3A, its modulation strategy is mainly to reduce the current flowing into or out of the midpoint N by shortening the duration of the +1 mode and the -1 mode. When the input power Vac is in the positive half cycle and the voltage Vab is between 0 and Vdc (Vdc is the output power), in each switching cycle Ds (i.e., each waveform substantially equal to a square wave), the controller 5 controls the three-level power factor rectifier 100 to switch between the +2 mode and the +0 mode briefly via the +1 mode for modulation, and the three-level power factor rectifier 100 only passes through the +1 mode for a short time for transition. Similarly, when the input power Vac is in the negative half cycle and the voltage Vab is between -0 and -Vdc, in each switching cycle Ds, the controller 5 controls the three-level power factor rectifier 100 to switch between the -2 mode and the -0 mode briefly via the -1 mode for modulation, and the three-level power factor rectifier 100 only passes through the -1 mode for a short time for transition.

[0082] Since the three-level power factor rectifier 100 switches between the +0 mode and the +2 mode, or switches between the -0 mode and the -2 mode in each switching cycle Ds, and the operation time of the +1 and -1 modes as transition modes is very short, the current flowing into or out of the midpoint N is small, which can reduce the voltage fluctuation of the midpoint N. At the same time, the current flowing through the first freewheeling element 242 and the second freewheeling element 244 is also small, which can reduce the specifications of the components and their costs.

[0083] See also Figure 4 The switching timing diagram of the three-level power factor rectifier of the present invention operating in a general mode within a switching cycle is shown in FIG. Figure 1 to Figure 3B .like Figure 4 As shown, the first switch S1 and the third switch S3 are complementary, and the controller 5 sets a first dead time Td1 between the operation of the first switch S1 state transition (i.e., from on to off or from off to on) and the third switch S3 state transition. Similarly, the second switch S2 and the fourth switch S4 are complementary, and the controller 5 sets a second dead time Td2 between the operation of the second switch S2 state transition and the fourth switch S4 state transition to avoid more than one current path at the same time. Figure 3B The process of the voltage Vab between the first node A and the second node B switching from 0 to Vdc corresponds to Figure 3B The three-stage power factor rectifier 100 shown in the figure switches from the +0 mode to the +2 mode (when the input current is in the positive direction) or switches from the -2 mode to the -0 mode (when the input current is in the negative direction), both of which are steps of boosting the voltage Vab. Figure 4In the step of boosting in a switching cycle Ds, the controller 5 first turns off the fourth switch S4, then turns on the second switch S2, then turns off the third switch S3, and finally turns on the first switch S1. The overlapping time of the second switch S2 and the third switch S3 being turned on simultaneously is Tx.

[0084] Similarly, see Figure 3B , the process of voltage Vab switching from Vdc to 0 corresponds to Figure 3B The three-stage power factor rectifier 100 shown in the figure switches from the +2 mode to the +0 mode (when the input current is in the positive direction) or switches from the -0 mode to the -2 mode (when the input current is in the negative direction), both of which are voltage reduction steps for reducing the voltage Vab. Figure 4 In the voltage reduction step within a switching cycle Ds, the controller 5 first turns off the first switch S1 , then turns on the third switch S3 , then turns off the second switch S2 , and finally turns on the fourth switch S4 .

[0085] See also Figure 5 The switching waveform diagram of the three-level power factor rectifier of the present disclosure operating in the burst mode without using a specific switching operation method is shown in FIG. Figure 1 to Figure 4 Since the switches S1 to S4 are not ideal switch elements, they all have parasitic capacitance Cp (such as but not limited to Ciss, Coss, etc., Figure 2A to Figure 2F (omitted and not shown). Therefore, when the three-level power factor rectifier 100 operates in the burst period B_on or the burst sleep period B_off of the burst mode BM, the voltage Vds1-Vds4 at the two ends of some switches S1-S4 will exceed the upper limit of the preset specification SP (for example but not limited to, 960V) due to the influence of the parasitic capacitance Cp. The reason why the voltage Vds1-Vds4 at the two ends of some switches S1-S4 exceeds the upper limit of the preset specification SP is that when the three-level power factor rectifier 100 operates in the burst mode BM, since the output end does not need too much energy when the load is light, the energy stored in the input inductor 3 is not completely provided to the capacitor group 4, so that the input inductor 3 has not been completely demagnetized. Therefore, when the three-level power factor rectifier 100 enters the burst period B_on from the burst sleep period B_off, causing the partial switches S1-S4 to be turned on, the parasitic capacitor Cp is charged, causing the voltage Vds1-Vds4 at the two ends of the partial switches S1-S4 to be temporarily raised to exceed the upper limit of the preset specification SP (as shown in the dashed box I).

[0086] On the other hand, when the three-level power factor rectifier 100 is in the burst sleep period B_off, since the input inductor 3 does not control the direction of the switch given demagnetization path through the controller 5, the energy can flow naturally according to the voltage magnitude of the interaction between the AC power source Vac and the DC power source Vdc, resulting in the energy in the parasitic capacitor Cp also being in a natural flow state. In this way, the voltage Vds1~Vds4 at the two ends of some switches S1~S4 may be thrown to an upper limit exceeding the preset specification SP (as shown in the virtual box II) through the natural voltage equalization method. Therefore, in summary, the main purpose and effect of the present disclosure is that when the three-level power factor rectifier 100 operates in the burst mode BM, the input inductor 3 is kept in the demagnetization state in the burst mode BM through the specific switch operation method of the present disclosure, so as to avoid the voltage Vds1~Vds4 at the two ends of the switches S1~S4 exceeding the upper limit of the preset specification SP when the three-level power factor rectifier 100 operates in the burst mode BM. In this way, the switches S1 - S4 can be made of switch elements with appropriate rated specifications, thereby reducing the construction cost of the three-level power factor rectifier 100 .

[0087] See also Fig. 6A The switching timing diagram of the three-level power factor rectifier of the present disclosure operating in the burst mode and entering the burst period from the burst sleep period is shown in FIG. Figure 1 to Figure 5 .exist Fig. 6A In the embodiment, when the controller 5 knows that the load 200 is lower than the load threshold through, for example but not limited to, the output current of the three-level power factor rectifier 100, the controller 5 operates the first bridge arm 22 in the light-load burst mode BM, and the burst mode BM includes a burst period B_on and a burst sleep period B_off. In the burst mode BM, the controller 5 usually sets the upper and lower voltage limits of the DC power source Vdc. When the controller 5 determines that the DC power source Vdc on the DC bus (DC-link) is still sufficient (i.e., not lower than the preset voltage value), the controller 5 operates the first bridge arm 22 in the burst sleep period B_off, and the voltage value of the DC power source Vdc gradually decreases. Since the load 200 is lower than the load threshold, the voltage value of the DC power source Vdc decreases slowly, so that the duration of the burst sleep period B_off can usually be much longer than the burst period B_on. On the contrary, when the controller 5 determines that the DC power source Vdc on the DC-link is insufficient (i.e., reaches the preset lower limit voltage value), the controller 5 operates the first bridge arm 22 in the burst period B_on to charge the first capacitor C1 and the second capacitor C2. When the voltage value of the DC power source Vdc charged to the first capacitor C1 and the second capacitor C2 reaches the upper limit voltage value, the operation period is changed from the burst period B_on to the burst sleep period B_off.

[0088] When the operation period enters the burst period B_on from the burst sleep period B_off, the controller 5 turns on the second switch S2 and the third switch S3 for a specific period TA. In this way, when entering the burst period B_on, the following is formed: Figure 2B , Figure 2E As shown in FIG. 1 , the discharge path from the input inductor 3 to the capacitor bank 4, that is, the demagnetization path for releasing the energy of the input inductor 3 to the capacitor bank 4, is used to maintain the demagnetization state of the input inductor 3. Therefore, when the specific period TA ends, the controller 5 controls the switching of the first bridge arm 22 to generate a voltage Vab between the first node A and the second node B as shown in FIG. Figure 3A , Figure 3B When the voltage Vds1 to Vds4 at the two ends of the switches S1 to S4 changes, the voltage Vds1 to Vds4 at the two ends of the switches S1 to S4 will not produce the same Figure 5 The high pulse ripple shown in the virtual box I causes the voltage Vds1-Vds4 at the two ends of the switches S1-S4 to exceed the upper limit of the preset specification SP. It is worth mentioning that in one embodiment, in a specific period of time TA, the controller 5 turns off the first switch S1 and the fourth switch S4, and turns on the second switch S2 and the third switch S3 to prevent the three-level power factor rectifier 100 from generating an additional current path.

[0089] Further, when the operation period enters the burst period B_on, and after the specific period TA ends, the controller 5 can operate the first bridge arm 22 to Figure 3A , Figure 3B The step-up and step-down steps of the voltage step-up and the switching timing of the step-down and the voltage step-down can be referred to in conjunction with Figure 4 , after the specific period TA ends, the step of voltage reduction is entered. In a switching cycle Ds, the controller 5 turns off the first switch S1 and the second switch S2 at the same time, keeps the third switch S3 turned on, and finally turns on the fourth switch S4. Then, in the same switching cycle Ds, the step of voltage increase follows, the controller 5 first turns off the fourth switch S4, then turns on the second switch S2, then turns off the third switch S3, and finally turns on the first switch S1.

[0090] See also Figure 6B The switching timing diagram of the three-level power factor rectifier of the present invention operating in the burst mode and in the burst sleep period is shown in FIG. Figure 1 to Figure 6A During the sudden sleep period B_off, the controller 5 can mainly control the switches S1~S4 to turn on / off at a low frequency (for example, but not limited to twice the mains frequency) to provide different current paths in different periods. In this way, the energy of the input inductor 3 or the capacitor group 4 can flow through these different current paths, avoiding the input inductor 3 from causing the parasitic capacitor Cp to cause a natural voltage equalization phenomenon due to the lack of the controller 5 to control the direction of the switch given demagnetization path. Figure 5Specifically, in the burst sleep period B_off, when the AC power source Vac is in the positive half cycle and the voltage value Vm of the AC power source Vac is higher than the first threshold value VH, the controller 5 turns on the first switch S1 and the second switch S2 to provide Figure 2A In the burst sleep period B_off, when the AC power source Vac is in the negative half cycle and the voltage value Vm of the AC power source Vac is lower than the second threshold value VL, the controller 5 turns on the third switch S3 and the fourth switch S4 to provide Figure 2D In this way, during the burst sleep period B_off, a current path as shown in the figure can be formed.

[0091] 2A, Figure 2D As shown, a demagnetization path is provided from the input inductor 3 to the capacitor group 4 to maintain the demagnetization state of the input inductor 3 .

[0092] The first threshold value VH set by the controller 5 is higher than the zero-crossing value 0 of the AC power source Vac, and the second threshold value VL set by the controller 5 is lower than the zero-crossing value 0. It is worth mentioning that, in one embodiment, when the controller 5 turns on the first switch S1 and the second switch S2 (i.e., when the voltage value Vm is higher than the first threshold value VH), the controller 5 can choose to turn off the third switch S3 and the fourth switch S4 to prevent the three-level power factor rectifier 100 from generating an additional current path. Similarly, when the controller 5 turns on the third switch S3 and the fourth switch S4 (i.e., when the voltage value Vm is lower than the second threshold value VL), the controller 5 can choose to turn off the first switch S1 and the second switch S2 to prevent the three-level power factor rectifier 100 from generating an additional current path.

[0093] On the other hand, in the burst sleep period B_off, when the voltage value Vm is between the first threshold value VH and the second threshold value VL during the crossover period Th1, the controller 5 turns on the second switch S2 and the third switch S3, and turns off the first switch S1 and the fourth switch S4, so as to provide Figure 2B , Figure 2E (Different from Figure 2A , Figure 2D) is shown in the current path. Therefore, the operating frequency of the controller 5 operating the switch in the first bridge arm 22 during the burst sleep period B_off is roughly twice the mains frequency (for example, but not limited to, 120Hz) to provide different current paths in different time periods. On the contrary, during the burst period B_on or the normal operation mode, the operating frequency of the controller 5 operating the switch in the first bridge arm 22 is usually much higher than the mains frequency, and its general operating frequency is usually above kilohertz (for example, but not limited to 4kHz, 16kHz, etc.). It is worth mentioning that in one embodiment, in the low-frequency operation of the burst sleep period B_off, the controller 5 can also set the first dead time Td1 between the operation of the first switch S1 state transition (i.e., from on to off or from off to on) and the third switch S3 state transition, and also set the second dead time Td2 between the operation of the second switch S2 state transition and the fourth switch S4 state transition to avoid more than one current path at the same time.

[0094] See also Figure 6C The switching timing diagram of the three-level power factor rectifier of the present invention operating in the burst mode is shown in FIG. Figure 1 to Figure 6B . Figure 6C The waveform is mainly integrated Fig. 6A The burst period B_on and Figure 6B The burst sleep period B_off. Figure 6B In the burst sleep period B_off operation structure of the switches S1 to S4 being turned on / off, when the controller 5 determines that the DC power source Vdc on the DC-link is insufficient, it enters the burst period B_on to maintain the DC power source Vdc. Moreover, after exiting the burst period B_on, the controller 5 still determines how to control the on / off of the switches S1 to S4 based on the voltage value Vm, so that in the burst mode BM, the controller 5 can control the on / off of the switches S1 to S4 by Figure 6C The specific switching operation method keeps the input inductor 3 in a demagnetized state.

[0095] See also Figure 7 The method flow chart of the operation method of the three-level power factor rectifier disclosed in the present invention is combined with Figure 1 to Figure 6C. The present disclosure mainly involves maintaining the input inductor 3 in a demagnetized state in the burst mode BM through a specific switch operation method when the three-level power factor rectifier 100 operates in the burst mode BM, thereby preventing the voltages Vds1 to Vds4 at the two ends of the switches S1 to S4 from exceeding the upper limit of the preset specification SP when the three-level power factor rectifier 100 operates in the burst mode BM. Therefore, the specific switch operation method of the present disclosure includes converting the AC power supply into a DC power supply (S100) by controlling the on / off of the first switch, the second switch, the third switch, and the fourth switch. A preferred embodiment is to use the controller 5 to provide control signals Sc1 to Sc4 to the switches S1 to S4, respectively, so as to control the three-level power factor rectifier 100 to convert the AC power supply Vac into a DC power supply Vdc by controlling the first bridge arm 22.

[0096] Then, it is determined that the three-level power factor rectifier is in a light load and enters a burst mode, and the burst mode includes a burst period and a burst sleep period (S200). The controller 5 has at least two operation modes. When the load 200 is higher than the load threshold, the controller 5 can operate the three-level power factor rectifier 100 in a normal mode, and when the load 200 is lower than the load threshold, the controller 5 can operate the three-level power factor rectifier 100 in a burst mode (Burst mode). When the controller 5 knows that the load 200 is lower than the load threshold through, for example but not limited to, the output current of the three-level power factor rectifier 100, the controller 5 operates the first bridge arm 22 in a light load burst mode BM, and the burst mode BM includes a burst period B_on and a burst sleep period B_off.

[0097] Then, when the AC power supply is in the positive half cycle and the voltage value of the AC power supply is higher than the first threshold value during the burst sleep period, the first switch and the second switch are turned on (S300); when the AC power supply is in the negative half cycle and the voltage value of the AC power supply is lower than the second threshold value during the burst sleep period, the third switch and the fourth switch are turned on (S400). During the burst sleep period B_off, the controller 5 can mainly control the switches S1 to S4 to turn on / off at a low frequency (for example, but not limited to twice the mains frequency) to provide different current paths in different time periods. In this way, the energy of the input inductor 3 or the capacitor group 4 can flow through these different current paths, avoiding the input inductor 3 not being demagnetized and still storing too much energy, resulting in the phenomenon of natural resonance between the input inductor 3 and the parasitic capacitor Cp.

[0098] Finally, when the burst sleep period enters the burst period, the second switch and the third switch are turned on for a specific period of time (S500). A preferred embodiment is to use the controller 5 to turn on the second switch S2 and the third switch S3 for a specific period of time TA, so that when entering the burst period B_on, the following is formed: Figure 2B , Figure 2EAs shown, the demagnetization path from the input inductor 3 to the capacitor group 4 is maintained, thereby maintaining the demagnetization state of the input inductor 3. It is worth mentioning that, in one embodiment, Figure 7 The detailed operation method of the three-stage power factor rectifier 100 not described in the specification can be referred to in conjunction with Figure 1 to Figure 6C , I will not elaborate on it here.

[0099] However, the above description is only a detailed description and drawings of the preferred specific embodiments of the present invention, but the features of the present invention are not limited thereto and are not used to limit the present invention. The entire scope of the present invention shall be based on the following claims. All embodiments that conform to the spirit of the claims of the present invention and similar variations thereof shall be included in the scope of the present invention. Any changes or modifications that can be easily thought of by any person skilled in the art within the field of the present invention shall be covered by the following claims of this case.

Claims

1. A three-stage power factor rectifier, comprising: A diode bridge arm includes a first diode and a second diode connected in series; A bridge arm group is connected in parallel with the diode bridge arm, and the bridge arm group includes: The first bridge arm comprises a first switch, a second switch, a third switch and a fourth switch connected in series in sequence; A second bridge arm is connected in parallel to the second switch and the third switch, and comprises a first freewheeling element and a second freewheeling element connected in series in sequence; an input inductor coupled between a first node between the second switch and the third switch, a second node between the first diode and the second diode, and an input terminal receiving an AC power source; a capacitor group, connected in parallel with the bridge arm group, and comprising a first capacitor and a second capacitor connected in series in sequence, wherein a midpoint between the first capacitor and the second capacitor is coupled to the first freewheeling element and the second freewheeling element; and A controller operates the first bridge arm in a burst mode, wherein the burst mode includes a burst period and a burst sleep period; When entering the burst period from the burst sleep period, the controller turns on the second switch and the third switch for a specific period of time.

2. The three-level power factor rectifier according to claim 1, wherein during the positive half cycle of the AC power source, the controller provides a step of boosting the voltage between the first node and the second node based on the voltage value of the AC power source, and provides a step of stepping down the voltage based on the voltage value; at the end of the specific time period and during the positive half cycle, the controller operates the first bridge arm in the step of boosting and the step of stepping down.

3. The three-level power factor rectifier according to claim 2, wherein in the step-up step, the controller operates the first bridge arm in the switching cycle in sequence of turning off the fourth switch, turning on the second switch, turning off the third switch, and turning on the first switch, and in the step-down step, the controller operates the first bridge arm in the switching cycle in sequence of turning off the first switch, turning on the third switch, turning off the second switch, and turning on the fourth switch.

4. The three-level power factor rectifier according to claim 1, wherein during the negative half cycle of the AC power source, the controller provides a step-down step for stepping down the voltage between the first node and the second node based on the voltage value of the AC power source, and provides a step-up step for stepping up the voltage based on the voltage value; at the end of the specific time period and during the negative half cycle, the controller operates the first bridge arm in the step-down step and the step-up step.

5. The three-level power factor rectifier according to claim 4, wherein in the step-down step, the controller operates the first bridge arm in the switching cycle in sequence of turning off the first switch, turning on the third switch, turning off the second switch, and turning on the fourth switch, and in the step-up step, the controller operates the first bridge arm in the switching cycle in sequence of turning off the fourth switch, turning on the second switch, turning off the third switch, and turning on the first switch. 6 . The three-level power factor rectifier according to claim 1 , wherein during the specific period, the controller turns off the first switch and the fourth switch.

7. A three-stage power factor rectifier comprising: A diode bridge arm includes a first diode and a second diode connected in series; A bridge arm group is connected in parallel with the diode bridge arm, and the bridge arm group includes: The first bridge arm comprises a first switch, a second switch, a third switch and a fourth switch connected in series in sequence; A second bridge arm is connected in parallel to the second switch and the third switch, and comprises a first freewheeling element and a second freewheeling element connected in series in sequence; an input inductor coupled between a first node between the second switch and the third switch, a second node between the first diode and the second diode, and an input terminal receiving an AC power source; a capacitor group, connected in parallel with the bridge arm group, and comprising a first capacitor and a second capacitor connected in series in sequence, wherein a midpoint between the first capacitor and the second capacitor is coupled to the first freewheeling element and the second freewheeling element; and A controller operates the first bridge arm in a light-load burst mode, wherein the burst mode includes a burst period and a burst sleep period; When the controller operates the first bridge arm in the burst sleep period, the AC power supply is in the positive half cycle, and the voltage value of the AC power supply is higher than a first threshold, the controller turns on the first switch and the second switch; when the controller operates the first bridge arm in the burst sleep period, the AC power supply is in the negative half cycle, and the voltage value of the AC power supply is lower than a second threshold, the controller turns on the third switch and the fourth switch.

8. The three-level power factor rectifier according to claim 7, wherein in the burst sleep period, when the AC power source is in the positive half cycle and the voltage value is higher than the first threshold, the controller turns off the third switch and the fourth switch.

9. The three-level power factor rectifier according to claim 7, wherein in the burst sleep period, when the AC power source is in the negative half cycle and the voltage value is lower than the second threshold, the controller turns off the first switch and the second switch.

10. The three-level power factor rectifier according to claim 7, wherein the first threshold is higher than the zero crossing value of the AC power source, and the second threshold is lower than the zero crossing value; in the burst sleep period, when the voltage value of the AC power source is between the first threshold and the second threshold, the controller turns on the second switch and the third switch, and turns off the first switch and the fourth switch.

11. The three-level power factor rectifier according to claim 7, wherein the operating frequency of the switches in the first bridge arm operated by the controller during the burst sleep period is substantially twice the mains frequency, and the operating frequency of the switches in the first bridge arm operated during the burst period is higher than the mains frequency.

12. The three-level power factor rectifier according to claim 7, wherein in the burst sleep period, the controller sets a first dead time between operating the first switch state and the third switch state, and sets a second dead time between operating the second switch state and the fourth switch state.

13. An operating method of a three-level power factor rectifier, the three-level power factor rectifier comprising a diode bridge arm, a bridge arm group and a capacitor group, and the bridge arm group comprises a first switch, a second switch, a third switch and a fourth switch connected in series in sequence to form a discharge path from an input inductor of the three-level power factor rectifier to the capacitor group, the operating method comprising the following steps: Converting an AC power source into a DC power source by controlling the on / off of the first switch, the second switch, the third switch, and the fourth switch; Determining that the three-level power factor rectifier is in a light load and enters a burst mode, and the burst mode includes a burst period and a burst sleep period; When, during the burst sleep period, the AC power source is in a positive half cycle and the voltage value of the AC power source is higher than a first threshold, turning on the first switch and the second switch; When, during the burst sleep period, the AC power source is in a negative half cycle and the voltage value of the AC power source is lower than a second threshold, turning on the third switch and the fourth switch; and When the burst period is entered from the burst sleep period, the second switch and the third switch are turned on for a specific period.

14. The operating method according to claim 13, wherein a first node is included between the second switch and the third switch, and a second node is included between the first diode and the second diode of the diode bridge arm, and the operating method further comprises the following steps: In the positive half cycle, based on the voltage value of the AC power source, a voltage boosting step is provided for boosting the voltage between the first node and the second node; In the positive half cycle, providing a voltage reduction step of reducing the voltage based on the voltage value; and At the end of the specific period and in the positive half cycle, the three-stage power factor rectifier is operated in the step-up step and the step-down step.

15. The operating method according to claim 13, wherein a first node is included between the second switch and the third switch, and a second node is included between the first diode and the second diode of the diode bridge arm, and the operating method further comprises the following steps: In the negative half cycle, providing a voltage reduction step of reducing the voltage between the first node and the second node based on the voltage value of the AC power supply; In the negative half cycle, providing a voltage boosting step for boosting the voltage based on the voltage value; and At the end of the specific period and during the negative half cycle, the three-stage power factor rectifier is operated in the voltage reduction step and the voltage increase step.

16. The operating method according to claim 13, further comprising the following steps: During the specific period, the first switch and the fourth switch are turned off.

17. The operating method according to claim 13, further comprising the following steps: In the burst sleep period, the AC power source turns off the third switch and the fourth switch in the positive half cycle when the voltage value is higher than the first threshold value; In the burst sleep period, the AC power source turns off the first switch and the second switch in the negative half cycle when the voltage value is lower than the second threshold value; and When the voltage value is between the first threshold and the second threshold, the second switch and the third switch are turned on, and the first switch and the fourth switch are turned off; The first threshold is higher than a zero crossing value of the AC power source, and the second threshold is lower than the zero crossing value.

18. The operating method according to claim 13, further comprising the following steps: In the burst sleep period, setting a first dead time between operating the first switch state and the third switch state; and In the burst sleep period, a second dead time is set between operating the second switch state and the fourth switch state.

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