Data receiving circuit, phase adjustment method, chip and equipment

Abstract

The invention discloses a data receiving circuit, a phase adjustment method, a chip and equipment, and belongs to the technical field of electronics. The PLL unit in the data receiving circuit is used for outputting a second clock signal based on the received first clock signal and the first phase step length; the data sampling unit is used for sampling the reference signal based on the second clock signal to obtain a first data signal; the PLL unit is further used for calibrating the first phase step length based on the first data signal to obtain a second phase step length, the second phase step length is used for adjusting the phase of a clock signal received by the PLL unit, and the adjusted clock signal is used for sampling a reference signal to obtain a second data signal. The second phase step length is obtained through dynamic calibration according to the sampling condition of the previously received first data signal, and the sampling accuracy corresponding to the second phase step length is higher.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of electronic technology, and in particular to a data receiving circuit, a phase adjustment method, a chip and a device. Background Art

[0002] With the development of electronic technology, more and more application scenarios involve transmitting data signals between two chips, such as sending data signals from an external chip to a main control chip. In the process of transmitting data signals using an external chip and a main control chip, due to the different path delays of the data signal and the clock signal between the external chip and the main control chip, the main control chip receiving the data signal may not be able to correctly sample the data signal based on the clock signal.

[0003] If the clock synchronization between the main control chip and the external chip is carried out by using the source synchronization method, the timing of the main control chip and the external chip can be unified, although the data signal can be sampled correctly, it is only applicable to low-speed data signals. Therefore, a data receiving circuit configured in the main control chip is urgently needed to sample any data signal. Summary of the invention

[0004] The embodiment of the present application provides a data receiving circuit, a phase adjustment method, a chip and a device, which can be used to provide a sampling accuracy of a data signal. The technical solution is as follows:

[0005] On the one hand, an embodiment of the present application provides a data receiving circuit, which includes a PLL (phase locked loop) unit and a data sampling unit; the PLL unit is used to output a second clock signal based on a received first clock signal and a first phase step; the data sampling unit is used to sample a reference signal based on the second clock signal to obtain a first data signal; the PLL unit is also used to calibrate the first phase step based on the first data signal to obtain a second phase step, and the second phase step is used to adjust the phase of the clock signal received by the PLL unit, and the adjusted clock signal is used to sample the reference signal to obtain a second data signal.

[0006] In a possible implementation manner, the first phase step includes 0, and the second clock signal is the same as the first clock signal.

[0007] In one possible implementation, the PLL unit is used to adjust the first phase step based on the first data signal and the reference signal, determine the phase calibration upper limit value and the phase calibration lower limit value of the PLL unit based on the adjustment result; and determine the second phase step based on the phase calibration upper limit value and the phase calibration lower limit value.

[0008] In a possible implementation, the PLL unit is configured to obtain a phase calibration upper limit value based on the addition of a first phase step and a first adjustment step when the first data signal and the reference signal are the same.

[0009] In one possible implementation, the PLL unit is used to add the first phase step and the first adjustment step to obtain a third phase step; adjust the phase of the received third clock signal based on the third phase step to obtain a fourth clock signal, and output the fourth clock signal; the data sampling unit is also used to sample the reference signal based on the fourth clock signal to obtain a third data signal; the PLL unit is also used to determine the third phase step as the phase calibration upper limit value when the third data signal and the reference signal are different, or, when the third data signal and the reference signal are the same, cyclically perform the operation of adding the first adjustment step and the third phase step until the data signal sampled based on the phase step obtained by addition is different from the reference signal, and the phase step obtained by addition is determined as the phase calibration upper limit value.

[0010] In one possible implementation, the PLL unit is used to obtain a fourth phase step based on the addition of the first phase step and the second adjustment step when the first data signal and the reference signal are different; obtain a phase calibration upper limit value based on the addition of the fourth phase step and the first adjustment step, and the first adjustment step is smaller than the second adjustment step.

[0011] On the other hand, a phase adjustment method is provided, comprising: outputting a second clock signal based on a received first clock signal and a first phase step; sampling a reference signal based on the second clock signal to obtain a first data signal; calibrating the first phase step based on the first data signal to obtain a second phase step, wherein the second phase step is used to adjust the phase of the received clock signal, and the adjusted clock signal is used to sample the reference signal to obtain a second data signal.

[0012] In a possible implementation manner, the first phase step includes 0, and the second clock signal is the same as the first clock signal.

[0013] In one possible implementation, calibrating the first phase step based on the first data signal to obtain the second phase step includes: adjusting the first phase step based on the first data signal and the reference signal, and determining a phase calibration upper limit value and a phase calibration lower limit value based on the adjustment result; and determining the second phase step based on the phase calibration upper limit value and the phase calibration lower limit value.

[0014] In one possible implementation, the first phase step is adjusted based on the first data signal and the reference signal, and the phase calibration upper limit value is determined based on the adjustment result, including: when the first data signal and the reference signal are the same, the phase calibration upper limit value is obtained by adding the first phase step and the first adjustment step.

[0015] In a possible implementation, a phase calibration upper limit value is obtained based on the addition of a first phase step and a first adjustment step, including: adding the first phase step and the first adjustment step to obtain a third phase step; adjusting the phase of a received third clock signal based on the third phase step to obtain a fourth clock signal, and sampling a reference signal based on the fourth clock signal to obtain a third data signal; when the third data signal and the reference signal are different, determining the third phase step as the phase calibration upper limit value, or, when the third data signal and the reference signal are the same, cyclically performing the operation of adding the first adjustment step and the third phase step until a data signal sampled based on the phase step obtained by addition is different from the reference signal, and determining the phase step obtained by addition as the phase calibration upper limit value.

[0016] In one possible implementation, the first phase step is adjusted based on the first data signal and the reference signal, and the phase calibration upper limit is determined based on the adjustment result, including: when the first data signal and the reference signal are different, a fourth phase step is obtained by adding the first phase step and the second adjustment step; and the phase calibration upper limit is obtained by adding the fourth phase step and the first adjustment step, and the first adjustment step is smaller than the second adjustment step.

[0017] On the other hand, a main control chip is provided, and the main control chip includes the data receiving circuit shown in any possible implementation manner described above.

[0018] In a possible implementation, the main control chip is a FPGA (Field Programmable Gate Array) chip or an ASIC (Application Specific Integrated Circuit) chip.

[0019] On the other hand, an electronic device is provided, the device comprising a main control chip shown in any possible implementation manner described above.

[0020] On the other hand, a computer-readable storage medium is provided, in which at least one computer program is stored. The at least one computer program is loaded and executed by a processor so that a computer implements any of the above-mentioned phase adjustment methods.

[0021] On the other hand, a computer program product or a computer program is also provided, the computer program product or the computer program comprising computer instructions, the computer instructions being stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs any of the above-mentioned phase adjustment methods.

[0022] The technical solution provided by this application brings at least the following beneficial effects:

[0023] In addition to the data sampling unit for sampling data, the data receiving circuit also includes a PLL unit, through which the phase of the clock signal can be adjusted, thereby adjusting the phase relationship between the clock signal and the data signal, and the adjustable phase relationship has a wider range and high versatility. The phase step in the PLL unit is dynamically calibrated according to the sampling situation of the first data signal received previously, so as to obtain a second phase step with higher sampling accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 It is a timing relationship diagram of a source synchronization design provided by an embodiment of the present application;

[0026] Figure 2 This is a schematic diagram of the connection between an external chip and a main control chip provided in an embodiment of the present application;

[0027] Figure 3 is a structural schematic diagram of a data receiving circuit provided in an embodiment of the present application;

[0028] Figure 4 is a structural diagram of another data receiving circuit provided in an embodiment of the present application;

[0029] Figure 5 is a structural schematic diagram of another data receiving circuit provided in an embodiment of the present application;

[0030] Figure 6 is a structural schematic diagram of a data receiving circuit provided in an embodiment of the present application;

[0031] Figure 7 is a flow chart for determining a second phase step provided in an embodiment of the present application;

[0032] Figure 8 It is a flow chart of a phase adjustment method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0034] In the field of electronic technology, more and more application scenarios involve the transmission of data signals between two chips, such as an external chip and a main control chip. Among them, the external chip refers to the data transmission source chip, and the main control chip refers to the receiving and processing chip for receiving data signals. In some cases, there is a problem of different path delays between the main control chip and the external chip, such as the PCB (Printed Circuit Board) delays of the main control chip and the external chip are inconsistent, or the working environment of the external chip and the main control chip causes the path delays of the main control chip and the external chip to differ greatly. Therefore, in addition to transmitting data signals between the external chip and the main control chip, clock synchronization is also performed to ensure the timing uniformity between the external chip and the main control chip, thereby ensuring reliable sampling of data signals.

[0035] In one possible case, the clock synchronization between the external chip and the main control chip can be achieved through asynchronous design, system synchronous design, self-synchronous design and source synchronous design. Among them, the asynchronous design is, for example, UART (Universal Asynchronous Receiver-Transmitter). In the asynchronous design, the clocks of the external chip sending the data signal and the main control chip receiving the data signal are not synchronized. Since there is no synchronous clock in the interface between the external chip and the main control chip, the external chip and the main control chip will agree on the baud rate. The external chip sends the data signal according to the baud rate, and the main control chip collects the data signal according to the baud rate, thereby ensuring that the timing of the external chip and the main control chip is consistent, and the main control chip can correctly collect the data signal.

[0036] System synchronization design means that the external chip and the main control chip configured on the same circuit board share the same clock, thereby ensuring that the timing of the external chip sending the data signal and the main control chip sampling the data signal is consistent.

[0037] Self-synchronous design is generally used in high-speed serdes (serializer / deserializer). After receiving the data signal, the main control chip can recover the clock signal from the data signal, thereby using the clock signal to achieve timing unification.

[0038] Source synchronous design means that the external chip sends the clock signal and data signal to the main control chip, and the main control chip can use the received clock signal to sample the data signal. Through the transmission of the clock signal, the phase relationship between the data signal and the clock signal sent by the external chip after reaching the main control chip can be controlled, thereby ensuring the sampling accuracy of the data signal. In source synchronous design, due to the presence of a clock, which refers to a clock signal sent together with the data signal, the main control chip that receives the data signal can perform data timing analysis based on the clock signal, and has a high degree of versatility.

[0039] Figure 1 An interactive schematic diagram of a source synchronization design provided in an embodiment of the present application, Figure 1 Both the external chip and the main control chip include logic (logic circuit) and FF (flip-flop). Figure 1 The d here refers to the input port of the trigger, q refers to the output port of the trigger, ck refers to the input clock port of the trigger, dp (data pin) refers to the pin of the chip data signal, cp (clock pin) refers to the pin of the chip clock signal, and S refers to the clock source point.

[0040] To make a distinction, Figure 1 The number 1 in the label is used to identify the external chip, and the number 2 is used to identify the main control chip. For example, d1 indicates that the input port is the input port of the trigger FF1 on the external chip, and d2 indicates that the input port is the input port of the trigger FF2 of the main control chip. Other labels have similar meanings and are not repeated here.

[0041] Figure 1 The T in the code indicates the delay. Figure 1 Take Tdp1_dp2 in the example to indicate the delay between the two ports dp1 and dp2. The description of other delays is similar and will not be repeated here. Figure 1 It can be seen that when the external chip sends the data signal to the main control chip through q1, it will also send the clock signal synchronously. In addition, since the delays Tdp1_dp2 and Tdp2_d2 in the PCB where the main control chip and the external chip are located are generally processed with equal length, after obtaining the phase relationship between the data signal output by dp1 of the external chip and the clock signal output by cp1, the main control chip can calculate the timing margin (setup & hold time) on the path of the input interface from dp2 to d2 based on the phase relationship, and set input_delay (input delay) based on the timing margin. The input delay indicates the phase relationship between the data signal received by dp2 and the clock signal received by cp2. The main control chip thus determines the layout and wiring of the input interface from dp2 to d2 and the input interface from cp2 to ck2 based on the phase relationship between the received data signal and the clock signal.

[0042] However, the method of adjusting the layout and routing is only applicable to the case where the transmitted data signal is a low-speed signal, such as the signal received by an SPI flash (Serial Peripheral Interface flash) operating at a frequency of 1MHz. Since the frequency is low and the timing is relatively generous, after determining the input_delay value based on the timing margin, the determined input_delay value has a path that meets the delay requirement. However, in the case where the data signal is a high-speed signal, since the high-speed design has high timing requirements when communicating through source synchronous communication, high-speed signals such as Figure 2 The signals transmitted in a Gigabit Ethernet application are shown.

[0043] Figure 2 RTL8211 in Figure 1 External chip, FPGA corresponding Figure 1 The main control chip has a receiver (Receiver) of RGMII (Reduced Gigabit Media Independent Interface Receiver), which is used to receive the signal sent from RTL8211. Figure 2 RXC in Figure 1 The clock signal, RXD and RXCTL correspond to Figure 1 See also Figure 2 , the clock signal is 125MHz, and the FPGA as the main control chip performs double-edge sampling on the data signal. It can be understood that the rate of the data signal in the DDR (dual data rate) mode is 250MHz. In this case, it is necessary to adjust the phase relationship between the data signal and the clock signal to achieve correct sampling of the data signal. Based on this, an embodiment of the present application provides a data receiving circuit for improving the sampling accuracy of the data signal when the data signal is a high-speed signal.

[0044] In a possible implementation, the data receiving circuit provided in the embodiment of the present application is configured in the main control chip, and the configuration position can be referred to in Figure 1 or Figure 2As shown, the main control chip can be an FPGA (Field Programmable Gate Array) chip or an ASIC (Application Specific Integrated Circuit) chip. In the embodiment of the present application, the main control chip can be any chip for receiving signals, and the external chip is a chip that communicates with the main control chip. The embodiment of the present application does not limit the types or names of the main control chip and the external chip.

[0045] Figure 3 A schematic diagram of a data receiving circuit provided in an embodiment of the present application is shown in FIG. Figure 3 The data receiving circuit includes a PLL unit 11 and a data sampling unit 12. The PLL unit 11 is connected to the data sampling unit 12.

[0046] Optionally, the PLL unit 11 is used to receive a first clock signal, and output a second clock signal based on the received first clock signal and a first phase step; the data sampling unit 12 is used to sample a reference signal based on the second clock signal to obtain a first data signal; the PLL unit 11 is also used to calibrate the first phase step based on the first data signal to obtain a second phase step, and the second phase step is used to adjust the phase of the clock signal received by the PLL unit 11, and the adjusted clock signal is used to sample the reference signal to obtain a second data signal.

[0047] In a possible implementation, the PLL unit 11 is a negative feedback control system that uses the voltage generated by phase synchronization to tune the voltage-controlled oscillator to generate a target frequency. The PLL unit 11 is a circuit for controlling frequency and phase, which detects and tracks the frequency and phase of the input signal and converts it into a stable output signal, thereby achieving frequency and phase synchronization and control.

[0048] Optionally, the PLL unit 11 includes a forward path and a feedback path. The forward path includes a PD (Phase Detector), a LF (Loop Filter) and a VCO (Voltage Controlled Oscillator), and the feedback path includes a frequency divider. The PLL unit 11 detects the phase difference between the input clock signal and the output clock signal, and converts the detected phase difference signal into a voltage signal output through a phase detector, and forms a control voltage of a voltage-controlled oscillator after filtering by a low-pass filter, controls the frequency of the oscillator output signal, and then feeds back the frequency and phase of the clock signal output by the oscillator to the phase detector through a feedback path, thereby ensuring that the phase difference between the input clock signal and the output clock signal is a fixed value, which is also the phase step in the embodiment of the present application.

[0049] Exemplarily, the phase step of the PLL unit 11 before adjustment, that is, the first phase step, can be an arbitrary value set based on experience and implementation environment. The first phase step can be set to 0. In this case, the second clock signal output by the PLL unit 11 is the same as the first clock signal. In this case, the PLL unit 11 does not phase-adjust the first clock signal, but directly outputs it. The first phase step can also be set to a non-zero value, which can be a positive number or a negative number. For example, the first phase step is set to the first adjustment step or the second adjustment step. In this case, the PLL unit 11 assumes that the first clock signal received by the PLL unit 11 needs to be phase-adjusted, and the phase of the first clock signal is adjusted based on the first phase step to obtain the second clock signal. The description of the first adjustment step and the second adjustment step is explained in the following embodiments and will not be repeated here.

[0050] Regardless of whether the PLL unit 11 adjusts the phase of the first clock signal, the output second clock signal can be sent to the data sampling unit 12, so that the data sampling unit 12 samples the received reference signal based on the second clock signal to obtain the first data signal.

[0051] Optionally, the reference signal received by the data sampling unit 12 may be a signal in a training phase, where the data receiving circuit is not formally used for transmission of service data, but is debugged and trained before transmission of service data. The signal in the training phase may be a user-defined signal, and the user may be a manufacturer that produces the data receiving circuit, or a customer that runs software to generate service data.

[0052] During the debugging and training phase, the data receiving circuit will adjust the phase step of the PLL unit 11, thereby improving the accuracy of the service data signal sampled subsequently to ensure the normal operation of the service. The reference signal can also be a signal in the use phase, which can be a signal of any type of service data, including but not limited to game data, video data, image data, and audio data. In this case, the data receiving circuit will continuously calibrate the phase step of the current PLL unit 11 configuration during the operation of the service to see whether it can correctly sample the service data signal, thereby dynamically adjusting the phase step.

[0053] Since the process of determining the second phase step based on the signal in the training phase is similar to the process of determining the second phase step based on the signal in the use phase, the following takes the reference signal as a fixed signal in the training phase as an example for illustration. For example, after receiving the second clock signal, the data sampling unit 12 starts to read the received reference signal when the edge of the second clock signal is reached to obtain the first data signal. The embodiment of the present application does not limit the edge of the clock signal referenced in the reference signal sampling process, which can be a rising edge or a falling edge.

[0054] After sampling and obtaining the first data signal, the data sampling unit 12 can output the first data signal so that the PLL unit 11 adjusts the first phase step based on the first data signal and the reference signal, and determines the phase calibration upper limit value and the phase calibration lower limit value of the PLL unit 11 based on the adjustment result; and determines the second phase step based on the phase calibration upper limit value and the phase calibration lower limit value.

[0055] The phase calibration upper limit value refers to the maximum value that can be adjusted by the PLL unit 11 in the process of adjusting the phase of the clock signal, and the phase calibration lower limit value refers to the minimum value that can be adjusted by the PLL unit 11 in the process of adjusting the phase of the clock signal. It can be understood that if the phase step referenced by the PLL unit 11 in the phase adjustment process is between the phase calibration upper limit value and the phase calibration lower limit value, the data signal obtained by sampling the clock signal output by the PLL unit 11 will not be wrong. Since the process of adjusting the phase calibration upper limit value and the phase calibration lower limit value is similar, the phase calibration upper limit value is taken as an example for explanation.

[0056] In one possible case, the PLL unit 11 adjusts the first phase step to obtain the phase calibration upper limit value, including two steps of coarse adjustment and fine adjustment. The coarse adjustment is used to determine the approximate position of the phase calibration upper limit value, and the fine adjustment is used to further determine the precise position of the phase calibration upper limit value near the approximate position. Optionally, the first adjustment step for fine adjustment is different from the second adjustment step for coarse adjustment, for example, the second adjustment step is larger than the first adjustment step. Among them, the first adjustment step and the second adjustment step can be set based on experience, and the first adjustment step can be set to 5 degrees and the second adjustment step to 45 degrees. Since the first data signal and the reference signal may be the same or different, the process of adjusting the phase calibration upper limit value for different situations is also different, and examples are given below to illustrate them respectively.

[0057] Adjustment process 1: when the first data signal and the reference signal are the same, the phase calibration upper limit value is obtained based on the addition of the first phase step and the first adjustment step.

[0058] In one possible case, the data receiving circuit can determine whether the first data signal and the reference signal are the same, so as to perform the adjustment process 1 through the PLL unit 11 based on the determination result. The data receiving circuit can perform the determination process through the PLL unit 11, or perform the determination operation through other units. Figure 4 The data receiving circuit further includes a judgment unit 13, which is respectively connected to the data sampling unit 12 and the PLL unit 11. Next, the judgment process of the judgment unit 13 executing the data signal is taken as an example to illustrate the process of the PLL unit 11 determining the phase calibration upper limit value based on the judgment result.

[0059] based on Figure 4 According to the connection relationship shown, after sampling the first data signal, the data sampling unit 12 can send the first data signal to the judgment unit 13, and the judgment unit 13 judges the first data signal. If the data sampling unit 12 and the judgment unit 13 are directly connected, the data sampling unit 12 can directly send the first data signal to the judgment unit 13. If the data sampling unit 12 and the judgment unit 13 are indirectly connected through other units, the data sampling unit 12 sends the first data signal to the judgment unit 13 through other units. That is, Figure 4 The purpose is to illustrate the connection relationship between the various units included in the data receiving circuit, rather than to limit whether the various units are directly connected or indirectly connected.

[0060] Figure 5 Another data receiving circuit provided in the embodiment of the present application is shown in FIG. Figure 5The data receiving circuit also includes AXI BUS (Advanced eXtensible Interface bus) 14. AXI BUS14 has independent read and write channels and flow control mechanisms. The read and write operations are processed separately through independent read and write channels, which can improve the efficiency and flexibility of communication. Based on the flow control mechanism, out-of-order processing and multi-command concurrency are allowed, thereby making full use of bandwidth resources. AXI BUS14 is widely used in high-speed data transmission scenarios.

[0061] Figure 5 In the embodiment, the AXI BUS 14 is connected to the data sampling unit 12 and the judging unit 13 respectively, the data sampling unit 12 can send the first data signal to the AXI BUS 14, and the AXI BUS 14 is used to send the first data signal to the judging unit 13, so that the judging unit 13 receives the first data signal.

[0062] Regardless of the method by which the judgment unit 13 obtains the first data signal sampled by the data sampling unit 12, it can be determined whether the first data signal and the reference signal are the same. Taking the reference signal sent by the external chip as 0000111 as an example, if the first data signal sampled by the data sampling unit 12 is also 0000111, the first data signal and the reference signal are the same, and it is determined that the first data signal is sampled correctly, or if the first data signal is 1001111, the first data signal and the reference signal are not the same, and it is determined that the first data signal is sampled incorrectly.

[0063] In one possible case, whether the first data signal is sampled correctly refers to whether the signal is read at the correct time. Since the data sampling unit 12 reads the reference signal based on the edge of the second clock signal, if the time of reading the reference signal is correct, it means that the phase of the edge of the second clock signal is accurate. On the contrary, if the time of reading the reference signal is wrong, it means that the phase of the edge of the second clock signal is wrong, that is, the phase relationship between the second clock signal and the first data signal is wrong. Since the phase of the second clock signal is obtained based on the adjustment of the first phase step, the PLL unit 12 can adjust the first phase step based on whether the first data signal is sampled correctly to obtain the second phase step, and the robustness of the second phase step is higher than that of the first phase step.

[0064] In a possible implementation, the judgment unit 13 is also used to send a first adjustment step to the PLL unit 11 when the first data signal and the reference signal are the same; after receiving the first adjustment step, the PLL unit 11 obtains the phase calibration upper limit value based on the addition of the first phase step and the first adjustment step.

[0065] In one possible case, if the judgment result of the first data signal is that the sampling is correct, it means that the phase of the second clock signal referenced by the sampling of the first data signal is accurate, that is, the first phase step used to adjust the second clock signal is already at the approximate position of the phase calibration upper limit value. Therefore, the PLL unit 11 does not need to perform coarse adjustment, but can directly find the boundary of the phase calibration, that is, the phase calibration upper limit value, through fine adjustment near the first phase step.

[0066] Similar to the interaction process between the data sampling unit 12 and the judgment unit 13, the interaction between the judgment unit 13 and the PLL unit 11 may also be direct interaction, for example, a direct communication connection is established between the judgment unit 13 and the PLL unit 11, and the judgment unit 13 directly sends the first adjustment step to the PLL unit 11. The interaction between the judgment unit 13 and the PLL unit 11 may also be indirect interaction, for example, an indirect communication connection is established between the judgment unit 13 and the PLL unit 11, and the indirect communication connection may be Figure 5 In a similar bus structure, in this case, the determination unit 13 may send the first adjustment step length to the connected bus, and the bus may send the first adjustment step length to the PLL unit 11 .

[0067] Figure 6 A schematic diagram of another data receiving circuit provided in an embodiment of the present application is shown in FIG. Figure 6 , the unit composed of PLL and Phase Sample corresponds to Figure 4 or Figure 5 The PLL unit 11 shown, Figure 6 PLL in Figure 4 or Figure 5 The forward path in the PLL unit 11 shown in FIG. 1 corresponds to Phase Sample. Figure 4 or Figure 5 In the feedback path of the PLL unit 11 shown in FIG. 1 , RISC-V (Reduced Instruction Set Computing Five) represents a processor corresponding to Figure 4 or Figure 5 The judgment unit 13 shown in the figure, GMII Receiver (Gigabit Media Independent Interface Receiver, Gigabit Media Independent Interface Receiver) corresponds to Figure 4 or Figure 5 In the data sampling unit 12 shown, RXC indicates a clock signal, and RXD or RXCTL represents a data signal.

[0068] See also Figure 6, the RISC-V as the judgment unit 13 is connected to the APB BUS (Advanced Periphera), and the PLL unit 11 is also connected to the APB BUS. Therefore, the judgment unit 13 can send the first adjustment step length to the APB BUS, and the APBBUS sends the first adjustment step length to the PLL unit 11, thereby realizing indirect communication between the judgment unit 13 and the PLL unit 11.

[0069] Optionally, after receiving the first adjustment step, the PLL unit 11 may start fine-tuning, and the fine-tuning process includes but is not limited to: the PLL unit 11 adds the first phase step and the first adjustment step to obtain a third phase step; adjusts the phase of the received third clock signal based on the third phase step to obtain a fourth clock signal, and outputs the fourth clock signal; the data sampling unit 12 is also used to sample the reference signal based on the fourth clock signal to obtain a third data signal; the PLL unit 11 is also used to determine the third phase step as the phase calibration upper limit value when the third data signal and the reference signal are different, or, when the third data signal and the reference signal are the same, cyclically execute the operation of adding the first adjustment step and the third phase step until the data signal sampled based on the phase step obtained by addition is different from the reference signal, and the phase step obtained by addition is determined as the phase calibration upper limit value.

[0070] Taking the first adjustment step of 5 degrees and the first phase step of 0 degrees in the above embodiment as an example, the PLL unit 11 adds the first phase step of 0 and the first adjustment step of 5 to obtain the third phase step of 5. After adjusting the first phase step, the PLL unit 11 will also check whether the data signal sampled by the third phase step is accurate to determine whether to continue fine-tuning. The data signal sampled by the third phase step refers to the phase of the referenced clock signal obtained by sampling the data signal based on the third phase step adjustment.

[0071] With the third phase step size of 5, Figure 6Taking the data receiving circuit shown as an example, the process of checking the third phase step is described. The PLL receives the third clock signal RXC, adds 5 degrees to the phase of the third clock signal RXC, obtains the fourth clock signal RXC2, and sends the fourth clock signal RXC2 to the GMII receiver as the data sampling unit 12. The GMII receiver samples the reference signal RXD according to the fourth clock signal RXC2 to obtain the third data signal, sends the third data signal to AXI BUS14, and AXI BUS14 sends the third data signal to RISC-V as the judgment unit 13. RISC-V judges whether the third data signal and the reference signal are the same through the Data statistics unit. Among them, the process of sampling the third data signal and judging the third data signal is similar to the process of sampling the first data signal and judging the first data signal. Please refer to the relevant description in the above embodiment, which will not be described here.

[0072] If the third data signal is the same as the reference signal, it means that the third phase step corresponding to the third data signal has not reached the phase calibration upper limit, and the fine adjustment is used to determine the phase calibration upper limit. Therefore, the third phase step does not meet the fine adjustment end condition, and the judgment unit 13 determines that the PLL unit 11 needs to continue fine adjustment based on this. Figure 6 For example, the data statistics unit of RISC-V as the judgment unit 13 sends the judgment result to the Phase Adjust unit, and the Phase Adjust unit sends the first adjustment step 5 to the APB BUS based on the judgment result being the same as the reference signal, and the APB BUS sends the first adjustment step 5 to the PLL unit 11. For example, the register in the PLL is configured through the APB BUS to adjust the phase step stored in the register based on the first adjustment step.

[0073] Afterwards, the PLL unit 11, the data sampling unit 12 and the judgment unit 13 in the data receiving circuit cyclically execute the process of adjusting the phase step in the above embodiment, adjusting the phase of the clock signal based on the phase step, sampling the data signal based on the clock signal, and determining the judgment result of the sampled data signal until the judgment result of the data signal is different from the reference signal.

[0074] If the data signal and the reference signal are different, it means that the period of the clock signal referenced by the data signal is wrong, that is, the phase step when the clock signal is phase adjusted exceeds the upper limit of normal sampling. In this case, the upper limit of normal sampling is between the phase step at the current moment and the phase step at the previous moment. The PLL unit 11 has located the upper limit of normal sampling, that is, within 5 degrees of the phase step at the current moment, and there is no need to continue to fine-tune upward. Based on this, the phase step at the current moment meets the fine-tuning end condition.

[0075] In one possible case, the third data signal obtained by sampling the third phase step may also be different from the reference signal. Based on the same principle shown in the above embodiment, it is determined that the third phase step meets the fine-tuning end condition, and the judgment unit 13 no longer needs to send the first adjustment step to the PLL unit 11, so the PLL unit 11 ends the fine-tuning of the phase step.

[0076] In one possible implementation, after determining that the phase step at the current moment meets the fine-tuning end condition, the judgment unit 13 may send a fine-tuning end signal to the PLL unit 11 to prompt the PLL unit 11 that no further fine-tuning is required and the phase step at the current moment may be determined as the phase calibration upper limit value.

[0077] Since the process of adjusting the phase step by the PLL unit 11 depends on the judgment unit 13 sending the first adjustment step, the judgment unit 13 can limit the sending of the first adjustment step to the PLL unit 11 when the phase step at the current moment meets the fine-tuning end condition. Since the PLL unit 13 will not receive the first adjustment step, it will not adjust the current phase step based on the first adjustment step.

[0078] Optionally, the PLL unit 11 may determine that the phase step at the current moment meets the fine-tuning end condition based on not receiving the first adjustment step within the reference time, and use the phase step at the current moment as the upper limit of the phase calibration. The reference time may be any duration set based on experience or implementation environment.

[0079] Although the phase calibration upper limit value determined by the above-mentioned PLL unit 11 is greater than the upper limit boundary of normal sampling, in the process of determining the second phase step, the phase calibration upper limit value and the phase calibration lower limit value are jointly determined, and the process of determining the phase calibration lower limit value is similar to the process of determining the phase calibration upper limit value, and a phase step value less than the lower limit boundary of normal sampling is determined by continuously fine-tuning the first adjustment step. Therefore, the part of the phase calibration upper limit value that is greater than the upper limit boundary can be complementarily offset with the part of the phase calibration lower limit value that is less than the lower limit boundary. The offset process will be illustrated in the process of determining the second phase step below.

[0080] Adjustment process two: when the first data signal and the reference signal are different, a fourth phase step is obtained by adding the second adjustment step and the first phase step; a phase calibration upper limit value is obtained by adding the fourth phase step and the first adjustment step, and the first adjustment step is smaller than the second adjustment step.

[0081] Similar to the adjustment process 1, whether the PLL unit 11 uses the second adjustment step for coarse adjustment can also be controlled by the judgment unit 13. For example, the judgment unit 13 is used to send the second adjustment step for coarse adjustment to the PLL unit 11 when the first data signal and the reference signal are different. After receiving the second adjustment step, the PLL unit 11 adds the second adjustment step and the first phase step, and determines whether the phase step obtained by adding meets the coarse adjustment end condition.

[0082] The process of judging whether the phase step meets the coarse adjustment end condition is similar to the process of judging whether the phase step meets the fine adjustment end condition in the adjustment process one, in which the PLL unit 11 uses the phase step to adjust the phase of the received clock signal, the data sampling unit 12 uses the adjusted clock signal to sample the data signal, and the judgment unit 13 judges whether the data signal is sampled correctly. The difference is that the phase step meets the coarse adjustment end condition means that the data signal and the reference signal obtained by sampling the phase step are the same, while the phase step meets the fine adjustment end condition means that the data signal and the reference signal obtained by sampling the phase step are different. For the setting principle of the coarse adjustment end condition, please refer to the introduction of the principle that the fine adjustment can be started directly when the first data signal is sampled correctly in the adjustment process one, which will not be repeated here.

[0083] Similar to the fine-tuning process in the first adjustment process, the coarse adjustment in the second adjustment process also includes a cyclic process, that is, if the judgment unit 13 detects that the data signal and the reference signal are different, it will continue to send the second adjustment step to the PLL unit 11, and the PLL unit 11, the data sampling unit 12 and the judgment unit 13 will cyclically execute the above coarse adjustment process until the fourth phase step that satisfies the end of the coarse adjustment is obtained. That is, the fourth phase step obtained by adding the first phase step and the second adjustment step in the embodiment of the present application can be obtained by adding once or multiple times.

[0084] Regardless of how many times the fourth phase step is obtained through coarse adjustment, the PLL unit 11 can fine-tune the fourth phase step after obtaining the fourth phase step that meets the coarse adjustment end condition to obtain the phase calibration upper limit value. Similar to the coarse adjustment process, the PLL unit 11 switches from coarse adjustment to fine adjustment, which can also be controlled by the judgment unit 13, that is, if the judgment unit 13 sends the first adjustment step to the PLL unit 11 after detecting that the fourth phase step meets the coarse adjustment end condition, the PLL unit 11 fine-tunes the fourth phase step based on the received first adjustment step. The process of fine-tuning the fourth phase step and the process of fine-tuning the first phase step can refer to the relevant description of the adjustment process 1, which will not be repeated here.

[0085] In addition, the above example is intended to illustrate the process of determining the upper limit value of the phase calibration by adjusting the first phase step, rather than to limit the interaction process between the PLL unit 11 and the judgment unit 13. The process of adjusting the phase step based on the judgment result involved in the above embodiment can be executed interactively by the judgment unit 13 and the PLL unit 11, or by the PLL unit 11.

[0086] The process performed by the PLL unit 11 is, for example, that after determining the judgment result of the first data signal, the judgment unit 13 may send the judgment result to the PLL unit 11, and the PLL unit 11 adjusts the first phase step length using the second adjustment step length based on the judgment result that the first data signal and the reference signal are different, and the PLL unit 11 determines that there is no need for coarse adjustment based on the judgment result that the first data signal and the reference signal are the same, and directly adjusts the first phase step length using the first adjustment step length. Alternatively, the PLL unit 11 receives the first data signal output by the data sampling unit 12, determines whether the first data signal and the reference signal are the same, and adjusts the first phase step length based on the judgment result.

[0087] In a possible implementation, the process of determining the phase calibration lower limit value based on the first phase step adjustment is similar to the process of determining the phase calibration upper limit value based on the first phase step adjustment. Since both the phase calibration upper limit value and the phase calibration lower limit value are further determined based on the approximate position obtained by coarse adjustment, the coarse adjustment result obtained in the process of determining the phase calibration upper limit value can be reused in the process of determining the phase calibration lower limit value. The coarse adjustment result refers to the phase step that meets the coarse adjustment end condition. If it is the situation shown in the adjustment process one, the coarse adjustment result is the first phase step. If it is the situation shown in the adjustment process two, the coarse adjustment result is the fourth phase step.

[0088] In addition, the embodiment of the present application does not limit the third adjustment step used for fine-tuning the coarse adjustment result in the process of determining the phase calibration lower limit value. It can be any positive integer set based on experience. The third adjustment step can be the same as the first adjustment step or different.

[0089] Regardless of the method by which the PLL unit 11 determines the phase calibration upper limit value and the phase calibration lower limit value, the second phase step can be determined using the phase calibration upper limit value and the phase calibration lower limit value. The second phase step refers to the phase step of the best acquisition. Since the phase calibration upper limit value and the phase calibration lower limit value reflect the correct upper and lower boundaries of the sampling, and the phase step between the upper and lower boundaries has the best robustness, the PLL unit 11 can determine the average value of the phase calibration upper limit value and the phase calibration lower limit value, and use the average value as the second phase step.

[0090] Figure 7 A flow chart for determining a second phase step length is provided in an embodiment of the present application. Figure 7As an example, the overall process of determining the second phase step of the data receiving circuit is described. In a possible implementation, the PLL unit 11 defaults to the first phase step of 0. Therefore, the PLL unit 11 directly outputs the first clock signal as the second clock signal. The data sampling unit 12 obtains the first data signal based on the second clock signal sampling, and determines whether the first data signal is correct. If it is not correct, it is determined that the first phase step does not meet the coarse adjustment end condition, and the first phase step and the second adjustment step are added by 45 degrees, that is, Figure 7 The phase is coarsely adjusted by +45 degrees to obtain a new phase step, and then the process of phase adjustment, sampling and judging whether it is correct based on the new phase step is repeated. If it is not correct, the phase is coarsely adjusted by +45 degrees until the judgment result indicates that it is correct, and it is determined that the current phase step meets the coarse adjustment end condition, and the coarse adjustment result is obtained. Figure 7 The coarse adjustment result is referred to as the current phase calibration reference value P base .

[0091] After that, the PLL unit 11 performs a base Fine-tune to P base Taking 135 degrees as an example, the PLL unit 11 adds a first adjustment step of 5 degrees on the basis of 135 degrees, that is, Figure 7 The current phase shown is fine-tuned by +5 degrees, and the phase of the received clock signal is adjusted by 140 degrees to obtain a new clock signal. The judgment unit 13 judges whether the data signal obtained by the data sampling unit 12 based on the clock signal corresponding to 140 degrees is correct. If it is correct, continue to fine-tune and execute the loop. Figure 7 In the current phase fine adjustment + 5 degrees operation, if the data is incorrect, for example, the data sampling unit 12 outputs an error when the phase step of the PLL unit 11 is 160 degrees, the current phase step is used as the phase calibration upper limit value, for example, the phase calibration upper limit value P H It is 160 degrees.

[0092] Similarly, the PLL unit 11 can also be based on the reference phase P base Continuously subtract the third adjustment step of 5 degrees to determine the phase calibration lower limit value P L The determination process is also to perform the -5 degree operation in a loop, for example, first in P base 135 degrees minus 5 degrees, the judgment unit 13 determines whether the data signal sampled by the data sampling unit 12 based on the clock signal corresponding to 130 degrees is correct. If it is correct, 5 degrees is subtracted again, and the number is continuously reduced until the judgment unit 13 detects a sampling error of the data signal. For example, when the phase step of the PLL unit 11 is 120 degrees, the data sampling unit 12 outputs an error, indicating that the lower limit of the phase calibration is 120 degrees. Based on this, the PLL unit 11 determines the second phase step, i.e. Figure 7The optimal phase is (160+120) / 2=140 degrees.

[0093] See also Figure 7 As shown in the flowchart, since the first adjustment step and the third adjustment step are the same, both are 5 degrees, and P H and P L When the error occurs for the first time, it can be understood that the upper boundary of the correct sampling should be at P H The correct lower boundary of sampling should be between P and the previous phase step, that is, between 160 and 155. L and the previous phase step, that is, between 120 and 125, if the middle value 157.5 of 160 to 155 is taken as the upper boundary, and the middle value 122.5 of 120 to 125 is taken as the lower boundary, even if the boundary value obtained thereby may be closer to the real boundary, the average value of 122.5 and 157.5 is the same as the average value of 120 and 160, both of which are 140. That is, the difference between the lower boundary of the phase calibration and the actual boundary is complementary to the difference between the upper boundary of the phase calibration and the actual boundary, and even if the PLL unit 11 uses the first erroneous phase step as the phase calibration upper limit value and the phase calibration lower limit value, it will not affect the accuracy of the second phase step, and thus determining the second phase step can still ensure the robustness of the data receiving circuit.

[0094] Optionally, after determining the second phase step, the PLL unit 11 may use the second phase step to adjust the received clock signal so that the data sampling unit 12 samples the reference signal based on the adjusted clock signal. In some cases, for each received clock signal, the PLL unit 11 adds the second phase step to the original phase of the clock signal to obtain a new clock signal. In the process of the data sampling unit 12 sampling the reference signal based on the new clock signal to obtain the second data signal, the timing margin is large, and the accuracy of the second data signal obtained by sampling is higher than the accuracy of the first data signal.

[0095] Since the physical structure of the main control chip and the external chip is fixed, for example, the layout and wiring between the main control chip and the external chip is Figure 1 As shown, therefore, for any data signal sent from the external chip to the main control chip, the path passed is fixed, and the reference signal and clock signal used in determining the second phase step are also obtained by transmission from the fixed path. Therefore, the second phase step adjusted based on the sampling result of the reference signal can be applicable to the system of the main control chip and the external chip. Regardless of the subsequent data signal transmitted between the main control chip and the external chip, whether it is the same as the reference signal, the data receiving circuit can sample the received data signal based on the second phase step, thereby realizing reliable transmission and sampling of the data signal.

[0096] In addition, the above examples are intended to illustrate the interaction process of each unit in the data receiving circuit, rather than to limit the various units included in the data receiving circuit. For example, the judgment unit 13 in the data receiving circuit can be configured in a processor, which can be Figure 6 The RISC-V CPU (Central Processing Unit) shown in FIG. 1 may also be other types of CPUs. The configuration positions of each unit may be as follows: Figure 3-Figure 5 As shown, different situations are also possible.

[0097] In summary, the data receiving circuit provided in the embodiment of the present application, in addition to including a data sampling unit 12 for sampling data, also adds a PLL unit 11. The phase of the clock signal is adjusted by the PLL unit 11, so as to adjust the phase relationship between the clock signal and the data signal. The adjustable range is wider and the versatility is high. In addition, the PLL unit 11 relies on the second phase step, which is dynamically adjusted according to the sampling situation of the first data signal received before, and is more suitable for data sampling of the data receiving circuit, and the sampling accuracy is higher. The approximate position of the optimal phase is quickly determined by coarse adjustment, and then the accurate phase calibration upper limit and phase calibration lower limit are obtained by fine adjustment. The second phase step determined based on the upper limit and the lower limit has higher robustness, and the data receiving circuit running based on the second phase step with higher robustness has higher stability.

[0098] The present application embodiment provides a phase adjustment method, which can be Figure 3-Figure 6 Any of the data receiving circuits shown in the figure is executed, and the flowchart of the method is as follows Figure 8 As shown, it includes steps 801 to 803.

[0099] In step 801, a second clock signal is output based on a received first clock signal and a first phase step.

[0100] Optionally, the data receiving circuit includes a PLL unit, the PLL unit is used to receive the first clock signal, and output the second clock signal according to the first clock signal and the first phase step. The detailed process of the PLL unit outputting the second clock signal is the same as the above Figure 3 In the embodiment shown, the process of the PLL unit 11 outputting the second clock signal is similar. For example, if the first phase step includes 0, the second clock signal is the same as the first clock signal. Therefore, see the above Figure 3 The relevant description of the embodiments will not be repeated here.

[0101] In step 802, a reference signal is sampled based on a second clock signal to obtain a first data signal.

[0102] In a possible implementation, the data receiving circuit further includes a data sampling unit, which receives the second clock signal output by the PLL unit, samples the reference signal according to the second clock signal, and obtains the first data signal. Optionally, the process of the data sampling unit receiving the second clock signal, sampling the first data signal, and sending the first data signal is similar to the above process. Figure 3 or Figure 4 In the illustrated embodiment, the process of the data sampling unit 12 receiving the second clock signal, sampling the first data signal and sending the first data signal is similar, and reference may be made to the relevant description, which will not be repeated here.

[0103] In step 803, the first phase step is calibrated based on the first data signal to obtain a second phase step, the second phase step is used to adjust the phase of the received clock signal, and the adjusted clock signal is used to sample the reference signal to obtain the second data signal.

[0104] In one possible implementation, the process of the PLL unit calibrating the first phase step based on the first data signal includes: adjusting the first phase step based on the first data signal and the reference signal, determining the phase calibration upper limit value and the phase calibration lower limit value based on the adjustment result; and determining the second phase step based on the phase calibration upper limit value and the phase calibration lower limit value.

[0105] Exemplarily, in the process of determining the phase calibration upper limit value, if the first data signal and the reference signal are the same, that is, the first data signal is sampled correctly, the PLL unit can obtain the phase calibration upper limit value based on the addition of the first phase step and the first adjustment step. The fine-tuning process includes but is not limited to: adding the first phase step and the first adjustment step to obtain a third phase step; adjusting the phase of the received third clock signal based on the third phase step to obtain a fourth clock signal, sampling the reference signal based on the fourth clock signal to obtain a third data signal; when the third data signal and the reference signal are different, determining the third phase step as the phase calibration upper limit value, or, when the third data signal and the reference signal are the same, cyclically performing the operation of adding the first adjustment step and the third phase step until the data signal sampled based on the phase step obtained by addition is different from the reference signal, and determining the phase step obtained by addition as the phase calibration upper limit value. For a detailed description of fine-tuning the first phase step, please refer to the above. Figure 3 The description of the adjustment process 1 in the illustrated embodiment will not be repeated here.

[0106] Optionally, if the first data signal is different from the reference signal, that is, the first data signal is sampled incorrectly, the data receiving circuit can obtain a fourth phase step based on the addition of the first phase step and the second adjustment step; and obtain a phase calibration upper limit value based on the addition of the fourth phase step and the first adjustment step, where the first adjustment step is smaller than the second adjustment step. The process of obtaining the phase calibration upper limit value through coarse adjustment and fine adjustment and Figure 3 In the illustrated embodiment, the processes of coarse adjustment and fine adjustment to obtain the phase calibration upper limit value are similar, and reference may be made to the related description of the adjustment process 2, which will not be repeated here.

[0107] Regardless of the method by which the data receiving circuit obtains the phase calibration upper limit value and the phase calibration lower limit value, the phase calibration upper limit value and the phase calibration lower limit value can be added and divided by two to obtain a second phase step. The second phase step can be used to sample the reference signal to obtain a second data signal, and the accuracy of the second data signal is higher than the accuracy of the first data signal, for example, the error between the second data signal and the reference signal is smaller than the error between the first data signal and the reference signal.

[0108] In summary, the phase adjustment method provided in the embodiment of the present application adjusts the phase of the clock signal through the PLL unit, thereby adjusting the phase relationship between the clock signal and the data signal, and has a wider adjustable range and high versatility. In addition, the PLL unit relies on the second phase step, which is dynamically adjusted according to the sampling situation of the first data signal received previously, and is more suitable for data sampling of the data receiving circuit, and has a higher sampling accuracy. The approximate position of the optimal phase is quickly determined by coarse adjustment, and then the accurate phase calibration upper limit and phase calibration lower limit are obtained by fine adjustment. The second phase step determined based on the upper limit and the lower limit has higher robustness, and the data receiving circuit running based on the more robust second phase step has higher stability.

[0109] The present application also provides a main control chip, which includes Figure 3-Figure 6 Any of the data receiving circuits shown, the data receiving circuit can be used to perform Figure 8 The phase adjustment method shown. Optionally, the main control chip can be an FPGA chip or an ASIC chip.

[0110] An embodiment of the present application also provides an electronic device, which includes a main control chip.

[0111] Exemplarily, the electronic device may be any device with a display function, and may be any terminal. Optionally, the terminal may be any electronic product that can interact with a user through one or more methods such as a keyboard, a touch pad, a touch screen, a remote control, voice interaction, or a handwriting device, such as a PC (Personal Computer), a mobile phone, a smart phone, a PDA (Personal Digital Assistant), a wearable device, a PPC (Pocket PC), a tablet computer, a smart car machine, a smart TV, etc.

[0112] On the other hand, the present application also provides a computer-readable storage medium, in which at least one computer program is stored, and at least one computer program is loaded and executed by a processor to enable the computer to implement the above Figure 8 Phase adjustment method shown.

[0113] On the other hand, the present application also provides a computer program product or a computer program, the computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the above Figure 8 Phase adjustment method shown.

[0114] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions. For example, the first clock signal involved in this application is obtained with full authorization.

[0115] It should be understood that the "plurality" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0116] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A data receiving circuit, characterized in that: The circuit comprises a phase-locked loop (PLL) unit and a data sampling unit; The PLL unit is used to output a second clock signal based on the received first clock signal and the first phase step; The data sampling unit is used to sample the reference signal based on the second clock signal to obtain a first data signal; The PLL unit is also used to calibrate the first phase step based on the first data signal to obtain a second phase step, and the second phase step is used to adjust the phase of the clock signal received by the PLL unit. The adjusted clock signal is used to sample the reference signal to obtain a second data signal.

2. The data receiving circuit according to claim 1, characterized in that: The PLL unit is configured to adjust the first phase step size based on the first data signal and the reference signal, and determine a phase calibration upper limit value and a phase calibration lower limit value of the PLL unit based on an adjustment result; The second phase step size is determined based on the phase calibration upper limit value and the phase calibration lower limit value.

3. The data receiving circuit according to claim 2, characterized in that: The PLL unit is used to obtain the phase calibration upper limit value based on the addition of the first phase step and the first adjustment step when the first data signal and the reference signal are the same.

4. The data receiving circuit according to claim 3, characterized in that: The PLL unit is configured to add the first phase step and the first adjustment step to obtain a third phase step; adjust the phase of the received third clock signal based on the third phase step to obtain a fourth clock signal, and output the fourth clock signal; The data sampling unit is further configured to sample the reference signal based on the fourth clock signal to obtain a third data signal; The PLL unit is further used to, when the third data signal and the reference signal are different, determine the third phase step as the phase calibration upper limit value, or, when the third data signal and the reference signal are the same, cyclically perform the operation of adding the first adjustment step and the third phase step until the data signal sampled based on the added phase step is different from the reference signal, and the phase step obtained by the addition is determined as the phase calibration upper limit value.

5. The data receiving circuit according to claim 2, characterized in that: The PLL unit is configured to obtain a fourth phase step size based on the addition of a second adjustment step size and the first phase step size when the first data signal and the reference signal are different; The phase calibration upper limit value is obtained based on the addition of the fourth phase step and the first adjustment step, and the first adjustment step is smaller than the second adjustment step.

6. A phase adjustment method, characterized in that: The method comprises: outputting a second clock signal based on the received first clock signal and the first phase step; Sampling a reference signal based on the second clock signal to obtain a first data signal; The first phase step is calibrated based on the first data signal to obtain a second phase step, the second phase step is used to adjust the phase of the received clock signal, and the adjusted clock signal is used to sample the reference signal to obtain a second data signal.

7. The method according to claim 6, characterized in that The step of calibrating the first phase step based on the first data signal to obtain a second phase step includes: Adjust the first phase step size based on the first data signal and the reference signal, and determine a phase calibration upper limit value and a phase calibration lower limit value based on an adjustment result; The second phase step size is determined based on the phase calibration upper limit value and the phase calibration lower limit value.

8. The method according to claim 7, characterized in that The adjusting the first phase step size based on the first data signal and the reference signal, and determining a phase calibration upper limit value based on an adjustment result, comprises: In a case where the first data signal is identical to the reference signal, the phase calibration upper limit value is obtained based on the addition of the first phase step and the first adjustment step.

9. The method according to claim 8, characterized in that The step of obtaining the phase calibration upper limit value based on the addition of the first phase step size and the first adjustment step size includes: Adding the first phase step and the first adjustment step to obtain a third phase step; adjusting the phase of the received third clock signal based on the third phase step to obtain a fourth clock signal, and sampling the reference signal based on the fourth clock signal to obtain a third data signal; When the third data signal and the reference signal are different, the third phase step is determined as the phase calibration upper limit value; or, when the third data signal and the reference signal are the same, the operation of adding the first adjustment step and the third phase step is cyclically performed until the data signal sampled based on the added phase step is different from the reference signal, and the phase step obtained by the addition is determined as the phase calibration upper limit value.

10. The method according to claim 7, characterized in that The adjusting the first phase step size based on the first data signal and the reference signal, and determining a phase calibration upper limit value based on an adjustment result, comprises: When the first data signal and the reference signal are different, obtaining a fourth phase step by adding the first phase step and the second adjustment step; The phase calibration upper limit value is obtained based on the addition of the fourth phase step and the first adjustment step, and the first adjustment step is smaller than the second adjustment step.

11. A main control chip, characterized in that: The main control chip includes the data receiving circuit as described in any one of claims 1-5.

12. The chip according to claim 11, characterized in that: The main control core includes a field programmable gate array FPGA chip or an application specific integrated circuit ASIC chip.

13. An electronic device, characterized in that: The device comprises the main control chip as described in any one of claims 11 or 12.

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