Sequence pattern generating device and setting method thereof

Abstract

To provide a sequence pattern generating device which enables a user to arbitrarily set output to be restarted synchronously with the restart of a sequence.SOLUTION: A sequence pattern generating device includes a synchronous setting screen 301 having a primary module selection button 311 and a secondary module selection button 312 for selecting a module to be synchronized, and synchronous selection buttons 313, 314, 315, and 316 provided for each output of the selected module and for selecting whether or not to synchronize when restarting a sequence.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a sequence pattern generator that generates and outputs an arbitrary sequence pattern set by a user.

Background Art

[0002] In recent years, various digital communication devices have been required to have a larger transmission capacity with the increase in the number of users and the spread of multimedia communication. As an index for evaluating the quality of digital signals in these digital communication devices, the bit error rate, which is defined as the comparison between the number of symbol errors occurring in the received data and the total number of received data, is known.

[0003] In the error rate measuring device for measuring the above-described bit error rate, a test signal including fixed data is transmitted to a device under test that is a test target, and the measured signal input through the device under test and a reference signal serving as a reference are compared bit by bit to measure the error rate of the measured signal.

[0004] In this type of error rate measuring device, a pulse pattern generator that generates a data signal of a predetermined pulse pattern input as a test signal to a device under test corresponding to recent high-speed data communication is used.

[0005] Patent Document 1 describes a pulse pattern generator that sets a slave-side phase difference target value using correction data in a storage unit while setting a master-side phase difference target value according to the frequency of a reference clock signal in order to keep the phase states of a plurality of data signals constant.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] In the standards of high-speed serial buses such as USB (Universal Serial Bus) and PCIe (Peripheral Component Interconnect Express), there is a state machine called Link Training & Status State Machine (LTSSM), which manages the initialization of communication between devices and the adjustment of link speed.

[0008] In addition, a conventional error rate measurement device has a function (sequence pattern function) of controlling the LTSSM of PCIe GEN1 to 5 and USB3.1 by quickly switching a specific pattern defined by the standard from a pulse pattern generator (PPG: Pulse Pattern Generator) and transitioning to a specific state. The patterns for transitioning the device under test (DUT) are defined by the standard, and the output order of these patterns can be combined and output by the sequence pattern function.

[0009] In the PCIe standard, the number of lanes is defined in variations such as x1, x2, x4, x8, x16, etc. A pattern defined for each lane is transmitted to transition the DUT to a state transition.

[0010] In the normal usage range, a PCIe device only needs to have data synchronized among multiple lanes. However, as a requirement on the developer side of PCIe devices, there is a need to temporarily stop the sequences of multiple or all lanes and resume the sequences of multiple or all lanes arbitrarily specified at any timing. However, such a setting was impossible with the conventional sequence pattern function.

[0011] Therefore, an object of the present invention is to provide a sequence pattern generator that allows a user to arbitrarily set an output to be restarted synchronously when the sequence is restarted.

Means for Solving the Problems

[0012] The sequence pattern generator of the present invention is a sequence pattern generator in which at least one module having an output of at least one data signal can be mounted, and the total number of outputs of the data signals is two or more, and in the setting of one of the output data signals, it includes a device control unit for setting an output to be restarted synchronously when the sequence is restarted.

[0013] With this configuration, in the setting of one of the output data signals, it is possible to set an output to be restarted synchronously when the sequence is restarted. Therefore, the user can arbitrarily set an output to be restarted synchronously when the sequence is restarted.

[0014] Further, in the sequence pattern generator of the present invention, the device control unit selects the module and allows selection of whether to restart the output of the selected module synchronously when the sequence is restarted.

[0015] With this configuration, the module is selected, and it is possible to select whether to restart the output of the selected module synchronously when the sequence is restarted. Therefore, since only the selected module is displayed, confusion of the user can be prevented.

[0016] Further, in the sequence pattern generator of the present invention, when only one module having two outputs is mounted, the device control unit allows selection of only whether to restart synchronously when the sequence is restarted.

[0017] With this configuration, when only one module having two outputs is mounted, only whether to resume synchronously at the time of sequence resumption can be selected. Therefore, when there are few outputs that can be synchronized, the user can make the target setting with a smaller number of operations.

[0018] The setting method of the sequence pattern generator of the present invention is a setting method of a sequence pattern generator capable of mounting at least one module having an output of at least one data signal, and the total number of outputs of the data signal is two or more, and in the setting of one of the data signals to be output, it includes a device control step of causing the output to resume synchronously at the time of sequence resumption.

[0019] With this configuration, in the setting of one of the data signals to be output, the output can be set to resume synchronously at the time of sequence resumption. Therefore, the user can arbitrarily set the output to resume synchronously at the time of sequence resumption.

[0020] In the setting method of the sequence pattern generator of the present invention, the device control step includes a selection step of selecting the module and selecting whether to resume synchronously at the time of sequence resumption for the output of the selected module.

[0021] With this configuration, the module is selected, and it is possible to select whether to resume synchronously at the time of sequence resumption for the output of the selected module. Therefore, since only the selected module is displayed, confusion of the user can be prevented.

[0022] In the setting method of the sequence pattern generator of the present invention, when only one module having two outputs is mounted, the device control step allows only selection of whether to resume synchronously at the time of sequence resumption.

[0023] With this configuration, when only one of the modules having two outputs is mounted, only whether to resume synchronously at the time of sequence resumption can be selected. Therefore, when there are few outputs that can be synchronized, the user can make the target setting with fewer operation times.

Advantages of the Invention

[0024] The present invention can provide a sequence pattern generator in which a user can arbitrarily set an output to resume synchronously at the time of sequence resumption.

Brief Description of the Drawings

[0025]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Embodiments for Carrying Out the Invention

[0026] Hereinafter, with reference to the drawings, a sequence pattern generator according to an embodiment of the present invention will be described in detail.

[0027] In FIG. 1, a sequence pattern generator 1 according to an embodiment of the present invention includes a primary module 2 and a secondary module 3, each of which can output two data signals. The primary module 2 and the secondary module 3 are connected by wiring via a bridge route 4. Note that the primary module 2 and the secondary module 3 may output one data signal or two or more data signals.

[0028] The primary module 2 and the secondary module 3 are detachably provided in a slot (not shown) of the device body of the measuring device 11. As shown in FIG. 1, in the slot (not shown) of the measuring device 11, in addition to the primary module 2 and the secondary module 3, a plurality of modules such as a clock module 12 and a measurement module 13 are detachably provided.

[0029] As shown in FIG. 1, the measuring device 11 includes an operation unit 14, a display unit 15, and a device control unit 16. A plurality of modules (such as the primary module 2, the secondary module 3, the clock module 12, and the measurement module 13) selected according to the measurement content can be freely added, removed, and recombined with respect to a slot (not shown), and various measurements of a measurement object based on a standard can be performed in various forms.

[0030] The clock module 12 is composed of a clock generator and generates a reference clock signal (1 / 2 half-rate clock or full-rate clock) for input to the primary module 2 and the secondary module 3.

[0031] Note that the clock module 12 is not limited to a configuration that is detachably provided in a slot (not shown) of the measuring device 11, and an external clock generator separate from the measuring device 11 can also be used.

[0032] The measurement module 13 performs various measurements of the measurement object based on the set values of the measurement parameters set by the operation of the operation unit 14.

[0033] The operation unit 14 includes, for example, a pointing device such as a mouse or a touch screen for operating a pointer or an icon on the display screen of the display unit 15, keys, switches, buttons, etc. provided on the apparatus main body of the measuring device 11. The operation unit 14 performs various operations related to measurement, such as setting an initial value (minimum value or maximum value) of the bit rate that can be generated by the sequence pattern generator 1, initial division ratios of the primary division unit 21 and the secondary division unit 31 of the primary module 2 and the secondary module 3 described later, initial delay amounts of the respective delay circuit units 22, 23, 24 of the primary module 2 and the respective delay circuit units 32, 33, 34 of the secondary module 3, allowable ranges of the phase difference target values of the primary phase comparison unit 25 and the secondary phase comparison unit 35, etc. in addition to initial settings, instructions for starting and stopping measurement, designation of a measurement channel for setting measurement parameters, and setting / change / reference of measurement parameters on the setting screen.

[0034] Note that the initial value of the bit rate is preferably set to the minimum value of the bit rate range with a large phase margin, but the maximum value of the bit rate range may be set as the initial value of the bit rate.

[0035] The display unit 15 is composed of, for example, a liquid crystal display provided on the apparatus main body of the measuring device 11, and displays a setting screen for performing initial settings by the operation unit 14, a setting screen for a predetermined measurement channel, a measurement screen, etc. on the display screen.

[0036] The apparatus control unit 16 is composed of, for example, a microcomputer equipped with a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), etc., and includes setting control of each module based on the operation of the operation unit 14, variable control of the bit rate, output control of the reference clock signal, various measurement controls of the object to be measured based on the measurement signal, display control of the setting screen and the measurement screen, etc., and comprehensively controls the primary module 2, the secondary module 3, the clock module 12, the measurement module 13, the operation unit 14, and the display unit 15.

[0037] Next, the configurations of the primary module 2 and the secondary module 3 that make up the sequence pattern generator 1 will be described.

[0038] As shown in FIG. 1, the primary module 2 includes a primary frequency divider 21, a primary first delay circuit section 22, a primary second delay circuit section 23, a primary third delay circuit section 24, a primary phase comparator 25, a primary data generator 26, a primary first data multiplexing section 27, a primary second data multiplexing section 28, and a primary control section 29.

[0039] The primary frequency divider 21 is composed of a 1 / N frequency divider (N: a positive integer of 2 or more), divides the reference clock signal generated by the clock module 12 or an external clock source by 1 / N, and inputs the divided clock signal divided by 1 / N to the primary first delay circuit section 22 and the primary phase comparator 25.

[0040] The reference clock signal is a half-rate clock or a full-rate clock having a frequency at which the sequence pattern generator 1 can operate (for example, 1.25 GHz to 16 GHz), and is generated by, for example, a clock source prepared by the user, an internal synthesizer built in the measuring device 11 together with the sequence pattern generator 1, an external synthesizer separate from the measuring device 11, and the like. Then, reference clock signals having the same phase are input to the primary module 2 and the secondary module 3.

[0041] The primary first delay circuit section 22 is constituted by, for example, an IQ modulator, and adjusts the delay amount by varying the phase angle of the divided clock signal from the primary frequency division section 21 under the control of the primary control section 29 so that the data signals (parallel data) input from the primary data generation section 26 to the primary first data multiplexing section 27 and the primary second data multiplexing section 28 and the reference clock signal have an optimal phase relationship. The divided clock signal with the adjusted delay amount is input to the primary phase comparison section 25 via the primary second delay circuit section 23, and is also input to the secondary second delay circuit section 33 and the secondary third delay circuit section 34 of the secondary module 3 via the bridge route 4.

[0042] The primary second delay circuit section 23 is constituted by an electronic delay in which delay elements (gate delays) that perform switching in units of several picoseconds electrically are connected in multiple stages, for example. The primary second delay circuit section 23 functions as a bypass circuit that allows the divided clock signal with the delay amount adjusted by the primary first delay circuit section 22 to pass through as it is and input it to the primary phase comparison section 25.

[0043] The primary third delay circuit section 24 is constituted by an electronic delay similar to the primary second delay circuit section 23, and includes the same number of electronic delays as the number of transmission lanes of the parallel data generated by the primary data generation section 26. For example, if the number of transmission lanes of the parallel data is 8, the primary third delay circuit section 24 is constituted by 8 electronic delays. The primary third delay circuit section 24 appropriately adjusts the delay amount for each data under the control of the primary control section 29 in order to perform skew adjustment of each data of the parallel data input from the primary data generation section 26 to the primary first data multiplexing section 27 and the primary second data multiplexing section 28.

[0044] The primary phase comparison unit 25 compares the divided clock signal P1 input from the primary frequency division unit 21 with the divided clock signal P2 input from the primary second delay circuit unit 23 via the bridge route 4 after passing through the primary first delay circuit unit 22 from the primary frequency division unit 21, regarding both divided clock signals P1 and P2 as clock and data to be input to the primary first data multiplexing unit 27 and the primary second data multiplexing unit 28, compares their phases, and outputs a phase difference signal (voltage signal) P2 - P1 corresponding to the phase difference to the primary control unit 29.

[0045] The primary data generation unit 26 is provided on one FPGA (Field Programmable Gate Array) capable of partial configuration, and generates parallel data of a predetermined number of transmission lanes (for example, 4 Gbps × 8) at the timing of the divided clock signal from the primary third delay circuit unit 24 as a data signal of an arbitrary pulse pattern set by the user, and outputs it to the primary first data multiplexing unit 27 and the primary second data multiplexing unit 28.

[0046] The primary first data multiplexing unit 27 and the primary second data multiplexing unit 28 are composed of, for example, a multiplexer (MUX), a D-type flip-flop circuit, etc., and multiplex the parallel data input from the primary data generation unit 26 into serial data at the timing of the reference clock signal and output it.

[0047] The primary control unit 29 comprehensively controls the primary frequency division unit 21, each delay circuit unit 22, 23, 24 of the primary module 2, the primary phase comparison unit 25, the primary data generation unit 26, the primary first data multiplexing unit 27, and the primary second data multiplexing unit 28 so as to synchronize and output the phases of a plurality of data signals with an arbitrary pulse pattern set by the user.

[0048] The primary control unit 29 stores, as correction data, the primary phase difference target value targeted by the primary phase comparison unit 25 of the primary module 2 in association with each predetermined step of the frequency (bit rate) of the reference clock signal and tabulates it.

[0049] The primary control unit 29 sets the primary phase difference target value targeted by the primary phase comparison unit 25 of the primary module 2 according to the frequency (bit rate) of the reference clock signal.

[0050] Note that the primary phase difference target value corresponds one-to-one to each frequency (bit rate) of the reference clock signal. For example, if the reference clock signal is a half-rate clock, it consists of a fixed allowable range with the maximum allowable value and the minimum allowable value being values shifted by ±1 cycle (e.g., ±31.25 psec in the case of 32 Gbit / s: corresponding to the cycle at which the turning of the primary frequency division unit 21 changes) from the center voltage value. Also, if the reference clock signal is a full-rate clock, it consists of a fixed allowable range with the maximum allowable value and the minimum allowable value being values shifted by ±0.5 cycle from the center voltage value.

[0051] When setting the primary phase difference target value at a frequency (bit rate) of the reference clock signal not stored by the primary control unit 29, it is calculated by linear interpolation from the correction data at two points at the frequencies (bit rates) of the reference clock signals before and after that frequency (bit rate) of the reference clock signal.

[0052] The primary control unit 29 adjusts and controls the delay amounts of the respective delay circuit units 22, 23, and 24 of the primary module 2. Specifically, when initial setting is performed by the operation unit 14, the primary control unit 29 adjusts and controls the respective delay circuit units 22, 23, and 24 of the primary module 2 to their initial delay amounts.

[0053] Also, when the primary control unit 29 outputs while keeping the pattern generation timings of the four data signals constant, it adjusts and controls the delay amount of the primary second delay circuit unit 23 so that the voltage read value (voltage value corresponding to the phase difference signal P2 - P1) of the primary phase comparison unit 25 becomes approximately equal to the center voltage value.

[0054] Similar to the primary module 2, the secondary module 3 includes a secondary frequency division unit 31, a secondary first delay circuit unit 32, a secondary second delay circuit unit 33, a secondary third delay circuit unit 34, a secondary phase comparison unit 35, a secondary data generation unit 36, a secondary first data multiplexing unit 37, a secondary second data multiplexing unit 38, and a secondary control unit 39.

[0055] Similar to the primary frequency division unit 21 of the primary module 2, the secondary frequency division unit 31 is composed of a 1 / N frequency divider (N: a positive integer of 2 or more), and divides the reference clock signal having the same phase as the reference clock signal input to the primary frequency division unit 21 of the primary module 2 by 1 / N, and inputs this 1 / N divided clock signal to the secondary first delay circuit unit 32 and the secondary phase comparison unit 35.

[0056] Similar to the primary first delay circuit unit 22 of the primary module 2, the secondary first delay circuit unit 32 is composed of an IQ modulator. Although this secondary first delay circuit unit 32 is an unnecessary configuration originally, it is provided for the purpose of sharing the primary module 2 and the secondary module 3. Here, the output of the secondary first delay circuit unit 32 is open so that it is not output anywhere even when the divided clock signal is input from the secondary frequency division unit 31.

[0057] Similar to the primary second delay circuit section 23 of the primary module 2, the secondary second delay circuit section 33 is composed of an electronic delay in which delay elements (gate delays) that perform switching in units of several picoseconds electrically, for example, are connected in multiple stages to adjust the delay amount of the divided clock signal. The secondary second delay circuit section 33 adjusts the delay amount of the divided clock signal received from the primary module 2 under the control of the secondary control section 39 so that the phase relationship between the data signal (parallel data) input from the secondary data generation section 36 to the secondary first data multiplexing section 37 and the secondary second data multiplexing section 38 and the reference clock signal is the same as the phase relationship between the data signal (parallel data) input to the primary first data multiplexing section 27 and the primary second data multiplexing section 28 of the primary module 2 and the reference clock signal.

[0058] Similar to the primary third delay circuit section 24 of the primary module 2, the secondary third delay circuit section 34 is composed of an electronic delay and has the same number of electronic delays as the number of transmission lanes of the parallel data generated by the secondary data generation section 36. The secondary third delay circuit section 34 appropriately adjusts the delay amount for each data under the control of the secondary control section 39 in order to perform skew adjustment of each data of the parallel data input from the secondary data generation section 36 to the secondary first data multiplexing section 37 and the secondary second data multiplexing section 38.

[0059] The secondary phase comparison section 35 compares the divided clock signal S1 from the secondary division section 31 with the divided clock signal S2 input from the secondary second delay circuit section 33 via the bridge route 4 from the primary first delay circuit section 22 of the primary module 2, and outputs a phase difference signal (voltage signal) corresponding to the phase difference S2 - S1 to the secondary control section 39.

[0060] Similar to the primary data generation unit 26 of the primary module 2, the secondary data generation unit 36 is provided on one FPGA that can be partially configured. As a data signal of an arbitrary pulse pattern set by the user, parallel data of a predetermined number of transmission lanes (for example, 4 Gbps × 8 channels) is generated at the timing of the divided clock signal from the secondary third delay circuit unit 34 and output to the secondary first data multiplexing unit 37 and the secondary second data multiplexing unit 38.

[0061] Similar to the primary first data multiplexing unit 27 and the primary second data multiplexing unit 28 of the primary module 2, the secondary first data multiplexing unit 37 and the secondary second data multiplexing unit 38 are composed of, for example, a multiplexer (MUX), a D-type flip-flop circuit, etc., and multiplex the parallel data input from the secondary data generation unit 36 into serial data at the timing of the reference clock signal and output it.

[0062] The secondary control unit 39 comprehensively controls the secondary division unit 31, each delay circuit unit 32, 33, 34 of the secondary module 3, the secondary phase comparison unit 35, the secondary data generation unit 36, the secondary first data multiplexing unit 37, and the secondary second data multiplexing unit 38 in order to synchronize and output the phases of a plurality of data signals according to an arbitrary pulse pattern set by the user.

[0063] The secondary control unit 39 stores, as correction data tabulated by associating, for each predetermined step of the frequency (bit rate) of the reference clock signal, the secondary phase difference target value targeted by the secondary phase comparison unit 35 of the secondary module 3 and the error of the delay amount caused by the characteristics and wiring variations of each delay circuit unit 22, 23, 24 of the primary module 2 and each delay circuit unit 32, 33, 34 of the secondary module 3, and the phase shift associated with the deterioration of the duty ratio of the primary division unit 21 and the secondary division unit 31.

[0064] Note that the correction value is obtained by subtracting the primary side phase difference target value (voltage reading value) from the secondary side phase difference target value (voltage reading value).

[0065] The secondary control unit 39 sets the secondary side phase difference target value targeted by the secondary phase comparison unit 35 of the secondary module 3 according to the frequency (bit rate) of the reference clock signal.

[0066] Note that the secondary side phase difference target value corresponds one-to-one to each frequency (bit rate) of the reference clock signal. For example, if the reference clock signal is a half-rate clock, a fixed allowable range is formed with the values shifted by ±1 cycle (for example, ±31.25 psec in the case of 32 Gbit / s: corresponding to the cycle at which the turning of the secondary frequency divider 31 changes) from the center voltage value as the allowable maximum value and the allowable minimum value. Also, if the reference clock signal is a full-rate clock, a fixed allowable range is formed with the values shifted by ±0.5 cycle from the center voltage value as the allowable maximum value and the allowable minimum value.

[0067] Also, when setting the secondary side phase difference target value at the frequency (bit rate) of the reference clock signal not stored by the secondary control unit 39, it is calculated by linear interpolation from the correction data at two points at the frequencies (bit rates) of the reference clock signals before and after the frequency (bit rate) of that reference clock signal.

[0068] Note that correction data can also be stored in advance, where the values obtained by adding the correction value to the center voltage value, the maximum value, and the minimum value of the primary side phase difference target value for each predetermined step of the frequency (bit rate) of the reference clock signal are used as the center voltage value, the maximum value, and the minimum value of the secondary side phase difference target value.

[0069] The secondary control unit 39 adjusts and controls the delay amounts of the respective delay circuit units 32, 33, and 34 of the secondary module 3. Specifically, when the initial setting is performed by the operation unit 14, the secondary control unit 39 adjusts and controls each of the delay circuit units 32, 33, and 34 of the secondary module 3 to the initial delay amount.

[0070] Also, when the secondary control unit 39 outputs while keeping the pattern generation timing of the four data signals constant, it adjusts and controls the delay amount of the secondary second delay circuit unit 33 so that the voltage reading value of the secondary phase comparison unit 35 (voltage value corresponding to the phase difference S2 - S1) becomes approximately equal to the center voltage value.

[0071] Furthermore, when the secondary control unit 39 determines that the voltage reading value of the primary phase comparison unit 25 of the primary module 2 (voltage value corresponding to the phase difference signal P2 - P1) and the voltage reading value of the secondary phase comparison unit 35 of the secondary module 3 (voltage value corresponding to the phase difference signal S2 - S1) are not equal, it adjusts and controls the delay amount of the secondary second delay circuit unit 33 so that the phase advances or lags by the reciprocal multiple of the reference clock signal according to the change state of the voltage reading value of the secondary phase comparison unit 35 of the secondary module 3.

[0072] For example, when the reference clock signal is a half-rate clock, if the change state of the voltage reading value of the secondary phase comparison unit 35 is rising with a right shoulder, the delay amount of the secondary second delay circuit unit 33 is adjusted and controlled so that the phase advances by 2UI. On the contrary, if the change state of the voltage reading value of the secondary phase comparison unit 35 is falling with a right shoulder, the delay amount of the secondary second delay circuit unit 33 is adjusted and controlled so that the phase lags by 2UI.

[0073] When the secondary control unit 39 outputs while keeping the pattern generation timing of the four data signals constant after the initial setting, when the bit rate is variably changed by a predetermined amount, it inhibits the secondary frequency division unit 31.

[0074] When the secondary control unit 39 variably changes the bit rate from the initial value (the minimum or maximum value of the bit rate range) by a predetermined amount and inhibits the secondary frequency division unit 31, the voltage reading value of the primary phase comparison unit 25 of the primary module 2 (the voltage value corresponding to the phase difference signal P2 - P1) is compared with the voltage reading value of the secondary phase comparison unit 35 of the secondary module 3 (the voltage value corresponding to the phase difference signal S2 - S1), and it is determined whether the voltage reading values of both are equal (whether P2 - P1 = S2 - S1).

[0075] By the way, in the configuration of FIG. 1 described above, in order to make the primary module 2 and the secondary module 3 common, the internal configurations of both modules 2 and 3 are made the same, but the secondary first delay circuit unit 32 of the secondary module 3 may be omitted.

[0076] In the sequence pattern generator 1 of the present embodiment, each of the primary module 2 and the secondary module 3 has two outputs (referred to as Data1 and Data2), and a maximum of four data signals can be output. Note that if modules are added, the number of outputs is not limited to this number and can be increased.

[0077] As shown in FIG. 2, the sequence pattern generator 1 of the present embodiment can output four data signals synchronously or output a plurality of the four data signals synchronously.

[0078] In FIG. 2, at the start of the sequence at time 3, the sequence progresses in all Lanes, and at time 7, the output of the set sequence ends and pauses due to the pause setting. After that, at time 10, when the sequence is restarted by an operation on the user operation unit 14, only the sequences of the set Lane0 and Lane2 are restarted.

[0079] An explanation will be given of the setting to resume output while synchronizing a plurality of data signals after such a pause of the sequence.

[0080] When the device control unit 16 selects a setting for the data signal output by any one of the primary first data multiplexing unit 27, the primary second data multiplexing unit 28, the secondary first data multiplexing unit 37, and the secondary second data multiplexing unit 38 through an operation on the operation unit 14, it causes the display unit 15 to display a sequence setting screen 101 as shown in FIG. 3.

[0081] FIG. 3 shows a sequence setting screen 101 in the case where there are two outputs using either the primary module 2 or the secondary module 3. The sequence setting screen 101 can perform the setting of the sequence for one output.

[0082] In FIG. 3, the sequence display unit 111 displays the pattern of the set sequence. The sequence patterns set for each row are output in ascending order of the numbers in the "Block No." column of the sequence display unit 111. If a value is set in the "Break" column of the sequence display unit 111, the sequence is temporarily stopped after the processing of that row is completed.

[0083] The sequence edit button 112 enables the content of the sequence display unit 111 to be edited when it is selected by an operation on the operation unit 14. By selecting the sequence edit button 112, it is possible to set the order of the sequence, the content of the data to be output, and the like.

[0084] The transmission button 113 starts the sequence when it is selected by an operation on the operation unit 14.

[0085] The synchronization button 114 is a toggle button, and when it is selected by an operation on the operation unit 14, it can be used to select whether to synchronize when restarting the sequence within the same module.

[0086] When the display of the synchronization button 114 is "Sync OFF", synchronization is not performed, and only the corresponding output sequence resumes. When the display of the synchronization button 114 is "Sync ON", the sequences of two outputs within the same module are synchronized and resume.

[0087] Figure 4 shows a sequence setting screen 201 when a total of four outputs are used with both the primary module 2 and the secondary module 3. The sequence setting screen 201 can set the sequence for one output.

[0088] In Figure 4, similar to the sequence display section 111 in Figure 3, the sequence display section 211 displays the set sequence pattern. The sequence patterns set for each row are output in ascending order of the numbers in the "Block No." column of the sequence display section 211. If a value is set in the "Break" column of the sequence display section 211, the sequence pauses temporarily after the processing of that row is completed.

[0089] The sequence edit button 212 enables the content of the sequence display section 211 to be edited when selected by an operation of the operation unit 14. By selecting the sequence edit button 212, the order of the sequence and the content of the data to be output can be set.

[0090] The transmission button 213 starts the sequence when selected by an operation of the operation unit 14.

[0091] The synchronization setting button 214 is a button for setting the outputs to be synchronized. When selected by an operation of the operation unit 14, a synchronization setting screen 301 as shown in Figure 5 is displayed.

[0092] In FIG. 5, the primary module selection button 311 and the secondary module selection button 312 are for selecting the modules to be synchronized. They are in the form of combo boxes and can be selected from a list or directly input by operating the operation unit 14. By enabling the selection of the modules to be synchronized using combo boxes in this way, unnecessary buttons other than the selected module can be hidden, preventing user confusion.

[0093] The synchronization selection buttons 313, 314, 315, and 316 are for selecting the outputs to be synchronized. They are toggle buttons and can be used to select whether to synchronize the outputs of the corresponding slots when the sequence resumes by operating the operation unit 14.

[0094] When the displays of the synchronization selection buttons 313, 314, 315, and 316 are "OFF", synchronization is not performed and the sequence is not output when the sequence resumes. When the displays of the synchronization selection buttons 313, 314, 315, and 316 are "ON", the corresponding outputs are synchronized and the sequence is output when the sequence resumes.

[0095] In this way, in the above-described embodiment, in the setting of the data signal to be output, the setting of the output to be resumed synchronously when the sequence resumes is performed. As a result, the user can arbitrarily set the output to be synchronized.

[0096] Also, the synchronization setting screen 301 enables the selection of modules and arbitrarily sets the outputs to be synchronized from among the outputs of the selected modules.

[0097] As a result, even when three or more modules are inserted but only two modules are to be synchronized, buttons other than the selected modules are not displayed, preventing user confusion.

[0098] In addition, the setting of the synchronization of the outputs within one module is only for setting whether to synchronize or not, and for the setting of the synchronization of the outputs of multiple modules, each output is set for synchronization.

[0099] In this way, by providing a setting screen according to the maximum number of synchronizations possible, the user can perform the target setting with a smaller number of operations.

[0100] Note that in this embodiment, the measurement device 11 is shown to have a configuration including an operation unit 14, a display unit 15, and a device control unit 16, but a personal computer connected to the measurement device 11 may replace the functions of the operation unit 14, the display unit 15, and the device control unit 16.

[0101] Although embodiments of the present invention have been disclosed, it is obvious that those skilled in the art can make changes without departing from the scope of the present invention. It is intended that all such modifications and equivalents be included in the following claims.

Explanation of Reference Numerals

[0102] 1 Sequence Pattern Generator 2 Primary Module 3 Secondary Module 14 Operation Unit 15 Display Unit 16 Device Control Unit 27 Primary First Data Multiplexing Unit 28 Primary Second Data Multiplexing Unit 29 Primary Control Unit 37 Secondary First Data Multiplexing Unit 38 Secondary Second Data Multiplexing Unit 39 Secondary Control Unit 101 Sequence Setting Screen 111 Sequence Display Unit 112 Sequence Edit Button 113 Transmission Button 114 Synchronization Button 201 Sequence Setting Screen 211 Sequence display section 212 Sequence editing button 213 Transmission button 214 Synchronization setting button 301 Synchronization setting screen 311 Primary module selection button 312 Secondary module selection button 313, 314, 315, 316 Synchronization selection buttons

Claims

1. A sequence pattern generator (1) capable of mounting at least one module (2, 3) having an output of at least one data signal, wherein the total number of outputs of the data signals is two or more, The sequence pattern generator includes a device control unit (16) for setting an output to be restarted synchronously when the sequence is restarted in the setting of one of the data signals to be output.

2. The sequence pattern generator according to claim 1, wherein the device control unit causes the module to be selected and selects whether to restart synchronously with the restart of the sequence for the output of the selected module.

3. The sequence pattern generator according to claim 1 or claim 2, wherein when only one module having two outputs is mounted, the device control unit selects only whether to restart synchronously with the restart of the sequence.

4. A method for setting a sequence pattern generator (1) capable of mounting at least one module (2, 3) having an output of at least one data signal, wherein the total number of outputs of the data signals is two or more, The method for setting a sequence pattern generator includes a device control step (S1) for setting an output to be restarted synchronously when the sequence is restarted in the setting of one of the data signals to be output.

5. The method for setting a sequence pattern generator according to claim 4, wherein the device control step includes a selection step (S2) for selecting the module and selecting whether to restart synchronously with the restart of the sequence for the output of the selected module.

6. The method for setting a sequence pattern generator according to claim 4 or claim 5, wherein when only one module having two outputs is mounted, the device control step selects only whether to restart synchronously with the restart of the sequence.

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