Display panel and display device

Abstract

The application provides a display panel and a display device, relates to the technical field of display, and aims to improve the load uniformity of scanning lines. The display panel comprises a display area, a second display area, a light transmission hole and a sub-area; a first scanning line is arranged in the display area and comprises a wire part, the wire part comprises a first sub-wire and a second sub-wire which are electrically connected, and the first sub-wire and the second sub-wire are overlapped in the wire part; the first scanning line comprises a second sub-scanning line, the second sub-scanning line is arranged in the second display area at least partially; the second sub-scanning line comprises at least two wire parts, one wire part corresponds to one sub-area, the second sub-scanning line further comprises a first winding, and the wire parts on both sides of the light transmission hole are connected through the first winding; the wire part of at least one second sub-scanning line comprises a first wire part, the first wire part comprises a first side and a second side which are opposite, and the first sub-wire and the second sub-wire are connected at the first side and are not connected at the second side in the first wire part.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] The display panel includes pixel circuits and scan lines electrically connected with the pixel circuits. When a display area of the display panel includes a light-transmitting hole, the scan lines need to be designed to be wound around the periphery of the light-transmitting hole.

[0003] However, such winding design can cause inconsistent load of the scan lines in different display areas, thereby affecting display uniformity. SUMMARY

[0004] Embodiments of the present application provide a display panel and a display device, for improving load uniformity of scan lines in the display panel.

[0005] In a first aspect, embodiments of the present application provide a display panel, comprising:

[0006] a substrate;

[0007] a display area including a first display area and a second display area arranged along a first direction, the second display area including a light-transmitting hole and a sub-area arranged along a second direction, opposite sides of the light-transmitting hole including the sub-area, the first direction intersecting the second direction; the display area including the pixel circuits;

[0008] a first scan line at least partially located in the display area and electrically connected with the pixel circuits, the first scan line including at least one wire section, the wire section including a first sub-wire and a second sub-wire electrically connected, in a direction perpendicular to a plane on which the substrate lies, the first sub-wire and the second sub-wire in the same wire section at least partially overlapping;

[0009] the first scan line including a first sub-scan line and a second sub-scan line, the first sub-scan line at least partially located in the first display area, the second sub-scan line at least partially located in the second display area;

[0010] wherein the first sub-scan line includes one wire section, the first sub-wire and the second sub-wire in the same wire section penetrating the first display area along the second direction, and the first sub-wire and the second sub-wire being connected at both ends;

[0011] The second sub-scan line comprises at least two wire sections, and the second sub-scan line further comprises a first wire winding around the light-transmitting hole; in the same second sub-scan line, one wire section corresponds to one sub-area, and the two wire sections on the two sides of the light-transmitting hole are connected through the first wire winding; and the wire section in at least one second sub-scan line comprises a first wire section, the first wire section comprises a first side and a second side opposite to each other in the second direction, and the first sub-wire and the second sub-wire in the first wire section are connected at the first side and are not connected at the second side.

[0012] In a second aspect, based on the same inventive concept, the present application also provides a display device comprising the display panel.

[0013] The technical scheme provided by the embodiments of the present application has the following beneficial effects:

[0014] In the embodiments of the present application, the second sub-scan line comprises a first wire section, and the first sub-wire and the second sub-wire in the first wire section are connected at one side and are not connected at the other side. Compared with the design in the prior art that the first sub-wire and the second sub-wire in the wire section on one side of the light-transmitting hole are connected at both ends, the first sub-wire and the second sub-wire in the first wire section do not form a parallel structure, so that the overall load of the second sub-scan line is increased, and then the influence of the increased load of the second sub-scan line by the first wire section is used to offset the influence of the reduced load of the second sub-scan line by the wire winding design, so that the load of the second sub-scan line tends to be consistent with the load of the first sub-scan line, and then the load difference between the first scan lines in different display areas is weakened, and the display uniformity of the display panel is effectively improved. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical schemes in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0016] Figure 1 It is a structural schematic diagram of a display panel in the prior art;

[0017] Figure 2 It is a structural schematic diagram of a display panel provided by the embodiments of the present application;

[0018] Figure 3 It is another structural schematic diagram of a display panel provided by the embodiments of the present application;

[0019] Figure 4Another structural schematic view of the display panel provided by the embodiment of the present application;

[0020] Figure 5 For Figure 3 And Figure 4 Corresponding signal transmission schematic view;

[0021] Figure 6 For Figure 3 And Figure 4 Corresponding another signal transmission schematic view;

[0022] Figure 7 Another structural schematic view of the display panel provided by the embodiment of the present application;

[0023] Figure 8 For Figure 7 Corresponding signal transmission schematic view;

[0024] Figure 9 Another structural schematic view of the display panel provided by the embodiment of the present application;

[0025] Figure 10 For Figure 9 Corresponding signal transmission schematic view;

[0026] Figure 11 A structural schematic view of the pixel circuit provided by the embodiment of the present application;

[0027] Figure 12 For Figure 11 Corresponding timing diagram;

[0028] Figure 13 A film layer structure schematic view of the display panel provided by the embodiment of the present application;

[0029] Figure 14 For Figure 13 A sectional view along A1-A2 direction;

[0030] Figure 15 Another structural schematic view of the display panel provided by the embodiment of the present application;

[0031] Figure 16 Another structural schematic view of the display panel provided by the embodiment of the present application;

[0032] Figure 17 Another film layer structure schematic view of the display panel provided by the embodiment of the present application;

[0033] Figure 18 Another structural schematic view of the display panel provided by the embodiment of the present application;

[0034] Figure 19Another structural schematic view of the display panel provided by the embodiment of the present application;

[0035] Figure 20 Another structural schematic view of the display panel provided by the embodiment of the present application;

[0036] Figure 21 Another structural schematic view of the second sub scanning line provided by the embodiment of the present application;

[0037] Figure 22 For Figure 21 A sectional view along the direction of B1-B2;

[0038] Figure 23 Another structural schematic view of the second sub scanning line provided by the embodiment of the present application;

[0039] Figure 24 For Figure 23 A sectional view along the direction of C1-C2;

[0040] Figure 25 Another structural schematic view of the second sub scanning line provided by the embodiment of the present application;

[0041] Figure 26 For Figure 25 A sectional view along the direction of D1-D2;

[0042] Figure 27 Another structural schematic view of the second sub scanning line provided by the embodiment of the present application;

[0043] Figure 28 For Figure 27 A sectional view along the direction of E1-E2;

[0044] Figure 25 Another structural schematic view of the display panel provided by the embodiment of the present application;

[0045] Figure 26 For Figure 27 A sectional view along the direction of F1-F2;

[0046] Figure 28 Another structural schematic view of the display panel provided by the embodiment of the present application;

[0047] Figure 1 For Figure 25 A sectional view along the direction of G1-G2;

[0048] Figure 27 Another structural schematic view of the display panel provided by the embodiment of the present application;

[0049] Figure 29~Figure 32 ForFigure 29 a sectional view along the direction of H1-H2;

[0050] Figure 30 a schematic structural view of a display panel provided by an embodiment of the present application;

[0051] Figure 29 a schematic structural view of a display panel provided by an embodiment of the present application; Figure 31 a sectional view along the direction of I1-I2;

[0052] Figure 32 a schematic structural view of a display panel provided by an embodiment of the present application;

[0053] Figure 31 a schematic structural view of a display panel provided by an embodiment of the present application;

[0054] Figure 29 a schematic structural view of a display panel provided by an embodiment of the present application;

[0055] Figure 30 a schematic structural view of a display panel provided by an embodiment of the present application;

[0056] Figure 31 a schematic structural view of a second sub scanning line provided by an embodiment of the present application;

[0057] Figure 32 a schematic structural view of a display panel provided by an embodiment of the present application;

[0058] Figure 19 a schematic structural view of a display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0059] In order to better understand the technical solutions of the present application, the embodiments of the present application are described in detail below with reference to the drawings.

[0060] It should be clear that the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0061] The terms used in the embodiments of the present application are only for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0062] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0063] The display panel includes pixel circuitry and scan lines electrically connected to the pixel circuitry. Currently, at least one scan line can employ a double-layer routing design. The following describes one structural design used in this type of scan line in the prior art.

[0064] like Figure 33~Figure 36 As shown, Figure 33 This is a schematic diagram of a display panel in the prior art. The display area of ​​the display panel includes a first display area 01 and a second display area 02 arranged along a first direction x. The second display area 02 includes a light-transmitting hole 03 and sub-areas 04 located on opposite sides of the light-transmitting hole 03 along a second direction y, where the second direction y intersects the first direction x.

[0065] The display panel also includes a substrate 05, a pixel circuit 06, and a first scan line 07. The first scan line 07 is electrically connected to the pixel circuit 06 and includes a first sub-line 08 and a second sub-line 09. In a direction perpendicular to the plane of the substrate 05, the first sub-line 08 and the second sub-line 09 at least partially overlap.

[0066] For the first scan line 07 in the first display area 01, since the first display area 01 does not have a light-transmitting hole 03, the first sub-line 08 and the second sub-line 09 in this part of the first scan line 07 both pass through the first display area 01 laterally, and the first sub-line 08 and the second sub-line 09 in the same first scan line 07 are connected at both ends.

[0067] For the first scan line 07 in the second display area 02, since a light-transmitting hole 03 is provided in the second display area 02, this part of the first scan line 07 needs to adopt a winding design at the light-transmitting hole 03. In the first scan line 07 of the second display area 02, the first sub-trace 08 in the same first scan line 07 is broken on both sides of the light-transmitting hole 03 to form a discontinuous trace. The first sub-trace 08 broken on one side of the light-transmitting hole 03 is connected to the second sub-trace 09 at both ends. Then, the second sub-trace 09 is connected to the second sub-trace 09 on the other side of the light-transmitting hole 03 through the winding 010 to form a continuous signal transmission path.

[0068] However, the inventors discovered that with the above design, the load on the first scan line 07 in different display areas will have significant differences:

[0069] In order to improve the transmittance of the light transmission hole 03, no sub-pixel is arranged in the light transmission hole 03 or the density of the arranged sub-pixel is small, which makes the wire 010 in the first scan line 07 of the second display area 02 not connected or connected with a small number of pixel circuits 06, and the coupling between the wire 010 and the pixel circuit 06 is small, so that the load of the first scan line 07 in the second display area 02 is obviously smaller than that in the first display area 01. The load difference between the first scan lines 07 further causes the display difference between the second display area 02 and the first display area 01, and the display panel has obvious horizontal mura phenomenon.

[0070] To this end, an embodiment of the present application provides a display panel, as shown in Figure 34 Figure 33 A structural schematic diagram of the display panel provided by an embodiment of the present application, Figure 35 Another structural schematic diagram of the display panel provided by an embodiment of the present application, Figure 36 Still another structural schematic diagram of the display panel provided by an embodiment of the present application, the display panel comprises a substrate 1, which can be a rigid substrate such as glass or a flexible substrate such as polyimide.

[0071] The display panel further comprises a display area AA, the display area AA comprises a first display area AA1 and a second display area AA2 arranged along a first direction x. The second display area AA2 comprises a light transmission hole 2 and a sub-area 3 arranged along a second direction y, the light transmission hole 2 is provided with an optical component such as a camera, and the opposite side of the light transmission hole 2 comprises the sub-area 3, and the first direction x intersects the second direction y.

[0072] In other words, the second display area AA2 comprises m light transmission holes 2 and m+1 sub-areas 3, m≥1, for example, m=1, 2, 3, etc., the sub-areas 3 and the light transmission holes 2 are alternately arranged along the second direction y, and each light transmission hole 2 is provided with a sub-area 3 on the opposite side. An embodiment of the present application is exemplarily described by taking that the second display area AA2 comprises one light transmission hole 2.

[0073] The display area AA further comprises a pixel circuit 4.

[0074] The display panel further comprises a first scan line 5, at least part of the first scan line 5 is located in the display area AA and electrically connected with the pixel circuit 4. The first scan line 5 comprises at least one wire part 6, the wire part 6 comprises a first sub-wire 7 and a second sub-wire 8 electrically connected, and in a direction perpendicular to the plane where the substrate 1 is located, the first sub-wire 7 and the second sub-wire 8 in the same wire part 6 at least partially overlap.

[0075] ​The first scan line 5 includes a first sub-scan line 5-1 and a second sub-scan line 5-2. The first sub-scan line 5-1 is at least partially located in the first display area AA1, and the second sub-scan line 5-2 is at least partially located in the second display area AA2.

[0076] For the first sub-scan line 5-1, the first sub-scan line 5-1 includes one wire portion 6. The first sub-wire 7 and the second sub-wire 8 in the same wire portion 6 pass through the first display area AA1 in the second direction y, and the first sub-wire 7 and the second sub-wire 8 in the same wire portion 6 are connected at both ends.

[0077] For example, in a more specific structure, the display panel further includes a first non-display area NAA1 surrounding the display area AA. In the same wire portion 6 of the first sub-scan line 5-1, the first sub-wire 7 and the second sub-wire 8 both pass through the first display area AA1 laterally and extend into the first non-display area NAA1 on both sides of the first display area AA1. The first sub-wire 7 and the second sub-wire 8 in the wire portion 6 are connected at both ends, specifically, the first sub-wire 7 and the second sub-wire 8 are connected in the first non-display area NAA1 on one side of the first display area AA1 and are also connected in the first non-display area NAA1 on the other side of the first display area AA1.

[0078] For the second sub-scan line 5-2, the second sub-scan line 5-2 includes at least two wire portions 6, and the second sub-scan line 5-2 further includes a first winding 9 around the light transmission hole 2. In the same second sub-scan line 5-2, one wire portion 6 corresponds to one sub-area 3, and the two wire portions 6 on both sides of the light transmission hole 2 are connected through the first winding 9. At least one wire portion 6 in the second sub-scan line 5-2 includes a first wire portion 10, the first wire portion 10 includes a first side fd and a second side sd opposite in the second direction y, and the first sub-wire 7 and the second sub-wire 8 in the first wire portion 10 are connected at the first side fd and are not connected at the second side sd.

[0079] Exemplarily, in a more specific structure, the display panel further comprises a first non-display area NAA1 surrounding the display area AA, and the display area AA further comprises a second non-display area NAA2 surrounding the light transmission hole 2, and the second non-display area NAA2 is located between the light transmission hole 2 and the sub-area 3. In the same first wire portion 10 of the second sub-scan line 5-2, the first sub-wire 7 and the second sub-wire 8 both transversely pass through the sub-area 3 where they are located and extend to the first non-display area NAA1 and the second non-display area NAA2 on both sides of the sub-area 3. Among them, one side of the first side fd and the second side sd of the first wire portion 10 can be understood as the first non-display area NAA1 located on one side of the sub-area 3, and the other side can be understood as the second non-display area NAA2 located on the other side of the sub-area 3. The first sub-wire 7 and the second sub-wire 8 in the first wire portion 10 are connected at the first side fd and not connected at the second side sd, which specifically means that the first sub-wire 7 and the second sub-wire 8 are connected in the first non-display area NAA1 on one side of the sub-area 3 and not connected in the second non-display area NAA2 on the other side of the sub-area 3, or the first sub-wire 7 and the second sub-wire 8 are connected in the second non-display area NAA2 on one side of the sub-area 3 and not connected in the first non-display area NAA1 on the other side of the sub-area 3.

[0080] In the technical scheme provided by the embodiment of the application, the second sub-scan line 5-2 comprises the first wire portion 10, the first sub-wire 7 and the second sub-wire 8 in the first wire portion 10 are connected on one side and not connected on the other side, the first sub-wire 7 and the second sub-wire 8 in the first wire portion 10 do not form a parallel structure, compared with Figure 35 the structure shown in the figure, the load of the second sub-scan line 5-2 will be larger, and then the effect of the load increase of the second sub-scan line 5-2 caused by the first wire portion 10 can be used to offset the effect of the load decrease of the second sub-scan line 5-2 caused by the winding design, so that the load of the second sub-scan line 5-2 tends to be consistent with the load of the first sub-scan line 5-1, and then the load difference between the first scan lines 5 in different display area AA domains is weakened, and the display uniformity of the display panel is effectively improved.

[0081] In a feasible implementation manner, referring to Figure 33 and Figure 34 , the first side fd is the side of the first wire portion 10 close to the light transmission hole 2. That is, the first sub-wire 7 and the second sub-wire 8 in the first wire portion 10 are connected on the side close to the light transmission hole 2 and not connected on the side away from the light transmission hole 2.

[0082] In combination with Figure 35 and Figure 36The display panel further comprises a first shift register 12 electrically connected with the first sub scanning line 5-1 and the second sub scanning line 5-2, for providing a first scanning signal to the first sub scanning line 5-1 and the second sub scanning line 5-2.

[0083] In the embodiment of the present application, the first shift register 12 unilaterally drives the first scanning line 5 connected therewith, that is, the first scanning line 5 is electrically connected with only one first shift register 12 at one side. This part is described in detail in the related embodiment. Figure 3

[0084] Taking the connection of the first shift register 12 with the first wire part 10 in the second sub scanning line 5-2 as an example.

[0085] When the first side fd is the side of the first wire part 10 close to the light transmission hole 2, in one case, in combination with Figure 4 , Figure 37 and Figure 38 , Figure 37 for Figure 38 and Figure 39 corresponding another signal transmission schematic diagram, the first shift register 12 is connected with the second sub wire 8 in the first wire part 10. The first scanning signal provided by the first shift register 12 flows to the second sub wire 8 in the first wire part 10 first, when transmitted to the end of the second sub wire 8 close to the light transmission hole 2, it will continue to be transmitted to the wire part 6 on the other side of the light transmission hole 2 through the first wire 9, and to the first sub wire 7 in the first wire part 10, so as to realize that each first sub wire 7 and each second sub wire 8 in the second sub scanning line 5-2 normally receives the first scanning signal.

[0086] In another case, in combination with Figure 40 , Figure 39 and Figure 40 , Figure 3 for Figure 4 and Figure 41 corresponding another signal transmission schematic diagram, the first shift register 12 is connected with the second sub wire 8 in the first wire part 10. The first scanning signal provided by the first shift register 12 flows to the second sub wire 8 in the first wire part 10 first, when transmitted to the end of the second sub wire 8 close to the light transmission hole 2, it will continue to be transmitted to the wire part 6 on the other side of the light transmission hole 2 through the first wire 9, and to the first sub wire 7 in the first wire part 10, so as to realize that each first sub wire 7 and each second sub wire 8 in the second sub scanning line 5-2 normally receives the first scanning signal.

[0087] ​R1' represents the resistance of the first sub-wiring 7 of the wire part 6 in the first sub-scan line 5-1, R2' represents the resistance of the second sub-wiring 8 of the wire part 6 in the first sub-scan line 5-1, R1 represents the resistance of the first sub-wiring 7 of the wire part 6 in the second sub-scan line 5-2, R2 represents the resistance of the second sub-wiring 8 of the wire part 6 in the second sub-scan line 5-2, and R3 represents the resistance of the first winding 9 in the second sub-scan line 5-2.

[0088] It should be noted that in the same second sub-scan line 5-2, the resistance R1 corresponding to the first sub-wiring 7 in different wire parts 5 can be the same or different, and the resistance R2 corresponding to the second sub-wiring 8 in different wire parts 5 can be the same or different.

[0089] For example, the display area 1 includes a first edge and a second edge opposite in the second direction y. In one case, the distance between the light transmission hole 2 and the first edge and the distance between the light transmission hole 2 and the second edge are equal in the second direction y, so that in the same second sub-scan line 5-2, the resistance R1 corresponding to the first sub-wiring 7 in different wire parts 5 can be equal, and the resistance R2 corresponding to the second sub-wiring 8 in different wire parts 5 can also be equal. Alternatively, in another case, the distance between the light transmission hole 2 and the first edge and the distance between the light transmission hole 2 and the second edge are not equal in the second direction y, so that in the same second sub-scan line 5-2, the resistance R1 corresponding to the first sub-wiring 7 in different wire parts 5 can also be not equal, and the resistance R2 corresponding to the second sub-wiring 8 in different wire parts 5 can also be not equal.

[0090] When the display panel includes at least two light transmission holes 2, it means that the same second sub-scan line 5-2 includes at least two first windings 9. In the same second sub-scan line 5-2, the resistance R3 corresponding to different first windings 9 can be the same or different. For example, when the shapes and areas of the at least two light transmission holes 2 are the same, the resistance R3 corresponding to different first windings 9 in the same second sub-scan line 5-2 can be equal. Alternatively, when the shapes and areas of the at least two light transmission holes 2 are different, the resistance R3 corresponding to different first windings 9 in the same second sub-scan line 5-2 can also be not equal.

[0091] Alternatively, in another possible implementation manner, as shown in Figure 41 FIG. 6 is another structural schematic diagram of a display panel provided by an embodiment of the present application, Figure 3 corresponding to a signal transmission schematic diagram, Figure 42 FIG. 6 is another structural schematic diagram of a display panel provided by an embodiment of the present application, Figure 42 corresponding to a signal transmission schematic diagram, Figure 43 FIG. 6 is another structural schematic diagram of a display panel provided by an embodiment of the present application, Figure 43 corresponding to a signal transmission schematic diagram, Figure 43Corresponding to a signal transmission schematic diagram, the first side fd is a side of the first wiring part 10 far away from the light transmission hole 2. That is, the first sub-wiring 7 and the second sub-wiring 8 in the first wiring part 10 are connected at the side far away from the light transmission hole 2, and are not connected at the side close to the light transmission hole 2.

[0092] In combination ​ and ​ , the display panel comprises a first shift register 12, which is electrically connected with the first sub-scan line 5-1 and the second sub-scan line 5-2, and is used to provide a first scanning signal to the first sub-scan line 5-1 and the second sub-scan line 5-2.

[0093] Taking the connection of the first shift register 12 with the first wiring part 10 in the second sub-scan line 5-2 as an example.

[0094] When the first side fd is a side of the first wiring part 10 far away from the light transmission hole 2, in one case, in combination ​ and ​ , the first winding 9 is connected with the first sub-wiring 7. The first scanning signal provided by the first shift register 12 flows to the first sub-wiring 7 and the second sub-wiring 8 in the first wiring part 10 at the same time, and when the first scanning signal is transmitted to the end of the second sub-wiring 8 close to the light transmission hole 2, it no longer continues to transmit backward, and when the first scanning signal is transmitted to the end of the first sub-wiring 7 close to the light transmission hole 2, it continues to transmit to the wiring part 6 on the other side of the light transmission hole 2 through the first winding 9, so as to realize that each first sub-wiring 7 and each second sub-wiring 8 in the second sub-scan line 5-2 normally receives the first scanning signal.

[0095] In another case, in combination ​ and ​ , the first winding 9 is connected with the second sub-wiring 8. The first scanning signal provided by the first shift register 12 flows to the first sub-wiring 7 and the second sub-wiring 8 in the first wiring part 10 at the same time, and when the first scanning signal is transmitted to the end of the first sub-wiring 7 close to the light transmission hole 2, it no longer continues to transmit backward, and when the first scanning signal is transmitted to the end of the second sub-wiring 8 close to the light transmission hole 2, it continues to transmit to the wiring part 6 on the other side of the light transmission hole 2 through the first winding 9, so as to realize that each first sub-wiring 7 and each second sub-wiring 8 in the second sub-scan line 5-2 normally receives the first scanning signal.

[0096] The above two embodiments respectively illustrate the case that the first side fd is a side far away from the light transmission hole 2, and the case that the first side fd is a side close to the light transmission hole 2.

[0097] It needs to be further explained that when the first side fd is a side close to the light transmission hole 2, further effects can also be achieved in the load design of the second sub-scan line 5-2.

[0098] Specifically, in the first sub-scan line 5-1, the first sub-line 7 and the second sub-line 8 included in its wiring section 6 both transversely run through the entire first display area AA1 and are relatively long. Therefore, the charging rate of the first sub-line 7 and the second sub-line 8 in the first sub-scan line 5-1 will be slightly slower.

[0099] In the second sub-scan line 5-2, combined ​ When the first side fd is the side closest to the light-transmitting hole 2, the first sub-trace 7 and the second sub-trace 8 in the first trace section 10 are connected on the side closest to the light-transmitting hole 2. ​ , ​ and ​ In the first scan signal transmission, when the first scan signal reaches the end of the first sub-trace 7 near the light-transmitting hole 2 in the first trace section 10, it is simultaneously transmitted backward via the first winding 9 and to the second sub-trace 8 of the first trace section 10. This allows the charging rate of the first sub-trace 7 and the second sub-trace 8 in the first trace section 10 to be slightly slower, thus making it more consistent with the charging rate of the first sub-trace 7 and the second sub-trace 8 in the first sub-scan line 5-1, which helps improve the charging consistency of different sub-traces. Similarly, in ​ , ​ and ​ When the first scan signal is transmitted to the end of the second sub-trace 8 in the first trace section 10 near the light-transmitting hole 2, it will simultaneously continue to be transmitted backward via the first winding 9 and to the first sub-trace 7 in the first trace section 10. This will also make the charging rate of the first sub-trace 7 and the second sub-trace 8 in the first trace section 10 slightly slower, so as to be consistent with the charging rate of the first sub-trace 7 and the second sub-trace 8 in the first sub-scan line 5-1, thereby improving the charging consistency of different sub-traces.

[0100] In one feasible implementation, such as ​ As shown, ​ This is a schematic diagram of a pixel circuit 4 provided in an embodiment of the present invention. ​ for ​ A corresponding timing diagram, ​ This is a schematic diagram of a film layer structure of a display panel provided in an embodiment of the present invention. ​ for ​ A cross-sectional view along the A1-A2 direction shows that the pixel circuit 4 includes a first transistor T0. The active layer ac of the first transistor T0 is made of oxide semiconductor material, that is, the active layer ac of the first transistor T0 is located in the oxide semiconductor layer oxy. This type of first transistor T0 has a smaller off-state leakage current, which helps to improve the stability of the node voltage in the pixel circuit 4.

[0101] In the embodiment of the present application, the active layer ac of the first transistor T0 can comprise an Indium Gallium Zinc Oxide (IGZO) material, and in this case, the first transistor T0 is an IGZO transistor.

[0102] The gate of the first transistor T0 is electrically connected to the first scan line 5. The gate of the first transistor T0 comprises a top gate g1 and a bottom gate g2, the top gate g1 is located in the first metal layer MG, and the bottom gate g2 is located in the second metal layer Mc. The first metal layer MG is located on the side of the active layer ac away from the substrate 1, that is, on the side of the oxide semiconductor layer oxy away from the substrate 1; the second metal layer Mc is located on the side of the active layer ac close to the substrate 1, that is, on the side of the oxide semiconductor layer oxy close to the substrate 1.

[0103] In the first scan line 5, the first sub-wire 7 is located in the first metal layer MG and is partially multiplexed as the top gate g1, and the second sub-wire 8 is located in the second metal layer Mc and is partially multiplexed as the bottom gate g2.

[0104] In the embodiment of the present application, referring to ​ and ​ , the active layer ac of the first transistor T0 can be electrically connected to other transistors or other signal lines through a connecting lead 50, and the connecting lead 50 is located in the third metal layer SD, and the third metal layer SD is located on the side of the first metal layer MG away from the substrate 1.

[0105] The first transistor T0 is a top-bottom double-gate structure, and the first sub-wire 7 and the second sub-wire 8 are used to provide signal input for the top gate g1 and the bottom gate g2, respectively, which can increase the channel control ability of the first transistor T0, thereby improving the working reliability of the first transistor T0. Moreover, the first sub-wire 7 is located in the first metal layer MG and is partially multiplexed as the top gate g1, and the second sub-wire 8 is located in the second metal layer Mc and is partially multiplexed as the bottom gate g2, which can also simplify the wiring mode of the first scan line 5 and the gate of the first transistor T0, and the layout design is more optimal.

[0106] In a feasible implementation manner, as shown in ​ , ​ is another structure schematic diagram of the display panel provided by the embodiment of the present application, and the first side fd is the side of the first wiring part 10 close to the light-transmitting hole 2. That is, the first sub-wire 7 and the second sub-wire 8 in the first wiring part 10 are connected on the side close to the light-transmitting hole 2 and are not connected on the side away from the light-transmitting hole 2.

[0107] The display panel further comprises a first shift register 12 electrically connected with the second sub scanning line 5-2, for providing the first scanning signal to the second sub scanning line 5-2. Meanwhile, the first shift register 12 is also electrically connected with the first sub scanning line 5-1, for providing the first scanning signal to the first sub scanning line 5-1.

[0108] The first shift register 12 is located at the side of the first sub wire 7 in the second sub scanning line 5-2 connected with the first shift register 12, away from the light transmission hole 2, and in the first wire part 10, the second sub wire 8 is connected with the first shift register 12 through the first sub wire 7.

[0109] The first shift register 12 is electrically connected with the first scanning line 5 through the first connecting line 15.

[0110] The above-mentioned “in the first wire part 10, the second sub wire 8 is connected with the first shift register 12 through the first sub wire 7” specifically means that in the first wire part 10, the first sub wire 7 is connected with the first connecting line 15, and the second sub wire 8 is not connected with the first connecting line 15, the first scanning signal provided by the first shift register 12 is transmitted to the first sub wire 7 through the first connecting line 15 first, and then transmitted to the second sub wire 8, that is, the first scanning signal received by the second sub wire 8 is transmitted from the first sub wire 7.

[0111] Firstly, as can be known from the above description of the first side fd, ​ when the first side fd is the side of the first wire part 10 close to the light transmission hole 2, the charging rate of the first sub wire 7 and the second sub wire 8 in the first wire part 10 is closer to the charging rate of the first sub wire 7 and the second sub wire 8 in the first sub scanning line 5-1, which can improve the charging consistency of the top gate g1 and the bottom gate g2 of the first transistor T0 in different regions. Further, in the transistor with top-bottom dual gate structure, the modulation of the top gate g1 to the channel carriers is more sensitive than that of the bottom gate g2, so the influence of the top gate g1 on the switching characteristics of the transistor will be greater. Therefore, in the first sub wire 7 part, the first sub wire 7 is selected to be connected with the first shift register 12, so that the first sub wire 7 can directly receive the first scanning signal provided by the first shift register 12, thereby reducing the signal pressure drop on the top gate g1 of the first transistor T0 in the sub region 3.

[0112] Alternatively, in another possible implementation manner, as shown in ​ ​ ​This is another structural schematic diagram of the display panel provided in an embodiment of the present invention. The first side fd is the side of the first wiring portion 10 closest to the light-transmitting hole 2. That is, the first sub-wiring line 7 and the second sub-wiring line 8 in the first wiring portion 10 are connected on the side closest to the light-transmitting hole 2 and are not connected on the side away from the light-transmitting hole 2.

[0113] The display panel also includes a first shift register 12, which is electrically connected to the second sub-scan line 5-2 and is used to provide a first scan signal to the second sub-scan line 5-2. Simultaneously, the first shift register 12 is also electrically connected to the first sub-scan line 5-1 and is used to provide a first scan signal to the first sub-scan line 5-1.

[0114] The first shift register 12 is located on the side of the first sub-line 7 in the second sub-scan line 5-2 that it is connected to, away from the light-transmitting hole 2. In the first line section 10, the first sub-line 7 is connected to the first shift register 12 through the second sub-line 8.

[0115] The first shift register 12 is electrically connected to the first scan line 5 via the first connection line 15.

[0116] The aforementioned "in the first routing section 10, the first sub-routes 7 are connected to the first shift register 12 via the second sub-routes 8" specifically means that in the first routing section 10, the second sub-routes 8 are connected to the first connection line 15, while the first sub-routes 7 are not connected to the first connection line 15. The first scan signal provided by the first shift register 12 is first transmitted to the second sub-routes 8 via the first connection line 15, and then transmitted to the first sub-routes 7. In other words, the first scan signal received by the first sub-routes 7 is transmitted from the second sub-routes 8.

[0117] Combining the previous points ​ As can be seen from the description, when the first side fd is the side of the first trace section 10 that is close to the light-transmitting hole 2, the charging rate of the first sub-trace 7 and the second sub-trace 8 in the first trace section 10 is close to the charging rate of the first sub-trace 7 and the second sub-trace 8 in the first sub-scan line 5-1, which can improve the charging consistency of the top gate g1 and the bottom gate g2 of the first transistor T0 in different regions.

[0118] In this structure, although the first sub-line 7 in the first routing section 10 is not directly connected to the first shift register 12, the transmission path of the signal output by the first shift register 12 to the first sub-line 7 is still relatively short. Therefore, the signal voltage drop of the top gate g1 of the first transistor T0 in this partition will not be too large.

[0119] In one feasible implementation, see again ​ The width of the second sub-line 8 is greater than the width of the first sub-line 7.

[0120] Part of the second sub-wire 8 is multiplexed as the bottom gate g2 of the first transistor T0 and is located below the active layer ac of the first transistor T0. The wider the second sub-wire 8 is, the flatter the active layer ac of the first transistor T0 is, the more regular the transmission path of the carrier in the active layer ac is, and the fewer obstacles the carrier encounters when moving in the active layer ac. Therefore, designing the line width of the first sub-wire 7 to be larger helps to increase the conductive capacity of the first transistor T0, thereby realizing higher switching speed and lower power consumption.

[0121] In an available embodiment, referring to ​ , the pixel circuit 4 comprises a driving transistor T1.

[0122] The first transistor T0 comprises a threshold compensation transistor T2, which is electrically connected between the second electrode of the driving transistor T1 and the gate electrode of the driving transistor T1. The first scan line 5 comprises a threshold compensation scan line S2N electrically connected with the threshold compensation transistor T2.

[0123] And / or, the first transistor T0 comprises a gate reset transistor T3, which is electrically connected between the first reset line Ref1 and the gate electrode of the driving transistor T1. The first scan line 5 comprises a reset scan line S1N electrically connected with the gate reset transistor T3.

[0124] The threshold compensation transistor T2 and the gate reset transistor T3 are both electrically connected with the gate electrode of the driving transistor T1, so the off-state leakage of these two transistors has a greater impact on the gate potential of the driving transistor T1. Therefore, the embodiment of the present application designs the threshold compensation transistor T2 and / or the gate reset transistor T3 as a transistor structure with top-bottom double gates, which can effectively reduce the impact of the off-state leakage of these two transistors on the gate potential of the driving transistor T1, thereby ensuring the stability of the working state of the driving transistor T1.

[0125] In addition, referring to ​ , the pixel circuit 4 can further comprise:

[0126] A data writing transistor T4, the gate electrode of which is electrically connected with the writing scan line Sp, the first electrode of which is electrically connected with the data line Data, and the second electrode of which is electrically connected with the first electrode of the driving transistor T1.

[0127] A first light-emitting control transistor T5, the gate electrode of which is electrically connected with the light-emitting control scan line Emit, the first electrode of which is electrically connected with the power supply line PVDD, and the second electrode of which is electrically connected with the first electrode of the driving transistor T1.

[0128] The second light emitting control transistor T6 has its gate electrically connected to the light emitting control scan line Emit, its first electrode electrically connected to the second electrode of the driving transistor T1, and its second electrode electrically connected to the light emitting element 1616.

[0129] The anode reset transistor T7 has its gate electrically connected to the write scan line Sp, its first electrode electrically connected to the second reset line Ref2, and its second electrode electrically connected to the light emitting element 16.

[0130] The storage capacitor Cst has its first plate electrically connected to the power supply line PVDD and its second plate electrically connected to the gate of the driving transistor T1.

[0131] The bias transistor T8 has its gate electrically connected to the bias scan line Sp*, its first electrode electrically connected to the bias signal line DVH, and its second electrode electrically connected to the first electrode of the driving transistor T1.

[0132] The light emitting element 16 can be an Organic Light Emitting Diode (OLED), a Light Emitting Diode (LED), or other types of devices.

[0133] In one possible structure, referring to ​ The first transistor T0 includes the threshold compensation transistor T2 and the gate reset transistor T3. The threshold compensation transistor T2 is turned on in response to a high level provided by the threshold compensation scan line S2N and is turned off in response to a low level. The gate reset transistor T3 is turned on in response to a high level provided by the reset scan line S1N and is turned off in response to a low level.

[0134] The pixel circuit further includes a second transistor T0'. The active layer of the second transistor T0' includes a silicon semiconductor material. For example, the active layer of the second transistor T0' includes a low temperature poly silicon material, and the second transistor T0' is a Low Temperature Poly Silicon (LTPS) transistor.

[0135] The second transistor T0' includes at least one of the driving transistor T1, the data write transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, the anode reset transistor T7, and the bias transistor T8. The second transistor T0' is turned on in response to a low level provided by the scan line to which it is connected and is turned off in response to a high level.

[0136] The embodiments of the present application are described by taking the second transistor T0' as an example, which includes the driving transistor T1, the data write transistor T4, the first light emitting control transistor T5, the second light emitting control transistor T6, the anode reset transistor T7, and the bias transistor T8.

[0137] In combination ​ and ​ , the driving period of the pixel circuit 4 includes a writing frame F1 and a holding frame F2.

[0138] The writing frame F1 includes a first non-light emitting period t11 and a first light emitting period t21, wherein the first non-light emitting period t11 includes a reset period t1 and a charging period t2. In the reset period t1, the gate reset transistor T3 is turned on to reset the gate of the driving transistor T1. In the charging period t2, the threshold compensation transistor T2, the data writing transistor T4 and the anode reset transistor T7 are turned on, the driving transistor T1 is charged and threshold compensated by the threshold compensation transistor T2 and the data writing transistor T4, and the anode of the light emitting element 16 is reset by the anode reset transistor T7. In the first light emitting period t21, the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on to transmit the driving current converted by the driving transistor T1 to the light emitting element 16.

[0139] The holding frame F2 includes a second non-light emitting period t12 and a second light emitting period t22, wherein the second non-light emitting period t12 includes a bias adjustment period t3. In the bias adjustment period t3, the bias transistor T8 is turned on to adjust the bias state of the driving transistor T1. In the second light emitting period t22, the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on to transmit the driving current converted by the driving transistor T1 to the light emitting element 16.

[0140] It should be noted that the driving process of the pixel circuit described above is only illustrative. In other possible driving modes, the bias transistor T8 can also be turned on in the first non-light emitting period t11 of the writing frame F1, and the bias transistor T8 can be turned on once, twice or more times in the first non-light emitting period t11 and / or the second non-light emitting period t12.

[0141] Based on the above structure, as shown in ​ , the display panel provided by the embodiment of the present application has the film layer structure shown in ​ , which further includes a silicon semiconductor layer ss and a fourth metal layer M1. The fourth metal layer M1 is located on the side of the silicon semiconductor layer ss away from the substrate 1, and the second metal layer Mc is located on the side of the fourth metal layer M1 away from the substrate 1.

[0142] The silicon semiconductor layer ss includes the active layer ac' of the second transistor T0', and the fourth metal layer M1 includes the gate g' of the second transistor T0'. The active layer ac' of the second transistor T0' can be electrically connected to other transistors or other signal lines through a connecting lead 50, which is located on the third metal layer SD.

[0143] In addition, the display panel can further include a fifth metal layer M0 located between the silicon semiconductor layer ss and the substrate 1, the fifth metal layer M0 including a shielding metal 60, at least part of the shielding metal 60 overlapping with the channel of the active layer ac' of the second transistor T0' in a direction perpendicular to the plane where the substrate 1 is located, preventing external light from irradiating the channel of the second transistor T0' and affecting the characteristics of the second transistor T0'.

[0144] Based on the above circuit structure, as shown in ​ , ​ Another structure diagram of the display panel provided by the embodiment of the present application is shown in

[0145] The display panel further includes a second shift register 16 electrically connected to the write scan line Sp, a third shift register 17 electrically connected to the light-emitting control scan line Emit, and a fourth shift register 18 electrically connected to the bias scan line Sp*.

[0146] In one arrangement, the display panel includes two second shift registers 16, which are respectively located at opposite sides of the display area AA, and drive the write scan line Sp from both sides to improve the driving capability of the write scan line.

[0147] The display panel includes one first sub-shift register 12-1, one second sub-shift register 12-2, one third shift register 17, and one fourth shift register 18. Among them, two of the above four shift registers are located at one side of the display area AA, and the other two are located at the other side of the display area AA. The above four shift registers drive the scan lines connected thereto from one side.

[0148] In a feasible implementation, as shown in ​ and ​ , ​ Another structure diagram of the display panel provided by the embodiment of the present application is shown in ​ Another structure diagram of the display panel provided by the embodiment of the present application is shown in

[0149] The display panel further comprises a first shift register 12, the first shift register 12 comprising a plurality of first shift units 20 connected in cascade, wherein one first shift unit 20 is electrically connected with m second sub scanning lines 5-2 corresponding to the m circuit rows 19, m≥2, and m wiring parts 6 located on the same side of the light transmission hole 2 of the m second sub scanning lines 5-2 are connected to the same first wiring 9. That is, the first wiring 9 included in the m second sub scanning lines 5-2 is the same first wiring 9. In this way, the number of first wirings 9 required to be arranged in the second sub scanning lines 5-2 can be reduced, and the wiring space occupied by the first wirings 9 can be reduced.

[0150] In addition, the first shift register 12 further comprises a plurality of second shift units 21 connected in cascade, and one second shift unit 21 is electrically connected with the first sub scanning lines 5-1 corresponding to the m circuit rows 19.

[0151] Further, referring to ​ In the m second sub scanning lines 5-2 electrically connected with the same first shift unit 20, the m second sub scanning lines 5-2 all comprise first wiring parts 10, so that the loads of the m second sub scanning lines 5-2 tend to be consistent, and the consistency of the loads of different second sub scanning lines 5-2 is improved.

[0152] Further, referring to ​ In the m second sub scanning lines 5-2 electrically connected with the same first shift unit 20, the first wiring parts 10 of the m second sub scanning lines 5-2 overlap along the first direction x. That is, the first wiring parts 10 of the m second sub scanning lines 5-2 are all on the left side of the light transmission hole 2 or all on the right side of the light transmission hole 2. In this way, no matter whether the first shift register 12 is located on the side away from the light transmission hole 2 of the first wiring part 10 or on the side close to the light transmission hole 2 of the first wiring part 10, the flow directions of signals in the m second sub scanning lines 5-2 are consistent, and the difference in signal pressure drop at different positions in the m second sub scanning lines 5-2 can be weakened.

[0153] In an available implementation, referring to ​ The first wiring part 10 is connected with the first via hole 22 and the second via hole 23 respectively.

[0154] On the first side fd of the first wiring part 10, the first sub wiring 7 and the second sub wiring 8 are connected through the first via hole 22; on the second side sd of the first wiring part 10, one of the first sub wiring 7 and the second sub wiring 8 is connected with the second via hole 23, and the other is not connected with the second via hole 23, so as to realize the disconnection of the first sub wiring 7 and the second sub wiring 8 on the second side sd. The signal in the first sub wiring 7 cannot be directly transmitted to the second sub wiring 8 through the second via hole 23 on the second side, or the signal in the second sub wiring 8 cannot be directly transmitted to the first sub wiring 7 through the second via hole 23 on the second side.

[0155] In one possible implementation, as shown in ​ ​ FIG. 5 is a schematic view of a structure of a second sub-scan line 5-2 provided by an embodiment of the present application, ​ ​ FIG. 6 is a sectional view along the direction of B1-B2, the first sub-wire 7 is located on the first metal layer MG, and the second sub-wire 8 is located on the second metal layer Mc, the first metal layer MG is located on the side of the second metal layer Mc away from the substrate 1. For example, the first metal layer MG is located on the side of the oxide semiconductor layer oxy away from the substrate 1, and the second metal layer Mc is located on the side of the oxide semiconductor layer oxy close to the substrate 1. ​ ​ FIG. 7 is another schematic view of a structure of the second sub-scan line 5-2 provided by an embodiment of the present application, ​ FIG. 8 is a sectional view along the direction of C1-C2, the first sub-wire 7 is located on the first metal layer MG, and the second sub-wire 8 is located on the second metal layer Mc, the first metal layer MG is located on the side of the second metal layer Mc away from the substrate 1. For example, the first metal layer MG is located on the side of the oxide semiconductor layer oxy away from the substrate 1, and the second metal layer Mc is located on the side of the oxide semiconductor layer oxy close to the substrate 1.

[0156] The display panel includes a first connecting part 24 and a second connecting part 25, the first connecting part 24 and the second connecting part 25 are located on the third metal layer SD, and the third metal layer SD is located on the side of the first metal layer MG away from the substrate 1.

[0157] Among them, at least one insulating layer 26 is arranged between the third metal layer SD and the first metal layer MG, and at least two insulating layers 26 are arranged between the third metal layer SD and the second metal layer Mc.

[0158] The first via hole 22 and the second via hole 23 each include a first sub-via hole 27 and a second sub-via hole 28, the first sub-via hole 27 penetrates the insulating layer 26 between the third metal layer SD and the first metal layer MG, and the second sub-via hole 28 penetrates the insulating layer 26 between the third metal layer SD and the second metal layer Mc.

[0159] ​ Referring to , on the first side fd of the first wire part 10, the first connecting part 24 is electrically connected with the first sub-wire 7 through the first sub-via hole 27 in the first via hole 22, and the first connecting part 24 is also electrically connected with the second sub-wire 8 through the second sub-via hole 28 in the first via hole 22.

[0160] ​ That is, referring to ​ ​​​​On the first side fd of the first wiring portion 10, the first connection portion 24 overlaps both the first sub-via 27 and the second sub-via 28 in the first via 22 in the direction perpendicular to the plane in which the substrate 1 lies, the first sub-wire 7 in the first wiring portion 10 overlaps the first sub-via 27 in the first via 22, and further, the first sub-wire 7 is connected to the first connection portion 24 through the first sub-via 27, and the second sub-wire 8 in the first wiring portion 10 overlaps the second sub-via 28 in the first via 22, and further, the second sub-wire 8 is connected to the first connection portion 24 through the second sub-via 28.

[0161] Referring to ​ and ​ On the second side sd of the first wiring portion 10, the second connection portion 25 is electrically connected to the first sub-wire 7 through the first sub-via 27 in the second via 23, and the second connection portion 25 is also connected to the second sub-via 28 in the second via 23, and in the direction perpendicular to the plane in which the substrate 1 lies, the second sub-wire 8 has a gap with the second sub-via 28 in the second via 23.

[0162] That is, on the second side sd of the first wiring portion 10, the second connection portion 25 overlaps both the first sub-via 27 and the second sub-via 28 in the second via 23 in the direction perpendicular to the plane in which the substrate 1 lies, the first sub-wire 7 in the first wiring portion 10 overlaps the first sub-via 27 in the second via 23, and further, the first sub-wire 7 is connected to the second connection portion 25 through the first sub-via 27, and the second sub-wire 8 in the first wiring portion 10 does not overlap the second sub-via 28 in the second via 23, and there is a gap between the projection of the second sub-wire 8 in the first wiring portion 10 and the projection of the second sub-via 28 in the second via 23, the second sub-wire 8 is not connected to the second sub-via 28, and further, the second sub-wire 8 is not connected to the second connection portion 25.

[0163] Alternatively, referring to ​ and ​ On the second side sd of the first wiring portion 10, the second connection portion 25 is electrically connected to the second sub-wire 8 through the second sub-via 28 in the second via 23, and the second connection portion 25 is also connected to the first sub-via 27 in the second via 23, and in the direction perpendicular to the plane in which the substrate 1 lies, the first sub-wire 7 has a gap with the first sub-via 27 in the second via 23.

[0164] That is, on the second side sd of the first trace portion 10, in the direction perpendicular to the plane of the substrate 1, the second connection portion 25 overlaps with the first sub-via 27 and the second sub-via 28 in the second via 23. The second sub-trace 8 in the first trace portion 10 overlaps with the second sub-via 28 in the second via 23, and is connected to the second connection portion 25 through the second sub-via 28. The first sub-trace 7 in the first trace portion 10 does not overlap with the first sub-via 27 in the second via 23. There is a gap between the projection of the first sub-trace 7 in the first trace portion 10 and the projection of the first sub-via 27 in the second via 23. The first sub-trace 7 is not connected to the first sub-via 27, and therefore the first sub-trace 7 is not connected to the second connection portion 25.

[0165] In the above structure, the first sub-line 7 and the second sub-line 8 are connected by a transition metal (first connecting part 24 and second connecting part 25).

[0166] When the second sub-scan line 5-2 is used ​ In the design concept of the structure shown, on the first side fd of the first routing portion 10, the first connecting portion 24 is electrically connected to the first sub-route 7 through the first sub-via 27 in the first via 22, and electrically connected to the second sub-route 8 through the second sub-via 28 in the first via 22. On the second side sd of the first routing portion 10, the second connecting portion 25 is electrically connected to the first sub-route 7 through the first sub-via 27 in the second via 23, and electrically connected to the second sub-route 8 through the second sub-via 28 in the second via 23. Therefore, both the first side fd and the second side sd have mask patterns for the connecting portions and mask patterns for the sub-vias.

[0167] When the second sub-scan line 5-2 is used ​ and ​ In the design concept, although there is no connection between the first sub-trace 7 and the second sub-trace 8 on the second side SD of the first trace portion 10, the second connecting portion 25 and the second via 23 connected by the second connecting portion 25 are still retained on the second side SD. In this way, it is not necessary to readjust the mask pattern of the third metal layer SD, nor is it necessary to readjust the mask pattern of the second via 23, and there is no need to replace the mask, thus saving process costs. Moreover, retaining the second connecting portion 25 and the second via 23 on the second side SD can also make the overall distribution of the connecting portion and the via more uniform, resulting in a better layout design.

[0168] Alternatively, in another feasible implementation, such as ​ As shown, ​ This is a schematic diagram of another structure of the second sub-scan line 5-2 provided in an embodiment of the present invention. ​ for ​ A sectional view along the D1-D2 direction.​ Fig. 5-2 is a schematic view of another structure of the second sub scanning line 5-2 provided in an embodiment of the present application, ​ Fig. 5-3 is a schematic view of another structure of the second sub scanning line 5-2 provided in an embodiment of the present application, ​ Fig. 5-4 is a schematic view of a cross section along the direction of E1-E2, the first sub trace 7 is located in the first metal layer MG, the second sub trace 8 is located in the second metal layer Mc, the first metal layer MG is located on the side of the second metal layer Mc away from the substrate 1. For example, the first metal layer MG is located on the side of the oxide semiconductor layer oxy away from the substrate 1, and the second metal layer Mc is located on the side of the oxide semiconductor layer oxy close to the substrate 1. There is at least one insulating layer 26 between the first metal layer MG and the second metal layer Mc.

[0169] Fig. 5-5 is a schematic view of a cross section along the direction of E1-E2, the first via 22 and the second via 23 both penetrate the insulating layer 26 between the first metal layer MG and the second metal layer Mc.

[0170] Fig. 5-6 is a schematic view of a cross section along the direction of E1-E2, the first sub trace 7 is connected to the second via 23 on the second side sd of the first trace portion 10, and there is a gap between the second sub trace 8 and the second via 23 in the direction perpendicular to the plane on which the substrate 1 is located. ​ ​ Fig. 5-7 is a schematic view of a cross section along the direction of E1-E2, the second sub trace 8 is connected to the second via 23 on the second side sd of the first trace portion 10, and there is a gap between the first sub trace 7 and the second via 23 in the direction perpendicular to the plane on which the substrate 1 is located.

[0171] That is, on the second side sd of the first trace portion 10, the first sub trace 7 in the first trace portion 10 overlaps and is connected to the second via 23 in the direction perpendicular to the plane on which the substrate 1 is located, but the second sub trace 8 in the first trace portion 10 does not overlap the second via 23, and there is a gap between the projection of the second sub trace 8 in the first trace portion 10 and the projection of the second via 23, and the second sub trace 8 is not connected to the first sub trace 7 via the second via 23.

[0172] Fig. 5-8 is a schematic view of a cross section along the direction of E1-E2, the second sub trace 8 is connected to the second via 23 on the second side sd of the first trace portion 10, and there is a gap between the first sub trace 7 and the second via 23 in the direction perpendicular to the plane on which the substrate 1 is located. ​ ​ That is, on the second side sd of the first trace portion 10, the second sub trace 8 in the first trace portion 10 overlaps the second via 23 in the direction perpendicular to the plane on which the substrate 1 is located, but the first sub trace 7 in the first trace portion 10 does not overlap the second via 23, and there is a gap between the projection of the first sub trace 7 in the first trace portion 10 and the projection of the second via 23, and the first sub trace 7 is not connected to the second sub trace 8 via the second via 23.

[0173]

[0174] Fig. 5-9 is a schematic view of another structure of the second sub scanning line 5-2 provided in an embodiment of the present application, ​ ​​​In the design concept of the structure shown, on the first side (fd) of the first routing section 10, the first sub-routes 7 and 8 are electrically connected through a first via 22. On the second side (sd) of the first routing section 10, the first sub-routes 7 and 8 are electrically connected through a second via 23. Therefore, via mask patterns exist on both the first side (fd) and the second side (sd).

[0175] When the second sub-scan line 5-2 is used ​ and ​ In the design scheme, although there is no connection between the first sub-trace 7 and the second sub-trace 8 on the second side SD of the first routing section 10, a second via 23 is still retained on the second side SD. In this way, the mask pattern of the via does not need to be readjusted, and the mask plate does not need to be replaced, saving process costs. Moreover, retaining the second via 23 on the second side SD can also make the overall distribution of vias more uniform and the layout design more optimized.

[0176] Furthermore, such as ​ As shown, ​ This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention. ​ for ​ A sectional view along the F1-F2 direction. ​ This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention. ​ for ​ A cross-sectional view along the G1-G2 direction shows that the display panel includes a first shift register 12, which is electrically connected to a second sub-scan line 5-2. The first shift register 12 is located on the side of the first trace portion 10 in the second sub-scan line 5-2 away from the light-transmitting hole 2.

[0177] The first shift register 12 is electrically connected to the first wiring section 10 via a first connection line 15, the first connection line 15 including a first sub-connection line 29.

[0178] See ​ and ​ On the second side sd of the first trace portion 10, the second via 23 is connected to the first sub-trace 7, and the first sub-connection line 29 is located in the second metal layer Mc, with the first sub-line connected to the second via 23. Alternatively, see... ​ and ​ On the second side SD of the first trace portion 10, the second via 23 is connected to the second sub-trace 8, and the first sub-connection line 29 is located in the first metal layer MG, and the first sub-line is connected to the second via 23.

[0179] In the arrangement, the second via hole 23 is reused as a connection via hole between the first shift register 12 and the second sub scanning line 5-2, which can not only realize reasonable use of the second via hole 23, but also prevent other wires from being deposited in the second via hole 23 and causing short circuit with the second sub scanning line 5-2.

[0180] Alternatively, in combination with ​ As shown in ​ , ​ is another structural schematic diagram of the display panel provided by the embodiment of the application, ​ is ​ a sectional view along the H1-H2 direction, ​ is another structural schematic diagram of the display panel provided by the embodiment of the application, ​ is ​ a sectional view along the I1-I2 direction, the display area AA includes a plurality of circuit rows 19 arranged along a first direction x, and each circuit row 19 includes a plurality of pixel circuits 4 arranged along a second direction y.

[0181] The display panel further includes a first shift register 12, and the first shift register 12 includes a plurality of first shift units 20 connected in cascade, wherein one first shift unit 20 is electrically connected with the second sub scanning line 5-2 corresponding to m circuit rows 19, m≥2, and the m second sub scanning lines 5-2 are connected by a second connection line 30.

[0182] Referring to ​ and ​ , the second via hole 23 is connected with the second sub wire 8 on the second side sd of the first wire part 10, the second connection line 30 is located on the first metal layer MG, and the second connection line 30 is connected with the second via hole 23. Alternatively, referring to ​ and ​ , the second via hole 23 is connected with the first sub wire 7 on the second side sd of the first wire part 10, the second connection line 30 is located on the second metal layer Mc, and the second connection line 30 is connected with the second via hole 23.

[0183] When one first shift unit 20 is electrically connected with the m second sub scanning lines 5-2, the m second sub scanning lines 5-2 are connected together by the second connection line 30, and the above arrangement is to reuse the second via hole 23 as a connection via hole between the second sub scanning line 5-2 and the second connection line 30, which can not only realize reasonable use of the second via hole 23, but also prevent other wires from being deposited in the second via hole 23 and causing short circuit with the second sub scanning line 5-2.

[0184] In a feasible implementation, referring again to ​ and ​In the second sub-scan line 5-2, the wire portion 6 further includes a second wire portion 31. In the second wire portion 31, the first sub-wire 7 and the second sub-wire 8 pass through the sub-area 3 in the second direction y, and the first sub-wire 7 and the second sub-wire 8 are connected at both ends.

[0185] If all the wire portions 6 in the second sub-scan line 5-2 are designed as the first wire portion 10, the overall load of the second sub-scan line 5-2 may be too large, which may increase the load difference between the second sub-scan line 5-2 and the first sub-scan line 5-1. By designing part of the wire portions 6 in the second sub-scan line 5-2 as the first wire portion 10 and part of the wire portions 6 as the second wire portion 31, the load of the second sub-scan line 5-2 can be improved within a reasonable range, so as to better weaken the load difference between the second sub-scan line 5-2 and the first sub-scan line 5-1.

[0186] Further, as shown in ​ and ​ , a structure diagram of another display panel provided by the embodiment of the present application is shown in ​ , and ​ a structure diagram of another display panel provided by the embodiment of the present application is shown in

[0187] In the second sub-scan line 5-2, the wire portion 6 further includes a second wire portion 31. In the second wire portion 31, the first sub-wire 7 and the second sub-wire 8 pass through the sub-area 3 in the second direction y, and the first sub-wire 7 and the second sub-wire 8 are connected at both ends.

[0188] The first shift register 12 drives the second sub-scan line 5-2 unilaterally. Since the first sub-wire 7 and the second sub-wire 8 in the first wire portion 10 are connected only on one side, the overall load of the first wire portion 10 is larger, and connecting the first shift register 12 with the first wire portion 10 can weaken the signal pressure drop difference on the wire portions 6 on both sides of the light transmission hole 2, and further weaken the display difference of the sub-areas 3 on both sides of the light transmission hole 2.

[0189] Alternatively, as shown in ​ and ​ , a structure diagram of another display panel provided by the embodiment of the present application is shown in ​ , and ​ a structure diagram of another display panel provided by the embodiment of the present application is shown in

[0190] In a feasible implementation, the first winding 9 is connected with the first sub-wiring 7 or the second sub-wiring 8, and the first winding 9 is arranged in the same layer as the first sub-wiring 7 or the second sub-wiring 8 connected with the first winding 9. For example, referring to ​ , the first winding 9 is connected with the second sub-wiring 8 and arranged in the same layer as the second sub-wiring 8, or referring to ​ , the first winding 9 is connected with the first sub-wiring 7 and arranged in the same layer as the first sub-wiring 7.

[0191] The first winding 9 is arranged in the same layer as the first sub-wiring 7 or the second sub-wiring 8 connected with the first winding 9, and the first winding 9 and the wriing part 6 do not need to be connected by punching, so that the wiring is simpler.

[0192] In a feasible implementation, as shown in ​ , as shown in ​ , another structure diagram of the second sub-scan line 5-2 provided by the embodiment of the present application is shown, the first winding 9 is arranged in different layers from at least one of the first sub-wiring 7 and the second sub-wiring 8. For example, the first winding 9 can be arranged in the third metal layer SD, or the first winding can also be arranged in the fourth metal layer M1 or the fifth metal layer M0.

[0193] In the above structure, according to the wiring condition in the area where the first winding 9 is arranged, other metal layers can be selected to arrange the first winding 9, and the wiring position of the first winding 9 is more flexible.

[0194] In addition, it also needs to be explained that the first winding 9 in the embodiment of the present application can be arranged around the light-transmitting hole 2 in the second non-display area NAA2 as shown in ​ , or as shown in ​ , as shown in ​ , another structure diagram of the display panel provided by the embodiment of the present application is shown, at least part of the first winding 9 can also be arranged around the light-transmitting hole 2 in the first display area AA1.

[0195] Based on the same inventive concept, the embodiment of the present application also provides a display device, as shown in ​ , as shown in ​ , a structure diagram of the display device provided by the embodiment of the present application is shown, the display device includes the display panel 100. Of course, ​ , the display device shown is only for illustrative purposes, and the display device can be any electronic device with display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic paper or a television.

[0196] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0197] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the same. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent replacements for some or all of the technical features therein. Such modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate; a display area comprising a first display area and a second display area arranged along a first direction, the second display area comprising a light-transmitting hole and a sub-area arranged along a second direction, opposite sides of the light-transmitting hole comprising the sub-area, the first direction intersecting the second direction; the display area comprising a pixel circuit; a first scan line at least partially located in the display area and electrically connected to the pixel circuit, the first scan line comprising at least one wire portion, the wire portion comprising a first sub-wire and a second sub-wire electrically connected, in a direction perpendicular to a plane in which the substrate is located, the first sub-wire and the second sub-wire in the same wire portion at least partially overlapping; the first scan line comprising a first sub-scan line and a second sub-scan line, the first sub-scan line being at least partially located in the first display area, the second sub-scan line being at least partially located in the second display area; wherein the first sub-scan line comprises one wire portion, the first sub-wire and the second sub-wire in the same wire portion penetrating the first display area along the second direction, and the first sub-wire and the second sub-wire being connected at both ends; the second sub-scan line comprising at least two wire portions, the second sub-scan line further comprising a first wire loop surrounding the light-transmitting hole, in the same second sub-scan line, one wire portion corresponding to one sub-area, the two wire portions on both sides of the light-transmitting hole being connected through the first wire loop; and the wire portion in at least one second sub-scan line comprising a first wire portion, the first wire portion comprising a first side and a second side opposite in the second direction, the first sub-wire and the second sub-wire in the first wire portion being connected at the first side and not connected at the second side.

2. The display panel of claim 1, wherein the first side is a side of the first wire portion close to the light-transmitting hole.

3. The display panel of claim 1, wherein the first side is a side of the first wire portion away from the light-transmitting hole.

4. The display panel of claim 1, wherein the pixel circuit comprises a first transistor, an active layer of the first transistor comprising an oxide semiconductor material, a gate of the first transistor being electrically connected to the first scan line; wherein the gate of the first transistor comprises a top gate and a bottom gate, the top gate being located in a first metal layer, the bottom gate being located in a second metal layer; the first metal layer being located on a side of the active layer away from the substrate, the second metal layer being located on a side of the active layer close to the substrate; in the first scan line, the first sub-wire is located in the first metal layer and is partially multiplexed as the top gate, and the second sub-wire is located in the second metal layer and is partially multiplexed as the bottom gate.

5. The display panel of claim 4, wherein the first side is a side of the first wire portion close to the light-transmitting hole. The display panel further comprises a first shift register, the first shift register is electrically connected with the second sub scanning line, the first shift register is located at a side of the first sub wiring part of the second sub scanning line away from the light transmission hole, and in the first wiring part, the second sub wiring is connected with the first shift register through the first sub wiring.

6. The display panel of claim 4, wherein, the first side is a side of the first wiring part close to the light transmission hole; The display panel further comprises a first shift register, the first shift register is electrically connected with the second sub scanning line, the first shift register is located at a side of the first sub wiring part of the second sub scanning line away from the light transmission hole, and in the first wiring part, the first sub wiring is connected with the first shift register through the second sub wiring.

7. The display panel of claim 4, wherein, the line width of the second sub wiring is greater than the line width of the first sub wiring.

8. The display panel of claim 4, wherein, the pixel circuit comprises a drive transistor; the first transistor comprises a threshold compensation transistor, the threshold compensation transistor is electrically connected between the second electrode of the drive transistor and the gate electrode of the drive transistor, the first scanning line comprises a threshold compensation scanning line electrically connected with the threshold compensation transistor; and / or, the first transistor comprises a gate reset transistor, the gate reset transistor is electrically connected between a first reset line and the gate electrode of the drive transistor, the first scanning line comprises a reset scanning line electrically connected with the gate reset transistor.

9. The display panel of claim 1, wherein, the display area comprises a plurality of circuit rows arranged along the first direction, the circuit rows comprise a plurality of pixel circuits arranged along the second direction; The display panel further comprises a first shift register, the first shift register comprises a plurality of first shift units connected in cascade, wherein one of the first shift units is electrically connected with the second sub scanning lines corresponding to m circuit rows, m≥2, and m wiring parts located on the same side of the light transmission hole of the m second sub scanning lines are connected to the same first wiring.

10. The display panel of claim 9, wherein, the first wiring part is located on the same side of the light transmission hole of the m second sub scanning lines.

11. The display panel of claim 10, wherein, the first wiring parts of the m second sub scanning lines overlap along the first direction.

12. The display panel of claim 1, wherein, the first wiring part is connected with a first via and a second via respectively; on the first side of the first wiring part, the first sub wiring and the second sub wiring are connected through the first via, and on the second side of the first wiring part, one of the first sub wiring and the second sub wiring is connected with the second via, and the other is not connected with the second via.

13. The display panel of claim 12, wherein, the first sub-wire is located at a first metal layer, and the second sub-wire is located at a second metal layer, the first metal layer being located at a side of the second metal layer away from the substrate; the display panel comprises a first connecting part and a second connecting part, the first connecting part and the second connecting part being located at a third metal layer, the third metal layer being located at a side of the first metal layer away from the substrate; the first via and the second via each comprise a first sub-via and a second sub-via, the first sub-via penetrating an insulating layer between the third metal layer and the first metal layer, and the second sub-via penetrating the insulating layer between the third metal layer and the second metal layer; on the first side of the first wire part, the first connecting part is electrically connected with the first sub-wire through the first sub-via in the first via, and the first connecting part is also electrically connected with the second sub-wire through the second sub-via in the first via; on the second side of the first wire part, the second connecting part is electrically connected with the first sub-wire through the first sub-via in the second via, and the second connecting part is also connected with the second sub-via in the second via, and in a direction perpendicular to a plane where the substrate is located, the second sub-wire has a spacing with the second sub-via in the second via; or, on the second side of the first wire part, the second connecting part is electrically connected with the second sub-wire through the second sub-via in the second via, and the second connecting part is also connected with the first sub-via in the second via, and in a direction perpendicular to a plane where the substrate is located, the first sub-wire has a spacing with the first sub-via in the second via.

14. The display panel of claim 12, wherein, the first sub-wire is located at a first metal layer, and the second sub-wire is located at a second metal layer, the first metal layer being located at a side of the second metal layer away from the substrate; the first via and the second via each penetrate an insulating layer between the first metal layer and the second metal layer; on the second side of the first wire part, the first sub-wire is connected with the second via, and in a direction perpendicular to a plane where the substrate is located, the second sub-wire has a spacing with the second via; or, on the second side of the first wire part, the second sub-wire is connected with the second via, and in a direction perpendicular to a plane where the substrate is located, the first sub-wire has a spacing with the second via.

15. The display panel of claim 14, wherein, the display panel comprises a first shift register, the first shift register being electrically connected with the second sub-scan line, and the first shift register being located at a side of the first wire part away from the light-transmitting hole in the second sub-scan line; the first shift register is electrically connected with the first wire part through a first connecting line, and the first connecting line comprises a first sub-connecting line. In the second side of the first wiring part, the second via hole is connected with the second sub-wiring, and the second connection line is located in the first metal layer and connected with the second via hole. Alternatively, in the second side of the first wiring part, the second via hole is connected with the first sub-wiring, and the second connection line is located in the second metal layer and connected with the second via hole.

16. The display panel of claim 14, wherein, the display area comprises a plurality of circuit rows arranged along the first direction, and each circuit row comprises a plurality of pixel circuits arranged along the second direction; the display panel further comprises a first shift register comprising a plurality of first shift units connected in cascade, wherein one first shift unit is connected with the second sub-scanning lines corresponding to m circuit rows, and m is greater than or equal to 2, and the second sub-scanning lines are connected by a second connection line; In the second side of the first wiring part, the second via hole is connected with the second sub-wiring, and the second connection line is located in the first metal layer and connected with the second via hole. Alternatively, in the second side of the first wiring part, the second via hole is connected with the first sub-wiring, and the second connection line is located in the second metal layer and connected with the second via hole.

17. The display panel of claim 1, wherein, in the second sub-scanning line, the wiring part further comprises a second wiring part; in the second wiring part, the first sub-wiring and the second sub-wiring penetrate the sub-area along the second direction, and the first sub-wiring and the second sub-wiring are connected at both ends.

18. The display panel of claim 17, wherein, the display panel further comprises a first shift register connected with the second sub-scanning line, and the first shift register is located on the side of the second wiring part away from the first wiring part in the second sub-scanning line and connected with the first wiring part.

19. The display panel of claim 17, wherein, the display panel further comprises a first shift register connected with the second sub-scanning line, and the first shift register is located on the side of the second wiring part away from the first wiring part in the second sub-scanning line and connected with the second wiring part.

20. The display panel of claim 1, wherein, the first winding is connected with the first sub-wiring or the second sub-wiring, and the first sub-wiring or the second sub-wiring connected with the first winding is arranged in the same layer.

21. The display panel of claim 1, wherein, the first winding is arranged in a different layer from at least one of the first sub-wiring and the second sub-wiring.

22. A display device comprising: The display panel as claimed in any one of claims 1-21.

Images