Instruction awakening module applied to processor, processor, equipment and method

Abstract

The invention discloses an instruction awakening module applied to a processor, the processor, equipment and a method, and relates to the technical field of chips. The first reservation unit is used for obtaining first indication information according to a first loading instruction in the first storage unit, and the first indication information is used for indicating a target register of the first loading instruction; the second reservation unit is used for determining at least one associated instruction matched with the first indication information in the second storage unit according to the first indication information in the process that the first loading instruction reaches the address generation unit from the first reservation unit; the first loading unit is used for loading the first loading instruction; the second loading unit is used for executing the at least one associated instruction under the condition that the first loading instruction is successfully loaded. According to the instruction wakeup scheme provided by the invention, two clock cycles are advanced, the staying time of the associated instruction in the second retention unit is shortened, and the performance of the instruction wakeup module of the processor is improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to an instruction wake-up module, processor, device and method applied to a processor. Background Art

[0002] Wake-up is a key operation of the transmit component in the processor. When an instruction enters the transmit queue, also known as the reservation station (RS), it will determine whether all its source operand registers are ready. If ready, its ready bit will be marked as 1. If not ready, it needs to be woken up by the instruction it depends on.

[0003] In the related technology, after the load instruction enters the RS, it needs to go through the wake-up operation, arbitration selection operation, read instruction additional information (payload read) operation, and read the physical register group (regfileread) operation, and then enter the load pipeline to perform data loading operations: address generation operation, virtual-to-real address conversion operation, and data cache reading operation. In the case of a load instruction cache hit, other instructions are woken up and finally read data is obtained.

[0004] However, in the above method, the time node when the load instruction wakes up other instructions is at a relatively late position in the pipeline when reading the data cache operation. Other instructions that depend on the load instruction need to stay in the RS for a long time, and the wake-up efficiency is low. Summary of the invention

[0005] The embodiment of the present application provides an instruction wake-up module, processor, device and method applied to a processor. The technical solution is as follows:

[0006] According to one aspect of an embodiment of the present application, an instruction wake-up module applied to a processor is provided, the instruction wake-up module comprising: a data retention unit and a data loading unit; the data retention unit comprises a first retention unit and a second retention unit; the data loading unit comprises a first loading unit matched with the first retention unit, and a second loading unit matched with the second retention unit; the first retention unit comprises a first storage unit, and the second retention unit comprises a second storage unit; the first loading unit comprises an address generation unit, an address conversion unit and a data reading unit;

[0007] The first retaining unit is used to obtain first indication information according to the first load instruction in the first storage unit, the first indication information is used to indicate the target register of the first load instruction, and the first load instruction is used to load data in the external memory into the target register;

[0008] The second reservation unit is used to determine, in a process in which the first load instruction reaches the address generation unit from the first reservation unit, according to the first indication information, at least one associated instruction in the second storage unit that matches the first indication information, wherein the associated instruction is an instruction executed based on the data in the target register;

[0009] The first loading unit is used to load the first loading instruction;

[0010] The second loading unit is used to execute the at least one associated instruction when the first loading instruction is loaded successfully.

[0011] According to one aspect of an embodiment of the present application, a processor is provided, wherein the processor includes the instruction wake-up module as described above.

[0012] According to one aspect of an embodiment of the present application, a computer device is provided, the computer device comprising a processor, and the processor comprising the instruction wake-up module as described above.

[0013] According to one aspect of an embodiment of the present application, a command wake-up method applied to a command wake-up module is provided, wherein the command wake-up module comprises: a data retention unit and a data loading unit; the data retention unit comprises a first retention unit and a second retention unit; the data loading unit comprises a first loading unit matching the first retention unit, and a second loading unit matching the second retention unit; the first retention unit comprises a first storage unit, and the second retention unit comprises a second storage unit; the first loading unit comprises an address generation unit, an address conversion unit and a data reading unit; the method comprises:

[0014] The first retaining unit obtains first indication information according to the first load instruction in the first storage unit, where the first indication information is used to indicate a target register of the first load instruction, and the first load instruction is used to load data in the external memory into the target register;

[0015] The second reservation unit determines, according to the first indication information, at least one associated instruction in the second storage unit that matches the first indication information when the first load instruction arrives at the address generation unit from the first reservation unit, wherein the associated instruction is an instruction executed based on the data in the target register;

[0016] The first loading unit loads the first loading instruction;

[0017] The second loading unit executes the at least one associated instruction when the first loading instruction is loaded successfully.

[0018] The technical solution provided in the embodiments of the present application can bring the following beneficial effects:

[0019] By determining at least one associated instruction matching the first indication information in the second storage unit during the process of the first load instruction reaching the address generation unit from the first reservation unit, and waking up at least the associated instruction when the first load instruction reaches the address generation unit, the associated instruction in the second storage unit can be awakened at the front position of the loading pipeline of the first load instruction. Compared with the related art in which the associated instruction is awakened when the first load instruction reaches the data reading unit, the instruction awakening scheme proposed in the present application is advanced by two clock cycles, shortens the time that the associated instruction stays in the second reservation unit, speeds up the efficiency of the instruction awakening, and thus improves the performance of the instruction awakening module of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of an instruction wake-up module applied to a processor provided by the related art;

[0021] Figure 2 is a schematic diagram of an instruction wake-up module applied to a processor provided by an embodiment of the present application;

[0022] Figure 3 It is a schematic diagram of a pipeline process of instruction wake-up provided by an embodiment of the present application;

[0023] Figure 4 It is a structural diagram of a command wake-up module provided by an embodiment of the present application;

[0024] Figure 5 It is a schematic diagram of generating encoding information of a load instruction provided by an embodiment of the present application;

[0025] Figure 6 is a schematic diagram of a process for determining joint coding information provided by an embodiment of the present application;

[0026] Figure 7 It is a schematic diagram of a command wake-up process of a command wake-up module provided by an embodiment of the present application;

[0027] Figure 8 This is a flowchart of a command wake-up method applied to a command wake-up module provided by an embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0029] Artificial Intelligence (AI) is the theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a comprehensive technology in computer science that attempts to understand the essence of intelligence and produce a new intelligent machine that can respond in a similar way to human intelligence. Artificial intelligence is to study the design principles and implementation methods of various intelligent machines so that machines have the functions of perception, reasoning and decision-making.

[0030] Artificial intelligence technology is a comprehensive discipline that covers a wide range of fields, including both hardware-level and software-level technologies. Basic artificial intelligence technologies generally include sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technology, pre-trained model technology, operation / interaction systems, mechatronics, etc. Among them, pre-trained models are also called large models and basic models. After fine-tuning, they can be widely used in downstream tasks in various major directions of artificial intelligence. Artificial intelligence software technology mainly includes computer vision technology, speech processing technology, natural language processing technology, and machine learning / deep learning.

[0031] With the research and progress of artificial intelligence technology, artificial intelligence technology has been studied and applied in many fields, such as common smart homes, smart wearable devices, virtual assistants, smart speakers, smart marketing, driverless cars, autonomous driving, drones, digital twins, virtual humans, robots, artificial intelligence generated content (Artificial Intelligence Generated Content, AIGC), conversational interaction, smart medical care, smart customer service, game AI, virtual reality (Virtual Reality, VR), augmented reality (Augmented Reality, AR), etc. It is believed that with the development of technology, artificial intelligence technology will be applied in more fields and play an increasingly important role.

[0032] The technical solution of this application mainly relates to the development and design of AI processors in artificial intelligence technology, and mainly to instruction wake-up modules applied to processors.

[0033] When the instruction to be awakened is located in the reservation station (RS) of the processor, it will determine whether the source register of each instruction to be awakened is in the ready state, that is, whether data is written in the source register of each instruction to be awakened. If the source register of a certain instruction to be awakened is in the ready state, it means that the instruction to be awakened has been awakened, and the awakened instruction can be marked as ready state, indicating that the awakened instruction has the execution conditions. If the source register of the instruction to be awakened is in the unready state, it means that the instruction to be awakened has not been awakened.

[0034] The source register of the wake-up instruction is the target register of another load instruction, so whether the wake-up instruction is awakened depends on whether the load instruction it depends on is loaded. If the load instruction is loaded successfully, the load instruction has loaded the data into the target register, indicating that the wake-up instruction can read data from the target register (that is, the source register of the wake-up instruction), that is, the wake-up instruction is awakened. If the load instruction fails to load, the source register of the wake-up instruction is in the unready state, and the wake-up instruction is not awakened.

[0035] The load instruction is an instruction for loading data in the external memory into the target register, and the wake-up instruction is an instruction for reading data from the target register for execution.

[0036] For example, the load instruction is LOAD X2, [SP], and the wake-up instruction is ADD X3, X2, 1. The LOAD instruction is used to load data from the external memory into the X2 register, and the ADD instruction is used to add 1 to the data in the X2 register and write it to the X3 register. Therefore, the ADD instruction has a data dependency on the LOAD instruction. If the ADD instruction has not been loaded before entering the RS, that is, the X2 register is not ready, then the source register of the ADD instruction needs to be marked as notready. When the LOAD instruction is loaded, the LOAD instruction will wake up all related instructions in the RS and mark the source register state of the ADD instruction as ready. After that, the ADD instruction has the execution conditions and can be executed.

[0037] There are many ways to wake up: one is normal wakeup, that is, the associated instructions can only be woken up after the load instruction is loaded. Due to the long pipeline length in the processor, waking up after the load instruction is loaded will generate a large number of instruction bubbles, affecting the processor performance. The other is fast wakeup, which can wake up the subsequent associated instructions in advance according to the loading delay of the load instruction. For single-cycle execution instructions such as addition, other instructions can be woken up after the ADD instruction is selected in RS, so that back-to-back execution of related instructions can be achieved. However, for load instructions, the loading pipeline is long, and how to perform subsequent wake-up operations needs to be considered carefully.

[0038] In the related art, reference can be made to Figure 1 The schematic diagram of the instruction wake-up module shown in the figure includes a first reservation unit, a first loading unit, a second reservation unit and a second loading unit. Among them, the first reservation unit is used to store the load instruction, and the first reservation unit includes a first storage unit, a first selection unit, a first instruction reading unit and a first register reading unit. After the load instruction is awakened from the first storage unit (wakeup), the load instruction is called out (select) through the first selection unit, the additional information of the load instruction is read through the first instruction reading unit (payloadread), and the target register in the load instruction is read through the first register reading unit. The first loading unit is used to load the load instruction, and the first loading unit includes an address generation unit, an address conversion unit and a data reading unit. The address generation unit is used to generate a virtual address of the target register according to the relevant information of the target register read by the first register reading unit. The address conversion unit is used to generate a physical address of the target register according to the virtual address of the target register. The data reading unit is used to read data from the physical address of the target register to obtain read data (read data).

[0039] If the data reading unit does not read the data, for example, the data in the target register is missing, the load instruction needs to be reloaded; if the data reading unit reads the data, the instruction in the second retention unit can be awakened.

[0040] The second reservation unit is used to store the instruction to be awakened, and the second reservation unit includes a second storage unit, a second selection unit, a second instruction reading unit and a second register reading unit. The load instruction awakens the sub instruction in the second storage unit, calls out the sub instruction through the second selection unit, reads the additional information of the sub instruction through the second instruction reading unit, reads the source register in the sub instruction through the second register reading unit, and finally executes the sub instruction through the second loading unit.

[0041] In the above method, the load instruction wakes up the sub instruction in the second reservation unit at the stage of reading the target register data, which is at a relatively late position in the loading pipeline of the load instruction. Other instructions that depend on the load instruction need to stay in the RS for a long time, and two instruction bubbles are generated during the instruction wake-up process, and the processor wake-up efficiency is low.

[0042] Please refer to Figure 2 , which shows a schematic diagram of an instruction wake-up module applied to a processor provided by an embodiment of the present application. The instruction wake-up module can be a unit of a pure hardware structure, which can be set on the chip of the processor. The instruction wake-up module includes: a data retention unit and a data loading unit; the data retention unit includes a first retention unit 10 and a second retention unit 30; the data loading unit includes a first loading unit 20 matching the first retention unit, and a second loading unit 40 matching the second retention unit; the first retention unit includes a first storage unit, and the second retention unit includes a second storage unit; the first loading unit 20 includes an address generation unit 21, an address conversion unit 22 and a data reading unit 23;

[0043] The first reservation unit 10 is used to obtain first indication information according to the first load instruction in the first storage unit, the first indication information is used to indicate the target register of the first load instruction, and the first load instruction is used to load data in the external memory into the target register.

[0044] The first reservation unit is a reservation unit for temporarily storing a load instruction. The first reservation unit includes a plurality of load instructions. The first load instruction is any load instruction in the first storage unit, and is used to load data in the external memory into a target register. The first reservation unit obtains indication information of a target register of the first load instruction according to relevant instruction information of the first load instruction.

[0045] After the first load instruction is called out from the first reservation unit, the first load instruction is loaded by the first load unit, and passes through the address generation unit, the address conversion unit and the data reading unit in sequence. Among them, the address generation unit is used to generate a virtual address of the target register according to the relevant information of the target register of the first load instruction. The address conversion unit is used to convert the virtual address of the target register into the physical address of the target register according to the mapping relationship between the virtual address and the physical address, thereby obtaining the physical address of the target register. The data reading unit is used to read data from the physical address according to the physical address of the target register.

[0046] Exemplarily, the earthquake generating unit may be an AGU (Address Generate Unit), the address translation unit may be a TLB (Translation Lookaside Buffer), and the data reading unit may be a CACHE (cache memory).

[0047] The second reservation unit 30 is used to determine at least one associated instruction matching the first indication information in the second storage unit according to the first indication information during the process in which the first load instruction reaches the address generation unit 21 from the first reservation unit 10, where the associated instruction is an instruction executed based on the data in the target register.

[0048] The second storage unit contains a plurality of instructions to be awakened, each of which has at least one source register, and the source register of the instruction to be awakened is the target register of the load instruction in the first reservation unit. The target register of the first load instruction is matched with at least one source register of each instruction to be awakened. If a source register in a certain instruction to be awakened is the same as the target register of the first load instruction, it means that the instruction to be awakened is awakened by the first load instruction, and the awakened instruction can be called an associated instruction matching the first load instruction.

[0049] The first loading unit 20 is used for loading a first loading instruction.

[0050] The first loading unit loads the first loading instruction through the address generating unit, the address converting unit and the data reading unit to obtain the data in the external memory corresponding to the first loading instruction.

[0051] The second loading unit 40 is used to execute at least one associated instruction when the first loading instruction is loaded successfully.

[0052] If the associated instruction contains a source register, for example, the associated instruction may be ADD X3, X2, 1, and the ADD instruction is used to add 1 to the data in the X2 register and write it to the X3 register, then the associated instruction contains a source register X2 and a source operand 1. Then, if the first load instruction is loaded successfully, the second load unit executes at least one associated instruction according to the data in the target register of the first load instruction. The first load instruction is loaded successfully, indicating that the first load instruction can read data from the corresponding external memory.

[0053] If the associated instruction contains multiple source registers, for example, the associated instruction may be ADD X4, X2, X3, and the ADD instruction is used to add the data in the X2 register to the data in the X3 register and write them into the X4 register, then the associated instruction contains source register X2 and source register X3, and the source register X2 and source register X3 respectively indicate the target registers of two different load instructions. Then, when both the two different load instructions are loaded successfully, at least one associated instruction is executed.

[0054] The pipeline process of instruction wake-up can be referred to Figure 3 As shown, the first reservation unit includes a first storage unit, a first selection unit, a first instruction reading unit and a first register reading unit, the first loading unit includes an address generation unit, an address conversion unit and a data reading unit, the second reservation unit includes a second storage unit, a second selection unit, a second instruction reading unit and a second register reading unit, and the second loading unit includes an execution unit.

[0055] The first selection unit selects and calls the first load instruction from the first storage unit to obtain relevant information of the first load instruction. The first instruction reading unit reads additional information of the first load instruction, and the first register reading unit reads the target register of the first load instruction, and then the first load instruction reaches the address generation unit. In the process of the first load instruction reaching the address generation unit from the first reservation unit, the source registers of each instruction to be awakened in the first indication information and the second storage unit are matched to determine at least one associated instruction. When the first load instruction reaches the address generation unit, at least one associated instruction is awakened. Figure 3 As shown, the associated instruction is awakened in the third clock cycle after the first load instruction in the first selection unit, so a delay chain needs to be added after the first selection unit for delaying the awakening operation. The at least one associated instruction determined here includes a source register, which is the target register of the first load instruction.

[0056] The second selection unit selects and calls at least one associated instruction from the second storage unit, reads additional information of the associated instruction through the second instruction reading unit, and reads the target register and source register of the associated instruction through the second register reading unit. When the first load instruction is loaded successfully, that is, when the data reading unit obtains the read data, the execution unit executes the at least one associated instruction.

[0057] Exemplarily, the execution unit may be an Arith Logic Unit (ALU).

[0058] The technical solution provided by the embodiment of the present application determines at least one associated instruction matching the first indication information in the second storage unit during the process of the first load instruction reaching the address generation unit from the first reservation unit, and wakes up at least the associated instruction when the first load instruction reaches the address generation unit, so that the associated instruction in the second storage unit can be woken up at the front position of the loading pipeline of the first load instruction. Compared with the related art of waking up the associated instruction when the first load instruction reaches the data reading unit, the instruction wake-up scheme proposed in the present application is advanced by two clock cycles, shortens the time that the associated instruction stays in the second reservation unit, speeds up the efficiency of instruction wake-up, and thus improves the performance of the instruction wake-up module of the processor.

[0059] The following is a detailed introduction to the command wake-up process of the command wake-up module. The structural diagram of the command wake-up module can be referred to Figure 4 shown.

[0060] The first storage unit contains at least one entry, each entry contains information of a load instruction, and the information of the load instruction includes attribute information of the load instruction and additional information of the load instruction. The attribute information of the load instruction includes encoding information of the load instruction, indication information of the source memory of the load instruction, and execution status of the load instruction. Among them, the encoding information of the load instruction is used to indicate the identification information of the load instruction, and different load instructions correspond to different encoding information. The indication information of the source memory of the load instruction is used to indicate the external memory from which the load instruction is to read data, and the execution status of the load instruction is used to indicate whether the load instruction has a loading condition. Exemplarily, if the execution status of the load instruction is marked as 1, it means that the load instruction is in a ready state and the load instruction has a loading condition. If the execution status of the load instruction is marked as 0, it means that the load instruction is in a not ready state and the load instruction has a loading condition. The additional information of the load instruction is used to indicate the information required for the load instruction to load, including indication information of the target register of the load instruction, indication information of the load path of the load instruction, time information of the load instruction being written into the first storage unit, etc.

[0061] For example, Figure 4As shown, the first storage unit contains 32 entries, entry0 to entry31, each entry contains information of a load instruction, including DLID (Dependency Load Index, dependency load instruction number), that is, the encoding information of the load instruction, psrc (physical source, physical source memory number), that is, the indication information of the source memory of the load instruction, psrc ready, that is, the execution status of the load instruction, uop (micro operation, micro instruction related field segment), that is, additional information of the load instruction.

[0062] The first reservation unit is a reservation unit for temporarily storing load instructions. The first load instruction is a load instruction contained in any entry in the first storage unit. The first load instruction is selected and called out from the first storage unit by the first selection unit. The first selection unit selects the load instruction from the first storage unit according to a selection strategy. The present application does not limit the selection strategy. For example, the selection strategy may be to select the load instruction written into the first storage unit earliest, or to select the load instruction written into the first storage unit most recently, or to randomly select a load instruction.

[0063] The selected first load instruction reads additional information of the first load instruction through the first instruction reading unit, and reads the target register of the first load instruction through the first register reading unit.

[0064] In some embodiments, the first retention unit further includes a coding generation unit. The coding generation unit is used to generate coding information of the first load instruction according to the first load instruction; wherein the coding information of the first load instruction is identification information used to indicate the first load instruction, and the coding information of the first load instruction is a one-hot code containing n bits, the value of the first bit of the n bits is a first numerical value, and n is a positive integer greater than or equal to 3.

[0065] The code generation unit is used to generate a one-hot code of n bits corresponding to the load instruction. The one-hot code refers to a code in which one and only one bit of the n bits has a value of a first value, and the values ​​of the remaining bits are all another value. For example, the first value can be 1, and the other value can be 0, then the one-hot code is a code in which one and only one bit has a value of 1, and the values ​​of the remaining bits are all 0.

[0066] Exemplarily, the initial encoding information generated by the encoding generation unit is a one-hot code whose last bit value among n bits is a first value. Then, whenever a load instruction passes through the encoding generation unit, the encoding generation unit will perform a cyclic left shift operation on the position of the first value by one bit according to the encoding information of the previous load instruction to obtain the encoding information of the load instruction. Figure 5As shown, the code generation unit is used to generate a 3-bit one-hot code corresponding to the load instruction, and the initial code information of the code generation unit is 001. When a load instruction passes through the code generation unit, the position of 1 is shifted left by one bit, and the code information of the load instruction is 010. If the code information of the current load instruction is 100, the code information of the next load instruction is 001.

[0067] Exemplarily, the initial encoding information generated by the encoding generation unit is a one-hot code in which the value of the first bit among n bits is a first numerical value. Then, whenever a load instruction passes through the encoding generation unit, the encoding generation unit will perform a cyclic right shift operation on the position of the first numerical value by one bit according to the encoding information of the previous load instruction to obtain the encoding information of the load instruction. For example, if the encoding information of the current load instruction is 100, the encoding information of the next load instruction is 010.

[0068] By using n-bit one-hot codes to encode each load instruction passing through the encoding generation unit, each load instruction has its own identification information, so that each load instruction can be distinguished and identified in the load pipeline of the load instructions.

[0069] In some embodiments, the first load instruction arrives at the code generation unit from the first storage unit through a delay chain, and the delay chain is used to delay at least one clock cycle.

[0070] like Figure 4 As shown, the first load instruction arrives at the code generation unit from the first selection unit after passing through a delay chain. Exemplarily, the delay chain can be used to delay three clock cycles, and the delay chain can be a 3-cycle delay line.

[0071] By adding a delay chain after the first selection unit, at least one associated instruction can be awakened when the first load instruction reaches the address generation unit, that is, after the first load instruction has read the target register of the first load instruction via the first register reading unit, thereby ensuring that the associated instruction can be awakened at the earliest time possible, thereby improving the efficiency of instruction awakening.

[0072] In some embodiments, each entry of the second storage unit stores attribute information of an instruction to be awakened, and the attribute information includes encoding information of the instruction to be awakened, indication information of a source register of the instruction to be awakened, and execution status of the instruction to be awakened.

[0073] like Figure 4As shown, the second storage unit includes at least one entry, each entry includes information of an instruction to be awakened, and the information of the instruction to be awakened includes attribute information of the instruction to be awakened and additional information of the instruction to be awakened. Different from the attribute information of the load instruction, the instruction to be awakened usually includes multiple operands, so for each operand, the encoding information corresponding to the operand, the indication information of the source register and the execution status of the operand are set respectively. For example, if the instruction to be awakened includes a first operand and a second operand, the attribute information corresponding to the first operand includes the encoding information (DLID0) of the instruction to load the first operand, the indication information (psrc0) of the first operand and the execution status (psrcready0) of the first operand, and the attribute information corresponding to the second operand includes the encoding information (DLID1) of the instruction to load the second operand, the indication information (psrc1) of the second operand and the execution status (psrc ready1) of the second operand.

[0074] If the indication information of the source register of the associated instruction is used to indicate a source register, then illustratively, for the wake-up instruction ADD X3,X2,1, it includes two operands, source register X2 and source operand 1, and the attribute information corresponding to source register X2 includes the encoding information of the instruction to load data in source register X2, the indication information of source register X2, and the execution status of the instruction to load data in source register X2. The attribute information corresponding to source operand 1 includes the encoding information of the instruction to load source operand 1, the indication information of the source operand, and the execution status of the instruction to load source operand 1.

[0075] If the indication information of the source register of the associated instruction is used to indicate multiple source registers, then illustratively, for the wake-up instruction ADD X4, X2, X3, it includes two operands, source register X2 and source register X3, and the attribute information corresponding to source register X2 includes the encoding information of the instruction to load data in source register X2, the indication information of source register X2, and the execution status of the instruction to load data in source register X2. The attribute information corresponding to source register X3 includes the encoding information of the instruction to load data in source register X3, the indication information of source register X3, and the execution status of the instruction to load data in source register X3.

[0076] The following describes a case where the indication information of the source register of the associated instruction is only used to indicate the first source register.

[0077] In some embodiments, the second storage unit is used to match the first indication information with the indication information of the source register of the instruction to be awakened during the process of the first load instruction reaching the address generation unit from the first reservation unit, and obtain at least one associated instruction matching the first indication information, and the first source register is the same as the target register indicated by the first indication information. The second storage unit is used to update the encoding information of the associated instruction to the encoding information of the first load instruction. The second storage unit is used to mark the execution status of at least one associated instruction as a second value, and the second value is used to indicate that at least one associated instruction has the execution condition.

[0078] The second storage unit is used to match the target register with each source register of the instruction to be awakened during the process of the first load instruction reaching the address generation unit from the first reservation unit, and the indication information of the source register is obtained only for indicating at least one associated instruction of the first source register. The first source register and the target register mentioned here are the same register.

[0079] After determining at least one associated instruction from the second storage unit, the second storage unit updates the encoding information corresponding to the first source register to the encoding information of the first load instruction, and marks the execution state corresponding to the first source register as a second value. Exemplarily, the second value may be 1, that is, when the execution state is marked as 1, the instruction to load the data in the first source register is in a ready state.

[0080] For example, for the entry where the associated instruction is located, the attribute information of the first operand (first source register) and the attribute information of the second operand are included. If the attribute information of the first source register corresponds to DLID0, psrc0 and psrc ready0, the value of DLID0 is updated to the encoding information of the first load instruction, and psrc ready0 is marked as the second value.

[0081] The first indication information is matched with the indication information of the source register of the instruction to be awakened through the second storage unit, at least one associated instruction is determined, and the encoding information of the associated instruction and the execution status of the associated instruction are updated, so as to realize the awakening of the associated instruction and the marking of the associated instruction, so as to facilitate the subsequent second selection unit to call it out from the second storage unit and read the relevant information of the associated instruction.

[0082] In some embodiments, during the process of the first loading unit loading the first loading instruction, the data reading unit is used to read data from the external memory according to the first loading instruction to obtain a data reading result; the data reading result includes a read success result and a read failure result, the read success result is used to indicate that the first loading instruction is loaded successfully, and the read failure result is used to indicate that the first loading instruction fails to load.

[0083] Data read success means that data can be read from the external memory according to the first load instruction, and data read failure means that data cannot be read from the external memory according to the first load instruction. Data read failure may be caused by data missing from the external memory, or by an error in the read path, etc.

[0084] When the first load instruction arrives at the data reading unit, at least one associated instruction arrives at the second instruction reading unit, and the second instruction reading unit is used to obtain additional information of the at least one associated instruction.

[0085] After acquiring the additional information of at least one associated instruction, the second instruction reading unit generates an instruction data queue corresponding to the at least one associated instruction.

[0086] By setting at least one associated instruction to arrive at the second instruction reading unit when the first loading instruction arrives at the data reading unit, the next operation strategy can be executed in time according to the data reading result, so that when the first loading instruction fails to load, the execution of the associated instruction can be stopped in time, avoiding the processor from executing unnecessary steps and improving the performance of the processor.

[0087] In some embodiments, the second retention unit also includes a second dependency checking unit; the second dependency checking unit is used to perform a dependency check on each instruction to be awakened in the second storage unit according to the encoding information of the first loading instruction to obtain the awakened instruction, and the value of the first bit of the encoding information of the awakened instruction is the first numerical value.

[0088] When the first loading instruction runs to the data reading unit, a dependency check will be performed on each encoding information in the second retention unit according to the data reading result, and the awakened instruction awakened by the first loading instruction in the second storage unit will be searched. Therefore, the awakened instruction mentioned here is at least one associated instruction awakened by the first loading instruction.

[0089] The value of the first bit of the encoding information of the first loading instruction is the first numerical value. Therefore, the second dependency checking unit checks the value of the first bit of the encoding information of each instruction to be awakened in the second storage unit according to the value of the first bit of the encoding information of the first loading instruction. The instruction to be awakened whose first bit of the encoding information is the first numerical value is the awakened instruction.

[0090] refer to Figure 4The second storage unit shown performs dependency checks on DLID0 and DLID1 in entry0 to DLID0 and DLID1 in entry31, and determines the to-be-awakened instruction corresponding to at least one DLID whose first bit value is the first numerical value as the awakened instruction. For example, if the encoding information of the first load instruction is 001, the to-be-awakened instruction corresponding to at least one DLID whose last bit value of the encoding information is 1 is determined as the awakened instruction.

[0091] By performing dependency checks on each instruction to be awakened in the second storage unit through the second dependency check unit, the associated instruction awakened by the first load instruction in the second storage unit can be determined, so that the attribute information of the awakened instruction can be modified according to the data reading result, thereby facilitating the implementation of the subsequent awakening process of other instructions.

[0092] In some embodiments, the second retaining unit is used to reset the encoding information of the awakened instruction to 0 when the first loading instruction is loaded successfully.

[0093] For example, if the encoding information of the first load instruction is 001, the determined awakened instruction is the instruction corresponding to entry1, where the value of the last bit of DLID1 in entry1 is 1, then if the first load instruction is loaded successfully, the second retention unit resets the value of DLID1 in entry1 to 0.

[0094] The second loading unit executes at least one associated instruction if the first loading instruction is loaded successfully. The second register reading unit reads the target register and source register of the associated instruction according to the additional information of the associated instruction, and then the execution unit executes the associated instruction according to the data in the target register of the first loading instruction.

[0095] In some embodiments, the second reservation unit is used to mark the execution status of the awakened instruction as a third value and clear the read information of the associated instruction in the second reservation unit when the first load instruction fails to load; wherein the third value is used to indicate that the associated instruction does not meet the execution conditions.

[0096] For example, if the encoding information of the first load instruction is 001, and the determined awakened instruction is the instruction corresponding to entry1, wherein the value of the last bit of DLID1 in entry1 is 1, then in the case where the first load instruction fails to load, the second retention unit marks psrc ready1 as a third value, and clears the reading information of the associated instruction in the data execution pipeline, and the associated instruction can wait to be awakened next time.

[0097] Exemplarily, the third value may be 0, that is, when the execution status mark is 0, the instruction to load the data in the first source register is in a not ready state.

[0098] By modifying the attribute information of the awakened instruction in the second storage unit according to the data reading result, each awakened instruction can continue to be awakened in the next awakening process, which facilitates the implementation of the instruction awakening process of the instruction awakening module.

[0099] Next, the case where the indication information of the source register of the associated instruction is used to indicate multiple source registers is introduced.

[0100] In some embodiments, if the indication information of the source register of the associated instruction is used to indicate the second source register and the third register, and the second source register is the same as the target register of the second load instruction, and the third source register is the same as the target register of the third load instruction, then the second storage unit is used to update the encoding information of the associated instruction to the joint encoding information.

[0101] The joint coding information is a bitwise OR result of the coding information of the second load instruction and the coding information of the third load instruction, the value of the second bit of the coding information of the second load instruction is the first value, and the value of the third bit of the coding information of the third load instruction is the first value.

[0102] The indication information of the source register of the associated instruction is used to indicate two different source registers, and the two source registers are respectively the same as the target registers of two different load instructions. In this case, the associated instruction depends on the second load instruction and the third load instruction, and the associated instruction can be awakened by the second load instruction or the third load instruction.

[0103] The encoding information of the associated instruction will be updated to the bitwise OR result of the encoding information of the second load instruction and the encoding information of the third load instruction. Figure 6As shown. The encoding information of the LOAD X2, [SP] instruction is 001. The ADD X3, X2, 1 instruction depends on the LOAD X2, [SP] instruction. When the ADD instruction is awakened, the encoding information of the LOAD X2, [SP] instruction is passed to the ADD instruction, and the encoding information of the ADD instruction is updated to 001. The encoding information of the LOAD X4, [SP] instruction is 010. The SUBX5, X3, X4 instruction depends on the ADD instruction and the LOAD X4, [SP] instruction. When the SUB instruction is awakened by any of the dependent instructions, the bitwise OR result of the encoding information of the ADD instruction and the encoding information of the LOAD X4, [SP] instruction is passed to the SUB instruction, that is, the bitwise OR result of 001 and 010 is passed to the SUB instruction. The bitwise OR result of 001 and 010 is 011, so the encoding information of the SUB instruction is 011.

[0104] When there are two bits in the encoding information of the associated instruction whose values ​​are both the first value, it can be indicated that the associated instruction is awakened by two load instructions at the same time.

[0105] By determining the encoding information of the associated instruction that depends on multiple load instructions as the bitwise OR result of the encoding information of the multiple load instructions, the values ​​on the second bit and the third bit of the encoding information of the associated instruction are both the first numerical value, so that the encoding information can be used to indicate that the associated instruction is awakened by two load instructions, thereby facilitating determining the executable condition of the associated instruction based on the encoding information.

[0106] For an associated instruction that depends on multiple load instructions, the associated instruction can be executed by the execution unit only when the multiple load instructions are loaded successfully. If one of the multiple load instructions fails to load, the associated instruction cannot be executed.

[0107] In some embodiments, the second loading unit is used to execute the associated instruction if the second loading instruction is loaded successfully and the third loading instruction is loaded successfully.

[0108] The second retaining unit is used for resetting the encoding information of the awakened instruction to 0 when the second loading instruction is loaded successfully and the third loading instruction is loaded successfully.

[0109] The second reservation unit is used to mark the execution status of the awakened instruction as a third value and clear the read information of the associated instruction in the second reservation unit when the second load instruction fails to load or the third load instruction fails to load; wherein the third value is used to indicate that the associated instruction does not meet the execution conditions.

[0110] The second dependency check unit can perform a dependency check on each instruction to be awakened in the second storage unit according to the encoding information of the second loading instruction and the encoding information of the third loading instruction, and search for the instruction to be awakened whose second bit and third bit in the encoding information have the first value, and determine it as the awakened instruction.

[0111] By setting the successful loading of the second load instruction and the successful loading of the third load instruction as the execution condition of the associated instruction, it is avoided that a certain load instruction fails to load data into the target register, thereby affecting the execution of the associated instruction, so as to facilitate the timely execution of the next operation strategy according to the data reading result.

[0112] The command wake-up process of the command wake-up module can be referred to Figure 7 shown.

[0113] In step 1, a first load instruction is selected and called out from a first storage unit via a first selection unit, and reaches a code generation unit after passing through a delay chain. The code generation unit generates code information of the first load instruction according to the first load instruction.

[0114] The implementation process of step 2 consists of two steps.

[0115] In step 2a, the first load instruction reads additional information of the first load instruction through the first instruction reading unit, and reads the target register of the first load instruction through the first register reading unit, and then reaches the address generation unit.

[0116] In step 2b, the second storage unit determines at least one associated instruction in the second storage unit that matches the first indication information based on the first indication information, performs a wake-up operation on the at least one associated instruction, updates the encoding information of the first loading instruction to the encoding information of the at least one associated instruction, and marks the execution status of the at least one associated instruction as a second value. At this time, the at least one associated instruction meets the execution condition.

[0117] The implementation process of step 3 consists of two steps.

[0118] In step 3a, the first load instruction is transmitted to the data reading unit in the load pipeline to obtain a data reading result.

[0119] In step 3b, at least one associated instruction is selected and called out from the second storage unit via the second selection unit, and the additional information of the associated instruction is read by the second instruction reading unit. When the first load instruction reaches the data reading unit, at least one associated instruction reaches the second instruction reading unit.

[0120] The execution process of step 4 consists of two steps.

[0121] In step 4a, the awakened instruction in the second storage unit is obtained by the second dependency checking unit according to the encoding information of the first loading instruction. If the first loading instruction is loaded successfully, the encoding information of the awakened instruction is reset to 0; if the first loading instruction fails to load, the execution state of the awakened instruction is marked as a third value.

[0122] Step 4b: If the first load instruction is loaded successfully, the target register and source register of the associated instruction are read by the second register reading unit, and at least one associated instruction is executed by the execution unit. If the first load instruction fails to be loaded, the read information of the associated instruction in the second retention unit is cleared.

[0123] The following is an embodiment of the method of the present application. For details not described in detail in the embodiment of the method of the present application, please refer to the above embodiment of the instruction wake-up module.

[0124] Please refer to Figure 8 , which shows a flowchart of an instruction wake-up method applied to an instruction wake-up module provided by an embodiment of the present application, the method is applied to the instruction wake-up module applied to the processor introduced above, the instruction wake-up module includes: a data retention unit and a data loading unit; the data retention unit includes a first retention unit and a second retention unit; the data loading unit includes a first loading unit matching the first retention unit, and a second loading unit matching the second retention unit; the first retention unit includes a first storage unit, and the second retention unit includes a second storage unit; the first loading unit includes an address generation unit, an address conversion unit and a data reading unit. The method may include at least one of the following steps 810 to 840.

[0125] Step 810: The first reservation unit obtains first indication information according to the first load instruction in the first storage unit, where the first indication information is used to indicate a target register of the first load instruction, and the first load instruction is used to load data in the external memory into the target register.

[0126] In some embodiments, the first retention unit also includes a coding generation unit; the coding generation unit generates coding information of the first loading instruction based on the first loading instruction; wherein the coding information of the first loading instruction is identification information used to indicate the first loading instruction, and the coding information of the first loading instruction is a unique hot code containing n bits, the value of the first bit of the n bits is a first numerical value, and n is a positive integer greater than or equal to 3.

[0127] In some embodiments, the first load instruction arrives at the code generation unit from the first storage unit through a delay chain, and the delay chain is used to delay at least one clock cycle.

[0128] Step 820, when the first load instruction reaches the address generation unit from the first reservation unit, the second reservation unit determines, based on the first indication information, at least one associated instruction in the second storage unit that matches the first indication information, where the associated instruction is an instruction executed based on the data in the target register.

[0129] In some embodiments, each entry of the second storage unit stores attribute information of an instruction to be awakened, the attribute information including encoding information of the instruction to be awakened, indication information of the source register of the instruction to be awakened, and execution status of the instruction to be awakened; the indication information of the source register of the associated instruction is used to indicate the first source register.

[0130] During the process in which the first load instruction reaches the address generation unit from the first reservation unit, the second storage unit matches the first indication information with the indication information of the source register of the instruction to be awakened, and obtains at least one associated instruction matching the first indication information, and the first source register is the same as the target register indicated by the first indication information.

[0131] The second storage unit updates the encoding information of the associated instruction to the encoding information of the first load instruction.

[0132] The second storage unit marks the execution status of at least one associated instruction as a second value, and the second value is used to indicate that the at least one associated instruction meets the execution condition.

[0133] In some embodiments, the second reservation unit further includes a second instruction fetch unit.

[0134] Step 830: The first loading unit loads the first loading instruction.

[0135] In some embodiments, the data reading unit reads data from the external memory according to the first loading instruction to obtain a data reading result; the data reading result includes a read success result and a read failure result, the read success result is used to indicate that the first loading instruction is loaded successfully, and the read failure result is used to indicate that the first loading instruction is loaded unsuccessfully.

[0136] When the first load instruction arrives at the data reading unit, at least one associated instruction arrives at the second instruction reading unit, and the second instruction reading unit is used to obtain additional information of the at least one associated instruction.

[0137] Step 840: When the first loading instruction is loaded successfully, the second loading unit executes at least one associated instruction.

[0138] In some embodiments, the second retention unit also includes a second dependency checking unit; the second dependency checking unit performs a dependency check on each instruction to be awakened in the second storage unit according to the encoding information of the first loading instruction to obtain the awakened instruction, and the value of the first bit of the encoding information of the awakened instruction is the first numerical value.

[0139] The second retaining unit resets the encoding information of the awakened instruction to 0 when the first loading instruction is loaded successfully.

[0140] When the first loading instruction fails to load, the second retaining unit marks the execution state of the awakened instruction as a third value and clears the read information of the associated instruction in the second retaining unit; wherein the third value is used to indicate that the associated instruction does not meet the execution condition.

[0141] The technical solution provided by the embodiment of the present application determines at least one associated instruction matching the first indication information in the second storage unit during the process of the first load instruction reaching the address generation unit from the first reservation unit, and wakes up at least the associated instruction when the first load instruction reaches the address generation unit, so that the associated instruction in the second storage unit can be woken up at the front position of the loading pipeline of the first load instruction. Compared with the related art of waking up the associated instruction when the first load instruction reaches the data reading unit, the instruction wake-up scheme proposed in the present application is advanced by two clock cycles, shortens the time that the associated instruction stays in the second reservation unit, speeds up the efficiency of instruction wake-up, and thus improves the performance of the instruction wake-up module of the processor.

[0142] If the indication information of the source register of the associated instruction is used to indicate the second source register and the third register, and the second source register is the same as the target register of the second load instruction, and the third source register is the same as the target register of the third load instruction, then the second storage unit updates the encoding information of the associated instruction to joint encoding information, wherein the joint encoding information is the bitwise OR result of the encoding information of the second load instruction and the encoding information of the third load instruction, the value of the second bit of the encoding information of the second load instruction is the first value, and the value of the third bit of the encoding information of the third load instruction is the first value.

[0143] Then, when the second loading instruction is loaded successfully and the third loading instruction is loaded successfully, the second loading unit executes the associated instruction.

[0144] The second retaining unit resets the encoding information of the awakened instruction to 0 when the second loading instruction is loaded successfully and the third loading instruction is loaded successfully.

[0145] When the second load instruction fails to load or the third load instruction fails to load, the second reservation unit marks the execution status of the awakened instruction as a third value and clears the read information of the associated instruction in the second reservation unit; wherein the third value is used to indicate that the associated instruction does not meet the execution conditions.

[0146] An exemplary embodiment of the present application further provides a processor, wherein the processor includes the instruction wake-up module introduced in the above embodiment.

[0147] An exemplary embodiment of the present application further provides a computer device, the computer device comprising a processor, and the processor comprising the instruction wake-up module introduced in the above embodiment.

[0148] Optionally, the processor is an AI processor, or other processor that requires instruction wake-up operation, which is not limited in this application.

[0149] Optionally, the computer device can be a server, or a terminal device such as a mobile phone, a tablet computer, a vehicle-mounted terminal, a wearable device, a smart home device, or any device that is applied to a processor, such as a robot or a base station, and this application does not limit this.

[0150] It should be noted that this application can display a prompt interface, pop-up window or output voice prompt information before collecting relevant data of users and during the process of collecting relevant data of users. The prompt interface, pop-up window or voice prompt information is used to prompt the user that relevant data is currently being collected, so that this application only starts to execute the relevant steps of obtaining relevant data of users after obtaining the confirmation operation issued by the user to the prompt interface or pop-up window, otherwise (that is, when the confirmation operation issued by the user to the prompt interface or pop-up window is not obtained), the relevant steps of obtaining relevant data of users are terminated, that is, the relevant data of users are not obtained. In other words, all user data collected by this application are processed strictly in accordance with the requirements of relevant national laws and regulations, and the informed consent or separate consent of the subject of personal information is obtained with the consent and authorization of the user. The subsequent data use and processing behavior is carried out within the scope of authorization of laws and regulations and the subject of personal information, and the collection, use and processing of relevant user data shall comply with the relevant laws, regulations and standards of relevant countries and regions.

[0151] It should be understood that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In addition, the step numbers described in this article only illustrate a possible execution sequence between the steps. In some other embodiments, the above steps may not be executed in the order of the numbers, such as two steps with different numbers are executed at the same time, or two steps with different numbers are executed in the opposite order to the diagram. The embodiments of the present application are not limited to this.

[0152] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. An instruction wake-up module applied to a processor, characterized in that: The instruction wake-up module includes: a data retention unit and a data loading unit; the data retention unit includes a first retention unit and a second retention unit; the data loading unit includes a first loading unit matching the first retention unit, and a second loading unit matching the second retention unit; the first retention unit includes a first storage unit, and the second retention unit includes a second storage unit; the first loading unit includes an address generation unit, an address conversion unit and a data reading unit; The first retaining unit is used to obtain first indication information according to the first load instruction in the first storage unit, the first indication information is used to indicate the target register of the first load instruction, and the first load instruction is used to load data in the external memory into the target register; The second reservation unit is used to determine, in a process in which the first load instruction reaches the address generation unit from the first reservation unit, according to the first indication information, at least one associated instruction in the second storage unit that matches the first indication information, wherein the associated instruction is an instruction executed based on the data in the target register; The first loading unit is used to load the first loading instruction; The second loading unit is used to execute the at least one associated instruction when the first loading instruction is loaded successfully.

2. The command wake-up module according to claim 1, characterized in that: The first retaining unit also includes a code generating unit; The encoding generation unit is used to generate encoding information of the first load instruction according to the first load instruction; wherein the encoding information of the first load instruction is identification information used to indicate the first load instruction, and the encoding information of the first load instruction is a one-hot code containing n bits, the value of the first bit of the n bits is a first numerical value, and n is a positive integer greater than or equal to 3.

3. The command wake-up module according to claim 2, characterized in that: Each entry of the second storage unit stores attribute information of an instruction to be awakened, wherein the attribute information includes encoding information of the instruction to be awakened, indication information of a source register of the instruction to be awakened, and execution status of the instruction to be awakened; the indication information of the source register of the associated instruction is used to indicate the first source register; The second storage unit is used for matching the first indication information with the indication information of the source register of the instruction to be awakened when the first load instruction arrives at the address generation unit from the first reservation unit, so as to obtain at least one associated instruction matching the first indication information, and the first source register is the same as the target register indicated by the first indication information; The second storage unit is used to update the encoding information of the associated instruction to the encoding information of the first load instruction; The second storage unit is used to mark the execution status of the at least one associated instruction as a second value, and the second value is used to indicate that the at least one associated instruction meets the execution condition.

4. The command wake-up module according to claim 1, characterized in that: The second reservation unit also includes a second instruction reading unit; The data reading unit is used to read data from the external memory according to the first loading instruction to obtain a data reading result; the data reading result includes a reading success result and a reading failure result, the reading success result is used to indicate that the first loading instruction is loaded successfully, and the reading failure result is used to indicate that the first loading instruction is loaded unsuccessfully; When the first load instruction reaches the data reading unit, the at least one associated instruction reaches the second instruction reading unit, and the second instruction reading unit is used to obtain additional information of the at least one associated instruction.

5. The command wake-up module according to claim 2, characterized in that: The second retaining unit further includes a second dependency checking unit; The second dependency checking unit is used to perform a dependency check on each to-be-awakened instruction in the second storage unit according to the encoding information of the first loading instruction to obtain the awakened instruction, and the value of the first bit of the encoding information of the awakened instruction is a first numerical value.

6. The command wake-up module according to claim 5, characterized in that: The second retaining unit is used for resetting the encoding information of the awakened instruction to 0 when the first loading instruction is loaded successfully; The second retention unit is used to mark the execution status of the awakened instruction as a third value and clear the read information of the associated instruction in the second retention unit when the first loading instruction fails to load; wherein the third value is used to indicate that the associated instruction does not meet the execution conditions.

7. The command wake-up module according to claim 2, characterized in that: The first load instruction arrives at the code generation unit from the first storage unit after passing through a delay chain, and the delay chain is used to delay at least one clock cycle.

8. The command wake-up module according to claim 1, characterized in that: If the indication information of the source register of the associated instruction is used to indicate a second source register and a third register, and the second source register is the same as the target register of the second load instruction, and the third source register is the same as the target register of the third load instruction, then the second storage unit is used to update the encoding information of the associated instruction to joint encoding information; The joint coding information is a bitwise OR result of the coding information of the second load instruction and the coding information of the third load instruction, the value of the second bit of the coding information of the second load instruction is the first numerical value, and the value of the third bit of the coding information of the third load instruction is the first numerical value.

9. The command wake-up module according to claim 8, characterized in that: The second loading unit is used to execute the associated instruction when the second loading instruction is loaded successfully and the third loading instruction is loaded successfully; The second retaining unit is used for resetting the encoding information of the awakened instruction to 0 when the second loading instruction is loaded successfully and the third loading instruction is loaded successfully; The second retention unit is used to mark the execution status of the awakened instruction as a third value and clear the read information of the associated instruction in the second retention unit when the second load instruction fails to load or the third load instruction fails to load; wherein the third value is used to indicate that the associated instruction does not meet the execution conditions.

10. A processor, characterized in that: The processor includes the instruction wake-up module as described in any one of claims 1 to 9.

11. A computer device, characterized in that: The computer device includes a processor, and the processor includes the instruction wake-up module as described in any one of claims 1 to 9.

12. A command wake-up method applied to a command wake-up module, characterized in that: The instruction wake-up module includes: a data retention unit and a data loading unit; the data retention unit includes a first retention unit and a second retention unit; the data loading unit includes a first loading unit matching the first retention unit, and a second loading unit matching the second retention unit; the first retention unit includes a first storage unit, and the second retention unit includes a second storage unit; the first loading unit includes an address generation unit, an address conversion unit and a data reading unit; the method includes: The first retaining unit obtains first indication information according to the first load instruction in the first storage unit, where the first indication information is used to indicate a target register of the first load instruction, and the first load instruction is used to load data in the external memory into the target register; The second reservation unit determines, according to the first indication information, at least one associated instruction in the second storage unit that matches the first indication information when the first load instruction arrives at the address generation unit from the first reservation unit, wherein the associated instruction is an instruction executed based on the data in the target register; The first loading unit loads the first loading instruction; The second loading unit executes the at least one associated instruction when the first loading instruction is loaded successfully.

13. The command wake-up method according to claim 12, characterized in that: The first retaining unit further includes a code generating unit; the method further includes: The encoding generation unit generates encoding information of the first loading instruction according to the first loading instruction; wherein the encoding information of the first loading instruction is identification information used to indicate the first loading instruction, and the encoding information of the first loading instruction is a one-hot code containing n bits, the value of the first bit of the n bits is a first numerical value, and n is a positive integer greater than or equal to 3.

14. The command wake-up method according to claim 13, characterized in that: Each entry of the second storage unit stores attribute information of an instruction to be awakened, wherein the attribute information includes encoding information of the instruction to be awakened, indication information of a source register of the instruction to be awakened, and execution status of the instruction to be awakened; the indication information of the source register of the associated instruction is used to indicate the first source register; The second reservation unit determines, according to the first indication information, at least one associated instruction in the second storage unit that matches the first indication information during a process in which the first load instruction arrives at the address generation unit from the first reservation unit, including: The second storage unit matches the first indication information with the indication information of the source register of the instruction to be awakened during the process that the first load instruction arrives at the address generation unit from the first reservation unit to obtain at least one associated instruction matching the first indication information, and the first source register is the same as the target register indicated by the first indication information; The second storage unit updates the encoding information of the associated instruction to the encoding information of the first load instruction; The second storage unit marks the execution status of the at least one associated instruction as a second value, where the second value is used to indicate that the at least one associated instruction meets the execution condition.

15. The command wake-up method according to claim 12, characterized in that: The second reservation unit also includes a second instruction reading unit; The first loading unit loads the first loading instruction, including: The data reading unit reads data from the external memory according to the first loading instruction to obtain a data reading result; the data reading result includes a reading success result and a reading failure result, the reading success result is used to indicate that the first loading instruction is loaded successfully, and the reading failure result is used to indicate that the first loading instruction is loaded unsuccessfully; When the first load instruction reaches the data reading unit, the at least one associated instruction reaches the second instruction reading unit, and the second instruction reading unit is used to obtain additional information of the at least one associated instruction.

16. The command wake-up method according to claim 13, characterized in that: The second reservation unit further includes a second dependency checking unit; the method further includes: The second dependency checking unit performs a dependency check on each instruction to be awakened in the second storage unit according to the encoding information of the first loading instruction to obtain an awakened instruction, wherein the value of the first bit of the encoding information of the awakened instruction is a first numerical value.

17. The command wake-up method according to claim 16, characterized in that: The second loading unit is used for executing the at least one associated instruction when the first loading instruction is loaded successfully, and further includes: The second retaining unit resets the encoding information of the awakened instruction to 0 when the first loading instruction is loaded successfully; When the first loading instruction fails to load, the second retaining unit marks the execution status of the awakened instruction as a third value and clears the read information of the associated instruction in the second retaining unit; wherein the third value is used to indicate that the associated instruction does not meet the execution condition.

18. The command wake-up method according to claim 13, characterized in that: The first load instruction arrives at the code generation unit from the first storage unit after passing through a delay chain, and the delay chain is used to delay at least one clock cycle.

19. The command wake-up method according to claim 12, characterized in that: The method further comprises: If the indication information of the source register of the associated instruction is used to indicate a second source register and a third register, and the second source register is the same as the target register of the second load instruction, and the third source register is the same as the target register of the third load instruction, then the second storage unit updates the encoding information of the associated instruction to joint encoding information; The joint coding information is a bitwise OR result of the coding information of the second load instruction and the coding information of the third load instruction, the value of the second bit of the coding information of the second load instruction is the first numerical value, and the value of the third bit of the coding information of the third load instruction is the first numerical value.

20. The command wake-up method according to claim 19, characterized in that: The method further comprises: The second loading unit executes the associated instruction when the second loading instruction is loaded successfully and the third loading instruction is loaded successfully; The second retaining unit resets the encoding information of the awakened instruction to 0 when the second loading instruction is loaded successfully and the third loading instruction is loaded successfully; When the second load instruction fails to load or the third load instruction fails to load, the second retention unit marks the execution status of the awakened instruction as a third value and clears the read information of the associated instruction in the second retention unit; wherein the third value is used to indicate that the associated instruction does not meet the execution conditions.

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