Data transmission method and system based on PCIE interruption

Abstract

The invention discloses a data transmission method and system based on PCIE (Peripheral Component Interface Express) interruption, and the method comprises the steps: an upper computer executes the data carrying operation of corresponding data packets in a data storage unit when receiving interruption requests corresponding to different data packets sent by an FPGA (Field Programmable Gate Array); the upper computer respectively starts monitoring operation on the data packet A and the data packet B; in the monitoring process, timing monitoring is started when an interrupt request of a corresponding data packet is received, when the interrupt request is received within a preset monitoring duration, the monitoring duration is cleared, monitoring is initiated again, and when the interrupt request is not received within the preset monitoring duration, an upper computer executes a carrying operation of the corresponding data packet after timeout. And after the monitoring duration is emptied, monitoring is initiated again. By monitoring the interrupt request of the corresponding data packet, data transmission is reliably carried out, and data packet loss is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to a data transmission method and system based on PCIE interruption. Background Art

[0002] FPGA (Field Programmable Gate Array) communicates with the host computer through PCIE (Peripheral Component Interconnect Express) technology to transmit data. After FPGA writes data into the data storage unit, FPGA sends an interrupt request to the host computer. After the host computer receives the interrupt request, it moves the data in the data storage unit to achieve data transmission. However, in actual operation, the host computer software may not receive the interrupt request sent by FPGA, which leads to packet loss during the transmission process. Summary of the invention

[0003] The purpose of the embodiment of the present invention is to provide a data transmission method based on PCIE interruption, which can reliably transmit data and avoid data packet loss by monitoring the interrupt request of the corresponding data packet.

[0004] In order to achieve the above-mentioned purpose, the present invention adopts the following technical solutions: The present application relates to a data transmission method based on PCIE interruption, comprising: For data packet A and data packet B, when the host computer receives interrupt requests corresponding to different data packets sent by the FPGA, it executes the data transfer operation of the corresponding data packet written into the data storage unit under the control of the FPGA; The host computer starts monitoring operations on data packets A and B respectively; During the monitoring process, the monitoring starts from the time when the interrupt request of the corresponding data packet is received, and when the interrupt request is received within the preset monitoring time, the monitoring time is cleared and the monitoring is initiated again; When no interrupt request is received within the preset monitoring time, the host computer performs the corresponding data packet transfer operation after timeout, and re-initiates monitoring after clearing the monitoring time; Among them, data transmission includes data writing and data transportation. The FPGA uses AB data packet cross-mode to write into the data storage unit, and the host computer uses AB data packet cross-mode to transport the corresponding data packet. The preset monitoring time is twice the maximum time difference between adjacent interrupt requests normally sent by the host computer monitoring the FPGA.

[0005] In some embodiments of the present application, when the host computer monitors the A data packet and the B data packet, two parallel first monitoring threads and second monitoring threads are triggered to start; The first monitoring thread is used to monitor the A data packet, and the second monitoring thread is used to monitor the B data packet.

[0006] In some embodiments of the present application, during the monitoring process, flags are set corresponding to different data respectively; When the host computer receives an interrupt request corresponding to the data packet, the flag is set to the first flag, and the host computer performs a transport operation of the corresponding data packet; During the monitoring process, proceed as follows: S1: Check the flag bit flag, if it is the first flag bit, proceed to S5, otherwise, proceed to S2; S2: Determine whether an interrupt request is received when the monitoring time is within the preset monitoring time. If so, proceed to S5; if not, proceed to S3; S3: Determine whether the monitoring time reaches the preset monitoring time. If yes, proceed to S4; if no, return to S2; S4: flag is set to the second flag bit, and the host computer performs the corresponding data packet transfer operation; S5: Clear the monitoring duration, restart monitoring, and return to S1.

[0007] In some embodiments of the present application, the FPGA controls writing the A data packet into the A region of the data storage unit, and writing the B data packet into the B region of the data storage unit; The A data packet carried by the host computer from area A and the B data packet carried from area B are cross-synthesized into complete data and stored in the buffer of the host computer software; When the size of the buffer reaches a specified size, the complete data is released from the buffer.

[0008] Compared with the prior art, the data transmission method of PCIE interruption proposed in this application has the following advantages and beneficial effects: The host computer monitors the interrupt requests of data packet A and data packet B respectively, and uses whether the interrupt request is received within the preset monitoring time to determine whether the host computer has not received the interrupt request. This ensures that even if the interrupt request is not received within the preset monitoring time, data can be transferred normally to avoid data packet loss caused by failure to receive the interrupt request, thereby ensuring reliable data transmission between FPGA and the host computer.

[0009] The present application also relates to a data transmission system based on PCIE interruption, comprising: A data acquisition unit, which is used to collect data; an FPGA connected to the data acquisition unit, outputting an interrupt request corresponding to the A data packet after the FPGA writes the A data packet collected by the data acquisition unit into the data storage unit, and outputting an interrupt request corresponding to the B data packet after the FPGA writes the B data packet collected by the data acquisition unit into the data storage unit, wherein the FPGA writes the A data packet into the data storage unit in an interleaved manner; A host computer is connected to the FPGA through a PCIE bus communication. When receiving an interrupt request of a corresponding data packet sent by the FPGA, the host computer performs a transport operation of the corresponding data packet, wherein the host computer transports the corresponding data packet in an AB data packet cross mode; The host computer also starts monitoring operations on data packets A and B respectively; During the monitoring process, the monitoring starts from the time when the interrupt request of the corresponding data packet is received, and when the interrupt request is received within the preset monitoring time, the monitoring time is cleared and the monitoring is initiated again; When no interrupt request is received within the preset monitoring time, the host computer performs the corresponding data packet transfer operation after timeout, and re-initiates monitoring after clearing the monitoring time; The preset monitoring time length is twice the maximum time difference between adjacent interrupt requests normally sent by the host computer monitoring the FPGA.

[0010] In some embodiments of the present application, when the host computer monitors the A data packet and the B data packet, two parallel first monitoring threads and second monitoring threads are triggered to start; The first monitoring thread is used to monitor the A data packet, and the second monitoring thread is used to monitor the B data packet.

[0011] In some embodiments of the present application, during the monitoring process, flags are set corresponding to different data respectively; When the host computer receives an interrupt request corresponding to the data packet, the flag is set to the first flag, and the host computer performs a transport operation of the corresponding data packet; During the monitoring process, proceed as follows: S11: Determine the flag bit flag, if it is the first flag bit, proceed to S15, otherwise, proceed to S12; S12: Determine whether an interrupt request is received when the monitoring time is within the preset monitoring time. If so, proceed to S15; if not, proceed to S13; S13: Determine whether the monitoring time reaches the preset monitoring time, if yes, proceed to S14, if no, return to S12; S14: flag is set to the second flag bit, and the host computer performs the corresponding data packet transfer operation; S15: Clear the monitoring time, restart monitoring, and return to S1.

[0012] In some embodiments of the present application, the host computer further includes: Buffer, FPGA controls writing data packet A into area A of the data storage unit, and writing data packet B into area B of the data storage unit. The data packet A carried from area A and the data packet B carried from area B by the host computer are cross-synthesized into complete data and stored in the buffer of the host computer software; When the size of the buffer reaches a specified size, the complete data is released from the buffer.

[0013] After reading the specific embodiments of the present invention in conjunction with the accompanying drawings, other features and advantages of the present invention will become more clear. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 A schematic diagram showing an embodiment of a data transmission system based on PCIE interruption proposed by the present invention; Figure 2 A schematic diagram showing a method for obtaining a time difference between adjacent interrupt requests; Figure 3 A flowchart showing the monitoring process of the host computer in the embodiment of the data transmission method based on PCIE interruption proposed by the present invention; Figure 4 Schematic diagram showing the monitoring process of the host computer in the embodiment of the data transmission method based on PCIE interruption proposed by the present invention Figure 1 ; Figure 5 Schematic diagram showing the monitoring process of the host computer in the embodiment of the data transmission method based on PCIE interruption proposed by the present invention Figure 2 ; Figure 6 A flowchart showing the transmission of data packet A in an embodiment of a data transmission method based on PCIE interruption proposed by the present invention is shown; Figure 7 A schematic diagram showing the integration of host computer data using an embodiment of the data transmission method based on PCIE interruption proposed by the present invention.

[0016] Reference numerals: 100, data acquisition unit; 200, FPGA; 300, host computer; 400, data storage unit. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0018] Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In the description of the present invention, it should be understood that the orientation or position relationship indicated by the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0019] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0020] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0021] In order to avoid the problem of packet loss due to the host computer not receiving the interrupt request sent by FPGA, the present application relates to a data transmission method based on PCIE interrupt. During the data transmission process, by introducing a monitoring process of the interrupt request corresponding to the data packet, when the host computer does not receive the interrupt request, it is ensured that the data in the data storage unit can be obtained to avoid packet loss.

[0022] Figure 1 A schematic diagram showing a data transmission system based on PCIE interruption.

[0023] The data transmission method based on PCIE interruption is performed by using a data transmission system based on PCIE interruption.

[0024] The data transmission system based on PCIE interruption includes a data acquisition unit 100, an FPGA 200 and a host computer 300.

[0025] The data acquisition unit 100 is connected to the FPGA 200 through a PCIE bus, and the data storage unit 400 can be set on the FPGA 200, or the data storage unit 400 is set independently of the FPGA 200 and connected to the FPGA 200.

[0026] As follows, the data transmission method will be described in conjunction with the data transmission system, and the specific description is as follows.

[0027] For data packet A and data packet B, when the host computer 300 receives interrupt requests corresponding to different data packets sent by the FPGA 200, it executes the data transfer operation of writing the corresponding data packet in the data storage unit under the control of the FPGA.

[0028] In the data transmission method, data transmission includes data writing and data moving.

[0029] The FPGA 200 collects data from the data collection unit 100 and writes the data into the data storage unit 400 in a round-robin manner in an AB data packet crossover manner.

[0030] The FPGA 200 is connected to the host computer 300 via a PCIE bus communication.

[0031] FPGA 200 writes data packet A into area A of data storage unit 400 (for example, address space is 0x00000000~0x10000000), and after writing data packet A in area A, it sends an interrupt request corresponding to data packet A (interrupt request A for short), notifying host computer 300 to move data packet A from area A.

[0032] FPGA 200 continues to write the B data packet into the B area of ​​the data storage unit 400 (for example, the address space is 0x10000000~0x20000000), and after writing the B data packet in the B area, it sends an interrupt request corresponding to the B data packet (interrupt request B for short), notifying the host computer 300 to move the B data packet from the B area.

[0033] The above writing and moving actions are executed in sequence in a cycle to realize data transmission.

[0034] See also Figure 2 , which is a schematic diagram showing FPGA 200 sending an interrupt request.

[0035] After FPGA 200 sends interrupt request A, it sends interrupt request B after a time difference of △t1. In this way, the time differences between adjacent interrupt requests are recorded in sequence: △t2, △t3, △t4, △t5, △t6 and △t7.

[0036] See also Figure 3 , which shows the monitoring process of the host computer 300.

[0037] The host computer 300 starts monitoring operations on the A data packet and the B data packet respectively.

[0038] The monitoring operations are started for data packet A and data packet B respectively. The monitoring operations for these two data packets are executed in parallel without interfering with each other.

[0039] In some embodiments of the present application, listening threads are triggered for data packet A and data packet B respectively. For example, a first listening thread is triggered for data packet A, and a second listening thread is triggered for data packet B. The first listening thread and the second listening thread are executed in parallel.

[0040] In some embodiments of the present application, a preset monitoring duration is pre-set before monitoring, and the preset monitoring duration is twice the maximum time difference between adjacent interrupt requests normally sent by the FPGA 200 monitored by the host computer 300.

[0041] See also Figure 2 , Figure 4 and Figure 5 , the interrupt request A and the interrupt request B are sent crosswise in the FPGA 200, and the maximum time difference △tMax is selected by recording the time difference between every two adjacent interrupt requests.

[0042] In the time period 2*△tMax from the reception of the interrupt request A or B, FPGA 200 will definitely send the interrupt request A or B. As for whether the upper computer 300 receives it, it is determined through judgment. When it is determined that the interrupt request A or B is not received, the upper computer 300 should also transfer the data when the time period 2*△tMax of the cyclic monitoring is reached. Otherwise, the upper computer 300 will cause packet loss due to failure to receive the interrupt request and no transfer.

[0043] In some embodiments of the present application, see Figure 3 In the process of monitoring the A data packet, the monitoring starts from the time when the interrupt request A of the A data packet is received, and when the interrupt request A is received within the preset monitoring time, the monitoring time is cleared and the monitoring is initiated again.

[0044] See also Figure 4, start timing monitoring from the first interrupt request A on the far left, and receive the second interrupt request A within 2*△tMax, which means that the host computer 300 will transfer data normally. At this time, clear the monitoring time and re-initiate monitoring, that is, start the second cycle monitoring time period 2*△tMax.

[0045] See also Figure 5 , starting from the first interrupt request A on the left, the second interrupt request A is not received within 2*△tMax (that is, Figure 4 When an interrupt request A is received (as indicated by the dotted arrow), after a timeout (i.e., the time reaches 2*△tMax), the host computer 300 performs the A data packet transfer operation (i.e., it transfers the A data packet corresponding to the A area at this time), and re-initiates the monitoring after clearing the monitoring time, i.e., starts the second cycle monitoring time period 2*△tMax.

[0046] Similarly, in the process of monitoring the B data packet, the monitoring is started from the reception of the interrupt request B of the B data packet, and when the interrupt request B is received within the preset monitoring time, the monitoring time is cleared and the monitoring is initiated again.

[0047] When the interrupt request B is not received within the preset monitoring time, the host computer 300 performs the transport operation of the B data packet after timeout, and re-initiates monitoring after clearing the monitoring time.

[0048] In some embodiments of the present application, a monitoring timer may be started to obtain the monitoring duration, and clearing the monitoring duration means restarting the monitoring timer.

[0049] In some embodiments of the present application, in order to better monitor the interrupt request, flags are set corresponding to the A data packet and the B data packet respectively.

[0050] The data transmission process of the A data packet and the B data packet is similar, so the data transmission process of the A data packet is taken as an example for description.

[0051] When the host computer 300 receives the interrupt request A of the data packet A, the flag at the listening point position corresponding to the interrupt request A is set to the first flag (for example, the first flag is 1), and at the same time, the host computer 300 performs the transport operation corresponding to the data packet A. That is, as long as the host computer 300 receives the interrupt request, the flag at the listening point position corresponding to the interrupt request is 1, and the transport operation of the corresponding data packet is performed at the same time.

[0052] See also Figure 6 , which shows that the host computer 300 executes the monitoring process of the A data packet, which is described in detail as follows.

[0053] S1: Determine the flag bit flag, if it is the first flag bit, proceed to S5, otherwise, proceed to S2.

[0054] As described above, during the monitoring process of the upper computer 300, if the upper computer 300 receives the interrupt request normally, the flag of the monitoring point position is 1. At this time, corresponding to the data transmission process, the upper computer 300 will normally perform the data transfer operation, and for the monitoring process, enter S5 to clear the monitoring time and re-initiate the monitoring, that is, restart the monitoring timer and continue to monitor.

[0055] See also Figure 4 When the first interrupt request A on the far left is received by the host computer 300, the flag at the corresponding position is 1 at this time, corresponding to the data transmission process, the host computer 300 performs the data transfer operation, for the monitoring process, the monitoring time is cleared, and the monitoring is re-initiated, that is, the first cycle monitoring time period 2*△tMax is started; when the second interrupt request A is received by the host computer 300, the flag at the corresponding position is 1 at this time, corresponding to the data transmission process, the host computer 300 performs the data transfer operation, for the monitoring process, the monitoring time is cleared, and the monitoring is re-initiated, that is, the second cycle monitoring time period 2*△tMax is started.

[0056] If the flag bit flag is not the first flag bit, it indicates that the host computer 300 has not received the interrupt request A.

[0057] S2: Determine whether the interrupt request A is received within the preset monitoring time. If so, proceed to S5; if not, proceed to S3.

[0058] See also Figure 4 When monitoring the A data packet, after monitoring the first interrupt request A, the timing monitoring starts. When the second interrupt request A is monitored within the preset monitoring time 2*△tMax, it means that during this preset monitoring time 2*△tMax, the second interrupt request A is sent normally and received by the host computer 300. In this way, this part of the data will be normally transferred by the host computer 300.

[0059] Corresponding to the first listening thread, the listening timer is restarted to continue listening for the preset listening time, that is, see Figure 4 , start the second loop monitoring time period 2*△tMax.

[0060] If the interrupt request A is not received within the preset monitoring time period, it indicates that the host computer 300 has not received the interrupt request A.

[0061] S3: Determine whether the monitoring time reaches the preset monitoring time. If so, proceed to S4; if not, return to S2.

[0062] When the monitoring time reaches the preset monitoring time and the interrupt request A is not received, it means that the interrupt request A is not received by the host computer 300 during the preset monitoring time. Figure 5 , when the monitoring time reaches the first cycle monitoring time period 2*△tMax, it is still not received Figure 5 The second interrupt request A shown by the dotted line in the middle, at this time, packet loss is not avoided, the host computer 300 performs the corresponding data packet transfer operation after the timeout, and the flag is set to 0, which is convenient for continuous monitoring, and then restarts the monitoring timer to continue to maintain the preset monitoring time. Figure 5 , start the second loop monitoring time period 2*△tMax.

[0063] If the monitoring time has not reached the preset monitoring time and no interrupt request A is received, it means that the interrupt request A may still be received during the preset monitoring time. Therefore, the process returns to determine whether the interrupt request A is received within the preset monitoring time.

[0064] S4: flag is set to the second flag bit, and the host computer 300 performs a corresponding data packet transport operation.

[0065] When the interrupt request A is not monitored within the preset monitoring time and the monitoring time has reached the preset monitoring time, at this time, the flag corresponding to the failure to receive the interrupt request A is set to the second flag bit (for example, the second flag bit is 0), that is, the flag corresponding to the data monitoring point position where the monitoring time has reached the preset monitoring time is set to the second flag bit.

[0066] At the same time, for the data transmission process, the host computer performs the transport operation on the A data packet to avoid packet loss when the host computer 300 does not receive the interrupt request A.

[0067] S5: Clear the monitoring duration, restart monitoring, and return to S1.

[0068] In some embodiments of the present application, when the host computer 300 normally receives the interrupt request A (for example, see Figure 4 In the example, when the first interrupt request A on the left is received, the monitoring timer is restarted and the monitoring for the preset monitoring time is continued.

[0069] In some embodiments of the present application, the host computer 300 receives an interrupt request A (for example, see Figure 4 In the figure, when the second interrupt request A on the left is received, it means that the interrupt request A is received normally during the preset monitoring time, and the monitoring timer is restarted to continue monitoring for the preset monitoring time.

[0070] In some embodiments of the present application, when the host computer 300 does not receive the interrupt request A within the preset monitoring time and the time has reached the preset monitoring time (for example, see Figure 5 In the example, when the second interrupt request A shown by the dotted line is not received, the monitoring timer is restarted and the monitoring for the preset monitoring time is continued.

[0071] In some embodiments of the present application, since the FPGA 200 is written in an AB data packet crosswise manner, the host computer 300 also uses the AB data packet crosswise manner to carry data, that is, the host computer 300 carries the A data packet and then the B data packet, and then the A data packet, and so on, until the reading is completed and the complete data of the ABAB... data packet crosswise is formed, see Figure 7 .

[0072] In some embodiments of the present application, a buffer (not shown) is opened in the software of the host computer 300, and the data moved by the host computer 300 is placed in the buffer. When the size of the buffer reaches a specified size, the data is released from the buffer.

[0073] The data transmission method involved in the present application avoids the phenomenon of packet loss due to failure of the host computer 300 to receive the interrupt request by adding interrupt monitoring based on PCIE interrupt, and avoids data exchange by monitoring the A data packet and the B data packet respectively.

[0074] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for a person skilled in the art to modify the technical solutions described in the aforementioned embodiments, or to replace some of the technical features therein by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions claimed to be protected by the present invention.

Claims

1. A data transmission method based on PCIE interruption, characterized in that: include: For data packet A and data packet B, when the host computer receives interrupt requests corresponding to different data packets sent by FPGA, it executes the data transfer operation of the corresponding data packet in the data storage unit; The host computer starts monitoring operations on data packets A and B respectively; During the monitoring process, the monitoring starts from the time when the interrupt request of the corresponding data packet is received, and when the interrupt request is received within the preset monitoring time, the monitoring time is cleared and the monitoring is initiated again; When no interrupt request is received within the preset monitoring time, the host computer performs the corresponding data packet transfer operation after timeout, and re-initiates monitoring after clearing the monitoring time; Among them, data transmission includes data writing and data transportation. The FPGA adopts AB data packet cross mode to write into the data storage unit, and the host computer adopts AB data packet cross mode to transport the corresponding data packet. The preset monitoring time is twice the maximum time difference between adjacent interrupt requests normally sent by the FPGA.

2. The data transmission method according to claim 1, characterized in that: When the host computer monitors data packets A and B, two parallel first monitoring threads and second monitoring threads are triggered and started; The first monitoring thread is used to monitor the A data packet, and the second monitoring thread is used to monitor the B data packet.

3. The data transmission method according to claim 1, characterized in that: During the monitoring process, flags are set for different data respectively; When the host computer receives an interrupt request corresponding to the data packet, the flag is set to the first flag, and the host computer performs a transport operation of the corresponding data packet; During the monitoring process, proceed as follows: S1: Check the flag bit flag, if it is the first flag bit, proceed to S5, otherwise, proceed to S2; S2: Determine whether an interrupt request is received within the preset monitoring time. If so, proceed to S5; if not, proceed to S3; S3: Determine whether the monitoring time reaches the preset monitoring time. If yes, proceed to S4; if no, return to S2; S4: flag is set to the second flag bit, and the host computer performs the corresponding data packet transfer operation; S5: Clear the monitoring duration, restart monitoring, and return to S1.

4. The data transmission method according to claim 1, characterized in that: The FPGA controls writing data packet A into area A of the data storage unit, and writing data packet B into area B of the data storage unit; The A data packet carried by the host computer from area A and the B data packet carried from area B are cross-synthesized into complete data and stored in the buffer of the host computer software; When the size of the buffer reaches a specified size, the complete data is released from the buffer.

5. A data transmission system based on PCIE interruption, characterized in that: include: A data acquisition unit, which is used to collect data; an FPGA connected to a data acquisition unit, and outputting an interrupt request corresponding to the A data packet after the FPGA writes the A data packet collected by the data acquisition unit into the data storage unit, and outputting an interrupt request corresponding to the B data packet after the FPGA writes the B data packet collected by the data acquisition unit into the data storage unit, wherein the FPGA writes the A data packet into the data storage unit in an interleaved manner; A host computer is connected to the FPGA through a PCIE bus communication. When receiving an interrupt request of a corresponding data packet sent by the FPGA, the host computer performs a transport operation of the corresponding data packet, wherein the host computer transports the corresponding data packet in an AB data packet cross mode; The host computer also starts monitoring operations on data packets A and B respectively; During the monitoring process, the monitoring starts from the time when the interrupt request of the corresponding data packet is received, and when the interrupt request is received within the preset monitoring time, the monitoring time is cleared and the monitoring is initiated again; When no interrupt request is received within the preset monitoring time, the host computer performs the corresponding data packet transfer operation after timeout, and re-initiates monitoring after clearing the monitoring time; The preset monitoring time length is twice the maximum time difference between adjacent interrupt requests normally sent by the FPGA.

6. The data transmission system according to claim 5, characterized in that: When the host computer monitors data packets A and B, two parallel first monitoring threads and second monitoring threads are triggered and started; The first monitoring thread is used to monitor the A data packet, and the second monitoring thread is used to monitor the B data packet.

7. The data transmission system according to claim 5, characterized in that: During the monitoring process, flags are set for different data respectively; When the host computer receives an interrupt request corresponding to the data packet, the flag is set to the first flag, and the host computer performs a transport operation of the corresponding data packet; During the monitoring process, proceed as follows: S11: Determine the flag bit flag, if it is the first flag bit, proceed to S15, otherwise, proceed to S12; S12: Determine whether an interrupt request is received when the monitoring time is within the preset monitoring time. If so, proceed to S15; if not, proceed to S13; S13: Determine whether the monitoring time reaches the preset monitoring time, if yes, proceed to S14, if no, return to S12; S14: flag is set to the second flag bit, and the host computer performs the corresponding data packet transfer operation; S15: Clear the monitoring time, restart monitoring, and return to S1.

8. The data transmission system according to claim 5, characterized in that: The host computer also includes: Buffer, FPGA controls writing data packet A into area A of the data storage unit, and writing data packet B into area B of the data storage unit. The data packet A carried from area A and the data packet B carried from area B by the host computer are cross-synthesized into complete data and stored in the buffer of the host computer software; When the size of the buffer reaches a specified size, the complete data is released from the buffer.

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