Apparatus for processing incoming and / or outgoing data elements

Abstract

An apparatus for processing incoming and / or outgoing data elements. The invention relates to a device (200) for cyclically processing incoming and / or outgoing data elements (11) representing numerical values and / or logical values associated with an upper layer application.

Description

Technical Field

[0001] The present invention relates to an apparatus for processing incoming and / or outgoing data elements. In addition, the present invention also relates to a system, a method, a computer program, a data processing apparatus and a computer-readable storage medium. Background Art

[0002] IO-Link is a communication protocol standardized in IEC 61131-9. It is often used in industrial fieldbus environments to connect sensors or actuators with various fieldbus systems. Special linking devices called IO-Link masters are used to connect IO-Link devices to various fieldbus systems. IO-Link communication is based on a simple point-to-point protocol. Therefore, IO-Link devices only need to support a single simple interface and can still interact with various host systems via a suitable IO-Link master. IO-Link masters are not only suitable for fieldbuses, but also for other client systems such as web browsers, MQTT servers, AI cloud systems and other IT-based technologies such as OPC UA or JSON.

[0003] The information transmitted via IO-Link is based on telegrams called m-sequences. An m-sequence is always initiated by the IO-Link master with a first part in a predefined cycle or period and answered by the IO-Link device responder with a second part. The m-sequence contains the data elements that are transmitted in each cycle. These data elements are called cyclic data or process data. They also contain elements that are usually spread over several cycles. These elements are only transmitted when requested - that is why they are called on-request or acyclic data. On-request data is used, for example, for parameter or event messages.

[0004] Different m-sequence types are used to specify different fixed-size data elements. Which m-sequence types are used during IO-Link communication is defined by the IO-Link device. An IO-Link master with, for example, 8 IO-Link ports allows up to 8 IO-Link devices to be connected. The characteristics of the connected IO-Link devices are described in an electronic data sheet called an IO-Link device descriptor "IODD" file. Each IO-Link device type is uniquely identified by an address consisting of a 16-bit vendor ID and a 24-bit device ID. This identification is listed in the IODD and can also be read out from the IO-Link device via the IO-Link protocol.

[0005] Current IO-Link systems are very successful and widely used, especially in combination with fieldbus systems and programmable logic controllers "PLC".

[0006] There are various disadvantages associated with the use of communication systems, and IO-Link in particular. This includes situations such as a lack of host ports. This occurs when additional sensors or actuators need to be added to expand or improve functionality, but all ports of the current host are already in use and adding a new host is not enough. Another disadvantage occurs when a given device needs to be replaced by a similar device with similar or comparable characteristics but a different cyclic data structure.

[0007] Providing low-latency feedback from sensors to actuators without using a PLC as a client is another challenge. It is also challenging to implement simple sequencing as an extension of the low-latency feedback that includes execution loops and decision making. Another challenge is meeting the requirements of clients that require data in specific pre-processed data formats that are not provided by the connected IO-Link devices.

[0008] Existing solutions are devices like the "BallufBNI IOL-302-002-K006" that allow the expansion of IO-Link devices with expander ports. However, these solutions are not universal because only specific devices can be connected to the expander ports. Summary of the invention

[0009] According to aspects of the invention, a device, a system, a method, a computer program, a data processing device and a computer-readable storage medium are provided. Further features and details of the invention are disclosed in the corresponding dependent claims, the description and the drawings. Features and details described in the context of the device according to the invention also correspond to the system, the method, the computer program, the data processing device and the computer-readable storage medium, and vice versa in each case.

[0010] According to one aspect of the invention, a device is provided for processing incoming and / or outgoing data elements, in particular cyclically. The data elements may represent numerical and / or logical values ​​associated with, in particular dedicated to, upper layer applications, such as industrial automation applications and / or the control and / or evaluation of sensors and / or actuators. In other words, the numerical and / or logical values ​​may be used in the upper layer applications and in particular evaluated and / or generated in the upper layer applications, for example for controlling an automation system. The device may be configured as an electronic device and / or a computer system and / or may comprise a computer program.

[0011] The apparatus may comprise a distributor block, also referred to as a distributor, for converting at least one or more (these) data elements into at least one or more input scalar signals (also referred to as input scalars) of a common data type (particularly IEEE 754 floating point) after linear operations (on the data elements) and / or into at least one or more Boolean signals (also referred to as bools or Boolean signals) after additional quantization. The distributor block may be configured as at least a part of a computer program and / or an electronic circuit.

[0012] The device may include a combiner block, also referred to as a combiner, for performing at least one or more combination operations. Each combination operation may include combining at least one or more of the input scalar signals into a (single) output scalar signal. In other words, the combination operation may combine multiple input scalar signals to create a single output scalar signal, also referred to as an output scalar. Therefore, in the case of performing multiple combination operations, each of them can create a single output scalar signal derived from a combination of at least one or more of the input scalar signals. The combiner block may be configured as at least a part of a computer program and / or an electronic circuit.

[0013] The apparatus may comprise a merger block for reconverting (or converting) at least one or more of the output scalar signal and / or Boolean signal and / or another output based on these signals into one or more data elements after a linear operation and / or a quantization step, in particular on these signals / outputs. In other words, the merger block may reconvert the output signal or Boolean signal into one or more data elements after a linear operation and an optional quantization step. The merger block may be configured as at least a part of a computer program and / or an electronic circuit.

[0014] The device may include a logic block for performing a logic operation on at least one or more Boolean signals, and in particular for providing both an input and an output for a Boolean signal. In other words, the logic block may perform a logic operation on a Boolean signal, and may provide both an input and an output for a Boolean signal. The logic block may also be configured as at least a part of a computer program and / or an electronic circuit.

[0015] The device may also include a processing block, which can be inserted between the distributor block and the combiner block, in particular into one or more input scalar signals, or between the combiner block and the merger block, in particular into one or more output scalar signals. In other words, the processing block can process the input / output scalar signal into which the processing block is inserted. The processing blocks can be inserted into the input scalar signal individually or collectively. Each processing block can be configured as at least a part of a computer program and / or an electronic circuit.

[0016] The device can use the described block structure to provide a configuration logic adapter and thereby allow flexible, reliable and easily configurable processing of data elements. Specifically, the device can be configured as an aggregator device and / or an IO-Link device and / or a fieldbus device and / or a network device and / or a communication device.

[0017] The device according to the present invention can be configured as a communication device, in particular an IO-Link device and / or for a communication system, which is configured to be connected to a main device, in particular an IO-Link host, and to at least one auxiliary device, in particular an IO-Link device of another type. The main device can provide a communication system, such as IO-Link, for exchanging data with auxiliary devices. The communication system can refer to a digital communication network that allows real-time data exchange between auxiliary devices in the form of industrial devices (such as sensors, actuators and controllers). For example, it can be used to connect devices in a manufacturing or process control environment, allowing efficient and reliable communication between devices. The communication system can be configured as a point-to-point communication system, thereby distinguishing itself from a fieldbus system. For this reason, in particular, IO-Link uses an IO-Link host to connect (point-to-point) to one or more IO-Link devices, i.e., sensors or actuators. The IO-Link host can provide an interface to a higher-level unit such as a higher-level controller (PLC), and control the communication with the connected IO-Link device. The IO-Link host can have one or more IO-Link ports, and only one device can be connected to these ports at a time. This can also be a "hub" which, as a concentrator, can connect classic switch sensors and actuators. In addition, the communication system can be configured as a wired communication system. Unlike wireless solutions, this communication system can therefore use a cable to establish a physical connection between the host port and the device.

[0018] Typically, (master) master devices are used for the interface connection between various fieldbuses or similar systems and multiple (auxiliary) devices. The master can be responsible for controlling the communication with the auxiliary devices (especially IO-Link), including data transmission, configuration and parameterization. Optionally, the master can also provide power to the auxiliary devices, thus achieving simplified and cost-effective wiring. The master can also act as an active peer, connected to 1 to n (auxiliary) devices via ports and provide an interface to the gateway to a higher-level communication system or a higher-level unit such as a PLC (Programmable Logic Controller).

[0019] IO-Link refers in particular to the standardized communication protocol standardized in IEC 61131-9 for connecting sensors and actuators to industrial automation systems. It enables bidirectional communication between devices and control systems, allowing real-time data exchange and parameterization. IO-Link is supported by a large number of industrial equipment suppliers. This makes it a cost-effective and flexible solution for industrial automation applications.

[0020] MCU (abbreviation of microcontroller unit) can be used to execute software, that is, at least one computer program, in particular a computer program according to the present invention, and / or is referred to as an application. MCU may include a processor, a memory and input / output peripherals. The application may implement a standard host interface (SMI) for superior communication and an IO-Link host interface for communicating with the device. The information transmitted on IO-Link may be based on a telegram referred to as an m-sequence. The m-sequence may always be initiated by the IO-Link host in a predefined cycle or period with a first part and answered by the IO-Link device transponder with a second part. The m-sequence may contain data elements transmitted in each cycle. These data elements are referred to as cyclic data or process data. They also contain elements that are usually distributed in multiple cycles. These elements can only be transmitted upon request-that is why they are referred to as on-request or non-cyclic data. On-request data is used, for example, for parameter or event messages. The processing unit of the device according to the present invention may also be configured as (another) MCU.

[0021] Different m-sequence types can be used to specify data elements of different fixed sizes. Preferably, which m-sequence types are used during IO-Link communication is defined by the IO-Link device. If an IO-Link master sends process data "PD" to a (auxiliary) device, these data can be called in the IO-Link interface and system specification PDOut. If the IO-Link master receives PD, these data can be called PDIn. The total size of the process data of an IO-Link device is in particular limited to 32 bytes PDOut and 32 bytes PDIn. If the direction of the data flow is not important for consideration, the suffix Input / Output can be omitted in the subsequent description.

[0022] A PHY may be provided, which is in particular a specific circuit connected to the MCU. It modifies the electrical characteristics of the MCU signal to a signal that complies with the IO-Link physical layer. Therefore, PHY refers in particular to the physical layer of the communication protocol. It may be the first layer of the ISO-OSI reference model, which provides mechanical, electrical, functional and procedural means to activate, maintain and deactivate the physical connection for bit transmission between data link entities. It may be responsible for transmitting electrical signals between the IO-Link host and the IO-Link device through a physical medium such as a wire or cable. The PHY layer may define the electrical characteristics of the communication, such as voltage levels, signal timing and signal encoding, and ensure reliable and accurate data transmission.

[0023] The physical layer may utilize a 3-wire connection system where three wires are used as follows: one for power, one for ground, and one (C / Q) for switching signals or SDCI (Single-Point Digital Communications Interface) communications. The physical layer is responsible for configuring the C / Q lines and associated line drivers and receivers for a specific port.

[0024] It is also possible for the device and / or method according to the invention that the processing blocks are configured to process one or more input scalar signals and / or one or more output scalar signals into which they are inserted, in particular processing blocks that perform digital filtering operations or spectral transformations such as Fast Fourier Transformations. Thus, the processing blocks can be constructed in such a way that the number of scalar signals is maintained, which enables a stable and resource-saving processing.

[0025] It is also possible that the blocks are configured to be processed in a well-defined order, preferably in a way that any input scalar of the current block is evaluated before evaluating the current block. This may have the advantage that the processing of the blocks is more reliable and / or more resource-efficient, in particular the results of previous blocks may be used as input to subsequent blocks in the same cycle. This may increase the overall accuracy of the system and reduce the likelihood of errors.

[0026] It is also possible that the apparatus is configured to process incoming and / or outgoing data elements cyclically in such a way that a Boolean signal evaluated in one cycle is given as input to a subsequent block in the next cycle. This may have the advantage that processing of data elements is more efficient and faster, since the Boolean signal may be passed on continuously without unnecessary delays.

[0027] At least one block, in particular a logic block, may also be configured based on a configuration specification. The configuration specification may be customizable by a user so that processing and in particular the insertion of logic operations and / or processing blocks are configurable. In particular, the configuration specification may be stored in a storage medium. Configuration may also be performed by loading a memory dump into the device. The configuration in the memory dump may then be associated with the operation of the device in a resource-efficient manner.

[0028] It is also possible that the apparatus provides a configurable logic adapter for processing, preferably converting and / or selecting data elements of data received from at least one or more secondary devices, and processing and / or combining these data elements to generate data to be sent to the primary device. This allows the apparatus to provide communication between devices, for example for data aggregation.

[0029] The device may also comprise and / or provide an interface, in particular an electronic and / or graphic and / or human-machine interface. An interface may be provided for configuring processing by a user, in particular configurable logic, so that the processing of the data elements is adapted to a higher-level application, in particular the evaluation and / or control of at least one or more auxiliary devices, in particular sensors and / or actuators.

[0030] Another aspect of the present invention is a system for providing communication in an automation system. The system may include at least one of the following:

[0031] - a superordinate unit, such as a programmable logic controller, for providing upper-level applications, especially automated control of industrial processes of the automation system,

[0032] - a master device, connected to said superordinate unit, in particular a programmable logic controller, for providing a communication system,

[0033] at least one or more auxiliary devices for being controlled and / or evaluated by the superordinate unit, in particular a programmable logic controller, via the master device in order to at least partially execute the upper-level application,

[0034] - an arrangement according to the invention for connecting said at least one or more auxiliary devices to said main device, thereby providing data exchange for control and / or evaluation of said auxiliary devices via said communication system.

[0035] Another aspect of the present invention is a method for cyclically processing incoming and / or outgoing data elements. As described above, the data elements may represent numerical and / or logical values ​​associated with upper layer applications. The method may include the following steps or at least one of the following steps, and the steps are particularly performed cyclically:

[0036] - converting at least one or more (the) data elements into at least one or more input scalar signals of a common data type (in particular IEEE 754 floating point) after a linear operation and / or into at least one or more Boolean signals after an additional quantization, said conversion being performed in particular by a distributor block,

[0037] - performing at least one or more combination operations, each combination operation may comprise combining at least one or more of said input scalar signals into one (single) output scalar signal, said combination operation may in particular be performed by a combiner block,

[0038] - after the linear operation and / or the quantization step, reconverting at least one or more of the output scalar signal and / or Boolean signal and / or outputs based on these signals into one or more data elements, said reconversion may in particular be performed by a merger block,

[0039] - performing a logic operation on at least one or more of said Boolean signals and in particular providing both an input and an output for said Boolean signals, said logic operation in particular being executable by a logic block,

[0040] - inserting the processing block between a distributor block and a combiner block, in particular into one or more input scalar signals, or between a combiner block and a merger block, in particular into one or more output scalar signals.

[0041] Therefore, the method according to the invention brings the same advantages as have been described in detail with reference to the device according to the invention. The method steps can be performed at least in part by a computer program and / or an electronic circuit. For this purpose, each of the above-mentioned blocks can be configured as a part of a computer program and / or an electronic circuit.

[0042] The processing blocks may process one or more input scalar signals and / or one or more output scalar signals into which they are inserted. Alternatively or additionally, the number of scalar signals may not change when passing through the processing blocks. This has the advantage of efficient processing using devices with limited resources.

[0043] Blocks can be processed in a well-defined order, preferably in a way that any input scalar of the current block is evaluated before evaluating the current block. Alternatively or additionally, a Boolean signal evaluated in one cycle can be given as input to a subsequent block in the next cycle. This also allows efficient processing using devices with limited resources.

[0044] Processing of data elements may include:

[0045] - inputting the data elements to a set of processing blocks, thereby generating outputs of the set of processing blocks,

[0046] - generating a modified data element based on said output of said set of processing blocks,

[0047] Therein, the connection and / or structure of the set of processing blocks may be defined by a customizable configuration of logic.

[0048] The device may also be configured to connect at least one or more auxiliary devices to a main device. The device may be configured as an IO-Link capable device for insertion between the at least one or more auxiliary devices (each of which is configured as an IO-Link device) and a main device (the main device is configured as an IO-Link host). The device may include a device port configured to be connected to the main device. In addition, the device may include at least one or more host ports configured to be connected to at least one or more auxiliary devices. In addition, it is conceivable that the device includes a processing unit, which is configured to establish data communication with the main device via the device port, and to establish data communication with the auxiliary device via at least one or more host ports, thereby providing data exchange between the auxiliary device and the main device via the device, wherein each data communication is configured as point-to-point communication. In addition, the processing unit may be configured to use configurable logic to process, preferably aggregate, data received from at least one or more auxiliary devices for point-to-point communication with the main device via the device port. The processing unit may also be configured to perform the steps of the method according to the present invention.

[0049] Another aspect of the invention may be a method for connecting at least one or more secondary devices to a primary device via an apparatus, the method comprising the following steps, in particular performed by an apparatus according to the invention and / or a system according to the invention:

[0050] - receiving data from said at least one or more auxiliary devices via at least one or more host ports of said apparatus, said at least one or more host ports being configured to be connected to said auxiliary devices, in particular by wire,

[0051] - processing the received data for point-to-point communication between the apparatus and the master device, the processing being performed using configurable logic,

[0052] - providing modified data based on the processing, the modified data being specific to the data received from each of the at least one or more auxiliary devices and to the current configuration of the logic,

[0053] - sending the modified data to the master device via a device port of the apparatus, the device port being configured to be connected to the master device, in particular by a wired connection.

[0054] In another aspect of the invention, a computer program, in particular a computer program product, may be provided, which comprises instructions which, when executed by a computer, cause the computer to perform the method according to the invention. Thus, the computer program according to the invention may have the same advantages as have been described in detail with reference to the method according to the invention.

[0055] The computer may be a data processing device that executes a computer program. The computer may include at least one processor that can be used to execute the computer program. In addition, a non-volatile data memory may be provided, in which the computer program can be stored and from which the processor can read the computer program for execution.

[0056] According to another aspect of the invention, a computer readable storage medium may be provided, comprising a computer program according to the invention. The storage medium may be formed as a data storage device, such as a hard disk and / or a non-volatile memory and / or a memory card and / or a solid state drive. The storage medium may, for example, be integrated into a computer.

[0057] Furthermore, the method according to the present invention may be realized as a computer-implemented method. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Other advantages, features and details of the invention will be apparent from the following description, in which embodiments of the invention are described in detail with reference to the accompanying drawings. In this respect, the features mentioned in the claims and in the description may each be essential to the invention individually or in any combination. In the drawings:

[0059] Figure 1 Parts of an apparatus according to an embodiment of the invention are shown.

[0060] Figure 2 Further parts of an apparatus according to an embodiment of the invention are shown.

[0061] Figure 3 A visualization of a method according to an embodiment of the present invention is shown.

[0062] Figure 4 An example of an IO-Link process data structure is shown.

[0063] Figures 5 to 13 Further visualizations of a method according to an embodiment of the invention and of a device according to the invention are shown.

[0064] Fig.14 A method, a computer program, a processing device and a storage medium according to embodiments of the present invention are shown.

[0065] Reference numerals list

[0066] 1 Host Port

[0067] 1a Primary (secondary) host port

[0068] 1b Secondary (auxiliary) host port

[0069] 1c Third (secondary) host port

[0070] 1d Fourth (secondary) host port

[0071] 1ao Output port

[0072] 1bo Output port

[0073] 1co output port

[0074] 1do output port

[0075] 2 Device port, device port connector, port to external host

[0076] 2i Input Port

[0077] 2o Output Port

[0078] 1ai input port

[0079] 1bi input port

[0080] 1ci input port

[0081] 1di input port

[0082] 3 Device, Aggregator Equipment, AGG

[0083] 4 Device PHY

[0084] 5 Microcontroller unit, controller unit

[0085] 6,6a-6d Host PHY

[0086] 7 External IO-Link master, master device, external host

[0087] 7a 7 ports

[0088] 7b Remaining ports

[0089] 8 IO-Link Device Stack

[0090] 8a,8b,8c,8d Auxiliary devices

[0091] 9 AGG equipment applications, IO-Link equipment, auxiliary equipment

[0092] 10a IO-Link Master Interface "SMI", Agg Device Application

[0093] 10b IO-Link Master Stack

[0094] 11 Data elements of AGG device ports

[0095] 11a,11b Data elements for embedded host ports

[0096] 11c Data Elements

[0097] 11d Data Elements

[0098] 11e Data Elements

[0099] 11f Data Elements

[0100] 12a Feedback Routing

[0101] 12b Transmission Routing

[0102] 13 Distributor

[0103] 14 Combiners

[0104] 14a Combiner row a

[0105] …

[0106] 14n Combiner row n

[0107] 15 Processing Blocks

[0108] 15a Binarizer Block

[0109] 16 Merger Block

[0110] 17 Logic Blocks

[0111] 18 Signal Generator

[0112] 19 CLA Profile

[0113] 20 CLA

[0114] 21 IODD File

[0115] 22 PBD files

[0116] 23 Selected Data Elements

[0117] 24 Arranger

[0118] PLC Programmable Logic Controller

[0119] 100 External IO-Link

[0120] 101 IO-Link to device 8a

[0121] 102 IO-Link to device 8b

[0122] 103 IO-Link to device 8c

[0123] 104 IO-Link to device 8d

[0124] 105 Scalar signal

[0125] 105a Input-Scalar

[0126] 105b Output - Scalar

[0127] 106 Boolean signals

[0128] 200 CLA

[0129] 201 Parser

[0130] 300 Methods

[0131] 301-304 Methods and Steps 400 Superior system, such as PLC

[0132] 410 Data processing device

[0133] 420 Computer Programs

[0134] 430 Storage Media

[0135] 500 Communication Systems DETAILED DESCRIPTION

[0136] Figures 1 to 14 , especially Figure 6A device 200 for cyclically processing incoming and / or outgoing data elements 11 according to an embodiment of the present invention is shown. The data elements 11 may represent numerical and / or logical values ​​associated with an upper layer application. The device 200 may include a distributor block 13, in particular a distributor group, which converts at least one or more of the data elements 11 into at least one or more input scalar signals 105a of a common data type (in particular IEEE 754 floating point) after linear operations and / or into at least one or more Boolean signals 106 after additional quantization. In addition, the device may include a combiner block 14 that performs at least one or more combination operations, each combination operation including combining at least one or more of the input scalar signals 105a into one output scalar signal 105b. In addition, the device may include a merger block 16, which converts at least one or more of the output scalar signals 105b and / or Boolean signals 106 and / or outputs based on these signals 105b, 106 back into one or more data elements 11 after linear operations and / or quantization steps. The device may further comprise a logic block 17, which performs a logic operation on at least one or more of the Boolean signals 106, and in particular provides both an input and an output for the Boolean signal 106. Furthermore, the device may comprise a processing block 15, which is configured to be inserted between the distributor block 13 and the combiner block 14, in particular into one or more input scalar signals 105a, or between the combiner block 14 and the merger block 16, in particular into one or more output scalar signals 105b.

[0137] There are several failure scenarios for traditional IO-Link setups. The first and simplest failure scenario is the lack of IO-Link master ports in a given industrial setup. This situation arises when additional sensors or actuators need to be added to expand or improve functionality, and all ports of the current IO-Link master are used and adding additional masters is not appropriate. The second failure scenario arises when a given device needs to be replaced by a similar device with similar or comparable characteristics but different loop data structure. The third failure scenario comes from the requirement for low latency feedback from sensors to actuators, especially in configurations where no PLC is used as a client. Simple sequencing is an extension of low latency feedback that provides a means for executing loops and making decisions. The fourth failure scenario occurs on the client side of an IO-Link system, which requires data in a specific, possibly pre-processed format that does not conform to the data format provided by the connected IO-Link device. These scenarios are addressed by embodiments of the present invention, particularly what is called an aggregator device "AGG" and the included configurable logic adapter "CLA".

[0138] Figure 1A schematic example view of an AGG device 3 is shown, which has one device port 2 that can be connected to an IO-Link master 7 and a plurality of master ports 1 a to 1 d that can be connected to IO-Link devices 8 .

[0139] Figure 2 The core components of the AGG device according to an embodiment of the present invention are shown. The device PHY 4 is an electronic circuit that converts IO-Link signals exchanged with an external IO-Link host 7 via a device connector 2 into signals compatible with a microcontroller unit 5 "MCU". The microcontroller unit executes software for exchanging data with the external host 7, and it executes software for exchanging data via a host PHY 6 and a host port 1 IO-Link device 8.

[0140] Figure 3 An exemplary basic structure of software executed by the MCU 5 is depicted. The IO-Link data exchange 100 with an external IO-Link master is handled by the IO-Link device stack 8. Another software module is the IO-Link master stack 10b, which is responsible for the IO-Link data exchange 101, 102, 103, 104 with the connected IO-Link devices 8. The AGG device application 9 including the configurable logic adapter 200 is responsible for processing the data exchanged with the IO-Link device stack 8 on the one hand and the IO-Link master 10b on the other hand. The data exchange with the IO-Link master 10b uses a standardized host interface 10a called "SMI".

[0141] Limitations of AGG Devices

[0142] According to an embodiment of the invention, if the IO-Link master sends process data "PD" to the device, these data are called in the IO-Link interface and system specification PDOut. If the IO-Link master receives PD, these data are called PDIn. The total size of the process data of an IO-Link device is limited to 32 bytes PDOut and 32 bytes PDIn. If the direction of the data flow is not important for some consideration, the suffix Input / Output is omitted in the subsequent description.

[0143] One limitation of the AGG device according to an embodiment of the invention is based on the fact that the sum of the accumulated PDIn / PDOut of the four arbitrary IO-Link devices 8 connected to the AGG device 3 can be up to 128 bytes in each direction. In this case, it is necessary to select which process data is to be transmitted to the external host 7 via the IO-Link interface 100. Another task of the AGG device application 9 is to make the corresponding selection.

[0144] According to an embodiment of the present invention, another limitation of the AGG device comes from the duration required to transmit a certain amount of data serialized over the IO-Link line. In the IO-Link System and Interface Specification, an estimated expression for this duration is given in Chapter A.3.6 M Sequence Time.

[0145] t M-sequence =11(m+n)T BIT +t A +t1(m-1)+t2(n-1)

[0146] Here, m is the number of bytes sent from the IO-Link master to the device, n is the number of bytes from the device to the IO-Link master, and T BIT is the duration required to transmit one bit, where 1T BIT ≤t A ≤10T BIT ,0T BIT ≤t1≤10T BIT and 0T BIT ≤t2≤3T BIT .

[0147] This formula shows how the time to transfer the amount of data increases. For the minimum cycle time of an IO-Link device the following inequality must always hold true t cycle >t M-sequence .

[0148] Therefore, if the processing data size of the AGG device is large, the minimum cycle time of the AGG device 3 may become larger than the minimum cycle time of the connected IO-Link device 8 .

[0149] Direct process data mapping

[0150] As already mentioned, PDIn or PDOut has a fixed byte length for a given m-sequence type.The structure of the process data as defined in the IODD divides the process data into smaller elements of a given data type, here called data elements.

[0151] Figure 4 An example of a typical process data structure is given in . Here, the process data with a total size of 4 bytes is divided into 5 typed data elements11: a 16-bit integer representing the distance, 2 Booleans representing the threshold, a 14-bit integer representing the level, and an 8-bit integer representing the temperature. The data structure and physical units of the data elements are specified in the electronic data sheet IODD of the IO-Link device.

[0152] According to an embodiment of the present invention, direct mapping between process data between the AGG device port 2 and the AGG host port can be performed as follows: Fig.11 This is done in the 2-step method shown in for two connected devices. In a first step, data elements 11a and 11b of the device 8 connected to the incoming AGG host ports 1a, 1b may be selected. A given PD structure based on the connected device specified in the IODD is selected. In a second step, these data elements may be combined to form a process data structure for the AGG device port 2 as a combination 11 of the selected data elements 11a and 11b. The combination of data elements is specified with the help of a configuration tool that allows combining PD elements in a flexible way.

[0153] However, direct mapping of process data may only provide a solution for the first scenario (port expansion).

[0154] Configurable logic adapter

[0155] Other scenarios require more complex device applications that allow routing and processing of process data according to embodiments of the invention. A practical solution to this task presents considerable challenges, as it must meet certain requirements to be generally applicable to automation systems. These requirements are:

[0156] The Device Application shall be available to any IO-Link device connected to port 1 of the Host8.

[0157] The device application 9 should allow routing of process data elements 11 between one IO-Link device and other IO-Link devices 12a and between an IO-Link device and an external host 12b, such as Figure 5 shown.

[0158] Configurable Logic Adapter CLA

[0159] The embodiments of the present invention provide a new solution to these requirements. The structure is referred to herein as a configurable logic adapter "CLA" 200, which can be Figure 6 A portion of the device shown in Application 9. The CLA is based on a fixed structure. Only one configuration is required to address the required scenario. In particular, no software changes are required. Therefore, the CLA can be verified once for its basic functionality and stability, because reconfiguration of the CLA will not affect the basic properties of the CLA, such as stability or integrity.

[0160] CLA Data Types

[0161] According to an embodiment of the present invention, CLA uses only two data types, called scalar 105 and Boolean 106, which are handled differently. Scalars can be used to transmit numerical process data in a universal manner. Therefore, their value range should be large enough to handle all numerical process data without significant loss of precision. In a preferred implementation of CLA, the data type FLOAT32 "floating point - float" according to IEEE754 is used. However, other data types (such as DOUBLE) can also meet these requirements.

[0162] According to an embodiment of the invention, the conversion of process data elements 11 to scalars changes their type to floating point. Conversion to scalars or Booleans is possible only for process data element types: BooleanT, UIntegerT, IntegerT and Float32T (see A.1.4 of the IO-Link Interface and System Specification). The remaining types (TimeT, TimeSpanT, StringT and OctetStringT) can in particular only be used for the aforementioned direct mapping and are not handled by the CLA.

[0163] The logic value 106 can be represented by two states, "true" and "false". In a preferred implementation of the CLA, these states are mapped to bytes, where a byte value of 0 is mapped to "false" and any other byte value is mapped to "true". Both data types can be used to transmit digital information within the CLA.

[0164] CLA Block

[0165] According to an embodiment of the present invention, a CLA block can have a scalar or Boolean as input data and generate a new scalar or Boolean as output data. The process of generating output data can be defined by an algorithm that executes a finite number of steps. In this context, the execution of the steps can be triggered by an event called a "block cycle".

[0166] Using the main loop “Loop”, all block loops of all CLA blocks can be executed in a well-defined configuration order at a specific point in time.

[0167] In a preferred embodiment of the invention, the execution order is chosen in such a way that any scalars that are input to the current block must be evaluated before the current block is executed.The initial input scalars from the data elements are all sampled in the main loop as the start of the loop.

[0168] In a preferred embodiment of the present invention, six types of blocks are defined.

[0169] (1) The distributor block 13 is characterized by taking a process data element as input and generating a scalar or Boolean as output.

[0170] (2) The processing block 15 is characterized by taking a scalar or Boolean as input and generating a scalar or Boolean. In a preferred embodiment of the present invention, a processing block must have the same number of incoming and outgoing scalars.

[0171] (3) Binarizer block 15a is a special processing block characterized by having at least one input scalar, no output scalar, and at least one Boolean output.

[0172] (4) Logic blocks 17 having only Booleans as input or output.

[0173] (5) Combiner 14, characterized by having multiple input scalars but only one output scalar.

[0174] (6) The merger block 16 is characterized by having an input scalar that can be routed to various output process data elements.

[0175] (7) A signal generator 18 that cyclically generates a simple signal in connection with the IO-Link signal.

[0176] CLA Operation

[0177] According to an embodiment of the present invention, the process data sources are considered to be data input devices 2i, 1ai, 1bi, 1ci, 1di and 18, and Figure 6 The incoming process data elements are selected by the distributor block 13 and converted to scalar or Boolean. The details about the selection and conversion are configurable.

[0178] In a preferred embodiment of the CLA, the conversion from a data element to a scalar is adjusted by a scale factor and an offset. For example, an integer type is converted to a scalar by implementing the following equation:

[0179] Scalar i =scale*float(IntegerT)+offset

[0180] According to an embodiment of the present invention, if the data element is not of Boolean type, the conversion from the data element to Boolean requires a quantization step. The quantization step can be completed by implementing the following inequality operation:

[0181] bool=(dataelement≥threshold)

[0182] Scalars and Booleans may be handled differently in configurable logic adapters.

[0183] Signal Generator

[0184] To support simple sequencing logic, an artificial device port 18 can be added to the AGG device according to an embodiment of the present invention, which generates some simple value sequence, such as a counter. The counter output can be used to generate the control signal required by the sequencing logic.

[0185] Scalar processing

[0186] According to an embodiment of the present invention, the input scalar 105a can be routed from the distributor 13 to the combiner block 14. A processing block 15 can be inserted into the routing. In a preferred embodiment of the present invention, the number of scalars input to the processing block is the same as the number of scalars output to the processing block. The processing block between the distributor and the combiner is also called a pre-processing block.

[0187] The output scalar 105b may be routed from the combiner 14 to the combiner 16. Into this routing may be inserted a processing block 15. The processing blocks between the combiner and the merger are referred to as post-processing blocks.

[0188] The operation of a processing block can be specified by a procedure that performs an operation on an input scalar to generate an output scalar. A processing block may contain a state memory. A typical example of a processing block with one input scalar and one output scalar is a moving average block, which generates the average of the last N input samples as an output sample.

[0189] A processing block with 2 input scalars can be a coordinate conversion block that converts from Cartesian coordinates (x, y) to polar coordinates (amplitude and phase). It can also support processing blocks that require configurable coefficients, such as a finite impulse response "FIR" filter block that performs the equation The operation defined in , where x(n) represents the input scalar, y(n) represents the output scalar, and h(i) are the filter coefficients.

[0190] An important feature of embodiments of the present invention is that scalars cannot be used to create direct feedback loops within the CLA.

[0191] Combiner 14

[0192] Figure 7 An exemplary structure of a combiner block 14 is depicted. The combiner blocks are organized in rows. Each row can combine any input scalars and generate one output scalar. The number of rows 14a...14n of combiner blocks is configurable.

[0193] The preferred implementation of the combiner operation is described by the following equation:

[0194]

[0195] A first preferred embodiment allows linear combinations of all input scalars. For example, if the input scalar si(0) represents a first distance measured by device 8a and the scalar si(1) represents a second distance measured by another device 8b, then a simple linear combination (where I = 2, c(i) = 1, m(i) = 1 and o(i) = 0) will produce an operation that calculates the sum of the two distances, i.e., so(j) = si(0) + si(1).

[0196] The second preferred embodiment is related to the product of the input scalars. For example, if the input scalar si(0) represents the current I measured by the device 8a, and if the scalar si(1) represents the voltage U measured by the device 8b, the product term (where o(j)=0, c(j)=1, m(i)=1) will result in an operation so(j)=si(0)*si(1)=U*I that evaluates the electric power as the product of the two scalars.

[0197] Merger 16

[0198] Finally, according to an embodiment of the present invention, a merger block 16 may be used to convert the scalars and Boolean values ​​back into data elements 11a ... 11f. The merger process may require a quantization step. In a preferred embodiment of the present invention, in order to convert the scalars into data elements, a linear operation may be applied to the output scalar so(j).

[0199] DataElement=Limit(Integer((so(j)*scale+offset))

[0200] The scale factor and offset are configurable to provide an appropriate match of the output scalar value range to the limited data range of the data element. For 8-bit integers, all floating point values ​​less than -128 will be mapped to -128, and all floating point values ​​> 127 will be mapped to 127. Non-integer portions of floating point values ​​will be discarded.

[0201] The outgoing merged data elements 11a ... 11f may be sent to output ports 2o, 1ao, 1bo, 1co, 1do. Output port 2o and input port 2i may be physically implemented as AGG device ports 2. Output port 1ao and corresponding input port 1ai may be physically implemented by the same host port 1a, etc.

[0202] Boolean processing

[0203] According to an embodiment of the present invention, Booleans can be arbitrarily routed from input data elements to output data elements. The order in which Booleans are processed may not be specified. Each block that uses Boolean values ​​will use the value stored before the block is executed. The results of the Boolean operation are stored and made accessible to other blocks in the next cycle.

[0204] Therefore, each Boolean may contain a delay. This allows feedback to be implemented with Booleans without creating unstable recursion. The conversion from scalar to Boolean values ​​can be done by a binarizer block 15a.

[0205] CLA Configuration

[0206] According to an embodiment of the present invention, a simple configuration with a CLA without programming and taking into account the requirements of the limited resources of the AGG hardware can be achieved as follows. The setup of the device application should be simple, should not include any programming, and should take into account the available memory resources of the AGG device hardware. The instrument application should be flexible and should have expansion means to meet future requirements. If the operations performed by the CLA are implemented by software programs, the requirements of the CLA can be easily addressed. However, this solution requires software engineers to write appropriate programs, which must be adjusted or modified and retested for any changes. Such programs are usually written in a programming language, which is interpreted by interpreter software that needs to be run within the CLA and slows down the execution of the code.

[0207] Configuration Tools

[0208] Figure 8 An example of how to provide a configuration tool "CLA-Composer" 20 that can be run on a PC is shown. Configuration tool (see Figure 8 ) has the functionality to import the IODD file 23 of the connected IO-Link device. The IODD contains information about the process data elements of the connected IO-Link device. The TCLA also provides the user with a list of processing blocks for insertion. The list of processing blocks refers to the processing blocks available in the current AGG device. The details of the processing blocks are described in a well-defined XML file called a processing block descriptor "PBD" file 21.

[0209] According to an embodiment of the present invention, if new requirements arise, such as the need to perform data transformation from the time domain, the existing processing blocks need to be expanded. In this case, the existing firmware of the AGG device can be upgraded with the new processing blocks by means of a firmware update.

[0210] Fig. 9 An example of the layout of a CLA is shown. The process data elements "alarm", "VMA" and "level" shown under the input items in the example are taken from the imported IODD of the connected device. The data element "level" in the example is mapped to two scalars "S1" and "S2". In the example, the signal is passed through 2 processing blocks "prcallpass_1_chain_1" and "prcblc_delay_1". These blocks can be inserted into the scalar line via the GUI component of the TCLA-composer tool.

[0211] Configuration transfer between TCLA composer and AGG devices

[0212] According to an embodiment of the present invention, after the routing of Booleans and scalars is completed and all blocks are configured, the configuration needs to be transferred to the AGG device.

[0213] Since AGG devices have limited resources, especially limited memory, it is desirable to already perform a resource check during the configuration phase. This is achieved in particular by generating an image of the entire volatile memory within the orchestrator 24.

[0214] The CLA can check whether the generated memory image fits in the memory area reserved in the AGG before performing the transfer. The memory image can be downloaded to the AGG device via an IO-Link feature called BLOB transfer.

[0215] The AGG device application may contain a parser 201 of the memory image 24 in order to associate coefficients, storage elements etc. to the CLA 200. The parsing relies on a formal description of the memory image. An example of the element "BLOCK" is given below.

[0216] Block(op_id,p_version,num_scalars,num_bool_in,num_bool_out){

[0217] level_start

[0218] BlockIdentification(op_id,p_version)

[0219] Array(typeid=Scalar_ID,num_scalars,typesize=8)

[0220] Array(typeid=Bool_ID,num_bool_in,typesize=4)

[0221] Array(typeid=Bool_ID,num_bool_out,typesize=4)

[0222] ArrayList

[0223] level_end

[0224] }

[0225] level_start:0x00,0x00,0x20,0x00

[0226] (increments level count)

[0227] level_end:BaseArray(level_end,0,0)=0x00,0x00,0x30,0x00

[0228] The memory image 24 of a processing block can be uniquely associated to the structural description of the PBD file 21. Therefore, if a new processing block is described by a PBD, the scalability requirement is met.

[0229] In a preferred embodiment of the invention, during parsing, identified portions of memory can be reorganized (e.g., to support different ENDIANESSes). In particular, elements of the memory image that contain only data to support proper parsing can be reused by the application after being parsed by the algorithm.

[0230] Alternatives to CLA

[0231] Fig.13 Another preferred embodiment of the CLA is shown. The CLA 200 is now directly connected to the upper side of the external IO-Link master 7 that controls at least one IO-Link line 100. The data exchange between the upper system 500, which can be a PLC, a web server or another client of the IO-Link master, passes through the CLA. In this case, the CLA can be used to perform signal shaping or feedback loops as described for the AGG device.

[0232] exist Fig.14, a method 300 for cyclically processing incoming and / or outgoing data elements 11, the data elements 11 representing numerical and / or logical values ​​associated with an upper layer application. According to a first method step 301, at least one or more of the data elements 11 can be converted into at least one or more input scalar signals 105a of a common data type (especially IEEE 754 floating point) after a linear operation and / or into at least one or more Boolean signals 106 after additional quantization, the conversion being especially performed by a distributor block 13. According to a further method step 302, at least one or more combination operations can be performed, each combination operation comprising combining at least one or more of the input scalar signals 105a into one output scalar signal 105b, the combination operation being especially performed by a combiner block 14. According to a further method step 303, at least one or more of the output scalar signals 105b and / or the Boolean signals 106 and / or outputs based on these signals 105b, 106 can be reconverted into one or more data elements 11 after a linear operation and / or a quantization step, the reconversion being especially performed by a merger block 16. According to a further method step 304, a logical operation may be performed on at least one or more of the Boolean signals 106, and in particular both an input and an output may be provided for the Boolean signal 106, this step being in particular performed by the logic block 17. Furthermore, the processing block 15 may be inserted between the distributor block 13 and the combiner block 14, in particular into one or more input scalar signals 105a, or between the combiner block 14 and the merger block 16, in particular into one or more output scalar signals 105b.

[0233] Fig.14 Also visualized are a computer program 420 , a data processing apparatus 410 , a system and a computer-readable storage medium 430 according to embodiments of the invention.

[0234] The foregoing explanation of the embodiments describes the invention in the context of the embodiments. Of course, the individual features of the embodiments can be freely combined with one another as long as it is technically reasonable without departing from the scope of the invention.

Claims

1. A device (200) for cyclically processing incoming and / or outgoing data elements (11), the data elements (11) representing numerical and / or logical values ​​associated with an upper layer application, the device (200) comprising: a distributor block (13) for converting at least one or more of the data elements (11) into at least one or more input scalar signals (105a) of a common data type, in particular IEEE 754 floating point, after a linear operation and / or into at least one or more Boolean signals (106) after an additional quantization, - a combiner block (14) for performing at least one or more combination operations, each combination operation comprising combining at least one or more of the input scalar signals (105a) into one output scalar signal (105b), a merger block (16) for reconverting at least one or more of the output scalar signal (105b) and / or the Boolean signal (106) and / or outputs based on these signals (105b, 106) into one or more data elements (11) after a linear operation and / or a quantization step, a logic block (17) for performing a logic operation on at least one or more of the Boolean signals (106), and in particular for providing both an input and an output for the Boolean signals (106), - a processing block (15), which is configured to be inserted between the distributor block (13) and the combiner block (14), in particular into one or more input scalar signals (105a), or between the combiner block (14) and the merger block (16), in particular into one or more output scalar signals (105b).

2. The device (200) according to claim 1, characterized in that The processing block (15) is configured to process the one or more input scalar signals (105a) and / or the one or more output scalar signals (105b) into which the processing block (15) is inserted, and in particular is a processing block configured to perform digital filtering operations or spectral transformations, such as fast Fourier transforms.

3. The device (200) according to any one of the preceding claims, characterized in that The combiner block (14), the processing block (15), the merger block (16) are configured to be processed in a well-defined order, preferably in a manner that any input scalar of the current block is evaluated before evaluating the current block.

4. The device (200) according to any one of the preceding claims, characterized in that The apparatus (200) is configured to process the incoming and / or outgoing data elements cyclically in such a way that the Boolean signal (106) evaluated in one cycle is given as input for a subsequent block in the next cycle.

5. The device (200) according to any one of the preceding claims, characterized in that The combiner block (14), the processing block (15), the merger block (16) and in particular the logic block (17) are configured based on a configuration specification, which can be customized by a user so that the processing and in particular the logic operation and / or the insertion of the processing block (15) can be configured, and the configuration specification is in particular stored in a storage medium.

6. The device (200) according to any one of the preceding claims, characterized in that The apparatus (200) provides a configurable logic adapter that uses configurable logic to process, preferably convert and / or select the data elements (11) of data received from at least one or more secondary devices (8), and processes and / or combines the data elements (11) to generate data to be sent to the primary device (7a).

7. The device (200) according to any one of the preceding claims, characterized in that The device (3) comprises an interface, which is provided for configuring the processing and in particular configurable logic by a user so that the processing of the data element (11) is adapted to the upper-level application, in particular the evaluation and / or control of at least one or more auxiliary devices (8), in particular sensors and / or actuators.

8. A system for providing communications in an automation system, the system comprising: - a programmable logic controller (PLC) for providing upper layer applications, in particular automated control of industrial processes of the automation system, - a master device (7a) for connecting to the programmable logic controller (PLC) to provide a communication system, - at least one or more auxiliary devices (8) for being controlled and / or evaluated by the programmable logic controller (PLC) via the main device (7a) so as to at least partially execute the upper layer application, - An apparatus (3) according to any one of claims 1 to 7, for connecting the at least one or more auxiliary devices (8) to the main device (7a), thereby providing data exchange for control and / or evaluation of the auxiliary devices (8) via the communication system.

9. A method (3001) for cyclically processing incoming and / or outgoing data elements (11), said data elements (11) representing numerical and / or logical values ​​associated with an upper layer application, said method comprising: - converting (301) at least one or more of the data elements (11) into at least one or more input scalar signals (105a) of a common data type after a linear operation, in particular IEEE 754 floating point, and / or into at least one or more Boolean signals (106) after an additional quantization, the conversion being in particular performed by a distributor block (13), - performing (302) at least one or more combination operations, each combination operation comprising combining at least one or more of the input scalar signals (105a) into one output scalar signal (105b), the combination operation being in particular performed by a combiner block (14), - reconverting (303) at least one or more of the output scalar signal (105b) and / or the Boolean signal (106) and / or an output based on these signals (105b, 106) into one or more data elements (11) after a linear operation and / or a quantization step, the reconversion being in particular performed by a merger block (16), - performing (304) a logic operation on at least one or more of the Boolean signals (106), and in particular providing both an input and an output for the Boolean signals (106), the logic operation being in particular performed by a logic block (17), - inserting the processing block (15) between the distributor block (13) and the combiner block (14), in particular into one or more input scalar signals (105a), or inserting between the combiner block (14) and the merger block (16), in particular into one or more output scalar signals (105b).

10. The method according to claim 9, characterized in that The processing block (15) processes the one or more input scalar signals (105a) and / or the one or more output scalar signals (105b) into which the processing block (15) is inserted.

11. The method according to claim 9 or 10, characterized in that: The quantity of the scalar signals (105a, 105b) does not change when passing through the processing block (150).

12. The method according to any one of claims 9 to 11, characterized in that The combiner block (14), the processing block (15), the merger block (16) are processed in a well-defined order, preferably in a way that any input scalar of the current block is evaluated before evaluating the current block.

13. The method according to any one of claims 9 to 12, characterized in that The Boolean signal (106) evaluated in one cycle is given as input to the subsequent block in the next cycle.

14. The method according to any one of claims 9 to 13, It is characterized in that The processing (102) of the data element (11) comprises: - inputting said data elements (11) to a set of processing blocks (150) thereby generating an output of said set of processing blocks (50), - generating a modified data element (11) based on said output of said set of processing blocks (150), Wherein the connection and / or structure of the set of processing blocks (150) is defined by a customizable configuration of logic.

15. A computer program comprising instructions which, when executed by a computer, cause the computer to perform the method according to any one of claims 9 to 14.

16. A data processing apparatus comprising means for performing the method according to any one of claims 9 to 14.

17. A computer-readable storage medium comprising instructions, which, when a computer program is executed by a computer, cause the computer to perform the method according to any one of claims 9 to 14.

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