Double-node interaction system architecture design method and device, equipment and medium

Abstract

The invention discloses a double-node interaction system architecture design method, device and equipment and a medium, and relates to the field of integrated circuits, and the method comprises the steps: configuring corresponding communication bus modules for a first node and a second node in double nodes; the communication bus module comprises a universal serial bus function realized based on integrated logic; the communication bus modules for controlling the double nodes are connected with respective video graphic array modules, management component transport protocol modules, data access interaction modules and universal extension control interfaces, and the respective video graphic array modules for controlling the double nodes are connected with respective image coding and decoding modules; the bandwidth of the communication bus module is calculated according to the bus characteristics of the communication bus module, and the bandwidth of the storage space is calculated according to the storage characteristics of the storage space, so that the bandwidth requirement of the double nodes is met. The problem of high cost of the multi-node server is effectively solved, the utilization rate of the substrate management controller is greatly improved, and simultaneous online control management of the host of the multi-node server is realized.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a dual-node interactive system architecture design method, device, equipment and medium. Background Art

[0002] BMC (Baseboard Management Controller) is responsible for server control and remote monitoring in the system. In traditional multi-node servers, each node (host) requires a separate baseboard management controller for management and control. When the number of nodes is large, a large number of baseboard management controllers are required, which leads to high costs for multi-node servers.

[0003] In summary, it can be seen that how to achieve simultaneous online control and management of multi-node server hosts, improve the utilization rate of baseboard management controllers, and reduce enterprise costs are important technical issues to be solved in this field. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a dual-node interactive system architecture design method, device, equipment and medium, which can realize simultaneous online control and management of multi-node server hosts, improve system utilization and reduce enterprise costs. The specific scheme is as follows:

[0005] In a first aspect, the present application discloses a dual-node interactive system architecture design method, including:

[0006] A corresponding communication bus module is configured for the first node and the second node of the dual node respectively; wherein the communication bus module includes a universal serial bus function implemented based on a preset integrated logic;

[0007] Control the communication bus module of the dual nodes to connect their respective video graphics array modules, management component transmission protocol modules, data access interaction modules and universal extension control interfaces, and control the video graphics array modules of the dual nodes to connect their respective image encoding and decoding modules;

[0008] The bandwidth of the communication bus module is calculated according to the bus characteristics of the communication bus module, and the bandwidth of the storage space is calculated according to the storage characteristics of the storage space, so that the bandwidth of the communication bus module and the bandwidth of the storage space meet the bandwidth requirements of the dual nodes.

[0009] Optionally, calculating the bandwidth of the communication bus module according to bus characteristics of the communication bus module includes:

[0010] determining a first bandwidth requirement of the video graphics array module to the communication bus module;

[0011] determining a second bandwidth requirement of the communication bus module by the universal serial bus function;

[0012] Determine a bus standard of the communication bus module according to the first bandwidth requirement and the second bandwidth requirement, and determine a coding rule corresponding to the bus standard;

[0013] Calculate the bandwidth of the communication bus module based on the bus standard and encoding rules.

[0014] Optionally, data generated by the image encoding and decoding module in the process of performing image encoding and decoding and data generated by the video graphics array module in the process of processing video are stored in the same storage space.

[0015] Optionally, the bandwidth of the storage space is calculated according to the storage characteristics of the storage space, including:

[0016] Determining the third bandwidth requirement of the video graphics array module for the storage space according to the maximum resolution, picture transmission rate and number of bits occupied by pixels of the video graphics array module;

[0017] Calculating a fourth bandwidth requirement of the image encoding and decoding module for the storage space according to the third bandwidth requirement; wherein the fourth bandwidth requirement is related to the data reading rate of the image encoding and decoding module;

[0018] Determine a minimum compression ratio of the image coding and decoding module, and calculate a fifth bandwidth requirement of the image coding and decoding module for storage space according to the fourth bandwidth requirement and the minimum compression ratio of the image coding and decoding module;

[0019] Calculating a sixth bandwidth requirement of the system for the storage space according to a first data transmission rate and a data transmission bit width when the storage space interacts with the target network controller;

[0020] determining a data bus width of the storage space according to the third bandwidth requirement, the fourth bandwidth requirement, the fifth bandwidth requirement, and the sixth bandwidth requirement;

[0021] The bandwidth of the storage space is calculated according to the data bus width of the storage space, the second data transmission rate of the storage space, and the minimum working efficiency of the storage space.

[0022] Optionally, the universal extension control interfaces of the two nodes are respectively connected to their respective universal serial bus interfaces, so as to communicate with corresponding external devices through their respective universal serial bus interfaces.

[0023] Optionally, the dual-node interactive system architecture design method further includes:

[0024] The serial peripheral interfaces of the two nodes are connected to the target network controller through their respective bus master interfaces, and the serial peripheral interfaces of the two nodes are connected to their respective four-wire serial peripheral interfaces and integrated circuit buses through their respective bus slave interfaces.

[0025] Optionally, the dual-node interactive system architecture design method further includes:

[0026] The low pin count bus of the two nodes is connected to the respective routing through the respective universal asynchronous receiver-transmitter, and the low pin count bus of the two nodes is connected to the target network controller through the respective virtual universal asynchronous receiver-transmitter.

[0027] In a second aspect, the present application discloses a dual-node interactive system architecture design device, comprising:

[0028] A node communication bus configuration module, used to configure corresponding communication bus modules for the first node and the second node in the dual node respectively; wherein the communication bus module includes a universal serial bus function implemented based on a preset integrated logic;

[0029] A multi-module connection control module is used to control the communication bus modules of the dual nodes to connect their respective video graphics array modules, management component transmission protocol modules, data access interaction modules and general extension control interfaces, and control the video graphics array modules of the dual nodes to connect their respective image encoding and decoding modules;

[0030] The storage bandwidth adaptation module is used to calculate the bandwidth of the communication bus module according to the bus characteristics of the communication bus module, and calculate the bandwidth of the storage space according to the storage characteristics of the storage space, so that the bandwidth of the communication bus module and the bandwidth of the storage space meet the bandwidth requirements of the dual nodes.

[0031] In a third aspect, the present application discloses an electronic device, comprising:

[0032] Memory, used to store computer programs;

[0033] The processor is used to execute a computer program to implement the aforementioned disclosed dual-node interactive system architecture design method.

[0034] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the system architecture design method for dual-node interaction disclosed above is implemented.

[0035] It can be seen that the present application proposes a system architecture design method for dual-node interaction, including: configuring corresponding communication bus modules for the first node and the second node in the dual node respectively; wherein the communication bus modules of the dual nodes respectively include universal serial bus functions implemented based on preset integrated logic; controlling the communication bus modules of the dual nodes to connect their respective video graphics array modules, management component transmission protocol modules, data access interaction modules and universal extension control interfaces, and controlling the respective video graphics array modules of the dual nodes to connect their respective image encoding and decoding modules; calculating the bandwidth of the communication bus module according to the bus characteristics of the communication bus module, and calculating the bandwidth of the storage space according to the storage characteristics of the storage space, so that the bandwidth of the communication bus module and the bandwidth of the storage space meet the bandwidth requirements of the dual nodes. It can be seen that the present application integrates the universal serial bus function implemented by the second communication bus module in the traditional technology into the first communication bus module, thereby reducing the number of communication bus modules used and effectively solving the problem of high cost of multi-node servers. Furthermore, the present application realizes centralized control of dual-node multi-modules by controlling the communication bus module of the dual-node to connect the video graphics array module, the management component transmission protocol module, the data access interaction module and the universal extension control interface, thereby greatly improving the utilization rate of the baseboard management controller. In addition, the present application ensures that the bandwidth of the communication bus module and the bandwidth of the storage space are met by calculating the bandwidth of the communication bus module, and ensures stable and efficient data transmission. Finally, the present application connects the video graphics array modules of the dual nodes to the image encoding and decoding module, and connects the above-mentioned key modules in combination with the communication bus module, so that the technicians can perform online control of the video, data and other aspects of the dual nodes in real time, and realize simultaneous online control and management of multi-node server hosts. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0037] Figure 1 A schematic diagram of a single-node solution of a traditional baseboard management controller system;

[0038] Figure 2 A schematic diagram of a single-node related module structure of a traditional baseboard management controller system;

[0039] Figure 3 A flow chart of a dual-node interactive system architecture design method disclosed in this application;

[0040] Figure 4A schematic diagram of a dual-node interactive system architecture disclosed in this application;

[0041] Figure 5 A schematic diagram of a related module structure of a dual-node interaction disclosed in this application;

[0042] Figure 6 A schematic diagram of a dual-node interactive system architecture design device disclosed in this application;

[0043] Figure 7 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] BMC is responsible for server control and remote monitoring in the system. In traditional multi-node servers, each node requires a separate baseboard management controller for management and control. When the number of nodes is large, more baseboard management controllers are required, resulting in high costs for multi-node servers.

[0046] To this end, the embodiment of the present application proposes a dual-node interactive system architecture design solution, which can realize simultaneous online control and management of multi-node server hosts, improve system utilization, and reduce enterprise costs.

[0047] The present application embodiment discloses a dual-node interactive system architecture design method, see Figure 5 As shown, the method includes:

[0048] Step S11: respectively configuring corresponding communication bus modules for the first node and the second node in the dual nodes; wherein the communication bus module includes a universal serial bus function implemented based on a preset integrated logic.

[0049] Figure 1A schematic diagram of a single-node (server) solution of a traditional baseboard management controller system is provided. The server is connected to the baseboard management controller system through a high-speed peripheral component interconnect express (PCIe) interface. There are two high-speed peripheral component interconnect standard modules in the baseboard management controller system, which are respectively connected to different functional modules. On the one hand, the AXI router is connected through the AXI master (Advanced eXtensible Interface Master, Axi Master) and AXI slave (Advanced eXtensible Interface Slave, Axi Slave) interfaces, the management component transport protocol (Management Component Transport Protocol, Mctp), the data access interaction module and the video graphics array module (Vga) are connected through the AXI router, and the image codec module (Joint Photographic Experts Group, Jpeg) is connected through the video graphics array module. The data in the image codec module and the video graphics array module are stored in a double data rate random access memory (Double Data Rate, Ddr). On the other hand, the USB 3.0 physical layer module (USB 3.0Physical Layer) and the USB 2.0 device control module (USB 2.0 Device Control, Usb2.0 devicectrl) are connected through the eXtensible Host Controller Interface (Xhci). It can be seen that in the traditional technology, two PCIe ep modules are used in the single-node solution of the baseboard management controller. When the number of nodes is large, a large number of baseboard management controllers and PCIe ep modules are required, which leads to a high cost of multi-node servers.

[0050] Figure 2A schematic diagram of the LPC (Linear Predictive Coding) and eSPI (Enhanced Serial Peripheral Interface module) related modules of a single node (server) of a traditional baseboard management controller system is provided. The server is the core device of the entire system and is connected to multiple other modules. The universal asynchronous receiver-transmitter (UART) includes a universal asynchronous receiver-transmitter 10 and a universal asynchronous receiver-transmitter , used to implement asynchronous serial communication. The Low Pin Count Bus (LPC Bus) communicates with the Universal Asynchronous Receiver / Transmitter (UATS) through the LPC control signal. The Uart Router is located in the Universal Asynchronous Receiver / Transmitter. It plays the role of data routing between the universal asynchronous receiver and transmitter 10. Universal asynchronous receiver and transmitter input and output port ( ) is connected to UART 10 and UARTs 1-4 to provide data input and output functions. The enhanced serial peripheral interface (eSPI) is connected to the quad serial peripheral interface through an advanced high-performance bus master interface, and is connected to the server, two virtual UARTs, and the network control port through an advanced high-performance bus slave interface. The quad serial peripheral interface (Quad Serial Peripheral Interface, QSPI) is connected to the enhanced serial peripheral interface for serial data communication. The network control port (Network ControlPort) is connected to the enhanced serial peripheral interface through an advanced high-performance bus slave interface and is connected to two virtual UARTs. It should be pointed out that the number of interfaces, module composition, DDR bandwidth, and PCIe bus rate in the current architecture of the baseboard management controller cannot meet the needs of dual-node management. To solve this problem, this embodiment redesigns the baseboard management controller architecture and adds functional modules and interfaces required for dual-node management. It also improves the DDR bandwidth and PCIe bus bandwidth and reuses previous design content as much as possible to meet all the functions and performance requirements of dual-node management and save corresponding manufacturing costs.

[0051] To this end, the present application configures corresponding communication bus modules (i.e. Figure 4The communication bus module includes a universal serial bus function implemented based on a preset integrated logic. That is, the present application integrates the universal serial bus function implemented by the second communication bus module in the conventional technology into the first communication bus module, thereby reducing the number of communication bus modules used and effectively solving the problem of high cost of multi-node servers.

[0052] Step S12: Control the communication bus modules of the two nodes to connect their respective video graphics array modules, management component transmission protocol modules, data access interaction modules and universal extension control interfaces, and control the video graphics array modules of the two nodes to connect their respective image codec modules.

[0053] See also Figure 4 As shown, this embodiment controls the communication bus modules of the dual nodes to connect their respective video graphics array modules, management component transmission protocol modules, data access interaction modules and general extension control interfaces through their respective AXI routings, and controls the video graphics array modules of the dual nodes to connect their respective image codec modules. Among them, the data generated by the image codec module in the process of performing image encoding and decoding and the data generated by the video graphics array module in the process of processing the video are stored in the same storage space (double data rate random access memory). In this way, there is no need to configure independent storage chips or storage areas for the two modules respectively, which effectively reduces the hardware procurement cost and the complexity of circuit board design. In addition, after the image encoding and decoding is completed, the video graphics array module can directly read data from the shared storage space for subsequent video processing without the need for cumbersome cross-storage area transmission, which significantly improves the real-time performance of data processing.

[0054] See also Figure 4 As shown, in this embodiment, the universal extension control interface (eXtensible Host Controller Interface) of each of the two nodes is respectively connected to the respective universal serial bus interface (USB3.0 physical layer module and USB2.0 device control module) to communicate with external devices through their respective universal serial bus interfaces.

[0055] See also Figure 5 As shown, the serial peripheral interfaces of the two nodes (enhanced serial peripheral interface 0 and enhanced serial peripheral interface 1) are connected to the target network controller (network interface controller 400) through their respective bus master interfaces (advanced high performance bus slave interfaces), and the serial peripheral interfaces of the two nodes are connected to their respective four-wire serial peripheral interfaces (quad-channel serial peripheral interface 0 and quad-channel serial peripheral interface 1) and integrated circuit bus (integrated circuit bus 1) through their respective bus slave interfaces. The low pin count buses of the two nodes (low pin count bus 0 and low pin count bus 1) are connected to the target network controller (network interface controller 400) through their respective bus master interfaces (advanced high performance bus slave interfaces). 、Universal Asynchronous Receiver / Transmitter 11、Universal Asynchronous Receiver / Transmitter ) are connected to their respective routes (UART route 0 and UART route 1), and the dual-node low pin count bus is connected to the target network controller through their respective virtual UARTs (2 virtual UARTs). It can be seen that this application adds another set of LPC1 and eSPI1 modules on the basis of the single-node solution, and mounts them on the same Nic400 bus, adding AXI Route1, , UART11 and GPIO function multiplexing module, the added modules are the same as AXIROute0, , UART10 and GPIO functions are consistent. LPC0, eSPI0, QSPI0, UART10, To support the first node Data processing, LPC1, eSPI1, QSPI1, UART11, To support the second node Data processing.

[0056] In this way, a single BMC can process the dual-node host LPC and eSPI interface data simultaneously. Through the above connection method, the requirements of the dual-node interface are met. The enhanced serial peripheral interface of the dual node is directly connected to the network interface controller 400, providing an exclusive high-speed data channel for the two nodes, so that each node can independently and quickly interact with the network for data, reduce transmission delays, meet the real-time data transmission requirements of the dual nodes, and ensure the efficient throughput of the dual node data in a complex network environment.

[0057] Step S13: Calculate the bandwidth of the communication bus module according to the bus characteristics of the communication bus module, and calculate the bandwidth of the storage space according to the storage characteristics of the storage space, so that the bandwidth of the communication bus module and the bandwidth of the storage space meet the bandwidth requirements of the two nodes.

[0058] In this embodiment, a first bandwidth requirement of the video graphics array module for the communication bus module is determined, a second bandwidth requirement of the universal serial bus function for the communication bus module is determined, a bus standard of the communication bus module is determined based on the first bandwidth requirement and the second bandwidth requirement, and a coding rule corresponding to the bus standard is determined, and then the bandwidth of the communication bus module is calculated based on the bus standard and the coding rule.

[0059] For example, the first bandwidth requirement of the VGA module to the PCIE module is (First bandwidth requirement), the USB module's PCIe bandwidth requirement is (Second bandwidth requirement), PCIe2.0 protocol support Each lane supports 5G bit transmission per second. Since the physical layer protocol of PCIe2.0 is The encoding scheme of PCIe 2.0 protocol supports: The rate ( ), that is, the available bandwidth of PCIe gen2 is only The bandwidth requirement of the USB module for PCIe is , the VGA module's PCIe bandwidth requirement is , at this time, the requirement that the USB and VGA modules share a PCIe interface cannot be met, so the PCIe bus needs to be upgraded. To this end, this embodiment upgrades the PCIe from PCIe gen2 to PCIe gen3 (the bus standards corresponding to different levels are inconsistent). Protocol support , that is, each lane supports 8G bits per second. The physical layer protocol used in PCIe 3.0 is The encoding scheme is 130 bits per 128 bits transmitted. Then, each lane of the PCIe 3.0 protocol supports: The rate (bandwidth is approximately ), which can meet the needs of dual-node management.

[0060] In this embodiment, a third bandwidth requirement of the video graphics array module for the storage space is determined according to the maximum resolution, picture transmission rate and number of bits occupied by pixels of the video graphics array module, and a fourth bandwidth requirement of the image codec module for the storage space is calculated according to the third bandwidth requirement; wherein the fourth bandwidth requirement is related to the data reading rate of the image codec module, a minimum compression ratio of the image codec module is determined, and a fifth bandwidth requirement of the image codec module for the storage space is calculated according to the fourth bandwidth requirement and the minimum compression ratio of the image codec module, a sixth bandwidth requirement of the storage space is calculated according to the first data transmission rate and the data transmission bit width when the storage space interacts with the target network controller, a data bus width of the storage space is determined according to the third bandwidth requirement, the fourth bandwidth requirement, the fifth bandwidth requirement and the sixth bandwidth requirement, and the bandwidth of the storage space is calculated according to the data bus width of the storage space, the second data transmission rate of the storage space and the minimum working efficiency of the storage space.

[0061] For example, the VGA operation on DDR is image writing and image reading. , 60 frames per second, 32bpp per pixel, the DDR bandwidth required by VGA is: (Third bandwidth requirement). Furthermore, Jpeg's DDR operations are image reading and compressed image writing, at maximum resolution , 60 frames per second, 32bpp per pixel, the Jpeg read data bandwidth is: (Fourth bandwidth requirement). Furthermore, the Jpeg compression ratio is According to the minimum compression ratio , the bandwidth after compression is: (Fifth bandwidth requirement). Furthermore, the system's operation on DDR is mainly for system and application operation, which interacts with DDR through Nic400. The bandwidth requirement is: (Sixth bandwidth requirement). Based on the above calculation, the total bandwidth requirement of the BMC system is: The minimum working efficiency of DDR module is: According to calculations, while maintaining the DDR bus width of 16 bits, the minimum requirement is , which can meet the bandwidth requirements: . According to the production process selection and back-end layout and wiring conditions, it is ensured that DDR can reach 2667Mbps after production to meet system requirements. The maximum rate of DDR4 under the existing process is 2667MHz. The modules that interact with DDR are VGA, Jpeg and Nic400. After each module is expanded to dual nodes, the bandwidth requirement for DDR is calculated according to the maximum value. The dual-node system has a bandwidth requirement for DDR of approximately: Therefore, the DDR solution of the single-node solution cannot meet the bandwidth requirements of two groups of VGA and JPEG of the dual-node solution, so the DDR bandwidth needs to be improved. The DDR process continues to use DDR4, the rate can reach 2667MB / s, and the DDR external interface is upgraded from 16 bits to 32 bits. At this time, the DDR bandwidth is: , meeting the dual-node bandwidth requirements.

[0062] In this embodiment, the original Pathway merged into All the way, the number of PCIe ep used can be reduced while ensuring the normal function is realized, thus saving hardware resources. Split into two IPs in the form of pcie IP and remaining logic IP (Intellectual Property) for integration into the system. By designing a new server management architecture, it is possible to support a single BMC to manage two hosts. Each functional module of the host management application uses a set of PCIe buses and shares a double data rate random access memory. Expand the eSPI and LPC interfaces, and the related functional interfaces UART and virtual UART, and merge them into the baseboard management controller architecture to support dual-node management requirements.

[0063] In addition, this embodiment can also dynamically adjust the operating frequency and power consumption of each module according to the real-time load of the system, and minimize the energy consumption of the system while ensuring that the system performance is not affected. In addition, this embodiment can also design a real-time communication priority scheduling algorithm. The system assigns different priorities to various types of data according to the data transmission requirements and real-time requirements of different modules. For example, the real-time video data transmitted by the video graphics array module is given the highest priority in order to prioritize the timeliness of its data transmission and avoid video freezes; while for some non-critical system configuration data transmission, a lower priority is set. It can be seen that this priority scheduling technology can effectively optimize the bandwidth utilization of the communication bus, thereby improving the overall real-time performance of the system.

[0064] It can be seen that the present application proposes a system architecture design method for dual-node interaction, including: configuring corresponding communication bus modules for the first node and the second node in the dual node respectively; wherein the communication bus modules of the dual nodes respectively include universal serial bus functions implemented based on preset integrated logic; controlling the communication bus modules of the dual nodes to connect their respective video graphics array modules, management component transmission protocol modules, data access interaction modules and universal extension control interfaces, and controlling the respective video graphics array modules of the dual nodes to connect their respective image encoding and decoding modules; calculating the bandwidth of the communication bus module according to the bus characteristics of the communication bus module, and calculating the bandwidth of the storage space according to the storage characteristics of the storage space, so that the bandwidth of the communication bus module and the bandwidth of the storage space meet the bandwidth requirements of the dual nodes. It can be seen that the present application integrates the universal serial bus function implemented by the second communication bus module in the traditional technology into the first communication bus module, thereby reducing the number of communication bus modules used and effectively solving the problem of high cost of multi-node servers. Furthermore, the present application realizes centralized control of dual-node multi-modules by controlling the communication bus module of the dual-node to connect the video graphics array module, the management component transmission protocol module, the data access interaction module and the universal extension control interface, thereby greatly improving the utilization rate of the baseboard management controller. In addition, the present application ensures that the bandwidth of the communication bus module and the bandwidth of the storage space are met by calculating the bandwidth of the communication bus module, and ensures stable and efficient data transmission. Finally, the present application connects the video graphics array modules of the dual nodes to the image encoding and decoding module, and connects the above-mentioned key modules in combination with the communication bus module, so that the technicians can perform online control of the video, data and other aspects of the dual nodes in real time, and realize simultaneous online control and management of multi-node server hosts.

[0065] Correspondingly, the present application embodiment also discloses a dual-node interactive system architecture design device, see Figure 6 As shown, the device comprises:

[0066] The node communication bus configuration module 11 is used to configure corresponding communication bus modules for the first node and the second node in the dual node respectively; wherein the communication bus module includes a universal serial bus function implemented based on a preset integrated logic;

[0067] The multi-module connection control module 12 is used to control the communication bus modules of the two nodes to connect their respective video graphics array modules, management component transmission protocol modules, data access interaction modules and universal extension control interfaces, and control the video graphics array modules of the two nodes to connect their respective image encoding and decoding modules;

[0068] The storage bandwidth adaptation module 13 is used to calculate the bandwidth of the communication bus module according to the bus characteristics of the communication bus module, and calculate the bandwidth of the storage space according to the storage characteristics of the storage space, so that the bandwidth of the communication bus module and the bandwidth of the storage space meet the bandwidth requirements of the two nodes.

[0069] Among them, for more specific working processes of the above-mentioned modules, please refer to the corresponding contents disclosed in the aforementioned embodiments, which will not be repeated here.

[0070] It can be seen that the present application proposes a dual-node interactive system architecture design device, including: a node communication bus configuration module 11, which is used to configure corresponding communication bus modules for the first node and the second node in the dual node respectively; wherein the communication bus modules of the dual nodes respectively include universal serial bus functions implemented based on preset integrated logic; a multi-module connection control module 12, which is used to control the communication bus modules of the dual nodes to connect their respective video graphics array modules, management component transmission protocol modules, data access interaction modules and universal extension control interfaces, and control the respective video graphics array modules of the dual nodes to connect their respective image encoding and decoding modules; a storage bandwidth adaptation module 13, which is used to calculate the bandwidth of the communication bus module according to the bus characteristics of the communication bus module, and calculate the bandwidth of the storage space according to the storage characteristics of the storage space, so that the bandwidth of the communication bus module and the bandwidth of the storage space meet the bandwidth requirements of the dual nodes. It can be seen that the present application integrates the universal serial bus function implemented by the second communication bus module in the traditional technology into the first communication bus module, thereby reducing the number of communication bus modules used and effectively solving the problem of high cost of multi-node servers. Furthermore, the present application realizes centralized control of dual-node multi-modules by controlling the communication bus module of the dual-node to connect the video graphics array module, the management component transmission protocol module, the data access interaction module and the universal extension control interface, thereby greatly improving the utilization rate of the baseboard management controller. In addition, the present application ensures that the bandwidth of the communication bus module and the bandwidth of the storage space are met by calculating the bandwidth of the communication bus module, and ensures stable and efficient data transmission. Finally, the present application connects the video graphics array modules of the dual nodes to the image encoding and decoding module, and connects the above-mentioned key modules in combination with the communication bus module, so that the technicians can perform online control of the video, data and other aspects of the dual nodes in real time, and realize simultaneous online control and management of multi-node server hosts.

[0071] Furthermore, an embodiment of the present application also provides an electronic device. Figure 7 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram cannot be regarded as any limitation on the scope of use of the present application.

[0072] Figure 7 A schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a display screen 23, an input and output interface 24, a communication interface 25, a power supply 26, and a communication bus 27. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the system architecture design method for dual-node interaction disclosed in any of the aforementioned embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0073] In this embodiment, the power supply 26 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 25 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 24 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0074] In addition, the memory 22, as a carrier for storing resources, may be a read-only memory, a random access memory, a disk or an optical disk, etc., and the resources stored thereon may include a computer program 221, and the storage method may be a temporary storage or a permanent storage. Among them, the computer program 221 may further include a computer program that can be used to complete the system architecture design method for dual-node interaction performed by the electronic device 20 disclosed in any of the aforementioned embodiments, and can be used to complete other specific tasks.

[0075] Furthermore, an embodiment of the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the aforementioned disclosed dual-node interactive system architecture design method is implemented.

[0076] For the specific steps of the method, reference may be made to the corresponding contents disclosed in the aforementioned embodiments, which will not be described in detail here.

[0077] Furthermore, an embodiment of the present application also discloses a computer program product, including a computer program / instruction, which implements the steps of the random number generation method disclosed above when executed by a processor.

[0078] The various embodiments in this application are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0079] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0080] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0081] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0082] The above is a detailed introduction to the system architecture design method, device, equipment, and storage medium for dual-node interaction provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, according to the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A dual-node interactive system architecture design method, characterized in that: include: A corresponding communication bus module is configured for the first node and the second node of the dual node respectively; wherein the communication bus module includes a universal serial bus function implemented based on a preset integrated logic; Control the communication bus modules of the dual nodes to connect their respective video graphics array modules, management component transmission protocol modules, data access interaction modules and universal extension control interfaces, and control the respective video graphics array modules of the dual nodes to connect their respective image codec modules; The bandwidth of the communication bus module is calculated according to the bus characteristics of the communication bus module, and the bandwidth of the storage space is calculated according to the storage characteristics of the storage space, so that the bandwidth of the communication bus module and the bandwidth of the storage space meet the bandwidth requirements of the dual nodes.

2. The dual-node interactive system architecture design method according to claim 1, characterized in that: The calculating the bandwidth of the communication bus module according to the bus characteristics of the communication bus module comprises: determining a first bandwidth requirement of the video graphics array module for the communication bus module; determining a second bandwidth requirement of the universal serial bus function for the communication bus module; Determining a bus standard of the communication bus module according to the first bandwidth requirement and the second bandwidth requirement, and determining a coding rule corresponding to the bus standard; The bandwidth of the communication bus module is calculated according to the bus standard and the encoding rule.

3. The dual-node interactive system architecture design method according to claim 1, characterized in that: The data generated by the image coding and decoding module in the process of performing image coding and image decoding and the data generated by the video graphics array module in the process of processing video are stored in the same storage space.

4. The dual-node interactive system architecture design method according to claim 3, characterized in that: The calculating the bandwidth of the storage space according to the storage characteristics of the storage space includes: Determining a third bandwidth requirement of the video graphics array module for the storage space according to the maximum resolution, picture transmission rate, and number of bits occupied by pixels of the video graphics array module; Calculating a fourth bandwidth requirement of the image encoding and decoding module for the storage space according to the third bandwidth requirement; wherein the fourth bandwidth requirement is related to a data reading rate of the image encoding and decoding module; determining a minimum compression ratio of the image coding and decoding module, and calculating a fifth bandwidth requirement of the image coding and decoding module for the storage space according to the fourth bandwidth requirement and the minimum compression ratio of the image coding and decoding module; Calculating a sixth bandwidth requirement of the storage space by the system according to a first data transmission rate and a data transmission bit width when the storage space interacts with the target network controller; Determine the data bus width of the storage space according to the third bandwidth requirement, the fourth bandwidth requirement, the fifth bandwidth requirement, and the sixth bandwidth requirement; The bandwidth of the storage space is calculated according to the data bus width of the storage space, the second data transmission rate of the storage space, and the minimum working efficiency of the storage space.

5. The dual-node interactive system architecture design method according to claim 1, characterized in that: The universal extension control interfaces of the two nodes are respectively connected to their respective universal serial bus interfaces, so as to communicate with corresponding external devices through their respective universal serial bus interfaces.

6. The dual-node interactive system architecture design method according to claim 1, characterized in that: Also includes: The serial peripheral interfaces of the dual nodes are connected to the target network controller through their respective bus master interfaces, and the serial peripheral interfaces of the dual nodes are connected to their respective four-wire serial peripheral interfaces and integrated circuit buses through their respective bus slave interfaces.

7. The dual-node interactive system architecture design method according to claim 1, characterized in that: Also includes: The low pin count bus of the dual nodes is connected to the respective routing through the respective universal asynchronous receiver-transmitter, and the low pin count bus of the dual nodes is connected to the target network controller through the respective virtual universal asynchronous receiver-transmitter.

8. A dual-node interactive system architecture design device, characterized in that: include: A node communication bus configuration module, used to configure corresponding communication bus modules for the first node and the second node in the dual node respectively; wherein the communication bus module includes a universal serial bus function implemented based on a preset integrated logic; A multi-module connection management and control module, used to control the communication bus modules of the dual nodes to connect to their respective video graphics array modules, management component transmission protocol modules, data access interaction modules and universal extension control interfaces, and to control the respective video graphics array modules of the dual nodes to connect to their respective image codec modules; The storage bandwidth adaptation module is used to calculate the bandwidth of the communication bus module according to the bus characteristics of the communication bus module, and calculate the bandwidth of the storage space according to the storage characteristics of the storage space, so that the bandwidth of the communication bus module and the bandwidth of the storage space meet the bandwidth requirements of the dual nodes.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor is used to execute the computer program to implement the system architecture design method for dual-node interaction as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store computer programs; wherein, when the computer program is executed by a processor, the system architecture design method for dual-node interaction as described in any one of claims 1 to 7 is implemented.

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