A method, electronic device and storage medium for accelerating system-level simulation verification

Abstract

The application discloses a method, an electronic device and a storage medium for accelerating system-level simulation verification, comprising: establishing a register model in a simulation verification environment, the register model comprising a built-in read function for accessing a target register through a backdoor path; after use case chaining is completed, reading an initial value of the target register through the backdoor path of the register model and storing; in the use case execution process, reading a current value of the target register through the backdoor path of the register model in real time, and comparing with a predefined condition to verify the simulation state; at the end of the simulation, reading a final value of the target register through the backdoor path of the register model again; comparing the initial value with the final value, and triggering an error report if they are inconsistent.

Description

Technical Field

[0001] This invention relates to the field of switching chips, and more specifically to a method, electronic device, and storage medium for accelerating system-level simulation verification. Background Technology

[0002] With the rapid development of network communication, the scale of switching chips is also increasing. Faced with the ever-growing functional requirements, verification engineers are also facing great challenges. How to save simulation time in the process of large-scale verification has become an urgent problem to be solved.

[0003] First, each use case requires checking the values ​​of numerous status registers before the simulation ends, such as interrupt status registers, error status registers, backpressure registers, and FIFO status, to prevent unexpected phenomena. As chip size increases, the number of registers that need to be read also increases, and this part of the simulation time becomes longer and longer. Second, traditional register checking relies on the verifier's understanding of the final state; that is, the check requires the verifier to provide expected values. If the verifier misunderstands the value, it may lead to check failure, thus missing the real bug. Summary of the Invention

[0004] To achieve the above and other related objectives, this invention discloses a method for accelerating system-level simulation verification, comprising the following steps:

[0005] Step S1: Establish a register model in the simulation verification environment, the register model including a built-in read function for accessing the target register through the backdoor path;

[0006] Step S2: After the use case chain is established, read the initial value of the target register through the backdoor path of the register model and store it;

[0007] Step S3: During the execution of the test case, the current value of the target register is read in real time through the backdoor path of the register model and compared with the predefined conditions to verify the simulation status;

[0008] Step S4: At the end of the simulation, read the final value of the target register again through the backdoor path of the register model;

[0009] Step S5: Compare the initial value with the final value. If they are inconsistent, trigger an error report.

[0010] Furthermore, step S2 is executed during the configure_phase of the UVM verification platform.

[0011] Furthermore, step S4 is executed during the shutdown phase of the UVM verification platform.

[0012] Furthermore, the predefined condition in step S3 is the expected state value of the state machine. If the current value does not match the expected state value, a real-time error alarm is triggered.

[0013] Furthermore, the target register includes at least one of an interrupt status register, an error status register, a backpressure register, and a FIFO status register.

[0014] Furthermore, the backdoor path access is implemented through the UVM_BACKDOOR mode and does not consume simulation time resources.

[0015] Furthermore, the establishment of the register model includes mapping relationships of status registers defined in the protocol specification, and non-blocking reading is achieved through built-in functions.

[0016] Furthermore, when an error report is triggered in step S5, the identification information of the specific register is associated to assist in locating the problem.

[0017] On the other hand, the present invention provides an electronic device including a processor and a memory, the memory storing a computer program, wherein the processor executes the computer program to implement the above-described method for accelerating system-level simulation verification.

[0018] On the other hand, the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the above-described method for accelerating system-level simulation verification.

[0019] By adopting the above technical solution, the traditional method of reading registers for pre-simulation state checks consumes approximately 20%-30% of the entire simulation process. Using this invention for pre-simulation state register checks eliminates simulation time consumption, reducing the overall simulation time by 20%-30%, thus improving verification efficiency. Traditional pre-simulation register state checks rely on the verifier's judgment, requiring expected values. This invention compares the value of the register after link establishment with the value before simulation end, improving simulation correctness and avoiding additional overhead due to verifier errors in register state assessment. During test case development, the current state is obtained by reading registers during execution. This process typically consumes approximately 5%-10% of the total simulation time. Replacing the register checking strategy in test cases with this invention significantly speeds up simulation. Attached Figure Description

[0020] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. The drawings are provided for a better understanding of the invention and are not intended to limit the scope of this disclosure. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0021] Figure 1 This is a flowchart of the method of the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] Reference Figure 1 This invention provides a method for accelerating system-level simulation verification, comprising the following steps:

[0024] Step S1: Establish a register model in the simulation verification environment, the register model including a built-in read function for accessing the target register through the backdoor path;

[0025] Step S2: After the use case chain is established, read the initial value of the target register through the backdoor path of the register model and store it;

[0026] Step S2 is executed during the configure_phase of the UVM verification platform.

[0027] Step S3: During the execution of the test case, the current value of the target register is read in real time through the backdoor path of the register model and compared with the predefined conditions to verify the simulation status;

[0028] The predefined condition in step S3 is the expected state value of the state machine. If the current value does not match the expected state value, a real-time error alarm is triggered.

[0029] Step S4: At the end of the simulation, read the final value of the target register again through the backdoor path of the register model;

[0030] Step S4 is executed during the shutdown phase of the UVM verification platform.

[0031] S5: Compare the initial value with the final value. If they are inconsistent, trigger an error report.

[0032] This invention accelerates simulation and improves verification efficiency by optimizing the register reading method. Simultaneously, it improves verification accuracy by optimizing the register value comparison method.

[0033] First, a register model is established for the status register that requires final_check.

[0034] The register model has a built-in function: read, which is used to read the value from the register backdoor path. The read function can be placed in configure_phase in the UVM platform, which is located in base_test.sv.

[0035] After the test case chain is established, the register value is read and recorded using the register model backdoor access method. This step does not consume any simulation time.

[0036] Example: reg_model.INTERRUPT_REQ.read(status,rdata,UVM_BACKDOOR);

[0037] During test case simulation, if there is a need to check registers, the register values ​​can be read using the register model backdoor access method and compared with the expected values. This step is placed in the run_phase of each test case, and different test cases may need to check different registers.

[0038] Specifically, taking the PCIe protocol as an example, use cases often require checking the value of the LTSSM status register. The backdoor path reading process is as follows:

[0039] reg_model.LTSSM_REQ.read(status,rdata_ltssm,UVM_BACKDOOR);

[0040] During test case execution, it is necessary to determine whether the LTSSM state machine is in state L0. If not, an error will be reported.

[0041] Specifically, including:

[0042] if (rdata_ltssm != 'h10) begin

[0043] `uvm_error(get_type_name(),$sformatf("check fail for L0 state")

[0044] end

[0045] Before each test case simulation ends, the register value is read again using the register model backdoor access method and recorded. This step consumes no simulation time. This step is placed in the UVM shutdown_phase, which is located in base_test.sv. The value obtained in this step is compared with the value read from the register backdoor path. If they are not equal (e.g., rdata != rdata1), an error is reported. Verification personnel analyze the error to determine which register check has a problem. Example: reg_model.INTERRUPT_REQ.read(status, rdata1, UVM_BACKDOOR).

[0046] The method of this invention uses traditional register reading to perform state checks before the simulation ends, with reading time accounting for approximately 20%-30% of the entire simulation process. Using this invention for state register checks before the simulation ends does not consume simulation time, reducing the overall simulation time by 20%-30%, thereby improving verification efficiency. Traditional register state checks before the simulation ends rely on the verifier's judgment, requiring the verifier to provide expected values. This invention compares the value of the register after link establishment with the register value before the simulation ends, improving simulation correctness and avoiding additional overhead caused by the verifier's incorrect judgment of the register state before the simulation ends. During test case development, the current state is obtained by reading registers during test case execution. This part of the time accounts for approximately 5%-10% of the total simulation time on average. Using this invention to replace the register checking strategy in test cases can significantly speed up the simulation.

[0047] On the other hand, the present invention provides an electronic device including a processor and a memory, the memory storing a computer program, wherein the processor executes the computer program to implement the above-described method for accelerating system-level simulation verification.

[0048] On the other hand, the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the above-described method for accelerating system-level simulation verification.

[0049] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the meaning consistent with their meaning in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined.

[0050] For the sake of simplicity, the method embodiments are described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0051] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for accelerating system-level simulation verification, characterized in that, Includes the following steps: Step S1: Establish a register model in the simulation verification environment, the register model including a built-in read function for accessing the target register through the backdoor path; Step S2: After the use case chain is established, read the initial value of the target register through the backdoor path of the register model and store it; Step S3: During the execution of the test case, the current value of the target register is read in real time through the backdoor path of the register model and compared with the predefined conditions to verify the simulation status; Step S4: At the end of the simulation, read the final value of the target register again through the backdoor path of the register model; Step S5: Compare the initial value with the final value; if they do not match, trigger an error report. The predefined condition in step S3 is the expected state value of the state machine. If the current value does not match the expected state value, a real-time error alarm is triggered. The backdoor path access is implemented through the UVM_BACKDOOR mode and does not consume simulation time resources; The execution timing of step S2 is during the configure_phase and shutdown_phase of the UVM verification platform; During the configure and shutdown phases of UVM, the reading and comparison are completed in a non-blocking manner through the backdoor of the register model within the verification platform. The comparison object during the runtime phase is the expected state of the protocol state machine. Once a mismatch occurs, a real-time error alarm is triggered. The register model has a built-in function: read, which is used to read the value in the register backdoor path. The read can be placed in configure_phase in the UVM platform. configure_phase is located in base_test.sv. After the test case chain is established, the register value is read and recorded by accessing the register backdoor.

2. The method for accelerating system-level simulation verification according to claim 1, characterized in that, The target register includes at least one of an interrupt status register, an error status register, a backpressure register, and a FIFO status register.

3. The method for accelerating system-level simulation verification according to claim 1, characterized in that, The establishment of the register model includes mapping relationships of status registers defined by the protocol specification, and non-blocking reading is achieved through built-in functions.

4. The method for accelerating system-level simulation verification according to claim 1, characterized in that, When an error report is triggered in step S5, the identification information of the specific register is associated to help locate the problem.

5. An electronic device, characterized in that, It includes a processor and a memory, the memory storing a computer program, and the processor executing the computer program to implement the method for accelerating system-level simulation verification as described in any one of claims 1 to 4.

6. A computer-readable storage medium, characterized in that, The system contains a computer program that, when executed by a processor, implements the method for accelerating system-level simulation verification as described in any one of claims 1 to 4.

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