Display panel and electronic equipment

Abstract

The invention provides a display panel and electronic equipment, and relates to the technical field of display driving. According to the technical scheme, the potential maintaining module electrically connected with the first node is arranged in the pixel driving circuit, the potential maintaining module can maintain the potential of the first node, and the problem that negative bias coupling of a threshold compensation transistor is enhanced after heating is solved. The pixel driving circuit solves the problem that charge of the first node is transmitted to the second node through coupling of the threshold compensation transistor due to the fact that the first node is connected with the second node, further avoids the problem that the potential of the second node is pulled down, ensures the accuracy of driving current generated by the driving transistor, improves the reliability of the pixel driving circuit, and ensures that the display effect of the display panel is high.

Description

Technical Field

[0001] The present application relates to the field of display driving technology, and more specifically, to a display panel and an electronic device. Background Art

[0002] With the continuous development of science and technology, more and more electronic devices with display functions are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable tool for people today. An important component for realizing the display function in electronic equipment is the display panel. The display panel generally includes a number of pixel units, and each pixel unit includes an electrically connected pixel driving circuit and a light-emitting element. When the display panel displays a picture, the pixel driving circuit outputs a driving current to the light-emitting element, and the light-emitting element lights up in response to the driving current. Therefore, the reliability of the pixel driving circuit directly affects the display effect of the display panel. Summary of the invention

[0003] In view of this, the present application provides a display panel and an electronic device, which effectively solve the technical problems existing in the prior art, improve the reliability of the pixel driving circuit, and ensure a high display effect of the display panel.

[0004] To achieve the above objectives, the technical solutions provided by this application are as follows:

[0005] A display panel, the display panel comprising a plurality of pixel driving circuits, the pixel driving circuits comprising:

[0006] A driving transistor, the driving transistor being used to generate a driving current;

[0007] a threshold compensation transistor, wherein a first electrode of the threshold compensation transistor is electrically connected to an output electrode of the driving transistor at a first node, a second electrode of the threshold compensation transistor is electrically connected to a gate electrode of the driving transistor at a second node, and a gate electrode of the threshold compensation transistor is electrically connected to a threshold compensation control signal line;

[0008] A potential maintaining module is electrically connected to the first node.

[0009] Based on the same inventive concept, the present application also provides an electronic device, which includes the above-mentioned display panel.

[0010] Compared with the prior art, the technical solution provided by this application has at least the following advantages:

[0011] The present application provides a display panel and an electronic device, wherein the display panel includes a plurality of pixel driving circuits, wherein the pixel driving circuit includes: a driving transistor, wherein the driving transistor is used to generate a driving current; a threshold compensation transistor, wherein a first electrode of the threshold compensation transistor is electrically connected to an output electrode of the driving transistor at a first node, a second electrode of the threshold compensation transistor is electrically connected to a gate electrode of the driving transistor at a second node, and a gate electrode of the threshold compensation transistor is electrically connected to a threshold compensation control signal line; and a potential maintaining module, wherein the potential maintaining module is electrically connected to the first node.

[0012] It can be seen from the above content that the technical solution provided by the present application is that a potential holding module electrically connected to the first node is provided in the pixel driving circuit, and the potential holding module can maintain the potential of the first node, thereby improving the problem of the charge of the first node being coupled to the second node through the threshold compensation transistor due to the enhanced negative bias coupling of the threshold compensation transistor after heating, thereby avoiding the problem of the potential of the second node being pulled down, ensuring the accuracy of the driving current generated by the driving transistor, improving the reliability of the pixel driving circuit, and ensuring a high display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0014] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0015] Figure 2 A schematic diagram of the structure of a pixel driving circuit provided in an embodiment of the present application;

[0016] Figure 3 A schematic diagram of the structure of another pixel driving circuit provided in an embodiment of the present application;

[0017] Figure 4 A schematic diagram of the structure of another pixel driving circuit provided in an embodiment of the present application;

[0018] Figure 5 A timing diagram provided for an embodiment of the present application;

[0019] Figure 6 Another timing diagram provided for an embodiment of the present application;

[0020] Figure 7A schematic diagram of the structure of another pixel driving circuit provided in an embodiment of the present application;

[0021] Figure 8 A schematic diagram of the structure of another pixel driving circuit provided in an embodiment of the present application;

[0022] Fig. 9 A schematic diagram of the structure of another pixel driving circuit provided in an embodiment of the present application;

[0023] Fig.10 Another timing diagram provided for an embodiment of the present application;

[0024] Fig.11 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0025] Fig.12 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0026] Fig.13 A partial layout diagram of a pixel driving circuit provided in an embodiment of the present application;

[0027] Fig.14 for Fig.13 A schematic structural diagram of a first semiconductor layer;

[0028] Fig.15 for Fig.13 A schematic structural diagram of a first gate metal layer;

[0029] Fig.16 for Fig.13 A schematic diagram of the structure of a capacitor metal layer;

[0030] Fig.17 for Fig.13 A schematic structural diagram of a second gate metal layer;

[0031] Fig.18 for Fig.13 A schematic structural diagram of a second semiconductor layer;

[0032] Fig.19 for Fig.13 A schematic diagram of the structure of a source-drain metal layer;

[0033] Fig. 20 for Fig.13 A schematic diagram of the structure of a circuit metal layer;

[0034] Fig.21 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0035] Fig. 22A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0036] Fig.23 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0037] Fig.24 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0038] Fig.25 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0039] Fig.26 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0041] As described in the background technology, with the continuous development of science and technology, more and more electronic devices with display functions are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable and important tool for people today. An important component for realizing the display function in an electronic device is a display panel. The display panel generally includes a plurality of pixel units, and each pixel unit includes an electrically connected pixel driving circuit and a light-emitting element. When the display panel displays a picture, the pixel driving circuit outputs a driving current to the light-emitting element, and the light-emitting element lights up in response to the driving current. Therefore, the reliability of the pixel driving circuit directly affects the display effect of the display panel.

[0042] Based on this, the embodiments of the present application provide a display panel and an electronic device, which effectively solve the technical problems existing in the prior art, improve the reliability of the pixel driving circuit, and ensure a high display effect of the display panel.

[0043] To achieve the above purpose, the technical solution provided in the embodiment of the present application is as follows, specifically combined with Figures 1 to 26 The technical solution provided in the embodiments of the present application is described in detail.

[0044] Combination Figure 1 and Figure 2 As shown, Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application is shown in FIG. Figure 2A schematic diagram of the structure of a pixel driving circuit provided in an embodiment of the present application. The display panel 10 provided in an embodiment of the present application includes a plurality of pixel units Pi, each pixel unit Pi includes a pixel driving circuit 11, and at least one light-emitting element 12 electrically connected to the pixel driving circuit 11, and the light-emitting element 12 may be a light-emitting diode. The pixel driving circuit 11 includes: a driving transistor T0, the driving transistor T0 is used to generate a driving current; a threshold compensation transistor Ty, the first electrode of the threshold compensation transistor Ty is electrically connected to the output electrode of the driving transistor T0 at a first node N1, the second electrode of the threshold compensation transistor Ty is electrically connected to the gate of the driving transistor T0 at a second node N2, and the gate of the threshold compensation transistor Ty is electrically connected to the threshold compensation control signal line Sy; a potential holding module 110, the potential holding module 110 is electrically connected to the first node N1.

[0045] It is understandable that after the pixel driving circuit 11 completes the writing of the data voltage, it will control the threshold compensation transistor Ty to turn off. Due to the influence of conditions such as long-term operation and / or environmental factors, the threshold compensation transistor Ty will be heated. After the threshold compensation transistor Ty is heated, its negative bias coupling will be enhanced. Therefore, at the moment when the threshold compensation transistor Ty is turned off, the charge of the first node N1 will be transmitted to the second node N2 through the threshold compensation transistor Ty coupling, thereby lowering the potential of the second node N2. The potential of the second node N2 directly affects the size of the driving current generated by the driving transistor T0. Therefore, the lowering of the potential of the second node N2 will cause the driving current generated by the driving transistor T0 to deviate, thereby causing the problem of display color deviation and reducing the display effect of the display panel. According to the technical solution provided by the embodiment of the present application, a potential holding module 110 electrically connected to the first node N1 is provided in the pixel driving circuit 11. The potential holding module 110 can maintain the potential of the first node N1, thereby improving the problem that the charge of the first node N1 is transmitted to the second node N2 through the coupling of the threshold compensation transistor Ty due to the enhanced negative bias coupling of the threshold compensation transistor Ty after heating, thereby avoiding the problem that the potential of the second node N2 is pulled down, ensuring the accuracy of the driving current generated by the driving transistor T0, improving the reliability of the pixel driving circuit 11, and ensuring a high display effect of the display panel.

[0046] In some embodiments, the potential maintaining module 110 provided in the embodiments of the present application may use a capacitor to achieve the potential maintaining effect on the first node N1. Figure 3As shown, it is a structural schematic diagram of another pixel driving circuit provided in an embodiment of the present application, wherein the potential holding module 110 provided in an embodiment of the present application includes: a potential holding capacitor C1, a first plate of the potential holding capacitor C1 is electrically connected to a reference voltage line Vref, and a second plate of the potential holding capacitor C1 is electrically connected to the first node N1. The reference voltage line Vref provided in the embodiment of the present application is used to provide a fixed voltage, which can be a newly added voltage line in the display panel, or it can also reuse the original voltage line in the display panel. Optionally, the reference voltage line Vref provided in the embodiment of the present application can be a power supply voltage line (such as a first power supply voltage line PVDD and a second power supply voltage line PVEE), a reset voltage line (such as a first reset voltage line REF1 and a second reset voltage line REF2), a bias voltage line DVH, etc., and this application does not make specific restrictions on this.

[0047] refer to Figure 4 , which is a structural schematic diagram of another pixel driving circuit provided by an embodiment of the present application, wherein the potential holding module 110 provided by the embodiment of the present application further includes: a potential holding transistor Td, a first electrode of the potential holding transistor Td is electrically connected to the second electrode plate of the potential holding capacitor C1, a second electrode of the potential holding transistor Td is electrically connected to the first node N1, and a gate of the potential holding transistor Td is electrically connected to a potential holding control signal line Sd. When the potential holding capacitor C1 is required to hold the potential of the first node N1, the potential holding control signal line Sd controls the potential holding transistor Td to turn on, thereby connecting the potential holding capacitor C1 to the first node N1, thereby avoiding the potential holding capacitor C1 from affecting the potential of the first node N1 in other stages, and improving the reliability of the pixel driving circuit 11. In one embodiment, the potential holding capacitor C1 provided in the embodiment of the present application needs to hold the potential of the first node N1 after the threshold compensation transistor Ty completes the threshold compensation. Therefore, while the threshold compensation control signal line Sy controls the threshold compensation transistor Ty to complete the threshold compensation and turn off, the potential holding control signal line Sd controls the potential holding transistor Td to turn on. Figure 5 As shown, it is a timing diagram provided by an embodiment of the present application. Figure 4Taking the illustrated threshold compensation transistor Ty as an N-type transistor and the potential holding transistor Td as a P-type transistor as an example, the threshold compensation control signal line Sy provided in the embodiment of the present application jumps to a low level and controls the moment when the threshold compensation transistor Ty is turned off, that is, the moment when the potential holding control signal line Sd jumps to a low level and controls the potential holding transistor Td to be turned on, completes the process of turning off the threshold compensation transistor Ty while turning on the potential holding transistor Td, thereby avoiding the potential holding capacitor C1 from affecting the threshold compensation process. Or in another embodiment, in order to ensure the timeliness of the potential holding of the first node N1 after the threshold compensation, the potential holding control signal line Sd controls the potential holding transistor Td to be turned on within the first preset time t1 before the threshold compensation control signal line Sy controls the threshold compensation transistor Ty to complete the threshold compensation and turn off; specifically combined with Figure 6 As shown, another timing diagram provided in the embodiment of the present application is also based on Figure 4 Taking the illustrated threshold compensation transistor Ty as an N-type transistor and the potential holding transistor Td as a P-type transistor as an example, the threshold compensation control signal line Sy provided in the embodiment of the present application jumps to a low level to control the threshold compensation transistor Ty to be turned off within the first preset time t1, and the potential holding control signal line Sd jumps to a low level to control the potential holding transistor Td to be turned on, thereby avoiding the problem of the potential holding capacitor C1 not being able to control the potential of the first node N1 in a timely manner, and by optimizing the size of the first preset time t1, the influence of the potential holding capacitor C1 on the potential of the first node N1 during the threshold compensation process within this time period is reduced and ignored, thereby improving the reliability of the pixel driving circuit 11.

[0048] Similarly, in order to prevent the potential holding capacitor C1 from affecting the potential of the first node N1 when the light emitting element 12 is turned on, the potential holding control signal line Sd controls the potential holding transistor Td to turn off while the pixel driving circuit 11 drives the electrically connected light emitting element 12 to emit light. Alternatively, within the second preset time before the pixel driving circuit 11 drives the light emitting element 12 to emit light, the potential holding control signal line Sd controls the potential holding transistor Td to turn off, thereby realizing the control process of first turning off the potential holding transistor Td and then turning on the light emitting element 12, more effectively avoiding the problem that the potential holding capacitor C1 affects the potential of the first node N1 when the light emitting element 12 is turned on, and by optimizing the size of the second preset time, the problem of the charge of the first node N1 being transmitted to the second node N2 through the threshold compensation transistor Ty coupling during this time period is minimized and ignored, thereby improving the reliability of the pixel driving circuit 11.

[0049] In some embodiments, the pixel driving circuit 11 provided in the embodiment of the present application further includes a capacitor, a data writing circuit, a reset control circuit, a light emitting control circuit and other circuit structures, so as to realize the pixel driving circuit 11 to control the lighting of the light emitting element 12. The pixel driving circuit 11 applicable to the embodiment of the present application is described in more detail below in conjunction with the accompanying drawings. Figure 7 As shown, it is a structural schematic diagram of another pixel driving circuit provided in an embodiment of the present application, wherein the pixel driving circuit provided in an embodiment of the present application includes: a storage capacitor C2, a first plate of the storage capacitor C2 is electrically connected to a first power supply voltage line PVDD, and a second plate of the storage capacitor C2 is electrically connected to a gate of the driving transistor T0 (that is, the second plate of the storage capacitor C2 is electrically connected to a second node N2). A data writing module 120, the data writing module 120 is electrically connected to an input electrode of the driving transistor T0, and the data writing module 120 transmits the data voltage transmitted by the data voltage line Vdata to the driving transistor T0. A light emitting control module 130, the light emitting control module 130 is electrically connected in series with the driving transistor T0, and the light emitting control module 130 controls the driving current to be transmitted to the light emitting element 12.

[0050] Further references Figure 8 As shown, it is a structural schematic diagram of another pixel driving circuit provided in an embodiment of the present application, wherein the pixel driving circuit 11 provided in an embodiment of the present application further includes: a first reset module 140, the first reset module 140 is electrically connected to the gate of the driving transistor T0 (that is, the first reset module 140 is electrically connected to the second node N2), wherein the first reset module 140 transmits the first reset voltage delivered by the first reset voltage line REF1 to the gate of the driving transistor T0, thereby resetting the potential of the gate of the driving transistor T0, ensuring high accuracy of subsequent control of the driving transistor T0, and improving the reliability of the pixel driving circuit 11.

[0051] Continue as Figure 8As shown, the pixel driving circuit 11 provided in the embodiment of the present application also includes: a second reset module 150, the second reset module 150 is electrically connected to the anode of the light-emitting element 12, the light-emitting element 12 can be a light-emitting diode, and the cathode of the light-emitting element 12 is electrically connected to the second power supply voltage line PVEE, the second reset module 150 transmits the second reset voltage delivered by the second reset voltage line REF2 to the light-emitting element 12, thereby achieving the purpose of resetting the anode of the light-emitting element 12, avoiding the problem that the light-emitting element 12 is not dark when it is extinguished, and further improving the reliability of the pixel driving circuit 11. Furthermore, the pixel driving circuit 11 provided in the embodiment of the present application further includes: a bias module 160, wherein the bias module 160 is electrically connected to the input electrode of the driving transistor T0, and the bias module 160 transmits the bias voltage delivered by the bias voltage line DVH to the driving transistor T0, so as to adjust the bias state of the driving transistor T0 in the bias stage, so that the driving transistor T0 is reverse biased, the degree of ion polarization inside the driving transistor T0 is weakened, and the threshold voltage drift problem caused by the hysteresis effect of the driving transistor T0 due to long-term operation in the forward bias state is compensated, so as to avoid fluctuations in the brightness of the light-emitting element 12 driven by the pixel driving circuit 11, thereby improving the display effect of the display panel.

[0052] In some embodiments, the data writing module 120, the light emitting control module 130, the first reset module 140, the second reset module 150 and the bias module 160 provided in the embodiments of the present application can all realize related functions through transistors. Fig. 9, which is a structural schematic diagram of another pixel driving circuit provided in an embodiment of the present application, wherein the data writing module 120 provided in the embodiment of the present application includes a data writing transistor Tj, a first electrode of the data writing transistor Tj is electrically connected to the data voltage line Vdata, a second electrode of the data writing transistor Tj is electrically connected to the input electrode of the driving transistor T0, and a gate of the data writing transistor Tj is electrically connected to the data writing control signal line Sj; and / or the light emitting control module 130 includes a first light emitting control transistor Tf1 and a second light emitting control transistor Tf2, the first light emitting control transistor Tf 1 is electrically connected to the first power supply voltage line PVDD, the second electrode of the first light-emitting control transistor Tf1 is electrically connected to the input electrode of the driving transistor T0, the first electrode of the second light-emitting control transistor Tf2 is electrically connected to the output electrode of the driving transistor T0, the second electrode of the second light-emitting control transistor Tf2 is electrically connected to the anode of the light-emitting element 12, the first light-emitting control transistor Tf1 and the second light-emitting control transistor Tf2 have the same conduction type, and the gate of the first light-emitting control transistor Tf1 and the gate of the second light-emitting control transistor Tf2 are both electrically connected to the light-emitting control signal line Sf. And, the first reset module 140 provided in the embodiment of the present application includes: a first reset transistor Tw1, the first electrode of the first reset transistor Tw1 is electrically connected to the first reset voltage line REF1, the second electrode of the first reset transistor Tw1 is electrically connected to the gate of the driving transistor T0, and the gate of the first reset transistor Tw1 is electrically connected to the first reset control signal line Sw1. The second reset module 150 includes: a second reset transistor Tw2, a first electrode of the second reset transistor Tw2 is electrically connected to the second reset voltage line REF2, a second electrode of the second reset transistor Tw2 is electrically connected to the anode of the light emitting element 12, and a gate of the second reset transistor Tw2 is electrically connected to the second reset control signal line Sw2. The bias module 160 includes: a bias transistor Tz, a first electrode of the bias transistor Tz is electrically connected to the bias voltage line DVH, a second electrode of the bias transistor Tz is electrically connected to the input electrode of the driving transistor T0, wherein the bias transistor Tz and the second reset transistor Tw2 have the same conduction type, and the gate of the bias transistor Tz is electrically connected to the second reset control signal line Sw2.

[0053] It should be noted that the embodiment of the present application does not specifically limit the conduction type of the first reset transistor Tw1, the second reset transistor Tw2, the first light emission control transistor Tf1, the second light emission control transistor Tf2, the threshold compensation transistor Ty, the data writing transistor Tj, the bias transistor Tz, the driving transistor T0 and the potential holding transistor Td, which can be N-type transistors or P-type transistors. In some embodiments, the second reset transistor Tw2, the first light emission control transistor Tf1, the second light emission control transistor Tf2, the data writing transistor Tj, the bias transistor Tz, the driving transistor T0 and the potential holding transistor Td provided in the embodiment of the present application can be P-type transistors, while the first reset transistor Tw1 and the threshold compensation transistor Ty can be N-type transistors, and the first reset transistor Tw1 and the threshold compensation transistor Ty can be oxide thin film transistors, so as to reduce the leakage current problem of the first reset transistor Tw1 and the threshold compensation transistor Ty, and improve the reliability of the pixel driving circuit 11.

[0054] Combination Fig.10 A timing diagram is shown to describe the working principle of the pixel driving circuit 11 provided in the embodiment of the present application, wherein Fig.10 by Fig. 9 Taking the illustrated pixel driving circuit 11 as an example, the second reset transistor Tw2, the first light emission control transistor Tf1, the second light emission control transistor Tf2, the data writing transistor Tj, the bias transistor Tz and the driving transistor T0 are P-type transistors, and the first reset transistor Tw1 and the threshold compensation transistor Ty can be N-type transistors. The operation of the pixel driving circuit 11 includes a first bias stage M1, an initialization stage M2, a data writing and threshold compensation stage M3, a second bias stage M4 and a light emission stage M5 which are performed in sequence.

[0055] In the first bias stage M1, the second reset control signal line Sw2 outputs a low-level valid signal, and the threshold compensation control signal line Sy outputs a high-level valid signal, so as to correspondingly control the bias transistor Tz, the second reset transistor Tw2 and the threshold compensation transistor Ty to be turned on, while the remaining transistors are in the off state, thereby achieving the purpose of bias adjustment of the driving transistor T0 and resetting the light-emitting element 12. It can be seen that due to the existence of the bias module 160, the threshold compensation transistor Ty will be controlled to be turned on or off more frequently, which makes it easier for the threshold compensation transistor Ty to be heated and cause negative bias coupling problems, and it is easier for the charge of the first node N1 to be coupled to the second node N2 and the potential of the second node N2 to be lowered. Based on this, the pixel driving circuit 11 provided in the embodiment of the present application is provided with a potential holding module 110 electrically connected to the first node N1. The potential holding module 110 maintains the potential of the first node N1 after the threshold compensation stage, thereby improving the problem of the charge of the first node N1 being transmitted to the second node N2 through the threshold compensation transistor Ty due to the enhanced negative bias coupling of the threshold compensation transistor Ty after heating, thereby avoiding the problem of the potential of the second node N2 being pulled down, ensuring the accuracy of the driving current generated by the driving transistor T0, improving the reliability of the pixel driving circuit 11, avoiding the display color deviation problem, and ensuring the high display effect of the display panel.

[0056] In the initialization stage M2, the first reset control signal line Tw1 outputs a high-level effective signal to control the first reset transistor Tw1 to be turned on accordingly, thereby resetting the gate of the driving transistor T0 (that is, the second node N2), preventing the residual voltage at the second node N2 from affecting the subsequent operation of the pixel driving circuit 11, and improving the reliability of the pixel driving circuit 11. Optionally, in the initialization stage M2, the threshold compensation control signal line Sy can also jump to a high-level effective signal at the end of the stage to control the threshold compensation transistor Ty to be turned on and connect the second node N2 and the first node N1, thereby resetting the first node N1, eliminating the residual voltage at the first node N1, and further improving the reliability of the pixel driving circuit 11.

[0057] In the data writing and threshold compensation stage M3, the threshold compensation control signal line Sy outputs a high-level valid signal, and the data writing control signal line Sj outputs a low-level valid signal to correspondingly control the threshold compensation transistor Ty and the data writing transistor Tj to be turned on. Through the conduction path of the data writing transistor Tj, the driving transistor T0 and the threshold compensation transistor Ty, the data voltage output by the data voltage line Vdata is written to the second node N2, and the threshold voltage of the driving transistor T0 is compensated to the second node N2, thereby achieving the purpose of data writing and threshold compensation.

[0058] At the second bias node M2, the second reset control signal line Sw2 outputs a low-level valid signal to correspondingly control the bias transistor Tz and the second reset transistor Tw2 to be turned on, thereby biasing the driving transistor T0 again and resetting the light-emitting element 12. Among them, at the moment when the threshold compensation control signal line Sy jumps to a low-level invalid signal or within a first preset time before jumping to a low-level invalid signal in the threshold compensation stage M3, the potential holding control signal line Sd controls the potential holding transistor Td to be turned on, so that the potential holding capacitor C1 maintains the potential of the first node N1, avoiding the problem of the potential of the second node N2 being pulled down, thereby avoiding the problem of display color deviation.

[0059] In the light-emitting stage M5, the light-emitting control signal line Sf outputs a low-level valid signal to correspondingly control the first light-emitting control transistor Tf1 and the second light-emitting control transistor Tf2 to be turned on, thereby realizing the path from the first power supply voltage line PVDD to the second power supply voltage line PVEE, so as to control the driving current generated by the driving transistor T0 to be transmitted to the light-emitting element 12, and the light-emitting element 12 lights up in response to the driving current.

[0060] The potential holding capacitor C1 provided in the embodiment of the present application can effectively maintain the potential of the first node N1, thereby improving the problem of the charge of the first node N1 being transmitted to the second node N2 through the coupling of the threshold compensation transistor Ty due to the enhanced negative bias coupling of the threshold compensation transistor Ty after heating, wherein the potential holding capacitor C1 can be prepared by reusing the original structural layer in the display panel. Optionally, in a direction perpendicular to the plane where the display panel is located, the display panel provided in the embodiment of the present application includes a blocking metal layer 21, a first semiconductor layer 22, a first gate metal layer 23, a capacitor metal layer 24, a second semiconductor layer 25, a second gate metal layer 26, a source-drain metal layer 27 and a circuit metal layer 28 arranged in sequence; or, in a direction perpendicular to the plane where the display panel is located, the display panel provided in the embodiment of the present application includes a blocking metal layer 21, a first gate metal layer 23, a first semiconductor layer 22, a capacitor metal layer 24, a second gate metal layer 26, a second semiconductor layer 25, a source-drain metal layer 27 and a circuit metal layer 28 arranged in sequence; wherein at least one electrode plate of the potential holding capacitor C1 is located at least one of the blocking metal layer 21, the first semiconductor layer 22, the first gate metal layer 23, the capacitor metal layer 24, the second semiconductor layer 25, the second gate metal layer 26, the source-drain metal layer 27 and the circuit metal layer 28. For specific reference Fig.11As shown, it is a structural schematic diagram of another display panel provided by an embodiment of the present application, wherein all transistors provided by the embodiment of the present application can be top-gate transistors, and the display panel includes: a substrate 30; a shielding metal layer 21 located on a surface of the substrate 30; a first insulating layer 311 located on the side of the shielding metal layer 21 away from the substrate 30; a first semiconductor layer 22 located on the side of the first insulating layer 311 away from the substrate 30, the first semiconductor layer 22 including an active layer forming a first transistor TFT1; a second insulating layer 312 located on the side of the first semiconductor layer 22 away from the substrate 30; a first gate metal layer 23 located on the side of the second insulating layer 312 away from the substrate 30, the first gate metal layer 23 including a gate electrode forming the first transistor TFT1; a third insulating layer 313 located on the side of the first gate metal layer 23 away from the substrate 30; a capacitor metal layer 24 located on the side of the third insulating layer 313 away from the substrate 30; a fourth insulating layer 24 located on the side of the capacitor metal layer 24 away from the substrate 30 314; a second semiconductor layer 25 located on the side of the fourth insulating layer 314 away from the substrate 30, the second semiconductor layer 25 includes an active layer forming a second transistor TFT2; a fifth insulating layer 315 located on the side of the second semiconductor layer 25 away from the substrate 30; a second gate metal layer 26 located on the side of the fifth insulating layer 315 away from the substrate 30, the second gate metal layer 26 includes a gate electrode forming the second transistor TFT2; a sixth insulating layer 316 located on the side of the second gate metal layer 26 away from the substrate 30; a source-drain metal layer 27 located on the side of the sixth insulating layer 316 away from the substrate 30, the source-drain metal layer 27 includes a source and a drain electrode forming the first transistor TFT1, and includes a source and a drain electrode forming the second transistor TFT2; a seventh insulating layer 317 located on the side of the source-drain metal layer 27 away from the substrate 30; a circuit metal layer 28 located on the side of the seventh insulating layer 317 away from the substrate 30; and an eighth insulating layer 318 located on the side of the circuit metal layer 28 away from the substrate 30.

[0061] In some embodiments, the first semiconductor layer 22 provided in the embodiment of the present application may be a low-temperature polycrystalline silicon semiconductor layer, and the second semiconductor layer 25 may be an oxide semiconductor layer, wherein the first transistor TFT1 may be used to prepare the second reset transistor Tw2, the first light emission control transistor Tf1, the second light emission control transistor Tf2, the data writing transistor Tj, the bias transistor Tz, the driving transistor T0 and the potential holding transistor Td, and the second transistor TFT2 may be used to prepare the first reset transistor Tw1 and the threshold compensation transistor Ty, and the present application does not impose any specific restrictions on this. The first transistor TFT1 and the second transistor TFT2 provided in the embodiment of the present application may both be Fig.11 Alternatively, the first transistor TFT1 and the second transistor TFT2 provided in the embodiment of the present application may both be bottom-gate transistors; Fig.12, which is a schematic diagram of the structure of another display panel provided by an embodiment of the present application, wherein all transistors provided by the embodiment of the present application may be bottom-gate transistors, and the display panel includes: a substrate 30; a shielding metal layer 21 located on a surface of the substrate 30; a first insulating layer 321 located on the side of the shielding metal layer 21 away from the substrate 30; a first gate metal layer 23 located on the side of the first insulating layer 321 away from the substrate 30, the first gate metal layer 23 including a gate electrode forming a first transistor TFT1; a second insulating layer 322 located on the side of the first gate metal layer 23 away from the substrate 30; a first semiconductor layer 22 located on the side of the second insulating layer 322 away from the substrate 30, the first semiconductor layer 22 including an active layer forming the first transistor TFT1; a third insulating layer 323 located on the side of the first semiconductor layer 22 away from the substrate 30; a capacitor metal layer 24 located on the side of the third insulating layer 323 away from the substrate 30; and a fourth insulating layer 24 located on the side of the capacitor metal layer 24 away from the substrate 30. 324; a second gate metal layer 26 located on the side of the fourth insulating layer 324 away from the substrate 30, the second gate metal layer 26 includes a gate electrode forming a second transistor TFT2; a fifth insulating layer 325 located on the side of the second gate metal layer 26 away from the substrate 30; a second semiconductor layer 25 located on the side of the fifth insulating layer 325 away from the substrate 30, the second semiconductor layer 25 includes an active layer forming a second transistor TFT2; a sixth insulating layer 326 located on the side of the second semiconductor layer 25 away from the substrate 30; a source-drain metal layer 27 located on the side of the sixth insulating layer 326 away from the substrate 30, the source-drain metal layer 27 includes a source and a drain electrode forming the first transistor TFT1, and includes a source and a drain electrode forming the second transistor TFT2; a seventh insulating layer 327 located on the side of the source-drain metal layer 27 away from the substrate 30; a circuit metal layer 28 located on the side of the seventh insulating layer 327 away from the substrate 30; and an eighth insulating layer 328 located on the side of the circuit metal layer 28 away from the substrate 30.

[0062] It should be noted that in the display panel provided in the embodiment of the present application, the first transistor TFT1 and the second transistor TFT2 can both be top-gate transistors, or the first transistor TFT1 and the second transistor TFT2 can both be bottom-gate transistors; or, the first transistor TFT1 can be a top-gate transistor, and the second transistor TFT2 can be a bottom-gate transistor (i.e., the first semiconductor layer 22 in the display panel is located between the shielding metal layer 21 and the first gate metal layer 23, and the second semiconductor layer 22 is located between the second gate metal layer 26 and the source-drain metal layer 27); or, the first transistor TFT1 can be a bottom-gate transistor, and the second transistor TFT2 can be a top-gate transistor (i.e., the first semiconductor layer 22 in the display panel is located between the first gate metal layer 22 and the capacitor metal layer 24, and the second semiconductor layer 25 is located between the capacitor metal layer 24 and the second gate metal layer 26), and the present application does not make specific restrictions on this, and needs to be specifically designed according to actual applications. Optionally, the material of all insulating layers provided in the embodiment of the present application can be nitride or oxide, such as silicon nitride or silicon oxide.

[0063] In some embodiments, the display panel provided by the embodiment of the present application may include pixel units Pi of multiple colors, and the light emitting colors of the light emitting elements 12 electrically connected to the pixel driving circuit 11 in the pixel units Pi of different colors are different. Among them, since the luminous efficiency of the pixel units Pi of different colors is different, the driving current generated by the driving transistor T0 in the different pixel units Pi is also different, which leads to different degrees of lowering the potential of the second node N2 of the pixel units Pi of different colors; that is, the lower the luminous efficiency of the pixel unit Pi, the greater the driving current required, which leads to a greater degree of lowering the potential of the second node N2 of the pixel unit Pi with lower luminous efficiency, causing more serious color deviation. In the pixel units Pi of different colors provided by the embodiment of the present application, the capacity of the potential holding capacitor C1 of the pixel unit Pi with low luminous efficiency is set to be greater than the capacity of the potential holding capacitor C1 of the pixel unit Pi with high luminous efficiency, thereby improving the problem of the potential of the second node N2 of the pixel unit Pi with lower luminous efficiency being pulled down to a greater extent, thereby avoiding the display color deviation problem. Optionally, the pixel driving circuit 11 provided in the embodiment of the present application includes a first pixel driving circuit 111 and a second pixel driving circuit 112, wherein the first pixel driving circuit 111 is electrically connected to a blue light emitting element, and the second pixel driving circuit 112 is electrically connected to a red light emitting element or a green light emitting element; the capacitance value of the potential holding capacitor C1 of the first pixel driving circuit 111 is greater than the capacitance value of the potential holding capacitor C1 of the second pixel driving circuit 112. And, the pixel driving circuit 11 provided in the embodiment of the present application includes a third pixel driving circuit 113, wherein the third pixel driving circuit 113 is electrically connected to the red light emitting element or the green light emitting element, and the light emitting colors of the light emitting elements electrically connected to the second pixel driving circuit 112 and the third pixel driving circuit 113 are different; the capacitance value of the potential holding capacitor C1 of the pixel driving circuit electrically connected to the red light emitting element is greater than the capacitance value of the potential holding capacitor C1 of the pixel driving circuit electrically connected to the green light emitting element.

[0064] It can be understood that the multiple pixel units Pi provided in the embodiment of the present application may include a blue light pixel unit, a red light pixel unit and a green light pixel unit, the pixel driving circuit 11 in the blue light pixel unit is electrically connected to the blue light emitting element, the pixel driving circuit 11 in the red light pixel unit is electrically connected to the red light emitting element, and the pixel driving circuit 11 in the green light pixel unit is electrically connected to the green light emitting element. Since the luminous efficiency of the blue light pixel unit is significantly lower than that of the red light pixel unit, and is much lower than that of the green light pixel unit, in order to balance the degree to which the second node N2 of the pixel driving circuit 11 in the blue light pixel unit, the red light pixel unit and the green light pixel unit is pulled down, the capacitance value of the potential holding capacitor C1 of the blue light pixel unit provided in the embodiment of the present application is greater than the capacitance value of the potential holding capacitor C1 of the red light pixel unit, and the capacitance value of the potential holding capacitor C1 of the blue light pixel unit is greater than the capacitance value of the potential holding capacitor C1 of the green light pixel unit; and the capacitance value of the potential holding capacitor C1 of the red light pixel unit can be set to be greater than the capacitance value of the potential holding capacitor C1 of the green light pixel unit, or, the capacitance value of the potential holding capacitor C1 of the red light pixel unit can be set to be equal to the capacitance value of the potential holding capacitor C1 of the green light pixel unit, and the present application does not make any specific restrictions on this.

[0065] Specific reference Figures 13 to 20 As shown, Fig.13 A partial layout diagram of a pixel driving circuit provided in an embodiment of the present application, Fig.14 for Fig.13 A schematic structural diagram of a first semiconductor layer, Fig.15 for Fig.13 A schematic structural diagram of a first gate metal layer; Fig.16 for Fig.13 A schematic diagram of the structure of a capacitor metal layer; Fig.17 for Fig.13 A schematic structural diagram of a second gate metal layer; Fig.18 for Fig.13 A schematic structural diagram of a second semiconductor layer; Fig.19 for Fig.13 A schematic diagram of the structure of a source-drain metal layer; Fig. 20 for Fig.13A schematic diagram of the structure of a circuit metal layer in the display panel. A blue light pixel unit, a green light pixel unit and a red light pixel unit can be adjacent to form a pixel point, wherein the first pixel driving circuit 111 is electrically connected to the blue light emitting element, the second pixel driving circuit 112 is electrically connected to the red light emitting element, and the third pixel driving circuit 113 is electrically connected to the green light emitting element. In order to balance the degree to which the second node N2 of the pixel driving circuit 11 in the blue light pixel unit, the red light pixel unit and the green light pixel unit is pulled down, the capacitance value of the potential holding capacitor C1 of the first pixel driving circuit 111 provided in the embodiment of the present application is greater than the capacitance value of the potential holding capacitor C1 of the second pixel driving circuit 113, and the capacitance value of the potential holding capacitor C1 of the first pixel driving circuit 111 is greater than the capacitance value of the potential holding capacitor C1 of the third pixel driving circuit 113; and the capacitance value of the potential holding capacitor C1 of the second pixel driving circuit 112 can be set to be greater than the capacitance value of the potential holding capacitor C1 of the third pixel driving circuit 113, or, the capacitance value of the potential holding capacitor C1 of the second pixel driving circuit 112 can be set to be equal to the capacitance value of the potential holding capacitor C1 of the third pixel driving circuit 113, and the present application does not make any specific restrictions on this. When the first pixel driving circuit 111 provided in the embodiment of the present application is electrically connected to the blue light emitting element, the second pixel driving circuit 112 is electrically connected to the red light emitting element, and the third pixel driving circuit 113 is electrically connected to the green light emitting element, the ratio of the capacitance value B of the potential holding capacitor C1 of the first pixel driving circuit 111, the capacitance value R of the potential holding capacitor C1 of the second pixel driving circuit 112, and the capacitance value G of the potential holding capacitor C1 of the third pixel driving circuit 113 can be B:R:G, which is a:b:1, wherein the values ​​of a and b are greater than 1 and less than or equal to 100, and a is greater than b, and the present application does not make any specific restrictions on this.

[0066] In some embodiments, in order to adjust the capacitance value of the potential holding capacitor C1, the overlapping area between the plates of the potential holding capacitor C1 can be adjusted. Specifically, the first pixel driving circuit 111 provided in the embodiment of the present application is electrically connected to the blue light emitting element, the second pixel driving circuit 112 is electrically connected to the red light emitting element, and the third pixel driving circuit 113 is electrically connected to the green light emitting element, wherein: the overlapping area between the first plate and the second plate of the potential holding capacitor C1 of the first pixel driving circuit 111 is greater than the overlapping area between the first plate and the second plate of the potential holding capacitor C1 of the second pixel driving circuit 112; and / or, the overlapping area between the first plate and the second plate of the potential holding capacitor C1 of the second pixel driving circuit 112 is greater than the overlapping area between the first plate and the second plate of the potential holding capacitor C1 of the third pixel driving circuit 113. Specifically as Fig.21 1 is a schematic diagram of the structure of another display panel provided by an embodiment of the present application, wherein, taking the case where the two plates of all potential holding capacitors C1 are respectively located on the first gate metal layer 23 and the capacitor metal layer 24, the overlapping area S1 of the first plate and the second plate of the potential holding capacitor C1 of the first pixel driving circuit 111 provided by the embodiment of the present application is greater than the overlapping area S2 of the first plate and the second plate of the potential holding capacitor C1 of the second pixel driving circuit 112; and the overlapping area S1 of the first plate and the second plate of the potential holding capacitor C1 of the first pixel driving circuit 111 is greater than the overlapping area S2 of the first plate and the second plate of the potential holding capacitor C1 of the third pixel driving circuit 113. The overlapping area S3 of the first plate and the second plate of the potential holding capacitor C1 of the second pixel driving circuit 112 is greater than the overlapping area S3 of the first plate and the second plate of the potential holding capacitor C1 of the third pixel driving circuit 113, thereby achieving a solution in which the capacitance value of the potential holding capacitor C1 of the first pixel driving circuit 111 is greater than the capacitance value of the potential holding capacitor C1 of the second pixel driving circuit 112, and the capacitance value of the potential holding capacitor C1 of the second pixel driving circuit 112 is greater than the capacitance value of the potential holding capacitor C1 of the third pixel driving circuit 113.

[0067] Alternatively, in order to adjust the capacitance value of the potential holding capacitor C1, the spacing between the plates of the potential holding capacitor C1 can be adjusted. Specifically, the first pixel driving circuit 111 provided in the embodiment of the present application is electrically connected to the blue light emitting element, the second pixel driving circuit 112 is electrically connected to the red light emitting element, and the third pixel driving circuit 113 is electrically connected to the green light emitting element, wherein: the spacing between the first plate and the second plate of the potential holding capacitor C1 of the first pixel driving circuit 111 is smaller than the spacing between the first plate and the second plate of the potential holding capacitor C1 of the second pixel driving circuit 112; and / or, the spacing between the first plate and the second plate of the potential holding capacitor of the second pixel driving circuit 112 is smaller than the spacing between the first plate and the second plate of the potential holding capacitor of the third pixel driving circuit 113. For specific reference, Fig. 22, which is a schematic diagram of the structure of another display panel provided by an embodiment of the present application, wherein, when the overlapping areas of the two pole plates of the potential holding capacitor C1 of the first pixel driving circuit 111, the second pixel driving circuit 112 and the third pixel driving circuit 113 are consistent, the two pole plates of the potential holding capacitor C1 of the first pixel driving circuit 111 provided by the embodiment of the present application are respectively located at the first gate metal layer 23 and the capacitor metal layer 24, and the distance between the two pole plates of the potential holding capacitor C1 of the first pixel driving circuit 111 is d1; the two pole plates of the potential holding capacitor C1 of the second pixel driving circuit 112 are respectively located at the first gate metal layer 23 and the second semiconductor layer 25, and the second pixel driving circuit 1 12 has a spacing between two plates of the potential holding capacitor C1 of the third pixel driving circuit 112 of d2; and, the two plates of the potential holding capacitor C1 of the third pixel driving circuit 112 are respectively located at the first gate metal layer 23 and the second gate metal layer 26, and the spacing between the two plates of the potential holding capacitor C1 of the third pixel driving circuit 112 is d3, wherein d1 is less than d2, and d2 is less than d3, thereby achieving a solution in which the capacitance value of the potential holding capacitor C1 of the first pixel driving circuit 111 is greater than the capacitance value of the potential holding capacitor C1 of the second pixel driving circuit 112, and the capacitance value of the potential holding capacitor C1 of the second pixel driving circuit 112 is greater than the capacitance value of the potential holding capacitor C1 of the third pixel driving circuit 113.

[0068] It should be noted that the embodiments of the present application provide Fig.21 and Fig. 22 The illustrated methods for adjusting the capacitance value of the potential holding capacitor C1 are only two of all the adjustment methods applicable to the present application; in some other embodiments, the overlapping area of ​​the two plates of the potential holding capacitor C1 can be adjusted separately, or the spacing between the two plates of the potential holding capacitor C1 can be adjusted separately; or, the overlapping area and spacing between the two plates of the potential holding capacitor C1 can be adjusted, and the present application does not impose any specific restrictions on this. In some embodiments, the technical solution provided in the embodiments of the present application, when adjusting the overlapping area of ​​the two plates of the potential holding capacitor C1, one of the plates can be set as a sub-plate of at least two different structural layers, and the purpose of adjusting the overlapping area of ​​the two plates of the potential holding capacitor C1 can be achieved by overlapping the at least two sub-plates with the other plate. Specific reference is made to Fig.23As shown, it is a structural schematic diagram of another display panel provided in an embodiment of the present application, wherein the pixel driving circuit provided in the embodiment of the present application includes a first pixel driving circuit 111, and the first pixel driving circuit 111 is electrically connected to the blue light emitting element; the first electrode plate of the potential holding capacitor C1 of the first pixel driving circuit 111 includes at least two sub-plates, such as a first sub-plate B11 located in the first semiconductor layer 22 and a second sub-plate B12 located in the constant capacitance metal layer 24; in the direction Y perpendicular to the plane where the display panel is located, one side of the second electrode plate B2 corresponds to at least one of the sub-plates, thereby achieving the purpose of increasing the capacitance value of the potential holding capacitor C1 of the first pixel driving circuit 111.

[0069] refer to Fig.25 As shown, it is a structural schematic diagram of another display panel provided in an embodiment of the present application, wherein the active layer of the driving transistor T0 provided in the embodiment of the present application is located in the first semiconductor layer 22; the first electrode B1 of the potential holding capacitor C1 can be located in the capacitor metal layer 24, the second electrode B2 of the potential holding capacitor C1 can be located in the first semiconductor layer 22, and the second electrode B2 of the potential holding capacitor C1 extends to contact and communicate with the active layer of the driving transistor T0, thereby achieving the purpose of electrically connecting the second electrode plate of the potential holding capacitor C1 and the output electrode of the driving transistor T0 at the first node N1, avoiding the electrical connection between the second electrode plate of the potential holding capacitor C1 and the output electrode of the driving transistor T0 by punching, simplifying the preparation process of the display panel, and improving the preparation yield of the display panel.

[0070] Based on the same inventive concept, the embodiment of the present application also provides an electronic device. Fig.26 As shown, it is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application, wherein the electronic device 1000 provided in an embodiment of the present application includes the display panel provided in any one of the above embodiments, or includes the spliced ​​display screen provided in any one of the above embodiments.

[0071] In some embodiments, the electronic device 1000 provided in the embodiment of the present application may be a large or small device such as a mobile terminal, a notebook, a tablet computer, a computer, a wearable device, etc., and the present application does not impose any specific restrictions on this.

[0072] In summary, the embodiment of the present application provides a display panel and an electronic device, the display panel includes a plurality of pixel driving circuits, the pixel driving circuit includes: a driving transistor, the driving transistor is used to generate a driving current; a threshold compensation transistor, the first electrode of the threshold compensation transistor is electrically connected to the output electrode of the driving transistor at a first node, the second electrode of the threshold compensation transistor is electrically connected to the gate of the driving transistor at a second node, and the gate of the threshold compensation transistor is electrically connected to the threshold compensation control signal line; a potential holding module, the potential holding module is electrically connected to the first node. From the above content, it can be seen that the technical solution provided by the embodiment of the present application, the pixel driving circuit is provided with a potential holding module electrically connected to the first node, the potential holding module can maintain the potential of the first node, improves the problem that the charge of the first node is transmitted to the second node through the coupling of the threshold compensation transistor due to the enhanced negative bias coupling after heating, thereby avoiding the problem that the potential of the second node is pulled down, ensuring the accuracy of the driving current generated by the driving transistor, improving the reliability of the pixel driving circuit, and ensuring the high display effect of the display panel.

[0073] In the description of the embodiments of the present application, it needs to be understood that the orientation or position relationship indicated by terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0074] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the embodiments of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0075] In the embodiments of the present application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0076] In the embodiments of the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0077] In the embodiments of the present application, if the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" appear, it means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradicting each other.

[0078] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A display panel, characterized in that: The display panel includes a plurality of pixel driving circuits, and the pixel driving circuits include: A driving transistor, the driving transistor being used to generate a driving current; a threshold compensation transistor, wherein a first electrode of the threshold compensation transistor is electrically connected to an output electrode of the driving transistor at a first node, a second electrode of the threshold compensation transistor is electrically connected to a gate electrode of the driving transistor at a second node, and a gate electrode of the threshold compensation transistor is electrically connected to a threshold compensation control signal line; A potential maintaining module is electrically connected to the first node.

2. The display panel according to claim 1, characterized in that: The potential holding module comprises: a potential holding capacitor, a first plate of the potential holding capacitor is electrically connected to a reference voltage line, and a second plate of the potential holding capacitor is electrically connected to the first node.

3. The display panel according to claim 2, characterized in that: The potential holding module also includes: a potential holding transistor, a first electrode of the potential holding transistor is electrically connected to the second electrode plate of the potential holding capacitor, a second electrode of the potential holding transistor is electrically connected to the first node, and a gate of the potential holding transistor is electrically connected to a potential holding control signal line.

4. The display panel according to claim 3, characterized in that: While the threshold compensation control signal line controls the threshold compensation transistor to be turned off after completing threshold compensation, the potential holding control signal line controls the potential holding transistor to be turned on.

5. The display panel according to claim 3, characterized in that: During a first preset time before the threshold compensation control signal line controls the threshold compensation transistor to complete threshold compensation and be turned off, the potential holding control signal line controls the potential holding transistor to be turned on.

6. The display panel according to claim 3, characterized in that: While the pixel driving circuit drives the electrically connected light emitting element to emit light, the potential holding control signal line controls the potential holding transistor to turn off.

7. The display panel according to claim 3, characterized in that: Within a second preset time before the pixel driving circuit drives the light emitting element to emit light, the potential holding control signal line controls the potential holding transistor to be turned off.

8. The display panel according to claim 2, characterized in that: The pixel driving circuit includes a first pixel driving circuit and a second pixel driving circuit, the first pixel driving circuit is electrically connected to the blue light emitting element, and the second pixel driving circuit is electrically connected to the red light emitting element or the green light emitting element; The capacitance value of the potential holding capacitor of the first type of pixel driving circuit is greater than the capacitance value of the potential holding capacitor of the second type of pixel driving circuit.

9. The display panel according to claim 8, characterized in that: The pixel driving circuit includes a third type of pixel driving circuit, wherein the third type of pixel driving circuit is electrically connected to the red light emitting element or the green light emitting element, and the light emitting colors of the light emitting elements electrically connected to the second type of pixel driving circuit and the third type of pixel driving circuit are different; The capacitance value of the potential holding capacitor of the pixel driving circuit electrically connected to the red light emitting element is greater than the capacitance value of the potential holding capacitor of the pixel driving circuit electrically connected to the green light emitting element.

10. The display panel according to claim 9, characterized in that: The first pixel driving circuit is electrically connected to the blue light emitting element, the second pixel driving circuit is electrically connected to the red light emitting element, and the third pixel driving circuit is electrically connected to the green light emitting element, wherein: The overlapping area between the first electrode plate and the second electrode plate of the potential holding capacitor of the first pixel driving circuit is greater than the overlapping area between the first electrode plate and the second electrode plate of the potential holding capacitor of the second pixel driving circuit; and / or, an overlapping area between the first plate and the second plate of the potential holding capacitor of the second pixel driving circuit is greater than an overlapping area between the first plate and the second plate of the potential holding capacitor of the third pixel driving circuit; And / or, the distance between the first electrode plate and the second electrode plate of the potential holding capacitor of the first pixel driving circuit is smaller than the distance between the first electrode plate and the second electrode plate of the potential holding capacitor of the second pixel driving circuit; And / or, the distance between the first plate and the second plate of the potential holding capacitor of the second pixel driving circuit is smaller than the distance between the first plate and the second plate of the potential holding capacitor of the third pixel driving circuit.

11. The display panel according to claim 9, characterized in that: The first pixel driving circuit is electrically connected to the blue light emitting element, the second pixel driving circuit is electrically connected to the red light emitting element, and the third pixel driving circuit is electrically connected to the green light emitting element; Among them, the ratio B:R:G of the capacitance value B of the potential holding capacitor of the first pixel driving circuit, the capacitance value R of the potential holding capacitor of the second pixel driving circuit, and the capacitance value G of the potential holding capacitor of the third pixel driving circuit is a:b:1, wherein the values ​​of a and b are greater than 1 and less than or equal to 100, and a is greater than b.

12. The display panel according to claim 2, characterized in that: In a direction perpendicular to the plane where the display panel is located, the display panel includes a blocking metal layer, a first semiconductor layer, a first gate metal layer, a capacitor metal layer, a second semiconductor layer, a second gate metal layer, a source-drain metal layer, and a circuit metal layer arranged in sequence; or, in a direction perpendicular to the plane where the display panel is located, the display panel includes a blocking metal layer, a first gate metal layer, a first semiconductor layer, a capacitor metal layer, a second gate metal layer, a second semiconductor layer, a source-drain metal layer, and a circuit metal layer arranged in sequence. Among them, at least one electrode plate of the potential holding capacitor is located at at least one of the blocking metal layer, the first semiconductor layer, the first gate metal layer, the capacitor metal layer, the second semiconductor layer, the second gate metal layer, the source and drain metal layer and the circuit metal layer.

13. The display panel according to claim 12, characterized in that: The active layer of the driving transistor is located in the first semiconductor layer; The second electrode plate of the potential holding capacitor is located on the first semiconductor layer, and the second electrode plate of the potential holding capacitor extends to contact and communicate with the active layer of the driving transistor.

14. The display panel according to claim 12, characterized in that: The pixel driving circuit includes a first pixel driving circuit, and the first pixel driving circuit is electrically connected to the blue light emitting element; The first electrode plate of the potential holding capacitor of the first pixel driving circuit includes at least two sub-electrode plates; in a direction perpendicular to the plane where the display panel is located, one side of the second electrode plate corresponds to at least one of the sub-electrode plates.

15. The display panel according to claim 1, characterized in that: The pixel driving circuit comprises: a storage capacitor, a first plate of the storage capacitor is electrically connected to a first power supply voltage line, and a second plate of the storage capacitor is electrically connected to a gate of the driving transistor; A data writing module, the data writing module is electrically connected to the input electrode of the driving transistor, and the data writing module transmits the data voltage to the driving transistor; A light emitting control module is electrically connected in series with the driving transistor, and controls the driving current to be transmitted to the light emitting element.

16. The display panel according to claim 15, characterized in that: The data writing module comprises a data writing transistor, a first electrode of the data writing transistor is electrically connected to a data voltage line, a second electrode of the data writing transistor is electrically connected to an input electrode of the driving transistor, and a gate of the data writing transistor is electrically connected to a data writing control signal line; And / or, the light-emitting control module includes a first light-emitting control transistor and a second light-emitting control transistor, the first electrode of the first light-emitting control transistor is electrically connected to the first power supply voltage line, the second electrode of the first light-emitting control transistor is electrically connected to the input electrode of the driving transistor, the first electrode of the second light-emitting control transistor is electrically connected to the output electrode of the driving transistor, the second electrode of the second light-emitting control transistor is electrically connected to the anode of the light-emitting element, and the gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor are both electrically connected to the light-emitting control signal line.

17. The display panel according to claim 1, characterized in that: The pixel driving circuit further includes: a first reset module, the first reset module is electrically connected to the gate of the driving transistor, wherein the first reset module transmits a first reset voltage to the gate of the driving transistor.

18. The display panel according to claim 17, characterized in that: The first reset module includes: a first reset transistor, a first electrode of the first reset transistor is electrically connected to a first reset voltage line, a second electrode of the first reset transistor is electrically connected to a gate of the driving transistor, and a gate of the first reset transistor is electrically connected to a first reset control signal line.

19. The display panel according to claim 17, characterized in that: The pixel driving circuit further includes: a second reset module, the second reset module is electrically connected to the anode of the light emitting element, and the second reset module transmits a second reset voltage to the light emitting element.

20. The display panel according to claim 19, characterized in that: The second reset module includes: a second reset transistor, a first electrode of the second reset transistor is electrically connected to a second reset voltage line, a second electrode of the second reset transistor is electrically connected to an anode of the light emitting element, and a gate of the second reset transistor is electrically connected to a second reset control signal line.

21. The display panel according to claim 19, characterized in that: The pixel driving circuit further includes: a bias module, the bias module is electrically connected to the input electrode of the driving transistor, and the bias module transmits a bias voltage to the driving transistor; The bias module includes: a bias transistor, a first electrode of the bias transistor is electrically connected to a bias voltage line, a second electrode of the bias transistor is electrically connected to an input electrode of the driving transistor, and a gate of the bias transistor is electrically connected to a second reset control signal line.

22. An electronic device, characterized in that: The electronic device comprises the display panel according to any one of claims 1-21.

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