High-frequency digital phase-locked amplifier based on parallel digital algorithm and control method

Abstract

The invention discloses a high-frequency digital phase-locked amplifier based on a parallel digital algorithm and a control method. The amplifier comprises an analog-to-digital converter module, a serial-to-parallel module, an N parallel frequency measurement module, an N parallel phase-locked loop module and an N parallel input coherent demodulation module. The method comprises the following steps: acquiring an analog input signal and a reference signal, and sampling; performing serial-parallel conversion processing on the sampled digital input signal and the digital reference signal; performing frequency measurement on the N parallel digital reference signals to obtain reference signal frequency measurement information; performing phase locking adjustment on the N parallel digital reference signals to obtain frequency information and phase information; and performing demodulation processing on the N parallel digital input signals to obtain amplitude information, phase information and XY component information of the digital input signals. The embodiment of the invention can reduce the rate of the data flow and improve the throughput of the data information, thereby improving the bandwidth of the phase-locked amplification system. The invention can be widely applied to the technical field of phase-locked amplification.

Description

Technical Field

[0001] The present application relates to the technical field of phase-locked amplifier, and in particular to a high-frequency digital phase-locked amplifier and a control method based on a parallel digital algorithm. Background Art

[0002] Lock-in amplifier technology is an important technology in the field of weak signal detection. Based on the principle of cross-correlation operation, it can extract signals of a specific frequency band under strong background noise, and has a wide range of applications in biomedicine, optics, electronics, etc. The bandwidth of the lock-in amplifier directly determines the frequency range that the lock-in amplifier can handle, which is a very critical parameter. For digital lock-in amplifiers, this parameter is mainly limited by the speed of the digital-to-analog converter, the analog-to-digital converter, and the digital processing module.

[0003] In the digital phase-locked amplifier of the related art, the input signal is collected into the FPGA through the analog-to-digital converter, the reference signal is passed through the sine-to-square wave module, or the reference signal is triggered and phase-shifted in the analog, and then collected into a digital signal for processing. The data stream is consistent with the sampling rate of the analog-to-digital converter, and the digital part is processed by a serial algorithm. Since the processing frequency of the FPGA generally reaches up to 300MHz-400MHz, its data stream is also up to 300MHz-400MHz, which causes the bandwidth of the phase-locked amplifier in the related art to be limited by this frequency, reducing the frequency range of the signal that the phase-locked amplifier can measure.

[0004] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the invention

[0005] The main purpose of the embodiments of the present application is to propose a high-frequency digital phase-locked amplifier and control method based on a parallel digital algorithm, which can reduce the rate of data flow and increase the throughput of data information, thereby increasing the bandwidth of the phase-locked amplifier system.

[0006] To achieve the above-mentioned purpose, an embodiment of the present application provides a high-frequency digital phase-locked amplifier based on a parallel digital algorithm, wherein the high-frequency digital phase-locked amplifier comprises an analog-to-digital converter module, a serial-to-parallel module, an N-parallel frequency measurement module, an N-parallel phase-locked loop module and an N-parallel input coherent demodulation module, wherein the output end of the analog-to-digital converter module is connected to the input end of the serial-to-parallel module, the first output end of the serial-to-parallel module is connected to the input end of the N-parallel frequency measurement module, the second output end of the serial-to-parallel module is connected to the first input end of the N-parallel phase-locked loop module, the output end of the N-parallel frequency measurement module is connected to the second input end of the N-parallel phase-locked loop module, the third output end of the serial-to-parallel module is connected to the first input end of the N-parallel input coherent demodulation module, and the output end of the N-parallel phase-locked loop module is connected to the second input end of the N-parallel input coherent demodulation module, wherein:

[0007] The analog-to-digital converter module is used to acquire an analog input signal and a reference signal and perform sampling processing to obtain a sampled digital input signal and a sampled digital reference signal;

[0008] The serial-to-parallel module is used to perform serial-to-parallel processing on the sampled digital input signal and the sampled digital reference signal to obtain N parallel digital input signals and N parallel digital reference signals;

[0009] The N parallel frequency measurement module is used to measure the frequency of the N parallel digital reference signals to obtain reference signal frequency measurement information;

[0010] The N parallel phase-locked loop module is used to perform phase-locked adjustment on the N parallel digital reference signals according to the reference signal frequency measurement information to obtain the frequency information of the reference signal and the phase information of the reference signal;

[0011] The N parallel input coherent demodulation module is used to demodulate the N parallel digital input signals according to the frequency information of the reference signal and the phase information of the reference signal to obtain the amplitude information of the digital input signal, the phase information of the digital input signal and the XY component information of the digital input signal.

[0012] In some embodiments, the N parallel frequency measurement module includes an N parallel pipeline zero-crossing detector, a delay compensation module, an N parallel rising edge detection module, an N parallel pipeline frequency divider and an N parallel pipeline counter, wherein the first output end of the N parallel pipeline zero-crossing detector is connected to the input end of the delay compensation module, the second output end of the N parallel pipeline zero-crossing detector is connected to the first input end of the N parallel rising edge detection module, the output end of the delay compensation module is connected to the second input end of the N parallel rising edge detection module, the output end of the N parallel rising edge detection module is connected to the input end of the N parallel pipeline frequency divider, and the output end of the N parallel pipeline frequency divider is connected to the input end of the N parallel pipeline counter, wherein:

[0013] The N parallel pipeline type zero-crossing detector is used to perform zero-crossing detection on the N parallel digital reference signals to obtain N parallel square wave reference signals;

[0014] The delay compensation module and the N parallel rising edge detection module are used to convert the N parallel square wave reference signals to obtain N parallel pulse reference signals;

[0015] The N parallel pipeline type frequency divider is used to divide the N parallel pulse reference signal according to the frequency division coefficient to obtain the divided N parallel pulse reference signal;

[0016] The N parallel pipeline counter is used to count the divided N parallel pulse reference signals to obtain the reference signal frequency measurement information.

[0017] In some embodiments, the N-parallel pipeline zero-crossing detector includes a first-stage delay compensation module, a hysteresis comparator, a second-stage delay compensation module and a hysteresis decision device, and the first-stage delay compensation module, the hysteresis comparator, the second-stage delay compensation module and the hysteresis decision device are connected in sequence, wherein:

[0018] The first-stage delay compensation module is used to perform a first compensation process on the N parallel digital reference signals to obtain N parallel digital reference signals after preliminary compensation;

[0019] The hysteresis comparator is used to compare the N parallel digital reference signals after preliminary compensation to obtain the compared N parallel digital reference signals;

[0020] The second-stage delay compensation module is used to perform a second compensation process on the compared N parallel digital reference signals to obtain compensated N parallel digital reference signals;

[0021] The hysteresis decision device is used to make a decision on the compensated N parallel digital reference signals to obtain the N parallel square wave reference signals.

[0022] In some embodiments, the N parallel phase-locked loop module includes an N parallel reference coherent demodulation module, a frequency locker and a phase locker, the N parallel reference coherent demodulation module, the frequency locker and the phase locker are connected in sequence, the output end of the frequency locker and the output end of the phase locker are both connected to the input end of the N parallel reference coherent demodulation module, wherein:

[0023] The frequency locker is used to obtain the frequency information of the reference signal frequency measurement information;

[0024] The phase locker is used to obtain the phase information of the reference signal frequency measurement information;

[0025] The N parallel reference coherent demodulation module is used to coherently demodulate the frequency information of the reference signal frequency measurement information and the phase information of the reference signal frequency measurement information to obtain the phase information of the reference signal;

[0026] The frequency locker and the phase locker are further used to adjust according to the phase information of the reference signal and the frequency measurement information of the reference signal to obtain the frequency information of the reference signal.

[0027] In some embodiments, the N parallel reference coherent demodulation module includes a first N parallel digital frequency synthesizer, a first N parallel pipeline multiplier, a first N parallel pipeline low-pass filter and an N parallel inverse tangent angle operation module, and the first N parallel digital frequency synthesizer, the first N parallel pipeline multiplier, the first N parallel pipeline low-pass filter and the N parallel inverse tangent angle operation module are connected in sequence, wherein:

[0028] The first N parallel digital frequency synthesizer is used to synthesize the frequency information and the phase information to obtain N parallel orthogonal triangular signals;

[0029] The first N-parallel pipeline multiplier is used to perform multiplication operation on the N-parallel orthogonal triangular signals and the N-parallel digital reference signals to obtain N-parallel reference signal product operation results;

[0030] The first N parallel pipeline low-pass filters are used to filter out double frequency terms from the product operation results of the N parallel reference signals to obtain XY component information of the reference signal;

[0031] The N parallel inverse tangent angle operation module is used to perform an inverse tangent angle operation on the XY component information of the reference signal to obtain the phase information of the reference signal.

[0032] In some embodiments, the N parallel input coherent demodulation module includes a second N parallel digital frequency synthesizer, a second N parallel pipeline multiplier, a second N parallel pipeline low-pass filter and an N parallel inverse tangent modulus operation module, and the second N parallel digital frequency synthesizer, the second N parallel pipeline multiplier, the second N parallel pipeline low-pass filter and the N parallel inverse tangent modulus operation module are connected in sequence, wherein:

[0033] The second N parallel digital frequency synthesizer is used to perform synthesis processing according to the phase information of the reference signal and the frequency information of the reference signal to obtain N parallel orthogonal triangular signals with the same frequency and phase;

[0034] The second N-parallel pipeline multiplier is used to perform a multiplication operation on the N-parallel same-frequency and same-phase orthogonal triangular signals and the N-parallel digital input signals to obtain a product operation result of the N-parallel digital input signals;

[0035] The second N parallel pipeline low-pass filter is used to filter out the double frequency term of the product operation result of the N parallel digital input signals to obtain XY component information of the digital input signal;

[0036] The N parallel inverse tangent modulo operation module is used to perform an inverse tangent modulo operation on the XY component information of the digital input signal to obtain the amplitude information of the digital input signal, the phase information of the digital input signal and the XY component information of the digital input signal.

[0037] To achieve the above object, another aspect of the embodiment of the present application provides a control method of a high-frequency digital lock-in amplifier based on a parallel digital algorithm, the control method comprising the following steps:

[0038] Acquire an analog input signal and a reference signal and perform sampling processing to obtain a sampled digital input signal and a sampled digital reference signal;

[0039] Performing serial-to-parallel processing on the sampled digital input signal and the sampled digital reference signal to obtain N parallel digital input signals and N parallel digital reference signals;

[0040] Performing frequency measurement on the N parallel digital reference signals to obtain reference signal frequency measurement information;

[0041] Performing phase-locked adjustment on the N parallel digital reference signals according to the reference signal frequency measurement information to obtain frequency information and phase information of the reference signal;

[0042] The N parallel digital input signals are demodulated according to the frequency information of the reference signal and the phase information of the reference signal to obtain the amplitude information of the digital input signal, the phase information of the digital input signal and the XY component information of the digital input signal.

[0043] In some embodiments, the performing frequency measurement on the N parallel digital reference signals to obtain reference signal frequency measurement information includes:

[0044] Performing zero-crossing detection on the N parallel digital reference signals to obtain N parallel square wave reference signals;

[0045] Converting the N parallel square wave reference signals to obtain N parallel pulse reference signals;

[0046] Divide the N parallel pulse reference signals according to the frequency division coefficient to obtain N parallel pulse reference signals after frequency division;

[0047] The divided N parallel pulse reference signals are counted to obtain the reference signal frequency measurement information.

[0048] In some embodiments, performing phase-locked adjustment on the N parallel digital reference signals according to the reference signal frequency measurement information to obtain the frequency information of the reference signal and the phase information of the reference signal includes:

[0049] Acquire frequency information of the reference signal frequency measurement information and phase information of the reference signal frequency measurement information;

[0050] Performing coherent demodulation on the frequency information of the reference signal frequency measurement information and the phase information of the reference signal frequency measurement information to obtain the phase information of the reference signal;

[0051] Adjustment is performed according to the phase information of the reference signal and the frequency measurement information of the reference signal to obtain the frequency information of the reference signal.

[0052] In some embodiments, the demodulating the N parallel digital input signals according to the frequency information of the reference signal and the phase information of the reference signal to obtain the amplitude information of the digital input signal, the phase information of the digital input signal and the XY component information of the digital input signal includes:

[0053] Performing synthesis processing according to the phase information of the reference signal and the frequency information of the reference signal to obtain N parallel orthogonal triangular signals with the same frequency and phase;

[0054] Multiplying the N parallel in-phase and in-frequency orthogonal triangular signals with the N parallel digital input signals to obtain a product operation result of the N parallel digital input signals;

[0055] Filtering out the double frequency term of the product operation result of the N parallel digital input signals to obtain XY component information of the digital input signal;

[0056] An arc tangent modulo operation is performed on the XY component information of the digital input signal to obtain the amplitude information of the digital input signal, the phase information of the digital input signal, and the XY component information of the digital input signal.

[0057] The embodiments of the present application include at least the following beneficial effects: The present application provides a high-frequency digital phase-locked amplifier and control method based on a parallel digital algorithm. The scheme samples the input signal and the reference signal through an analog-to-digital converter module and a serial-to-parallel module, and performs serial-to-parallel processing to realize the conversion of serial analog signals to N parallel digital signals, thereby reducing the rate of the data stream. Further, the N parallel frequency measurement modules measure the frequency of the N parallel digital reference signals, and the N parallel phase-locked loop modules perform phase-locked adjustment on the N parallel digital reference signals according to the reference signal frequency measurement information. Finally, the N parallel input coherent demodulation modules demodulate the N parallel digital input signals, so that the equivalent operating frequency of the digital module can be N times the maximum operating rate of the FPGA. For modules with data dependencies and modules that require multi-cycle operations, a pipeline structure is adopted, so that the throughput is also improved, thereby improving the bandwidth of the phase-locked amplifier system. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 It is a schematic diagram of the module structure of a high-frequency digital lock-in amplifier based on a parallel digital algorithm provided in an embodiment of the present application;

[0059] Figure 2 It is a schematic flow chart of the steps of a control method of a high-frequency digital lock-in amplifier based on a parallel digital algorithm provided in an embodiment of the present application;

[0060] Figure 3 It is a schematic diagram of the framework principle of the high-frequency digital lock-in amplifier provided in the embodiment of the present application;

[0061] Figure 4 Schematic diagram of the structure principle of the N parallel frequency measurement module provided in the embodiment of the present application;

[0062] Figure 5 Schematic diagram of the structure principle of an N-parallel phase-locked loop module provided in an embodiment of the present application;

[0063] Figure 6 It is a schematic diagram of the structural principle of an N parallel input coherent demodulation module provided in an embodiment of the present application.

[0064] Figure numerals: 101, first analog-to-digital converter; 102, first serial-to-parallel module; 103, N parallel input coherent demodulation module; 104, second analog-to-digital converter; 105, second serial-to-parallel module; 106, N parallel phase-locked loop module; 107, N parallel reference coherent demodulation module; 108, frequency locker; 109, phase locker; 110, N parallel frequency measurement module; 111, N parallel pipeline zero-crossing detector module; 112, N parallel pipeline counter; 113, N parallel rising edge detection module; 114, N parallel pipeline divider; 201, first pipeline zero-crossing detection module; 202, second pipeline zero-crossing detection module; 20N, Nth pipeline Zero crossing detection module; 211, first parallel rising edge detection module; 212, second parallel rising edge detection module; 21N, Nth parallel rising edge detection module; 210, first delay compensation module; 220, N parallel pipeline type frequency divider; 221, N parallel pipeline type counter; 301, first reference digital frequency synthesizer; 302, second reference digital frequency synthesizer; 30N, Nth reference digital frequency synthesizer, 311, first reference pipeline type multiplier; 312, first second reference pipeline type multiplier; 31N, 1Nth reference pipeline type multiplier; 321, second reference pipeline type multiplier; 322, second second reference pipeline type multiplier; 3 2N, 2Nth reference pipeline multiplier; 331, the first parallel low-pass filter; 332, the first second parallel low-pass filter; 33N, the 1Nth parallel low-pass filter; 341, the second parallel low-pass filter; 342, the second second parallel low-pass filter; 34N, the 2Nth parallel low-pass filter; 330, the second delay compensation module; 340, the third delay compensation module; 350, the Nth parallel inverse tangent angle operation module; 351, the frequency locker; 352, the phase locker; 401, the first input digital frequency synthesizer; 402, the second input digital frequency synthesizer; 40N, the Nth input digital frequency synthesizer; 411, the first input pipeline type multiplier; 412, the first second input pipeline multiplier; 41N, the 1Nth input pipeline multiplier; 421, the second input pipeline multiplier; 422, the second second input pipeline multiplier; 42N, the 2Nth input pipeline multiplier; 431, the first pipeline low-pass filter; 432, the first second pipeline low-pass filter; 43N, the 1Nth pipeline low-pass filter; 441, the second pipeline low-pass filter; 442, the second second pipeline low-pass filter; 44N, the 2Nth pipeline low-pass filter; 430, the fourth delay compensation module; 440, the fifth delay compensation module; 450, N parallel inverse tangent modulus operation modules. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of systems and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0066] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0067] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0068] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0069] Reference Figure 1 , Figure 1 A flowchart of a high-frequency digital lock-in amplifier based on a parallel digital algorithm provided by an embodiment of the present invention, referring to Figure 1The high-frequency digital phase-locked amplifier includes an analog-to-digital converter module, a serial-to-parallel module, an N-parallel frequency measurement module, an N-parallel phase-locked loop module and an N-parallel input coherent demodulation module. The output end of the analog-to-digital converter module is connected to the input end of the serial-to-parallel module, the first output end of the serial-to-parallel module is connected to the input end of the N-parallel frequency measurement module, the second output end of the serial-to-parallel module is connected to the first input end of the N-parallel phase-locked loop module, the output end of the N-parallel frequency measurement module is connected to the second input end of the N-parallel phase-locked loop module, the third output end of the serial-to-parallel module is connected to the first input end of the N-parallel input coherent demodulation module, and the output end of the N-parallel phase-locked loop module is connected to the second input end of the N-parallel input coherent demodulation module, wherein:

[0070] The analog-to-digital converter module is used to obtain the analog input signal and the reference signal and perform sampling processing to obtain the sampled digital input signal and the sampled digital reference signal;

[0071] The serial-to-parallel module is used to perform serial-to-parallel processing on the sampled digital input signal and the sampled digital reference signal to obtain N parallel digital input signals and N parallel digital reference signals;

[0072] In this embodiment, the analog-to-digital converter samples the input signal and the reference signal respectively. The sampled digital signal is converted into N parallel signals through a serial-to-parallel module. The data flow rate of the digital signal is 1 / N of the sampling rate. Therefore, a lower data flow rate can be obtained at a higher sampling rate to adapt to the slower operating rate of the FPGA.

[0073] The N parallel frequency measurement module is used to measure the frequency of the N parallel digital reference signals to obtain the reference signal frequency measurement information;

[0074] Further, it should be noted that the N parallel frequency measurement module includes N parallel pipeline zero-crossing detectors, a delay compensation module, an N parallel rising edge detection module, an N parallel pipeline frequency divider and an N parallel pipeline counter, the first output end of the N parallel pipeline zero-crossing detector is connected to the input end of the delay compensation module, the second output end of the N parallel pipeline zero-crossing detector is connected to the first input end of the N parallel rising edge detection module, the output end of the delay compensation module is connected to the second input end of the N parallel rising edge detection module, the output end of the N parallel rising edge detection module is connected to the input end of the N parallel pipeline frequency divider, and the N parallel pipeline The output end of the N-parallel pipeline type frequency divider is connected to the input end of the N-parallel pipeline type counter, wherein the N-parallel pipeline type zero-crossing detector is used to perform zero-crossing detection on the N-parallel digital reference signal to obtain the N-parallel square wave reference signal; the delay compensation module and the N-parallel rising edge detection module are used to convert and process the N-parallel square wave reference signal to obtain the N-parallel pulse reference signal; the N-parallel pipeline type frequency divider is used to divide the N-parallel pulse reference signal according to the frequency division coefficient to obtain the N-parallel pulse reference signal after the frequency division; the N-parallel pipeline type counter is used to count the N-parallel pulse reference signal after the frequency division to obtain the reference signal frequency measurement information.

[0075] Furthermore, the N-parallel pipeline zero-crossing detector includes a first-stage delay compensation module, a hysteresis comparator, a second-stage delay compensation module and a hysteresis decision device, and the first-stage delay compensation module, the hysteresis comparator, the second-stage delay compensation module and the hysteresis decision device are connected in sequence, wherein the first-stage delay compensation module is used to perform a first compensation processing on the N parallel digital reference signals to obtain N parallel digital reference signals after preliminary compensation; the hysteresis comparator is used to compare the N parallel digital reference signals after preliminary compensation to obtain N parallel digital reference signals after comparison; the second-stage delay compensation module is used to perform a second compensation processing on the N parallel digital reference signals after comparison to obtain N parallel digital reference signals after compensation; the hysteresis decision device is used to make a decision on the compensated N parallel digital reference signals to obtain N parallel square wave reference signals.

[0076] In this embodiment, the N parallel frequency measurement part includes N parallel pipeline zero-crossing detectors, delay compensation modules, N parallel rising edge detection, N parallel pipeline frequency dividers and N parallel pipeline counters. The N parallel reference signals are converted into N parallel square waves by the zero-crossing detection module, and the N parallel square waves output by the zero-crossing detection module are converted into N parallel pulse signals by the rising edge detection and delay compensation modules, and the frequency measurement information of the reference signal is obtained by dividing and counting the N parallel pulse signals. The N parallel pipeline frequency divider includes a hysteresis comparator inside, and the frequency division coefficient adopts hysteresis control to prevent the frequency division coefficient from jumping and ensure the accuracy and time of measurement.

[0077] The N parallel phase-locked loop module is used to perform phase-locked adjustment on the N parallel digital reference signals according to the reference signal frequency measurement information to obtain the frequency information and phase information of the reference signal;

[0078] Furthermore, it should be noted that the N parallel phase-locked loop module includes N parallel reference coherent demodulation modules, a frequency locker and a phase locker, and the N parallel reference coherent demodulation modules, the frequency locker and the phase locker are connected in sequence, and the output end of the frequency locker and the output end of the phase locker are both connected to the input end of the N parallel reference coherent demodulation module, wherein the frequency locker is used to obtain the frequency information of the reference signal frequency measurement information; the phase locker is used to obtain the phase information of the reference signal frequency measurement information; the N parallel reference coherent demodulation module is used to coherently demodulate the frequency information of the reference signal frequency measurement information and the phase information of the reference signal frequency measurement information to obtain the phase information of the reference signal; the frequency locker and the phase locker are also used to adjust according to the phase information of the reference signal and the reference signal frequency measurement information to obtain the frequency information of the reference signal.

[0079] Furthermore, the N parallel reference coherent demodulation module includes a first N parallel digital frequency synthesizer, a first N parallel pipeline multiplier, a first N parallel pipeline low-pass filter and an N parallel inverse tangent angle operation module, and the first N parallel digital frequency synthesizer, the first N parallel pipeline multiplier, the first N parallel pipeline low-pass filter and the N parallel inverse tangent angle operation module are connected in sequence, wherein the first N parallel digital frequency synthesizer is used to synthesize frequency information and phase information to obtain N parallel orthogonal triangular signals; the first N parallel pipeline multiplier is used to multiply the N parallel orthogonal triangular signals with the N parallel digital reference signals to obtain the product operation results of the N parallel reference signals; the first N parallel pipeline low-pass filter is used to filter out the double frequency terms of the product operation results of the N parallel reference signals to obtain the XY component information of the reference signal; the N parallel inverse tangent angle operation module is used to perform inverse tangent angle operation on the XY component information of the reference signal to obtain the phase information of the reference signal.

[0080] In this embodiment, the N parallel phase-locked loop module includes N parallel reference coherent demodulation modules, frequency lockers and phase lockers, and the N parallel reference coherent demodulation module includes N parallel digital frequency synthesizers, N parallel pipeline multipliers, N parallel pipeline low-pass filters and N parallel inverse tangent angle operations. The module mainly adopts a method of combining coherent demodulation with a phase-frequency controller, obtains the phase difference between the reference signal and the digital frequency direct synthesizer through coherent demodulation, and adjusts the phase difference to 0 through the frequency locker and the phase locker. Specifically, N parallel digital frequency synthesizers generate N parallel orthogonal triangular signals according to the phase information and frequency information provided by the frequency locker and the phase locker, and provide them to N parallel pipeline multipliers to perform multiplication with N parallel reference signals, and then filter out the double frequency terms through N parallel pipeline low-pass filters to obtain x, y components, and obtain the phase information of the reference signal through N parallel inverse tangent angle operations. The frequency locker and the phase locker are adjusted according to the phase information and the frequency measurement information of the N parallel frequency measurement modules, so that the sinusoidal signal generated by the N parallel digital frequency synthesizer is of the same frequency and phase as the reference signal, and the phase information and frequency information are provided to the N parallel input coherent demodulation modules.

[0081] The N parallel input coherent demodulation module is used to demodulate the N parallel digital input signals according to the frequency information and phase information of the reference signal to obtain the amplitude information, phase information and XY component information of the digital input signal.

[0082] Further, it should be noted that the N parallel input coherent demodulation module includes a second N parallel digital frequency synthesizer, a second N parallel pipeline multiplier, a second N parallel pipeline low-pass filter and an N parallel inverse tangent modulo operation module, and the second N parallel digital frequency synthesizer, the second N parallel pipeline multiplier, the second N parallel pipeline low-pass filter and the N parallel inverse tangent modulo operation module are connected in sequence, wherein the second N parallel digital frequency synthesizer is used to perform synthesis processing according to the phase information of the reference signal and the frequency information of the reference signal to obtain N parallel same-frequency and same-phase orthogonal triangular signals; The second N parallel pipeline multiplier is used to multiply the N parallel same-frequency and same-phase orthogonal triangular signals with the N parallel digital input signals to obtain the product operation results of the N parallel digital input signals; the second N parallel pipeline low-pass filter is used to filter out the double frequency terms of the product operation results of the N parallel digital input signals to obtain the XY component information of the digital input signal; the N parallel inverse tangent modulo operation module is used to perform an inverse tangent modulo operation on the XY component information of the digital input signal to obtain the amplitude information of the digital input signal, the phase information of the digital input signal and the XY component information of the digital input signal.

[0083] In this embodiment, the N parallel input coherent demodulation part also includes N parallel digital frequency synthesizers, N parallel pipeline multipliers, N parallel pipeline low-pass filters and N parallel inverse tangent modulo operations. The N parallel digital frequency synthesizers generate N parallel in-phase and in-frequency orthogonal triangular signals according to the phase information and frequency information provided by the N parallel phase-locked loop modules, and provide them to the N parallel pipeline multipliers to perform multiplication operation with the N parallel input signals, and then filter out the double frequency terms through the N parallel pipeline low-pass filters to obtain the x and y components, and finally obtain the amplitude R and phase Φ through the N parallel inverse tangent modulo operations.

[0084] In summary, the phase-locked amplification system of the embodiment of the present invention includes an analog-to-digital converter module, a serial-to-parallel module, an N-parallel frequency measurement module, an N-parallel phase-locked loop module and an N-parallel input coherent demodulation module. The analog-to-digital converter directly samples the analog input signal and the reference signal. The sampled serial high-speed digital signal is converted into parallel data through the serial-to-parallel part. The N-parallel frequency measurement module obtains reference signal frequency information according to the N-parallel reference signal, and provides the frequency information to the N-parallel phase-locked loop part. The N-parallel phase-locked loop obtains stable tracking frequency information and phase information according to the reference signal and the frequency information. The N-parallel input coherent demodulation part demodulates the parallel digital input signal according to the frequency information and the phase information to obtain the amplitude and phase of the input signal.

[0085] See also Figure 2 The embodiment of the present application also provides a control method of a high-frequency digital lock-in amplifier based on a parallel digital algorithm, which can realize the above-mentioned high-frequency digital lock-in amplifier based on a parallel digital algorithm. The control method includes the following steps:

[0086] S100, acquiring an analog input signal and a reference signal and performing sampling processing to obtain a sampled digital input signal and a sampled digital reference signal;

[0087] S200, performing serial-to-parallel processing on the sampled digital input signal and the sampled digital reference signal to obtain N parallel digital input signals and N parallel digital reference signals;

[0088] S300, performing frequency measurement on N parallel digital reference signals to obtain reference signal frequency measurement information;

[0089] It should be noted that, in some embodiments, step S300 may include: S310, performing zero-crossing detection on N parallel digital reference signals to obtain N parallel square wave reference signals; S320, performing conversion processing on the N parallel square wave reference signals to obtain N parallel pulse reference signals; S330, dividing the N parallel pulse reference signals according to the frequency division coefficient to obtain N parallel pulse reference signals after division; S340, counting the N parallel pulse reference signals after division to obtain reference signal frequency measurement information.

[0090] S400, performing phase-locking adjustment on N parallel digital reference signals according to the reference signal frequency measurement information to obtain frequency information and phase information of the reference signal;

[0091] It should be noted that, in some embodiments, step S400 may include: S410, obtaining frequency information of reference signal frequency measurement information and phase information of reference signal frequency measurement information; S420, coherently demodulating the frequency information of reference signal frequency measurement information and the phase information of reference signal frequency measurement information to obtain the phase information of the reference signal; S430, adjusting according to the phase information of the reference signal and the reference signal frequency measurement information to obtain the frequency information of the reference signal.

[0092] S500, demodulating the N parallel digital input signals according to the frequency information of the reference signal and the phase information of the reference signal to obtain the amplitude information of the digital input signal, the phase information of the digital input signal and the XY component information of the digital input signal;

[0093] It should be noted that, in some embodiments, step S500 may include: S510, performing synthesis processing based on the phase information of the reference signal and the frequency information of the reference signal to obtain N parallel in-phase and in-frequency orthogonal triangular signals; S520, multiplying the N parallel in-phase and in-frequency orthogonal triangular signals with the N parallel digital input signals to obtain the product operation result of the N parallel digital input signals; S530, filtering out the double frequency term of the product operation result of the N parallel digital input signals to obtain the XY component information of the digital input signal; S540, performing an inverse tangent modulo operation on the XY component information of the digital input signal to obtain the amplitude information of the digital input signal, the phase information of the digital input signal, and the XY component information of the digital input signal.

[0094] Further, the following is described in conjunction with the accompanying drawings of the embodiments of the present invention:

[0095] like Figure 3As shown, the phase-locked amplifier system of the embodiment of the present invention comprises a first analog-to-digital converter 101 and a second analog-to-digital converter 104, a first serial-to-parallel module 101 and a second serial-to-parallel module 104, an N-parallel frequency measurement module 110, an N-parallel input coherent demodulation module 103 and an N-parallel phase-locked loop module 106. The input signal and the reference signal are converted into serial digital signals by the first digital-to-analog converter 101 and the second digital-to-analog converter 102, respectively, and then converted into parallel digital signals by the first serial-to-parallel module 102 and the second serial-to-parallel module 105. The parallel input signal is provided to the parallel input coherent demodulation module 103, and the parallel reference signal is provided to the N-parallel frequency measurement module 110 and the N-parallel phase-locked loop module 106. The N parallel frequency measurement module 110 obtains frequency measurement information according to the reference signal, and provides it to the N parallel phase-locked loop module 106. The N parallel phase-locked loop module 106 obtains phase information and frequency information according to the reference signal and the frequency measurement information, and provides it to the parallel input coherent demodulation module 103. Then, the N parallel input coherent demodulation module 103 demodulates the input signal according to the phase information and the frequency information to obtain the amplitude R, phase φ and XY components of the input signal.

[0096] The specific block diagram of the N parallel frequency measurement module 110 of the embodiment of the present invention is as follows: Figure 4As shown. The parallel reference signal is respectively transmitted to the parallel first pipeline zero-crossing detection module 201, the second pipeline zero-crossing detection module 202 and the Nth pipeline zero-crossing detection module 20N. Each zero-crossing detection module is composed of a first-level delay compensation, a hysteresis comparator, a second-level delay compensation, and a hysteresis decision device connected in sequence. The output of each hysteresis comparator will be affected by the hysteresis comparator of the previous level, so the hysteresis comparator output of the first pipeline zero-crossing detection module 201 needs to be connected to the hysteresis comparator input of the second pipeline zero-crossing detection module 202, and so on to the hysteresis comparator of the 2nd (N-1)th pipeline zero-crossing detection module connected to the hysteresis comparator of the Nth pipeline zero-crossing detection module 20N. Due to the data dependency between the multi-level hysteresis comparators, the two-level delay compensation module is used to align the pipelines of different zero-crossing detection modules. For first pipeline type zero crossing detection module 201, the delay time of its first level delay compensation is 0 cycle, and the time of second level delay compensation is N cycle.For second pipeline type zero crossing detection module 202, the delay time of its first level delay compensation is 1 cycle, and the time of second level delay compensation is N-1 cycle.By analogy, for Nth pipeline type zero crossing detection module 20N, the delay time of its first level delay compensation is N cycle, and the time of second level delay compensation is 0 cycle.The hysteresis decision device output of Nth pipeline type zero crossing detection module 20N needs to be connected to the input of the hysteresis decision device of first pipeline type zero crossing detection module 201, second pipeline type zero crossing detection module 202 and Nth pipeline type zero crossing detection module 20N. After the hysteresis judgment, the parallel reference signal will be converted into a parallel square wave. Since the rising edge detection requires multiple data for detection, the output of the first pipeline zero-crossing detection module 201 needs to be connected to the first parallel rising edge detection module 211 and the second parallel rising edge detection module 212, and the output of the second pipeline zero-crossing detection module 202 needs to be connected to the second parallel rising edge detection module 212 and the third parallel rising edge detection module. By analogy, the output of the 2nd (N-1)th pipeline zero-crossing detection module needs to be connected to the 21st (N-1)th parallel rising edge detection module and the Nth parallel rising edge detection module 21N. For the Nth pipeline zero-crossing detection module 20N, its output needs to be connected to the Nth parallel rising edge detection module 21N and the first delay compensation module 210, and after one cycle of delay compensation, it is connected to the first parallel rising edge detection module 211. The N parallel rising edge detection modules each make a judgment based on their two inputs and output a parallel pulse signal. The converted pulse signals are provided to the N-parallel pipeline frequency divider 220 and the N-parallel pipeline counter 221 respectively.The N-parallel pipelined divider 220 has a hysteresis comparison structure inside. According to the input pulse result, the appropriate frequency division coefficient is selected. If the pulse signal frequency is detected to be low, the frequency division coefficient is reduced to reduce the frequency division measurement time; if the pulse signal frequency is detected to be high, the frequency division coefficient is increased to improve the frequency division measurement accuracy. The N-parallel pipelined divider 220 divides the frequency according to the pulse input of the frequency division coefficient, and the N-parallel pipelined counter 221 counts the pulses after the frequency division to obtain the counting result, which is transmitted to the N-parallel phase-locked loop module 106 as the frequency measurement information. Since both the counter and the divider need multiple cycles to operate, they are both pipelined.

[0097] The structure of the N parallel phase-locked loop module 106 is as follows Figure 5As shown. It is divided into 2N pipeline multipliers, specifically including the first reference pipeline multiplier 311, the first second reference pipeline multiplier 312, the 1Nth reference pipeline multiplier 31N, the second reference pipeline multiplier 321, the second second reference pipeline multiplier 322, and the 2Nth reference pipeline multiplier 32N, and N digital frequency synthesizers, specifically including the first reference digital frequency synthesizer 301, the second reference digital frequency synthesizer 302, and the Nth reference digital frequency synthesizer 303. Device 30N, 2N pipeline low-pass filters, specifically including the first parallel low-pass filter 331, the first parallel low-pass filter 332, the 1Nth parallel low-pass filter 33N, the second parallel low-pass filter 341, the 2nd parallel low-pass filter 342, the 2Nth parallel low-pass filter 34N, N parallel inverse tangent angle operation modules 350, the second delay compensation module 330 and the third delay compensation module 340, a frequency locker 351 and a phase locker 352. The first reference digital frequency synthesizer 301, the second reference digital frequency synthesizer 302, and the Nth reference digital frequency synthesizer 30N generate triangular signals of the same frequency, same phase, parallel and mutually orthogonal according to the phase information and frequency information of the frequency locker 351 and the phase locker 352, respectively. One group of sine-triangle signals is provided to the first reference pipeline multiplier 311, the first second reference pipeline multiplier 312, and the 1Nth reference pipeline multiplier 31N, and another group of cosine-triangle signals is provided to the second reference pipeline multiplier 321, the second second reference pipeline multiplier 322, and the 2Nth reference pipeline multiplier 32N. Since the multiplier requires multiple operation cycles, a pipeline design is adopted. Since the pipeline low-pass filter requires multiple data before and after, the first reference pipeline multiplier 311 multiplies the reference signal 1 and the sinusoidal signal of the first reference digital frequency synthesizer 301, and outputs the result to the first parallel low-pass filter 331 and the second delay compensation module 330, and the second delay compensation module 330 outputs the result to the 1Nth parallel low-pass filter 33N. Similarly, the first second reference pipeline multiplier 312 multiplies the reference signal 2 and the sinusoidal signal of the second reference digital frequency synthesizer 302, and outputs the result to the first second parallel low-pass filter 332 and the first parallel low-pass filter 331.By analogy, the 1Nth reference pipeline multiplier 31N multiplies the reference signal N with the sine signal of the Nth reference digital frequency synthesizer 30N, and outputs the result to the 1Nth parallel low-pass filter 33N and the 1N-1th parallel low-pass filter. The second reference pipeline multiplier 321 multiplies the reference signal 1 with the cosine signal of the first reference digital frequency synthesizer 301, and outputs the result to the second parallel low-pass filter 341 and the third delay compensation module 340. The third delay compensation module 340 then outputs the result to the 2Nth parallel low-pass filter 34N. The second second reference pipeline multiplier 322 multiplies the reference signal 2 with the cosine signal of the second reference digital frequency synthesizer 302, and outputs the result to the second second parallel low-pass filter 342 and the second first parallel low-pass filter 341. By analogy, the 2Nth reference pipeline multiplier 32N multiplies the reference signal N and the cosine signal of the Nth reference digital frequency synthesizer 30N, and outputs the result to the 2Nth parallel low-pass filter 34N and the 2N-1th parallel low-pass filter. Since the low-pass filter requires multiple cycles of operation, it also requires pipeline processing. The first parallel low-pass filter 331, the first second parallel low-pass filter 332, and the 1Nth parallel low-pass filter 33N are combined with two inputs to perform low-pass filtering to obtain parallel X components. Similarly, the second parallel low-pass filter 341, the second second parallel low-pass filter 342, and the 2Nth parallel low-pass filter 34N are combined with two inputs to perform low-pass filtering to obtain parallel Y components. The X component and the Y component are respectively connected to the N parallel inverse tangent angle operation modules 350. The N parallel inverse tangent angle operation module 350 performs inverse tangent operation to obtain phase information, which is the phase difference between the reference signal and the triangular signal output by the parallel digital frequency synthesizer. The phase difference and frequency measurement information are input to the frequency locker 351 and the phase locker 352. The frequency locker 351 and the phase locker 352 adjust the frequency and phase of the first reference digital frequency synthesizer 301, the second reference digital frequency synthesizer 302, and the Nth reference digital frequency synthesizer 30N, so that the phase difference is finally 0, that is, the triangular signal output by the digital frequency synthesizer is in the same frequency and phase as the reference signal, and the phase information and frequency information at this time are transmitted to the N parallel input coherent demodulation module 103.

[0098] The N parallel input coherent demodulation module 103 is similar to the N parallel phase-locked loop module 106. The specific block diagram is as follows: Figure 6As shown, it is divided into 2N pipeline multipliers, specifically including the first input pipeline multiplier 411, the first second input pipeline multiplier 412, the 1Nth input pipeline multiplier 41N, the second input pipeline multiplier 421, the 2nd second input pipeline multiplier 422, and the 2Nth input pipeline multiplier 42N, and N digital frequency synthesizers, specifically including the first input digital frequency synthesizer 401, the second input digital frequency synthesizer 402, the Nth Input digital frequency synthesizer 40N, 2N pipelined low-pass filters, specifically including the 1st pipelined low-pass filter 431, the 1st second pipelined low-pass filter 432, the 1Nth pipelined low-pass filter 43N, the 2nd pipelined low-pass filter 441, the 2nd second pipelined low-pass filter 442, the 2Nth pipelined low-pass filter 44N, N parallel inverse tangent modulo operation modules 450, the fourth delay compensation module 430 and the fifth delay compensation module 440. The first input digital frequency synthesizer 401, the second input digital frequency synthesizer 402, and the Nth input digital frequency synthesizer 40N respectively generate triangular signals of the same frequency, same phase, parallel and mutually orthogonal according to the phase information and frequency information of the N parallel phase-locked loop module 106. One group of sine-triangle signals is provided to the first input pipeline multiplier 411, the first second input pipeline multiplier 412, and the 1Nth input pipeline multiplier 41N, and another group of cosine-triangle signals is provided to the second input pipeline multiplier 421, the second second input pipeline multiplier 422, and the 2Nth input pipeline multiplier 42N. Since the multiplier requires multiple operation cycles, a pipeline design is adopted. Since the pipeline low-pass filter requires multiple data before and after, the first input pipeline multiplier 411 multiplies the input signal 1 with the sine signal of the first input digital frequency synthesizer 401, and outputs the result to the first pipeline low-pass filter 431 and the fourth delay compensation module 430, and the fourth delay compensation module 430 outputs the result to the 1Nth pipeline low-pass filter 43N. Similarly, the first second input pipeline multiplier 412 multiplies the input signal 2 with the sine signal of the second input digital frequency synthesizer 402, and outputs the result to the first second pipeline low-pass filter 432 and the first pipeline low-pass filter 431.By analogy, the 1Nth input pipeline multiplier 41N multiplies the input signal N with the sine signal of the Nth input digital frequency synthesizer 40N, and outputs the result to the 1Nth pipeline low-pass filter 43N and the 1N-1th pipeline low-pass filter; the second input pipeline multiplier 421 multiplies the input signal 1 with the cosine signal of the first input digital frequency synthesizer 401, and outputs the result to the second pipeline low-pass filter 441 and the fifth delay compensation module 440, and the fifth delay compensation module 440 then outputs the result to the 2Nth pipeline low-pass filter 44N. The second second input pipeline multiplier 422 multiplies the input signal 2 with the cosine signal of the second input digital frequency synthesizer 402, and outputs the result to the second second pipeline low-pass filter 442 and the second first pipeline low-pass filter 441. By analogy, the 2Nth input pipeline multiplier 42N multiplies the input signal N and the cosine signal of the Nth input digital frequency synthesizer 40N, and outputs the result to the 2Nth pipeline low-pass filter 44N and the 2N-1th pipeline low-pass filter. Since the low-pass filter requires multiple cycles of operation, it also requires pipeline processing. The first pipeline low-pass filter 431, the first second pipeline low-pass filter 432, and the 1Nth pipeline low-pass filter 43N combine the two inputs to perform low-pass filtering to obtain parallel X components. Similarly, the second pipeline low-pass filter 441, the second second pipeline low-pass filter 442, and the 2Nth pipeline low-pass filter 44N combine the two inputs to perform low-pass filtering to obtain parallel Y components. The X component and the Y component are respectively connected to the N parallel inverse tangent modulo operation module 450, and the N parallel inverse tangent modulo operation module 450 performs an inverse tangent modulo operation to obtain amplitude information R, phase information Φ, X, and Y components.

[0099] It can be understood that the contents of the above method embodiments are all applicable to the present system embodiments, the functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0100] The preferred embodiments of the present application are described above with reference to the accompanying drawings, but the scope of the rights of the present application is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present application should be within the scope of the rights of the present application.

Claims

1. A high-frequency digital lock-in amplifier based on a parallel digital algorithm, characterized in that: The high-frequency digital phase-locked amplifier comprises an analog-to-digital converter module, a serial-to-parallel module, an N-parallel frequency measurement module, an N-parallel phase-locked loop module and an N-parallel input coherent demodulation module, the output end of the analog-to-digital converter module is connected to the input end of the serial-to-parallel module, the first output end of the serial-to-parallel module is connected to the input end of the N-parallel frequency measurement module, the second output end of the serial-to-parallel module is connected to the first input end of the N-parallel phase-locked loop module, the output end of the N-parallel frequency measurement module is connected to the second input end of the N-parallel phase-locked loop module, the third output end of the serial-to-parallel module is connected to the first input end of the N-parallel input coherent demodulation module, and the output end of the N-parallel phase-locked loop module is connected to the second input end of the N-parallel input coherent demodulation module, wherein: The analog-to-digital converter module is used to acquire an analog input signal and a reference signal and perform sampling processing to obtain a sampled digital input signal and a sampled digital reference signal; The serial-to-parallel module is used to perform serial-to-parallel processing on the sampled digital input signal and the sampled digital reference signal to obtain N parallel digital input signals and N parallel digital reference signals; The N parallel frequency measurement module is used to measure the frequency of the N parallel digital reference signals to obtain reference signal frequency measurement information; The N parallel phase-locked loop module is used to perform phase-locked adjustment on the N parallel digital reference signals according to the reference signal frequency measurement information to obtain the frequency information of the reference signal and the phase information of the reference signal; The N parallel input coherent demodulation module is used to demodulate the N parallel digital input signals according to the frequency information of the reference signal and the phase information of the reference signal to obtain the amplitude information of the digital input signal, the phase information of the digital input signal and the XY component information of the digital input signal.

2. The high frequency digital lock-in amplifier according to claim 1, characterized in that: The N parallel frequency measurement module includes an N parallel pipeline zero-crossing detector, a delay compensation module, an N parallel rising edge detection module, an N parallel pipeline frequency divider and an N parallel pipeline counter. The first output end of the N parallel pipeline zero-crossing detector is connected to the input end of the delay compensation module, the second output end of the N parallel pipeline zero-crossing detector is connected to the first input end of the N parallel rising edge detection module, the output end of the delay compensation module is connected to the second input end of the N parallel rising edge detection module, the output end of the N parallel rising edge detection module is connected to the input end of the N parallel pipeline frequency divider, and the output end of the N parallel pipeline frequency divider is connected to the input end of the N parallel pipeline counter, wherein: The N parallel pipeline type zero-crossing detector is used to perform zero-crossing detection on the N parallel digital reference signals to obtain N parallel square wave reference signals; The delay compensation module and the N parallel rising edge detection module are used to convert the N parallel square wave reference signals to obtain N parallel pulse reference signals; The N parallel pipeline type frequency divider is used to divide the N parallel pulse reference signal according to the frequency division coefficient to obtain the divided N parallel pulse reference signal; The N parallel pipeline counter is used to count the divided N parallel pulse reference signals to obtain the reference signal frequency measurement information.

3. The high frequency digital lock-in amplifier according to claim 2, characterized in that: The N-parallel pipeline zero-crossing detector comprises a first-stage delay compensation module, a hysteresis comparator, a second-stage delay compensation module and a hysteresis decision device, wherein the first-stage delay compensation module, the hysteresis comparator, the second-stage delay compensation module and the hysteresis decision device are connected in sequence, wherein: The first-stage delay compensation module is used to perform a first compensation process on the N parallel digital reference signals to obtain N parallel digital reference signals after preliminary compensation; The hysteresis comparator is used to compare the N parallel digital reference signals after preliminary compensation to obtain the compared N parallel digital reference signals; The second-stage delay compensation module is used to perform a second compensation process on the compared N parallel digital reference signals to obtain compensated N parallel digital reference signals; The hysteresis decision device is used to make a decision on the compensated N parallel digital reference signals to obtain the N parallel square wave reference signals.

4. The high frequency digital lock-in amplifier according to claim 1, characterized in that: The N parallel phase-locked loop module includes an N parallel reference coherent demodulation module, a frequency locker and a phase locker, the N parallel reference coherent demodulation module, the frequency locker and the phase locker are connected in sequence, the output end of the frequency locker and the output end of the phase locker are both connected to the input end of the N parallel reference coherent demodulation module, wherein: The frequency locker is used to obtain the frequency information of the reference signal frequency measurement information; The phase locker is used to obtain the phase information of the reference signal frequency measurement information; The N parallel reference coherent demodulation module is used to coherently demodulate the frequency information of the reference signal frequency measurement information and the phase information of the reference signal frequency measurement information to obtain the phase information of the reference signal; The frequency locker and the phase locker are further used to adjust according to the phase information of the reference signal and the frequency measurement information of the reference signal to obtain the frequency information of the reference signal.

5. The high frequency digital lock-in amplifier according to claim 4, characterized in that: The N parallel reference coherent demodulation module includes a first N parallel digital frequency synthesizer, a first N parallel pipeline multiplier, a first N parallel pipeline low-pass filter and an N parallel inverse tangent angle operation module, wherein the first N parallel digital frequency synthesizer, the first N parallel pipeline multiplier, the first N parallel pipeline low-pass filter and the N parallel inverse tangent angle operation module are connected in sequence, wherein: The first N parallel digital frequency synthesizer is used to synthesize the frequency information and the phase information to obtain N parallel orthogonal triangular signals; The first N-parallel pipeline multiplier is used to perform multiplication operation on the N-parallel orthogonal triangular signals and the N-parallel digital reference signals to obtain N-parallel reference signal product operation results; The first N parallel pipeline low-pass filters are used to filter out double frequency terms from the product operation results of the N parallel reference signals to obtain XY component information of the reference signal; The N parallel inverse tangent angle operation module is used to perform an inverse tangent angle operation on the XY component information of the reference signal to obtain the phase information of the reference signal.

6. The high frequency digital lock-in amplifier according to claim 1, characterized in that: The N parallel input coherent demodulation module includes a second N parallel digital frequency synthesizer, a second N parallel pipeline multiplier, a second N parallel pipeline low-pass filter and an N parallel inverse tangent modulo operation module, and the second N parallel digital frequency synthesizer, the second N parallel pipeline multiplier, the second N parallel pipeline low-pass filter and the N parallel inverse tangent modulo operation module are connected in sequence, wherein: The second N parallel digital frequency synthesizer is used to perform synthesis processing according to the phase information of the reference signal and the frequency information of the reference signal to obtain N parallel orthogonal triangular signals with the same frequency and phase; The second N-parallel pipeline multiplier is used to perform a multiplication operation on the N-parallel same-frequency and same-phase orthogonal triangular signals and the N-parallel digital input signals to obtain a product operation result of the N-parallel digital input signals; The second N parallel pipeline low-pass filter is used to filter out the double frequency term of the product operation result of the N parallel digital input signals to obtain XY component information of the digital input signal; The N parallel inverse tangent modulo operation module is used to perform an inverse tangent modulo operation on the XY component information of the digital input signal to obtain the amplitude information of the digital input signal, the phase information of the digital input signal and the XY component information of the digital input signal.

7. A control method for a high-frequency digital lock-in amplifier based on a parallel digital algorithm, characterized in that: The control method comprises the following steps: Acquire an analog input signal and a reference signal and perform sampling processing to obtain a sampled digital input signal and a sampled digital reference signal; Performing serial-to-parallel processing on the sampled digital input signal and the sampled digital reference signal to obtain N parallel digital input signals and N parallel digital reference signals; Performing frequency measurement on the N parallel digital reference signals to obtain reference signal frequency measurement information; Performing phase-locked adjustment on the N parallel digital reference signals according to the reference signal frequency measurement information to obtain frequency information and phase information of the reference signal; The N parallel digital input signals are demodulated according to the frequency information of the reference signal and the phase information of the reference signal to obtain the amplitude information of the digital input signal, the phase information of the digital input signal and the XY component information of the digital input signal.

8. The method according to claim 7, characterized in that The performing frequency measurement on the N parallel digital reference signals to obtain reference signal frequency measurement information includes: Performing zero-crossing detection on the N parallel digital reference signals to obtain N parallel square wave reference signals; Converting the N parallel square wave reference signals to obtain N parallel pulse reference signals; Divide the N parallel pulse reference signals according to the frequency division coefficient to obtain N parallel pulse reference signals after frequency division; The divided N parallel pulse reference signals are counted to obtain the reference signal frequency measurement information.

9. The method according to claim 7, characterized in that: The performing phase-locking adjustment on the N parallel digital reference signals according to the reference signal frequency measurement information to obtain the frequency information of the reference signal and the phase information of the reference signal includes: Acquire frequency information of the reference signal frequency measurement information and phase information of the reference signal frequency measurement information; Performing coherent demodulation on the frequency information of the reference signal frequency measurement information and the phase information of the reference signal frequency measurement information to obtain the phase information of the reference signal; Adjustment is performed according to the phase information of the reference signal and the frequency measurement information of the reference signal to obtain the frequency information of the reference signal.

10. The method according to claim 7, characterized in that The demodulating process is performed on the N parallel digital input signals according to the frequency information of the reference signal and the phase information of the reference signal to obtain the amplitude information of the digital input signal, the phase information of the digital input signal and the XY component information of the digital input signal, including: Performing synthesis processing according to the phase information of the reference signal and the frequency information of the reference signal to obtain N parallel orthogonal triangular signals with the same frequency and phase; Multiplying the N parallel in-phase and in-frequency orthogonal triangular signals with the N parallel digital input signals to obtain a product operation result of the N parallel digital input signals; Filtering out the double frequency term of the product operation result of the N parallel digital input signals to obtain XY component information of the digital input signal; An arc tangent modulo operation is performed on the XY component information of the digital input signal to obtain the amplitude information of the digital input signal, the phase information of the digital input signal, and the XY component information of the digital input signal.

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