Adaptive ultra-wideband space-time digital beam forming method and system based on multi-term filter

Abstract

The invention provides an adaptive ultra-wideband space-time digital beam forming method and system based on a multi-term filter. The system comprises an FPGA chip module and an AD / DA conversion module, the FPGA chip module is connected with the AD / DA conversion module and is used for forming a wave beam and sending wave beam data to the AD / DA conversion module, generating an intermediate frequency broadband signal and transmitting the intermediate frequency broadband signal to a subsequent circuit; the AD / DA conversion module is used for inputting the intermediate frequency signal subjected to AD sampling into the FPGA chip module and receiving beam data; a multi-term filter structure is adopted, the signal bandwidth is effectively reduced through the time delay function preposition and multi-phase filter combined technology, the time domain ultra-wideband beam forming function is efficiently achieved, and the time domain ultra-wideband beam forming device can be widely applied to radar wideband digital beam forming, microphone arrays, sonar arrays and other systems.

Description

Technical Field

[0001] The present application relates to the technical field of digital array signal processing, and in particular to an adaptive ultra-wideband space-time digital beamforming method and system based on multiple filters. Background Art

[0002] In recent years, as an emerging research direction, ultra-wideband beamforming technology has shown great potential in improving the quality of information transmission. It can be applied in a variety of scenarios, such as improving the quality of wireless communications, enhancing the effects of medical imaging technology, and improving radar detection accuracy. UWB-based technology has several significant advantages: first, it has an extremely wide operating frequency band, which enables the device to adapt to different working environments more flexibly; second, UWB signals have strong penetration capabilities and can maintain good communication effects even in the presence of many obstacles; finally, due to the use of high-frequency spectrum resources, it supports very high data transmission rates, meeting the needs of modern society for rapid information exchange.

[0003] For the typical adaptive ultra-wideband space-time digital beamforming architecture in the current small-scale array context, a tapped delay architecture is adopted. As the number of array elements and bandwidth increase, the space-time beamforming will increase the length of the delay line, making the implementation complex and the cost relatively high.

[0004] At present, the highest frequency at which high-performance digital signal processing chips such as FPGA and DSP can stably operate is no longer able to support the signal processing of high-speed data streams after A / D sampling. Summary of the invention

[0005] The present application provides an adaptive ultra-wideband space-time digital beamforming method and system based on multiple filters, which can be used to solve the technical problem that the highest frequency at which a high-performance digital signal processing chip can stably operate is no longer able to support the signal processing of high-speed data streams after A / D sampling.

[0006] The present application provides an adaptive ultra-wideband space-time digital beamforming system based on multiple filters, the system comprising:

[0007] FPGA chip module, AD / DA conversion module;

[0008] The FPGA chip module is connected to the AD / DA conversion module to form a beam and send the beam data to the AD / DA conversion module to generate an intermediate frequency broadband signal and transmit it to the subsequent circuit;

[0009] The AD / DA conversion module is used to input the intermediate frequency signal after AD adoption into the FPGA chip module and receive the beam data generated by the FPGA chip module;

[0010] Among them, the FPGA chip module includes a parameter configuration module, a digital down-conversion module, a delay module, a multi-phase filtering module, a judgment module, a steering vector generation module and a beamforming module;

[0011] The multiple filtering modules include a digital downsampling module, a filtering module, and a channelization module.

[0012] Furthermore, the parameter configuration module pre-stores AD / DA configuration parameters through RAM, and automatically completes AD / DA parameter configuration through the SPI interface and parameter configuration protocol when powered on;

[0013] The digital down-conversion module receives the sampling signal from the AD unit and performs digital down-conversion on the signal. By mixing with the sinusoidal signal generated by the local oscillator, the signal is down-converted from the intermediate frequency to the baseband.

[0014] The delay module uses a first-in-first-out data buffer FIFO to achieve a delay difference between D-channel baseband signals that is an integer multiple of the clock cycle;

[0015] The digital down-sampling module selects a low-speed clock whose sampling rate matches the number of channels D, and reduces the signal data rate to 1 / D through a D-fold decimator to obtain D-channel decimated data;

[0016] A filtering module, used for performing multi-phase filtering on the D-channel extracted data to obtain D-channel filtered data;

[0017] A channelization module, used for performing discrete Fourier transform DFT or fast Fourier transform FFT on the D-channel filtered data, and outputting D-channel channel data;

[0018] A judgment module, used for judging the relative bandwidth: judging the bandwidth of the divided digital signal according to the relative bandwidth criterion, and determining whether to generate a narrowband or broadband steering vector;

[0019] A steering vector generation module, used to generate D groups of steering vectors adapted to the system according to the result of the judgment module;

[0020] The beam forming module is used to conjugate and multiply the D groups of steering vectors with the D channel signals and output the D groups of beam data.

[0021] Furthermore, the beamforming module also includes an overflow judgment module, which judges the signal size, moves the signal to cut off the bit, and cuts off the number of signal bits that have not overflowed.

[0022] Furthermore, the filtering module is specifically used to convolve the D-channel extracted data with the corresponding multi-phase filter to obtain D-channel filtered data; the filtering module is implemented by using the multi-phase component of the prototype low-pass filter through the multi-phase filter.

[0023] Furthermore, the relative bandwidth in the judgment module is defined as: BF =(f h -f l ) / 2(f h +f l ), f h is the highest frequency, f l is the lowest frequency; narrowband corresponds to 0 F <0.01; broadband corresponds to 0.01 F <0.25.

[0024] Furthermore, the steering vector generation module is specifically used to generate D groups of steering vectors using the center frequency points of each channel for narrowband, and to generate D groups of steering vectors using the assumed frequency points of each channel frequency band for broadband.

[0025] The present application also provides an adaptive ultra-wideband space-time digital beamforming method based on multiple filters, which is implemented by the system provided by the present application, and the method includes:

[0026] Step 1: The parameter configuration module stores the parameters required for AD / DA and completes the configuration of the digital-analog chip upon power-on;

[0027] The parameter configuration module of the FPGA chip stores the parameters in the RAM through the header file. After the power-on reset initialization, it reads the pre-stored configuration-related parameters and transmits the configuration data to the AD\DA unit through the SPI interface for parameter configuration;

[0028] Step 2: After completing the parameter configuration, the AD unit starts working; after AD sampling, the FPGA chip receives the incoming wave data transmitted by the AD / DA module, and down-converts the sampled intermediate frequency signal to zero intermediate frequency signal data through the data down-conversion module;

[0029] Step 3: Send the down-converted data to the delay module. Assuming the number of channels is D, delay the d-th channel by d-1 clock cycles, and obtain D-1 delayed signals and one channel of real-time data to send to the polyphase filtering module. The method of data channelization is as follows:

[0030] Define the real-time and delayed signal group x of array element m m (k):

[0031] x m (k) = [x m (k),x m (k-1),x m (k-2)……,x m (k-d+1)]

[0032] x m (k) is the real-time signal, x m ​​(k-d+1) is a delayed signal of d-1 clock cycles, with a size of D×1.

[0033] The data rate of the output signal after filtering and extraction is f s / D, the number of time domain taps is D, that is, the actual effective data rate is f s ;

[0034] Step 4: By choosing the sampling rate f s f that matches the number of channelization D s / D low-speed clock, the signal data rate is reduced to 1 / D through the D-times decimator to obtain D-channel decimated data;

[0035] Then, the D-channel extracted data is subjected to polyphase filtering to obtain D-channel filtered data;

[0036] Perform discrete Fourier transform DFT or fast Fourier transform FFT on the D-channel filtered data, and output D-channel channel data;

[0037] The method of multiple filtering is as follows:

[0038]

[0039] Among them, y m (k, D) represents the complex channelized output signal of the mth array element with a size of D×1, which is the result of multi-phase filtering of the kth sampling snapshot and D-1 delayed snapshots. p (m) is the filter coefficient, D is the channel number, ranging from [0, D-1], and p represents the number of signal delay snapshots;

[0040] Step 5: Determine the relative bandwidth of the channel in the determination module, and output the determination result to the steering vector generation module; wherein the relative bandwidth in the determination module is defined as: B F =(f h -f l ) / 2(f h +f l ), f h is the highest frequency, f l is the lowest frequency; the range corresponding to the narrow band is 0 F <0.01; the corresponding range of broadband is 0.01 F <0.25;

[0041] Step 6: The steering vector generation module generates a corresponding steering vector according to the result of the judgment module; if the judgment result is broadband, a multi-hypothesis frequency steering vector is generated, otherwise a narrowband steering vector is generated; the hypothetical steering vector is represented as The narrowband steering vector is denoted by e j2πf(m-1)dsinθ ​​, in the steering vector, (m-1)d is the distance between the mth array element and the first array element;

[0042] Step 7: Send the generated steering vector, real-time data, and delayed data to the beamforming module to achieve beamforming. The specific process is to perform conjugate processing on the steering vector, and then perform convolution and summation of the conjugated steering vector and the data to generate D groups of beam data.

[0043] The present invention provides a digital processing solution based on a brand-new architecture and suitable for engineering implementation. A delay module is used to increase the amount of real-time parallel data and increase the degree of freedom of the algorithm. A plurality of filter modules are used to reduce the real-time bandwidth of the broadband signal, realize data channelization, reduce the difficulty of implementing beamforming, and reduce resource requirements. Then, a steering vector of the adaptation system is selected through a judgment module. Finally, a beamforming module is used to realize the convolution multiplication of the steering vector and the channelized data, so as to realize the in-phase superposition of array signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A structural diagram of a digital channelized ultra-wideband digital beamforming system based on FPGA provided by an embodiment of the present invention is shown.

[0045] Figure 2 A flowchart of ultra-wideband digital beamforming based on digital channelization provided by one embodiment of the present invention is shown.

[0046] Figure 3 A diagram showing an ultra-wideband digital beamforming architecture based on digital channelization provided by one embodiment of the present invention.

[0047] Figure 4 The data flow of an ultra-wideband digital beamforming system based on digital channelization provided by one embodiment of the present invention is shown.

[0048] Figure 5 A schematic diagram of a digital channelization structure of one channel provided by an embodiment of the present invention is shown.

[0049] Figure 6 A schematic diagram of a digital 8-channel structure of one channel provided by an embodiment of the present invention is shown.

[0050] Figure 7 A schematic diagram of a beamforming structure after a judgment module outputs a broadband is shown in an embodiment of the present invention.

[0051] Figure 8 A schematic diagram of a beamforming structure after a judgment module outputs a narrowband is shown in an embodiment of the present invention. DETAILED DESCRIPTION

[0052] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0053] The following first introduces the embodiments of the present application in conjunction with the accompanying drawings.

[0054] Aiming at breaking through the idea of ​​the existing radar signal processing technology architecture, the present invention provides an ultra-wideband digital beamforming design based on digital channelization, and designs a brand-new radar signal processing architecture in engineering.

[0055] An adaptive ultra-wideband digital beamforming system based on multiple filters, including an FPGA chip module and an AD / DA conversion module;

[0056] The FPGA chip module is connected to the AD / DA conversion module to form a beam and send the beam data to the AD / DA conversion module to generate an intermediate frequency broadband signal for transmission to subsequent circuits.

[0057] The AD / DA conversion module is used to input the intermediate frequency signal after AD adoption into the FPGA chip module and receive the beam data generated by the FPGA chip module.

[0058] The FPGA chip module includes a parameter configuration module, a digital down-conversion module, a delay module, a polyphase filtering module, a judgment module, a steering vector generation module and a beamforming module;

[0059] The parameter configuration module is used to generate the parameter configuration required for the sampling of the corresponding AD unit according to the frequency of the broadband signal, store it in the FPGA chip through the header file, and start automatically after power-on to complete the function configuration of the AD unit;

[0060] The digital down-conversion module is used to down-convert the intermediate frequency signal sampled by the AD unit in the AD / DA conversion module to a zero intermediate frequency signal. The digital down-conversion module uses the principle of software radio, optimizes the center frequency and sampling frequency, and adopts a mixing-free digital orthogonal down-conversion structure to convert the incoming wave data into two-way orthogonal I / Q data;

[0061] The delay module is used to store channel data and implement signal delay processing for each channel, increasing the amount of real-time data in the system, facilitating subsequent multi-phase filtering and broadband beamforming, and improving the algorithm's degree of freedom;

[0062] The multi-filter module is used to digitally channelize the multiple groups of delayed and real-time data output by the delay module, reduce the data rate and single-channel instantaneous bandwidth, and reduce the computational complexity for subsequent data processing;

[0063] The judgment module is used to judge the relative bandwidth of the channelized data output by the multiple filtering modules, providing a basis and guidance for the subsequent steering vector generation and beam forming;

[0064] The beamforming calculation module is used to read the corresponding steering vector coefficients and channelized data, and perform beamforming calculations according to the results of the judgment module to obtain the final beamforming data, and send the beamformed data to the DA unit in the AD / DA conversion module.

[0065] The multi-filter module is specifically used for: selecting a low-speed clock whose sampling rate matches the number of channelization D, reducing the signal data rate to 1 / D through a D-fold decimator, and obtaining D-channel decimated data; then performing multi-phase filtering on the D-channel decimated data to obtain D-channel filtered data; then performing discrete Fourier transform DFT or fast Fourier transform FFT on the D-channel filtered data to output D-channel channel data.

[0066] The present invention will be further described below in conjunction with specific embodiments.

[0067] Example

[0068] like Figure 1 , Figure 2 and Figure 3 As shown, an ultra-wideband digital beamforming system based on digital channelization includes an FPGA module and an AD / DA conversion module;

[0069] The FPGA chip module is connected to the AD / DA conversion module to form a beam and send the beam data to the AD / DA conversion module to generate an intermediate frequency broadband signal for transmission to subsequent circuits.

[0070] The AD / DA conversion module is used to input the intermediate frequency signal after AD adoption into the FPGA chip module and receive the beam data generated by the FPGA chip module.

[0071] The FPGA chip module includes a parameter configuration module, a digital down-conversion module, a delay module, a polyphase filtering module, a judgment module, a steering vector generation module and a beamforming module;

[0072] The parameter configuration module is used to generate the parameter configuration required for the sampling of the corresponding AD unit according to the frequency of the broadband signal, store it in the FPGA chip through the header file, and start automatically after power-on to complete the function configuration of the AD unit;

[0073] The digital down-conversion module is used to down-convert the intermediate frequency signal sampled by the AD unit in the AD / DA conversion module to a zero intermediate frequency signal. The digital down-conversion module uses the principle of software radio, optimizes the center frequency and sampling frequency, and adopts a mixing-free digital orthogonal down-conversion structure to convert the incoming wave data into two-way orthogonal I / Q data;

[0074] The delay module is used to store channel data and implement signal delay processing for each channel, increasing the amount of real-time data in the system, facilitating subsequent multi-phase filtering and broadband beamforming, and improving the algorithm's degree of freedom;

[0075] The multi-filter module is used to digitally channelize the multiple groups of delayed and real-time data output by the delay module, reduce the data rate and single-channel instantaneous bandwidth, and reduce the computational complexity for subsequent data processing;

[0076] The judgment module is used to judge the relative bandwidth of the channelized data output by the multiple filtering modules, providing a basis and guidance for the subsequent steering vector generation and beam forming;

[0077] The beamforming calculation module is used to read the corresponding steering vector coefficients and channelized data, and perform beamforming calculations according to the results of the judgment module to obtain the final beamforming data, and send the beamformed data to the DA unit in the AD / DA conversion module.

[0078] The multi-filter module is specifically as follows: by selecting a low-speed clock whose sampling rate matches the number of channelization D, the signal data rate is reduced to 1 / D through a D-fold decimator to obtain D-channel decimated data; then, multi-phase filtering is performed on the D-channel decimated data to obtain D-channel filtered data; then, discrete Fourier transform (DFT) or fast Fourier transform (FFT) is performed on the D-channel filtered data to output D-channel channel data.

[0079] The judgment module is specifically: Relative bandwidth definition: B F =(f h -f l ) / 2(f h +f l ), f h is the highest frequency, f l is the lowest frequency; narrowband corresponds to 0 F <0.01; broadband corresponds to 0.01 F <0.25.

[0080] In this embodiment, the number of delay taps is 8, the sampling rate is 1.25 GHz, the working clock is 156.25 MHz, and the broadband digital beamforming data stream based on digital channelization in this embodiment is as follows: Figure 4 As shown;

[0081] like Figure 5 As shown, the present invention provides a multi-phase filtering basic structure. k (D)(k=0,1,…,D-1) is the multiphase component of D-channel filters, with a common input signal x(D) and D output signals y k ​​(D)(k=0,1,…,D-1), delay the input signal D-1 times, each time delaying an integer snapshot, to obtain D signals, and perform D times decimation on the D signals.

[0082] The digital channelization structure based on filtering in this embodiment is as follows: Figure 6 As shown, the number of channels is 8, the number of delay taps in this embodiment is 8, the sampling rate is 1.25 GHz, and the working clock is 156.25 MHz. k (D)(k=0,1,…,7 is the multiphase component of D-channel filter, with a common input signal x(D) and 8 output signals y k (D) (k = 0, 1, ..., 7), the input signal is delayed 7 times, each time by an integer snapshot, to obtain 8 signals, and the 8 signals are decimated 8 times.

[0083] In this embodiment, the 4-element wideband digital beamforming frost structure based on digital channelization is as follows: Figure 7 and Figure 8 shown; Figure 7 The beamforming module is the module after the judgment module outputs the broadband, and Figure 8 The output of the module determines the narrowband beamforming structure. m,k represents the signal of the mth array element delayed by k-1 snapshots, w m,k Indicates the weight corresponding to the k-1th delayed signal of the mth array element. The corresponding numbered signal and the corresponding weight are conjugated and multiplied, and finally superimposed in phase to obtain a set of beamforming output signals.

[0084] An adaptive ultra-wideband space-time digital beamforming based on multiple filters includes the following steps:

[0085] Step 1, the parameter configuration module stores the parameters required for AD / DA to complete the configuration of the digital-analog chip at power-on; the parameter configuration module of the FPGA chip stores the parameters in RAM through the header file, and after power-on reset initialization, reads the pre-stored configuration-related parameters and transmits the configuration data to the AD\DA unit through the SPI interface for parameter configuration;

[0086] Step 2: After completing the parameter configuration, the AD unit starts working; after AD sampling, the FPGA chip receives the 16-bit incoming wave data transmitted by the AD / DA module, and down-converts the sampled intermediate frequency signal to zero intermediate frequency 16-bit signal data through the data down-conversion module;

[0087] Step 3: Send the down-converted 16-bit data to the delay module. Assuming the number of channels is D, delay the d-th channel by d-1 clock cycles to obtain D-1 delayed 16-bit signals and one channel of real-time data, which are sent to the polyphase filtering module. The data channelization method is as follows:

[0088] Define the real-time and delayed signal group x of array element m m (k):

[0089] x m (k) = [x m (k),x m (k-1),x m (k-2)……,x m (k-d+1)]

[0090] x m (k) is the real-time signal, x m (k-d+1) is a delayed signal of d-1 clock cycles, with a size of D×1.

[0091] The data rate of the output signal after filtering and extraction is f s / D, the number of time domain taps is D, that is, the actual effective data rate is f s .

[0092] Step 4: By choosing the sampling rate f s f that matches the number of channelization D s / D low-speed clock, reduce the signal data rate to 1 / D through a D-times decimator to obtain D-channel decimated data; then perform multi-phase filtering on the D-channel decimated data to obtain D-channel filtered data; then perform discrete Fourier transform DFT or fast Fourier transform FFT on the D-channel filtered data to output D-channel channel data;

[0093] The multi-filtering process is as follows:

[0094]

[0095] Among them, y m (k, D) represents the complex channelized output signal of the mth array element with a size of D×1, which is the result of multi-phase filtering of the kth sampling snapshot and D-1 delayed snapshots. p (m) is the filter coefficient, D is the channel number, ranging from [0, D-1], and p represents the number of signal delay snapshots;

[0096] Step 5: Determine the relative bandwidth of the channel in the determination module, and output the determination result to the steering vector generation module; wherein the relative bandwidth in the determination module is defined as: B F =(f h -f l) / 2(f h +f l ), f h is the highest frequency, f l is the lowest frequency; the range corresponding to the narrow band is 0 F <0.01; the corresponding range of broadband is 0.01 F <0.25;

[0097] Step 6: The steering vector generation module generates a corresponding steering vector according to the result of the judgment module; if the judgment result is broadband, a multi-hypothesis frequency steering vector is generated, otherwise a narrowband steering vector is generated; the multi-hypothesis steering vector is represented as The narrowband steering vector is denoted by e j2πf(m-1)dsinθ , in the steering vector, (m-1)d is the distance between the mth array element and the first array element;

[0098] Step 7: Send the generated steering vector, real-time data and delayed data to the beamforming module to achieve beamforming. The specific process is to conjugate the steering vector, then convolve and sum the conjugated steering vector with the data to generate D groups of 16-bit beam data;

[0099] The present invention provides a digital processing architecture based on a brand-new architecture and suitable for engineering implementation. An FPGA platform is used to implement ultra-wideband digital beamforming. Through digital down-conversion and multi-phase filtering, beamforming completes the engineering implementation of ultra-wideband digital beamforming, effectively reducing the complexity and cost of engineering implementation.

[0100] The above-described embodiments of the present application do not constitute a limitation on the protection scope of the present application.​​

Claims

1. An adaptive ultra-wideband space-time digital beamforming system based on multiple filters, characterized in that: The system comprises: FPGA chip module, AD / DA conversion module; The FPGA chip module is connected to the AD / DA conversion module to form a beam and send the beam data to the AD / DA conversion module to generate an intermediate frequency broadband signal and transmit it to the subsequent circuit; The AD / DA conversion module is used to input the intermediate frequency signal after AD adoption into the FPGA chip module and receive the beam data generated by the FPGA chip module; Among them, the FPGA chip module includes a parameter configuration module, a digital down-conversion module, a delay module, a multi-phase filtering module, a judgment module, a steering vector generation module and a beamforming module; The multiple filtering modules include a digital downsampling module, a filtering module, and a channelization module.

2. The system according to claim 1, characterized in that Parameter configuration module, which pre-stores AD / DA configuration parameters in RAM and automatically completes AD / DA parameter configuration through SPI interface and parameter configuration protocol after power-on; The digital down-conversion module receives the sampling signal from the AD unit and performs digital down-conversion on the signal. By mixing with the sinusoidal signal generated by the local oscillator, the signal is down-converted from the intermediate frequency to the baseband. The delay module uses a first-in-first-out data buffer FIFO to achieve a delay difference between D-channel baseband signals that is an integer multiple of the clock cycle; The digital down-sampling module selects a low-speed clock whose sampling rate matches the number of channels D, and reduces the signal data rate to 1 / D through a D-fold decimator to obtain D-channel decimated data; A filtering module, used for performing multi-phase filtering on the D-channel extracted data to obtain D-channel filtered data; A channelization module is used to perform discrete Fourier transform DFT or fast Fourier transform FFT on the D-channel filtered data and output D-channel channel data; A judgment module, used for judging the relative bandwidth: judging the bandwidth of the divided digital signal according to the relative bandwidth criterion, and determining whether to generate a narrowband or broadband steering vector; A steering vector generation module, used to generate D groups of steering vectors adapted to the system according to the result of the judgment module; The beam forming module is used to conjugate and multiply the D groups of steering vectors with the D channel signals and output the D groups of beam data.

3. The system according to claim 2, characterized in that The beamforming module also includes an overflow judgment module, which judges the signal size, moves the signal to cut off the bit, and cuts off the number of signal bits that have not overflowed.

4. The system according to claim 2, characterized in that The filtering module is specifically used to convolve the D-channel extracted data with the corresponding polyphase filter to obtain D-channel filtered data; the filtering module is implemented by using the polyphase component of the prototype low-pass filter through the polyphase filter.

5. The system according to claim 2, characterized in that The relative bandwidth in the judgment module is defined as: B F =(f h -f l ) / 2(f h +f l ), f h is the highest frequency, f l is the lowest frequency; narrowband corresponds to 0 F <0.01; broadband corresponds to 0.01 F <0.25.​​ 6. The system according to claim 2, characterized in that The steering vector generation module is specifically used to generate D groups of steering vectors using the center frequency points of each channel for narrowband, and to generate D groups of steering vectors using the assumed frequency points of each channel frequency band for broadband.

7. An adaptive ultra-wideband space-time digital beamforming method based on multiple filters, the method being implemented by using any system of claims 1 to 6, characterized in that: The method comprises: Step 1: The parameter configuration module stores the parameters required for AD / DA and completes the configuration of the digital-analog chip upon power-on; The parameter configuration module of the FPGA chip stores the parameters in the RAM through the header file. After the power-on reset initialization, it reads the pre-stored configuration-related parameters and transmits the configuration data to the AD\DA unit through the SPI interface for parameter configuration; Step 2: After completing the parameter configuration, the AD unit starts working; after AD sampling, the FPGA chip receives the incoming wave data transmitted by the AD / DA module, and down-converts the sampled intermediate frequency signal to zero intermediate frequency signal data through the data down-conversion module; Step 3: Send the down-converted data to the delay module. Assuming the number of channels is D, delay the d-th channel by d-1 clock cycles, and obtain D-1 delayed signals and one channel of real-time data to send to the polyphase filtering module. The method of data channelization is as follows: Define the real-time and delayed signal group x of array element m m (k): x m (k)=[x m (k),x m (k-1),x m (k-2)……,x m (k-d+1)] x m (k) is the real-time signal, x m (k-d+1) is a delayed signal of d-1 clock cycles, with a size of D×1. The data rate of the output signal after filtering and extraction is f s / D, the number of time domain taps is D, that is, the actual effective data rate is f s ; Step 4: By choosing the sampling rate f s f that matches the number of channelization D s / D low-speed clock, the signal data rate is reduced to 1 / D through the D-times decimator to obtain D-channel decimated data; Then, the D-channel extracted data is subjected to polyphase filtering to obtain D-channel filtered data; Perform discrete Fourier transform DFT or fast Fourier transform FFT on the D-channel filtered data, and output D-channel channel data; The method of multiple filtering is as follows: Among them, y m (k, D) represents the complex channelized output signal of the mth array element with a size of D×1, which is the result of multi-phase filtering of the kth sampling snapshot and D-1 delayed snapshots. p (m) is the filter coefficient, D is the channel number, ranging from [0, D-1], and p represents the number of signal delay snapshots; Step 5: Determine the relative bandwidth of the channel in the determination module, and output the determination result to the steering vector generation module; wherein the relative bandwidth in the determination module is defined as: B F =(f h -f l ) / 2(f h +f l ), f h is the highest frequency, f l is the lowest frequency; the range corresponding to the narrow band is 0 F <0.01; the corresponding range of broadband is 0.01 F <0.25;​​ Step 6: The steering vector generation module generates a corresponding steering vector according to the result of the judgment module; if the judgment result is broadband, a multi-hypothesis frequency steering vector is generated, otherwise a narrowband steering vector is generated; the hypothetical steering vector is represented by e j2 πf i (m-1)dsinθ , the narrowband steering vector is represented by e j2πf(m-1)dsinθ , in the steering vector, (m-1)d is the distance between the mth array element and the first array element; Step 7: Send the generated steering vector, real-time data, and delayed data to the beamforming module to achieve beamforming. The specific process is to perform conjugate processing on the steering vector, and then perform convolution and summation of the conjugated steering vector and the data to generate D groups of beam data.

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