Method and device for reducing Hash conflict probability of Mac address table of switch chip

Abstract

The invention discloses a method and a device for reducing the Hash conflict probability of a Mac address table of a switch chip. The method comprises the following steps: S1, generating Hash indexes for different storage block spaces through a Hash generator based on a Mac address and a Vlan value; s2, on the basis of the Hash index result generated in the step S1, the corresponding Hash bucket depth, namely the chain table length, is checked on the corresponding blocks, the chain table length conditions on different blocks are compared, and the number of the blocks is larger than or equal to 2; and S3, selecting the corresponding Hash bucket on the corresponding block with the shortest chain table length, and taking the corresponding Hash bucket as the storage position of the Mac address. According to the method, the corresponding buckets on the block are selected in combination with the Hash result and written into the block with many idle resources, and the Hash conflict probability is reduced instead of a traditional linear resource writing mode on duty, so that the resource utilization rate is maximized.

Description

Technical Field

[0001] The present invention relates to the technical field of switching chips, and in particular to a method and device for reducing the probability of Hash conflict in a Mac address table of a switching chip. Background Art

[0002] In modern network devices, especially switches and routers, the Layer 2 address table (Mac address table) is used to store the mapping relationship between Mac addresses and ports. The switch forwards frame data based on the Mac address, so maintaining an efficient and reliable Mac address table is the key to ensuring the high-performance operation of the switch. In the Mac address table, a hash table is usually used to store Mac addresses. This is because the hash table has the advantages of fast search and update. The hash table maps the Mac address to a specific storage location through a hash function, and can perform search and insertion operations in constant time. However, the hash collision problem is a common problem in hash tables, especially when the number of Mac addresses is large, multiple addresses may be mapped to the same hash.

[0003] In order to resolve hash conflicts, existing technologies use a variety of methods to handle conflicts, but each method has its own limitations, affecting the performance and efficiency of switches. Improper handling of hash conflicts may cause query and insertion operations to slow down, and even affect the response time of network devices, thereby affecting the performance of the entire network.

[0004] The main ways to resolve hash conflicts are:

[0005] 1. Chaining:

[0006] Use linked lists to resolve hash conflicts. When multiple Mac addresses are mapped to the same hash, the hash table will create a linked list in the bucket and store the conflicting addresses in the linked list nodes. This method can effectively store multiple conflicting addresses. Figure 1 As shown, when multiple Mac addresses are mapped to the same hash bucket, the hash table creates a linked list in the bucket and stores the conflicting addresses in the linked list nodes.

[0007] 2. Linear Probing:

[0008] When a collision occurs, the next available hash is searched in a linear manner. If the current position is occupied, the next position is checked until an available position is found. Figure 2 As shown in Figure 1, when a conflict occurs, the next available hash bucket is found by linear probing. If the current position is occupied, try to check the next position until an empty position is found.

[0009] At present, the second-layer address table of the switching chip adopts different HASH algorithms to solve the HASH conflict problem of different storage block spaces, or adopts the migration method to solve the HASH conflict. The conflict resolution requires software to move or completely solve it through the HASH algorithm. Summary of the invention

[0010] In view of the above technical problems, the present invention selects the corresponding bucket on the block in combination with the HASH result and writes it to the block with more free resources, instead of following the traditional step-by-step linear writing method to reduce the probability of HASH conflict and maximize resource utilization.

[0011] In order to achieve the above-mentioned purpose, the technical solution of the present invention provides a method for reducing the probability of Hash conflict in the Mac address table of a switching chip, which comprises the following steps: S1: generating a Hash index for different storage block spaces based on the Mac address and the Vlan value through a Hash generator; S2: checking the corresponding Hash bucket depth, that is, the linked list length, on the corresponding block based on the Hash index result generated in step S1, and comparing the linked list lengths on different blocks, wherein the number of blocks is greater than or equal to 2; S3: selecting the corresponding Hash bucket on the corresponding block with the shortest linked list length, and using it as the storage location of the Mac address.

[0012] Further, in step S1, the Hash generator uses a CRC polynomial algorithm to generate a Hash index, and selects a corresponding CRC polynomial algorithm based on the chip specification or the chip storage space, so that the number of Hash indexes generated by the CRC polynomial matches the size of the storage space.

[0013] Furthermore, in step S2, the Hash index generated for each block corresponds to 4 Hash buckets, and the corresponding Hash bucket on a block with the shortest linked list length is determined by comparing the linked list lengths of all Hash buckets of all blocks.

[0014] The technical solution of the present invention also provides a device for reducing the probability of Hash conflict in the Mac address table of a switching chip, which includes the following modules: a Hash index generation module, which is used to generate Hash indexes for different storage block spaces based on the Mac address and the Vlan value through a Hash generator; a Hash bucket depth comparison module, which is used to check the corresponding Hash bucket depth, that is, the linked list length, on the corresponding block based on the Hash index result generated by the Hash index generation module, and compare the linked list lengths on different blocks, wherein the number of blocks is greater than or equal to 2; a Hash bucket selection module, which is used to select the corresponding Hash bucket on the corresponding block with the shortest linked list length, and use it as the storage location of the Mac address.

[0015] Furthermore, in the hash index generation module, the hash generator uses a CRC polynomial algorithm to generate a hash index, and selects a corresponding CRC polynomial algorithm based on chip specifications or chip storage space, so that the number of hash indexes generated by the CRC polynomial matches the size of the storage space.

[0016] Furthermore, in the Hash bucket depth comparison module, the Hash index generated for each block corresponds to 4 Hash buckets. By comparing the linked list lengths of all Hash buckets of all blocks, the corresponding bucket on a block with the shortest linked list length is determined. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 This is a schematic diagram of using a linked list to resolve Hash conflicts;

[0019] Figure 2 This is a schematic diagram of using linear probing to resolve Hash conflicts;

[0020] Figure 3 It is a schematic diagram of the method for reducing the probability of Hash conflicts of the present invention. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] The present invention mainly selects the corresponding bucket on the block according to the HASH result, and writes it to the block with more free resources, instead of following the traditional step-by-step linear writing method. This can reduce HASH conflicts, avoid conflict probability, and improve resource utilization. To ensure the maximum use of resources, the present invention is not limited to the HASH storage related to the second-layer address table, and can be used in any scenario where data is mapped to specific multiple storage locations through a hash function according to actual needs.

[0023] The present invention combines linear hashing and chain hashing to more efficiently solve the probability of hash conflicts and maximize the use of hash block resources. Figure 3 As shown (taking two Hash blocks as an example), the method includes:

[0024] S1: In the method of generating hash index by Hash generator (Hash-gen, Hash generation tool), the corresponding CRC polynomial algorithm (for example, CRC11 is selected according to chip specifications or storage space) is used to accurately hash gen the process based on mac and FID data (or vlan value) to reduce the probability of hash conflict.

[0025] For example, CRC8 can generate a polynomial of 256 hash indexes, while CRC11 can generate a polynomial of 2048 hash indexes. Therefore, if the data depth index of the resource is 256 entries, CRC8 can be used, and if the data depth index of the resource is 2048 entries, CRC11 should be used, because using CRC8 will result in different data calculating (mapping) the same hash index value, resulting in a high conflict rate.

[0026] S2: At this time, by generating the HASH1 index result, check the bucket depth of the corresponding 4 HASH buckets on block 1, that is, the length of the linked list, and then continue to check the bucket depth of the corresponding 4 HASH buckets on block 2, that is, the length of the linked list, and compare the lengths of the linked lists on the two blocks.

[0027] S3: Based on the hash result, select the corresponding hash bucket on the block, that is, the place where the linked list length is the shortest, so that the Mac address is actually written to the block with more free resources.

[0028] Figure 3 The illustrated embodiment only takes two Hash blocks as an example. It is understandable that the number of HASH blocks can be expanded to more according to design requirements.

[0029] In an embodiment of the present invention, a method for reducing the probability of Hash conflict in a Mac address table of a switching chip is provided, which comprises the following steps: S1: generating a Hash index for different storage block spaces based on a Mac address and a Vlan value through a Hash generator; S2: checking the corresponding Hash bucket depth, i.e., the linked list length, on the corresponding block based on the Hash index result generated in step S1, and comparing the linked list lengths on different blocks, wherein the number of blocks is greater than or equal to 2; S3: selecting a corresponding bucket on the corresponding block with the shortest linked list length, and using it as the storage location of the Mac address.

[0030] Further, in step S1, the Hash generator uses a CRC polynomial algorithm to generate a Hash index, and selects a corresponding CRC polynomial algorithm based on the chip specification or the chip storage space, so that the number of Hash indexes generated by the CRC polynomial matches the size of the storage space.

[0031] Furthermore, in step S2, the Hash index generated for each block corresponds to 4 Hash buckets, and the corresponding Hash bucket on a block with the shortest linked list length is determined by comparing the linked list lengths of all Hash buckets of all blocks.

[0032] In another embodiment of the present invention, a device for reducing the probability of Hash conflict in the Mac address table of a switching chip is also provided, which includes the following modules: a Hash index generation module, which is used to generate a Hash index for different storage block spaces based on the Mac address and the Vlan value through a Hash generator; a Hash bucket depth comparison module, which is used to check the corresponding Hash bucket depth, that is, the linked list length, on the corresponding block based on the Hash index result generated by the Hashindex generation module, and compare the linked list lengths on different blocks, wherein the number of blocks is greater than or equal to 2; a Hash bucket selection module, which is used to select the corresponding Hash bucket on the corresponding block with the shortest linked list length, and use it as the storage location of the Mac address.

[0033] Furthermore, in the hash index generation module, the hash generator uses a CRC polynomial algorithm to generate a hash index, and selects a corresponding CRC polynomial algorithm based on chip specifications or chip storage space, so that the number of hash indexes generated by the CRC polynomial matches the size of the storage space.

[0034] Furthermore, in the Hash bucket depth comparison module, the Hash index generated for each block corresponds to 4 Hash buckets, and the corresponding Hash bucket on a block with the shortest linked list length is determined by comparing the linked list lengths of all Hash buckets of all blocks.

[0035] The present invention selects the corresponding bucket on the block in combination with the HASH result and writes it to the block with more free resources, instead of following the traditional step-by-step linear writing method of resources, thereby reducing the probability of HASH conflict and maximizing resource utilization.

[0036] The present invention is not limited to the HASH storage of the second-layer address table, and can be used in any scenario where data is mapped to specific multiple storage locations through a hash function according to actual needs.

[0037] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A method for reducing the probability of Hash conflict in a switching chip Mac address table, characterized in that: The steps include: S1: Generate Hashindex for different storage block spaces based on Mac address and Vlan value through Hash generator; S2: Based on the Hashindex result generated in step S1, check the corresponding Hash bucket depth, that is, the length of the linked list, on the corresponding block, and compare the lengths of the linked lists on different blocks, where the number of blocks is greater than or equal to 2; S3: Select the corresponding Hash bucket on the corresponding block with the shortest linked list length and use it as the storage location of the Mac address.

2. The method according to claim 1, characterized in that In step S1, the Hash generator uses a CRC polynomial algorithm to generate a Hash index, and selects a corresponding CRC polynomial algorithm based on the chip specification or the chip storage space, so that the number of Hashindexes generated by the CRC polynomial matches the size of the storage space.

3. The method according to claim 1, characterized in that In step S2, the Hashindex generated for each block corresponds to 4 Hash buckets, and the corresponding Hash bucket on the block with the shortest linked list length is determined by comparing the linked list lengths of all Hash buckets of all blocks.

4. A device for reducing the probability of Hash conflict in a switching chip Mac address table, characterized in that: Includes the following modules: Hashindex generation module, used to generate Hashindex for different storage block spaces based on Mac address and Vlan value through Hash generator; The Hash bucket depth comparison module is used to check the corresponding Hash bucket depth, that is, the length of the linked list, on the corresponding block based on the Hash index result generated by the Hashindex generation module, and compare the length of the linked lists on different blocks, where the number of blocks is greater than or equal to 2; The Hash bucket selection module is used to select the corresponding Hash bucket on the corresponding block with the shortest linked list length and use it as the storage location of the Mac address.

5. The device according to claim 5, characterized in that In the Hashindex generation module, the Hash generator uses a CRC polynomial algorithm to generate a Hashindex, and selects a corresponding CRC polynomial algorithm based on the chip specification or the chip storage space so that the number of Hashindexes generated by the CRC polynomial matches the size of the storage space.

6. The device according to claim 5, characterized in that In the Hash bucket depth comparison module, the Hashindex generated for each block corresponds to 4 Hash buckets. By comparing the linked list lengths of all Hash buckets of all blocks, the corresponding Hash bucket on the block with the shortest linked list length is determined.

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