Dynamic instantiation-based error correction in-memory computing system, method and apparatus

Abstract

The invention provides an error correction in-memory computing system, method and device based on dynamic instantiation, and belongs to the technical field of in-memory computing. The system comprises an in-memory computing input module, an error correction in-memory computing module and an in-memory computing output module; the in-memory calculation input module is used for dividing characteristic values and generating parity check bits; in the error correction in-memory calculation module, an on-chip anti-radiation MRAM unit sends the weight to an instantiation in-memory calculation unit, in-memory calculation is carried out on the weight and the characteristic value, a calculation result is sent to a result judgment unit, if parity check is correct, the result is output, and if parity check is incorrect, an instantiation in-memory calculation unit is newly added for outputting a correct result; and the in-memory calculation output module is used for receiving an output result of the error correction in-memory calculation module to obtain an output characteristic value. According to the method, flexible dynamic instantiation of the in-memory computing unit is supported, instantiation or hardware resource release is carried out according to the computing result, and the flexibility and the system performance of the in-memory computing system are enhanced.

Description

Technical Field

[0001] The present invention relates to the field of in-memory computing technology, and in particular to an error-correcting in-memory computing system, method and device based on dynamic instantiation. Background Art

[0002] With the rapid development of aerospace technology, onboard computing systems are facing increasingly complex computing requirements, especially in tasks such as image processing and navigation positioning, which require onboard computing systems to have efficient processing capabilities and reliability. However, the traditional von Neumann architecture has a data bottleneck problem due to the frequent transmission of data between the memory and the processor, which limits the performance improvement of onboard computing systems. In addition, the radiation effect and space electromagnetic interference in the aerospace environment pose severe challenges to the reliability of electronic devices. How to ensure the high reliability of computing systems has become an important issue in aerospace electronic design.

[0003] In recent years, in-memory computing technology has gradually become an effective way to solve the bottlenecks of computing performance and energy efficiency. In-memory computing integrates storage and computing functions into the same hardware unit. By reducing data transmission, it improves computing efficiency and reduces energy consumption. It is suitable for aerospace applications with strict energy efficiency and volume constraints. The in-memory computing architecture directly performs computing tasks such as matrix multiplication in the memory, greatly reducing data movement overhead and improving parallel processing capabilities. However, due to the harsh conditions of the aerospace environment and the long-term operation requirements of onboard computing systems, traditional in-memory computing architectures face many challenges in terms of radiation resistance and fault tolerance, and cannot fully meet the requirements of high reliability.

[0004] In onboard computing systems, radiation effects and hardware aging can cause permanent or temporary errors in computing units. To ensure stable system operation, traditional error correction methods rely mainly on redundant hardware design (such as triple-module redundancy), which detects and repairs errors by comparing the output results of multiple identical computing units. However, this static redundancy method increases hardware complexity and power consumption, resulting in a waste of hardware resources and insufficient system flexibility. Summary of the invention

[0005] In view of the defects in the prior art, the object of the present invention is to provide an in-memory computing system, method and device for error correction based on dynamic instantiation.

[0006] According to the present invention, an error correction in-memory computing system based on dynamic instantiation includes: an in-memory computing input module, an error correction in-memory computing module and an in-memory computing output module; The in-memory calculation input module is used to divide the characteristic values ​​and generate parity check bits, and send them to the error correction in-memory calculation module; The error correction in-memory calculation module performs in-memory calculation on the characteristic value, performs parity check on the calculation result, outputs a correct result according to the check result, and sends the result to the in-memory calculation output module; The in-memory calculation output module is used to receive the output result of the error correction in-memory calculation module to obtain an output characteristic value.

[0007] Preferably, a parity generation unit is provided in the in-memory calculation input module for generating parity bits.

[0008] Preferably, the error correction in-memory computing module comprises an on-chip radiation-resistant MRAM unit, an instantiated in-memory computing unit and a result decision unit; The on-chip radiation-resistant MRAM unit sends the weight to the instantiated in-memory calculation unit, performs in-memory calculation with the eigenvalue, and sends the calculation result to the result judgment unit. If the parity check is correct, the result is output; if the parity check is incorrect, a new in-memory calculation unit to be instantiated is added to output the correct result.

[0009] Preferably, the result judgment unit performs a parity check based on the parity check bits from the in-memory calculation input module, the parity check bits of the instantiated in-memory calculation unit, and the parity values ​​of the number of groups of eigenvalues ​​and weights to determine whether the current calculation result is correct. If the calculation result is correct, the result is sent to the in-memory calculation output module; if the calculation result is incorrect, a new in-memory calculation unit to be instantiated is instantiated to recalculate, and the calculation result is sent to the in-memory calculation output module.

[0010] Preferably, the on-chip radiation-resistant MRAM unit is used to store neural network weight parameters.

[0011] Preferably, the instantiated in-memory computing unit and the in-memory computing unit to be instantiated are configured with the same hardware structure for performing in-memory computing.

[0012] Preferably, the result determination unit is provided with a parity check unit and a parity check generation unit for performing parity check.

[0013] According to the present invention, an in-memory calculation method for error correction based on dynamic instantiation is provided, comprising: Step S1: Send the same neural network weight parameters from the on-chip radiation-resistant MRAM unit to the instantiated in-memory computing units #0 and #1; Step S2: Send the input eigenvalue to the in-memory calculation input module, generate parity bits through the parity generation unit, split the input eigenvalue into output eigenvalues ​​#0 and #1, and send the output eigenvalues ​​#0, #1 and parity bits to the error correction in-memory calculation module; Step S3: the instantiated in-memory computing units #0 and #1 receive the eigenvalues ​​from the in-memory computing input module and the weights of the on-chip radiation-resistant MRAM units, obtain the calculation results and send them to the result judgment unit, and the result judgment unit performs parity check according to the parity check bits from the in-memory computing input module, the parity check bits of the instantiated in-memory computing units #0 and #1, the eigenvalues ​​and the parity values ​​of the (1,0) groups of the weights, to determine whether the current calculation result is correct; Step S4: If the calculation result is correct, the result is sent to the in-memory calculation output module; if the calculation result is incorrect, a new in-memory calculation unit #2 to be instantiated is instantiated to recalculate, and the calculation result is sent to the in-memory calculation output module.

[0014] According to the present invention, an in-memory computing device for error correction based on dynamic instantiation is provided, comprising a processor and a memory, wherein the memory stores executable program instructions, and when the processor calls the program instructions in the memory, the processor is used for the steps of the in-memory computing method for error correction based on dynamic instantiation.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The present invention provides an error-correcting in-memory computing system and method based on dynamic instantiation, which supports flexible and dynamic instantiation of in-memory computing units, instantiates or releases hardware resources according to the calculation results, and enhances the flexibility and system performance of the in-memory computing system. Compared with traditional methods, the system significantly improves the computing power and radiation resistance of the onboard computing system, ensuring long-term stable operation in complex space environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings: Figure 1 A schematic diagram of the structure of an in-memory computing system for error correction based on dynamic instantiation provided by the present invention; Figure 2 A schematic diagram of the structure of the in-memory computing input module provided by the present invention; Figure 3 A schematic diagram of the structure of a result determination unit in an error correction in-memory calculation module provided by the present invention; Figure 4 A flowchart of an in-memory calculation method for error correction based on dynamic instantiation provided by the present invention.

[0017] Description of reference numerals: In-memory computing input module 101, error correction in-memory computing module 102, in-memory computing output module 103, on-chip radiation-resistant MRAM unit 1021, instantiated in-memory computing unit 1022, in-memory computing unit to be instantiated 1023, and result judgment unit 1024. DETAILED DESCRIPTION

[0018] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0019] Figure 1 A schematic diagram of a structure of an in-memory computing system for error correction based on dynamic instantiation provided by the present invention, such as Figure 1 As shown, the present invention provides an in-memory computing system for error correction based on dynamic instantiation, including an in-memory computing input module 101, an error correction in-memory computing module 102 and an in-memory computing output module 103, wherein: The in-memory calculation input module 101 is used to divide the characteristic values ​​and generate parity check bits, and send them to the error correction in-memory calculation module 102.

[0020] First, the eigenvalue is split into bits, such as an 8-bit eigenvalue is split into 8 1-bit binary numbers. Second, the number of 1s in these bits is counted. If the number of 1s is odd, the check bit is 1; if it is even, the check bit is 0.

[0021] In the present invention, the in-memory calculation input module 101 is provided with a parity generation unit for generating parity bits.

[0022] In the error correction in-memory calculation module 102, the on-chip radiation-resistant MRAM unit 1021 sends the weight to the instantiated in-memory calculation unit 1022, performs in-memory calculation with the eigenvalue, and sends the calculation result to the result judgment unit 1024. If the parity check is correct, the result is output; if the parity check is incorrect, a new in-memory calculation unit to be instantiated 1023 is instantiated to recalculate, and the calculation result is sent to the in-memory calculation output module 103.

[0023] The parity check bit of the input eigenvalue only reflects the number of 1s in the eigenvalue, and cannot directly reflect the number of 1s in the result after the eigenvalue is multiplied by the weight. Figure 3Analysis of the table in : When the eigenvalue is 0, no matter what the weight is, the multiplication result is 0, which will not cause parity check failure; when the eigenvalue is 1 and the weight is 1, the multiplication result is 1, which will not cause parity check failure; when the eigenvalue is 1 and the weight is 0, the multiplication result is 0, and the parity check result of the eigenvalue and the parity check result of the multiplication result will be inconsistent. In order to solve this problem, a correction item is added on the basis of the eigenvalue parity check, that is, the parity check bit of the case where the eigenvalue is 1 and the weight is 0 is counted, and it is XORed with the parity check bit of the eigenvalue to obtain a new parity check bit. This new parity check bit can accurately reflect the parity of the multiplication result. Finally, by comparing it with the parity check bit of the actual multiplication result, it can be determined whether an error occurred in the calculation process.

[0024] In the present invention, the on-chip radiation-resistant MRAM unit 1021 is used to store neural network weight parameters.

[0025] In the present invention, the instantiated in-memory computing unit 1022 and the in-memory computing unit to be instantiated 1023 are configured with the same hardware structure for performing in-memory computing.

[0026] In the present invention, the result determination unit 1024 is provided with a parity check unit and a parity check generation unit for performing parity check.

[0027] The in-memory calculation output module 103 is used to receive the output result of the error correction in-memory calculation module 102 to obtain an output characteristic value.

[0028] The present invention provides an error-correcting in-memory computing system and method based on dynamic instantiation, which supports flexible and dynamic instantiation of in-memory computing units, instantiates or releases hardware resources according to calculation results, and enhances the flexibility and system performance of the in-memory computing system.

[0029] In the present invention, Figure 2 Schematic diagram of the structure of the in-memory computing input module 101 provided by the present invention. Figure 2 As shown, the present invention sends the input eigenvalue to the in-memory calculation input module 101, generates parity bits through a parity generation unit, and splits the input eigenvalue into output eigenvalues ​​#0 and #1, and sends the output eigenvalues ​​#0, #1 and parity bits to the error correction in-memory calculation module 102.

[0030] In the present invention, Figure 3 This is a schematic diagram of the structure of the result judgment unit in the error correction in-memory calculation module provided by the present invention. Figure 3As shown, the instantiated in-memory computing units 1022 #0 and #1 receive the eigenvalues ​​from the in-memory computing input module 101 and the weights of the on-chip radiation-resistant MRAM unit 1021, obtain the calculation results and send them to the result judgment unit 1024, and the result judgment unit 1024 performs parity check based on the parity check bits from the in-memory computing input module 101, the parity check bits of the instantiated in-memory computing units 1022 #0 and #1, the eigenvalues ​​and the parity values ​​of the (1,0) groups of weights to determine whether the current calculation result is correct. If the calculation result is correct, the result is sent to the in-memory computing output module 103; if the calculation result is incorrect, the new in-memory computing unit 1023 #2 to be instantiated is instantiated to recalculate and send the calculation result to the in-memory computing output module 103.

[0031] In the present invention, the decision basis of the result decision unit 1024 is established for the following two reasons: ① The probability of bit flipping caused by space radiation is not high, and the probability of multiple bit flipping occurring at the same time is extremely low; ② The parity check bit of the eigenvalue cannot correspond to the parity check bit of the calculation result in the memory. The reason is that the calculation result when the eigenvalue is 1 and the weight is 0 has a parity flip problem compared with the eigenvalue. Therefore, it is only necessary to add the parity check bit of the eigenvalue to the parity value of the number of (1,0) groups with the eigenvalue of 1 and the weight of 0 to obtain a new parity check bit, which is compared with the parity check bit of the calculation result to determine whether the calculation result is correct.

[0032] Figure 4 A flowchart of an in-memory calculation method for error correction based on dynamic instantiation provided by the present invention is shown in FIG. Figure 4 As shown, the present invention provides an in-memory computation based on dynamic instantiation of error correction, including: Step S1, sending the same neural network weight parameters from the on-chip radiation-resistant MRAM unit to the instantiated in-memory computing units #0 and #1; Step S2, sending the input eigenvalue to the in-memory calculation input module, generating parity bits through the parity generation unit, and splitting the input eigenvalue into output eigenvalues ​​#0 and #1, and sending the output eigenvalues ​​#0, #1 and the parity bits to the error correction in-memory calculation module; Step S3, the instantiated in-memory computing units #0 and #1 receive the characteristic values ​​from the in-memory computing input module and the weights of the on-chip radiation-resistant MRAM units, obtain the calculation results and send them to the result judgment unit, and the result judgment unit performs parity check according to the parity check bits from the in-memory computing input module, the parity check bits of the instantiated in-memory computing units #0 and #1, the characteristic values ​​and the parity values ​​of the (1,0) groups of the weights to determine whether the current calculation result is correct; Step S4, if the calculation result is correct, the result is sent to the in-memory calculation output module; if the calculation result is incorrect, a new in-memory calculation unit #2 to be instantiated is instantiated to recalculate and the calculation result is sent to the in-memory calculation output module.

[0033] The present invention also provides an in-memory computing device for error correction based on dynamic instantiation, comprising: a processor and a memory, wherein the memory stores executable program instructions, and when the processor calls the program instructions in the memory, the processor is used to execute the steps of the in-memory computing method for error correction based on dynamic instantiation as described above.

[0034] The present invention also provides a computer-readable storage medium for storing a program, wherein when the program is executed, the steps of the above-mentioned error correction in-memory computing method based on dynamic instantiation are implemented.

[0035] It should be noted that those skilled in the art will appreciate that various aspects of the present invention may be implemented as systems, methods or program products. Therefore, various aspects of the present invention may be specifically implemented in the following forms, namely: complete hardware implementation, complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software, which may be collectively referred to as "circuit", "module" or "platform" herein.

[0036] In addition, an embodiment of the present application further provides a computer-readable storage medium, in which computer-executable instructions are stored. When at least one processor of a user device executes the computer-executable instructions, the user device executes the above-mentioned various possible methods. Among them, the computer-readable medium includes a computer storage medium and a communication medium, wherein the communication medium includes any medium that facilitates the transmission of a computer program from one place to another. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC. In addition, the ASIC can be located in a user device. Of course, the processor and the storage medium can also exist in a communication device as discrete components.

[0037] The present application also provides a program product, which includes a computer program. The computer program is stored in a readable storage medium. At least one processor of the server can read the computer program from the readable storage medium. At least one processor executes the computer program so that the server implements any method of the above-mentioned embodiments of the present invention.

[0038] The program product may adopt any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, a system, device or component of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0039] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. An error-correcting in-memory computing system based on dynamic instantiation, characterized in that: include: An in-memory computing input module (101), an error correction in-memory computing module (102) and an in-memory computing output module (103); The in-memory calculation input module (101) is used to divide the characteristic values ​​and generate parity check bits, and send them to the error correction in-memory calculation module (102); The error correction in-memory calculation module (102) performs in-memory calculation on the characteristic value, performs parity check on the calculation result, outputs a correct result according to the check result, and sends the result to the in-memory calculation output module (103); The in-memory calculation output module (103) is used to receive the output result of the error correction in-memory calculation module (102) to obtain an output characteristic value.

2. The in-memory computing system based on dynamic instantiation of error correction according to claim 1, characterized in that: The in-memory calculation input module (101) is provided with a parity check generating unit for generating parity check bits.

3. The in-memory computing system based on dynamic instantiation of error correction according to claim 1, characterized in that: The error correction in-memory computing module (102) comprises an on-chip radiation-resistant MRAM unit (1021), an instantiated in-memory computing unit (1022), an instantiated in-memory computing unit (1023) and a result judgment unit (1024); The on-chip radiation-resistant MRAM unit (1021) sends the weight to the instantiated in-memory calculation unit (1022), performs in-memory calculation with the characteristic value, and sends the calculation result to the result judgment unit (1024). If the parity check is correct, the result is output; if the parity check is incorrect, a new in-memory calculation unit to be instantiated is added to output the correct result.

4. The in-memory computing system based on dynamic instantiation of error correction according to claim 3, characterized in that: The result judgment unit (1024) performs a parity check based on the parity check bits from the in-memory calculation input module (101), the parity check bits of the instantiated in-memory calculation unit (1022), and the parity values ​​of the number of groups of eigenvalues ​​and weights to determine whether the current calculation result is correct. If the calculation result is correct, the result is sent to the in-memory calculation output module (103); if the calculation result is incorrect, a new in-memory calculation unit to be instantiated (1023) is instantiated to recalculate, and the calculation result is sent to the in-memory calculation output module (103).

5. The in-memory computing system based on dynamic instantiation of error correction according to claim 3, characterized in that: The on-chip radiation-resistant MRAM unit (1021) is used to store neural network weight parameters.

6. The in-memory computing system based on dynamic instantiation of error correction according to claim 3, characterized in that: The instantiated in-memory computing unit (1022) and the in-memory computing unit to be instantiated (1023) are configured with the same hardware structure for performing in-memory computing.

7. The in-memory computing system based on dynamic instantiation of error correction according to claim 3, characterized in that: The result determination unit (1024) is provided with a parity check unit and a parity check generation unit for performing parity check.

8. An in-memory calculation method for error correction based on dynamic instantiation, based on the in-memory calculation system for error correction based on dynamic instantiation according to any one of claims 3 to 7, characterized in that: include: Step S1: Sending the same neural network weight parameter from the on-chip radiation-resistant MRAM unit (1021) to the instantiated in-memory computing unit (1022) #0 and #1; Step S2: sending the input eigenvalue to the in-memory calculation input module (101), generating parity check bits through the parity check generation unit, splitting the input eigenvalue into output eigenvalues ​​#0 and #1, and sending the output eigenvalues ​​#0, #1 and the parity check bits to the error correction in-memory calculation module (102); Step S3: the instantiated in-memory computing units (1022) #0 and #1 receive the characteristic values ​​from the in-memory computing input module (101) and the weights of the on-chip radiation-resistant MRAM units (1021), obtain the calculation results and send them to the result judgment unit (1024), and the result judgment unit (1024) performs parity check based on the parity check bits from the in-memory computing input module (101), the parity check bits of the instantiated in-memory computing units (1022) #0 and #1, the characteristic values ​​and the parity values ​​of the (1,0) groups of weights, to determine whether the current calculation result is correct; Step S4: If the calculation result is correct, the result is sent to the in-memory calculation output module (103); if the calculation result is incorrect, a new in-memory calculation unit #2 to be instantiated is instantiated to recalculate, and the calculation result is sent to the in-memory calculation output module (103).

9. An in-memory computing device for error correction based on dynamic instantiation, comprising a processor and a memory, wherein the memory stores executable program instructions, and when the processor calls the program instructions in the memory, the processor is used to execute the steps of the in-memory computing method for error correction based on dynamic instantiation as described in claim 8.

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