Driving circuit, panel driving system and display device
By grouping the output channels of the display panel and adjusting the output delay time using clock signals and delay setting modules, the problem of high driving cost for large-size panels is solved, achieving efficient PPCC functionality and improved product yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HKC CORP LTD
- Filing Date
- 2025-03-17
- Publication Date
- 2026-07-24
AI Technical Summary
Large-size panel products have high driving costs and long charging times, and the existing PPCC function cannot be adjusted according to the actual impedance of the product and the differences between panels, resulting in wasted space and cost.
The output channels of the display panel are divided into multiple groups. The output delay is controlled by the first and second clock signals. Combined with the delay setting module, the output delay time is adjusted according to the input voltage of the external voltage divider circuit to realize the delay control of the output channels.
It saves space and cost for the drive circuit, while meeting the PPCC functional requirements of large-size panels and improving product yield.
Smart Images
Figure CN120014953B_ABST
Abstract
Description
Technical Field
[0001] The embodiments disclosed in this application relate to the field of display technology, and more specifically, to a driving circuit, a panel driving system, and a display device. Background Technology
[0002] With the continuous development of the display industry, various technologies to improve display effects are emerging one after another. Currently, due to market demand, product sizes are getting larger and larger, which leads to an increase in the overall power consumption of products and an increase in driver costs. At the same time, in order to improve the charging time and display effect of large-size panel products, higher requirements are also placed on the PPCC function (Programmable PanelCharging CompensationShiftFunction). Summary of the Invention
[0003] According to embodiments of this application, this application proposes a driving circuit, a panel driving system, and a display device to solve the above-mentioned problems.
[0004] The first aspect of this application discloses a driving circuit applied to a display panel, the display panel including multiple columns of pixels, the multiple columns of pixels being divided into m groups, including: multiple output channels, the multiple output channels being divided into the m groups, each group of output channels being connected to a group of pixel columns; wherein, the m groups of output channels sequentially output in response to a first clock signal and a second clock signal; wherein, at least two groups of output channels in the m groups of output channels output once in response to the first clock signal and the second clock signal, and any adjacent outputs are spaced apart by an output delay time.
[0005] In some embodiments, the first clock signal and the second clock signal have the same period, and the timing of the first clock signal and the second clock signal are opposite but the levels are the same.
[0006] In some embodiments, in response to the rising edge of the first clock signal and the second clock signal being at a low level, the current two output channels in the m output channels perform the current output; in response to the first clock signal being at a low level and the second clock signal being at a high level, the next two output channels in the m output channels perform the next output.
[0007] In some embodiments, the driving circuit further includes a delay setting module connected to an external voltage divider circuit, used to set the output delay time based on the input voltage of the external voltage divider circuit.
[0008] In some embodiments, the output delay time is related to the period of the first clock signal or the second clock signal.
[0009] In some embodiments, setting the output delay time based on the input voltage of the external voltage divider circuit includes: in response to the input voltage being a first value, setting the output delay time to a first preset multiple of the period of the first clock signal or the second clock signal; in response to the input voltage being a second value, setting the output delay time to a second preset multiple of the period of the first clock signal or the second clock signal; wherein, if the first value is greater than the second value, then the first preset multiple is less than the second preset multiple.
[0010] The second aspect of this application discloses a panel driving system, comprising: at least one driving circuit connected to the display panel, wherein each of the driving circuits is a driving circuit as described in the first aspect; and a timing control circuit connected to the at least one driving circuit for generating a first clock signal and a second clock signal.
[0011] In some embodiments, the timing control circuit is further configured to receive output grayscale data on the display panel corresponding to the corresponding driving circuit, and determine the target delay time corresponding to the corresponding driving circuit based on the output grayscale data; the at least one driving circuit is further configured to adjust the output delay time of the corresponding driving circuit based on the target delay time.
[0012] In some embodiments, determining the target delay time corresponding to the corresponding driving circuit based on the output grayscale data includes: obtaining the impedance data of the corresponding driving circuit from a first preset table based on the output grayscale data; and obtaining the target delay time corresponding to the corresponding driving circuit from a second preset table based on the impedance data of the corresponding driving circuit.
[0013] The third aspect of this application discloses a display device, including a display panel and the driving circuit described in the first aspect, or including the display panel and the panel driving system as described in the second aspect.
[0014] The beneficial effects of this application are as follows: The driving circuit is applied to the display panel, the driving circuit includes multiple output channels, the display panel includes multiple pixel columns, the multiple pixel columns and multiple output channels are divided into m groups, the m groups of output channels respond to the first clock signal and the second clock signal to output sequentially, wherein at least two groups of output channels in the m groups of output channels respond to the first clock signal and the second clock signal to output once, and the interval between any adjacent output is an output delay time. The output delay of multiple output channels is controlled by the first clock signal and the second clock signal, which saves space and cost while meeting the high requirements of PPCC function of large-size panels, thereby improving product yield. Attached Figure Description
[0015] The present application will be further described below with reference to the accompanying drawings and embodiments. In the drawings:
[0016] Figure 1 This is a schematic diagram of the structure of a serial output line in related technologies;
[0017] Figure 2 This is a timing diagram of the clock signal in the related technology;
[0018] Figure 3 This is a schematic diagram of the driving circuit according to an embodiment of this application;
[0019] Figure 4 This is a timing diagram of the clock signal in an embodiment of this application;
[0020] Figure 5 This is a schematic diagram of the structure of a driving circuit according to an embodiment of this application;
[0021] Figure 6 This is a schematic diagram of the structure of the panel driving system according to an embodiment of this application;
[0022] Figure 7 This is a schematic diagram of the structure of a display device according to an embodiment of this application. Detailed Implementation
[0023] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0024] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Additionally, the character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, "many" in this application means two or more. Moreover, the term "at least one" in this application means any combination of at least two of any one or more of a plurality of objects. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C. Furthermore, the terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.
[0025] To facilitate understanding, a brief explanation of the drive output and PPCC function is provided. For example... Figure 1 As shown, Figure 1 This is a schematic diagram of the serial output line structure in related technologies. Due to the size of large-size display panels, the length of each driver output SOUT (Swap OUT, serial output line) cannot be completely consistent. To ensure that the impedance of the in-plane SOUT remains consistent while maintaining the same architectural design, and to ensure that the charging effect of the data output from the driver to the in-plane remains consistent within the same time frame, the driver's middle section closer to the in-plane is routed in a curved "serpentine" pattern, while the ends are relatively straight broken lines. This ensures that the trace length of the driver's output SOUT to the in-plane SOUT remains consistent between the middle and the ends. The driver output SOUT is connected to the in-plane, but for the same driver, the number of output SOUTs is large, such as 726ch, 966ch, 1366ch, etc.
[0026] If multiple channels simultaneously output SOUT data into the plane during output, the current drawn from the in-plane load to the driver at the instant of output is enormous, causing a sudden and sharp increase in the driver load and placing very high demands on the driver. The PPCC function can be used to solve this problem by controlling the SOUT data to not be output simultaneously at the moment of output, grouping all driver channels, such as... Figure 2 As shown, Figure 2 This is a timing diagram of the clock signal in related technologies. Taking a single driver with 966 channels as an example, the channels are divided into groups of 12 channels each, resulting in 81 groups. Each of the 81 groups of channels can be controlled by 10 DCLK (clock signals). For example, DCLK1 controls the output of the first group, DCLK2 controls the output of the second group, and so on. When it reaches the 11th group, it is controlled by the second high level of DCLK1 in a loop. Each of the 81 groups is delayed by a fixed time interval.
[0027] The number of groups that the drive output SOUT can be divided into for output, as well as the interval time between each group, are fixed and cannot be adjusted. They are determined by the IC (Integrated Circuit) manufacturer at the beginning of the design and cannot be modified after the product is manufactured. They also cannot be adjusted according to the actual impedance of the product or the differences between different products. Furthermore, using DCLK1-DCLK10 to control the grouped output requires the IC to generate 10 clock signals internally, which requires a lot of space and cost for the timing control circuit.
[0028] To address these issues, this application provides a driving circuit, a panel driving system, and a display device.
[0029] To enable those skilled in the art to better understand the technical solution of this application, the technical solution of this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0030] Please see Figure 3 , Figure 3 This is a schematic diagram of the driving circuit according to an embodiment of this application. The driving circuit 100 is applied to the display panel 200, which includes a plurality of pixel columns 210, wherein the plurality of pixel columns 210 are divided into m groups.
[0031] The drive circuit 100 includes multiple output channels 110, which are divided into m groups, such as... Figure 3 As shown, multiple output channels 110 are divided into m groups, namely N1, N2...Nm. Each group of output channels is connected to a group of pixel columns, wherein there is a one-to-one correspondence between the output channels 110 and the pixel columns 210 and the number of each group is the same. The output channels 110 can be used to provide output voltage to the pixel columns 210. For example, the display panel 200 includes 966 pixel columns 210, and 12 pixel columns 210 are divided into groups, resulting in 81 groups, i.e., m = 81. Correspondingly, the driving circuit 100 includes 966 output channels 110, which are divided into 81 groups.
[0032] Among them, m output channels respond to the first clock signal and the second clock signal sequentially to output. For example... Figure 4 As shown, Figure 4 This is a timing diagram of the clock signal in an embodiment of this application. For example, in response to the state changes of the first clock signal DCLK_a and the second clock signal DCLK_b, m groups of output channels output sequentially.
[0033] Among them, at least two output channels in each of the m output channels respond to the first clock signal and the second clock signal to output once, and the interval between any adjacent outputs is the output delay time. For example, at least two output channels may include 2 groups, 3 groups, 4 groups, etc.
[0034] like Figure 4As shown, the m groups of output channels include output channels N1, N2...N10, and output channels Nn (n = 1, 2, ... m) represent a group of output channels. Each group of output channels can include 12 output channels 110. In some examples, at least two output channels in the m output channels output once in response to the first clock signal and the second clock signal, and the interval between any adjacent outputs is an output delay time. For example, output channels N1-N2 output once in response to the first clock signal DCLK_a being in the first timing state and the second clock signal DCLK_b being in the second timing state; output channels N3-N4 output once in response to the first clock signal DCLK_a being in the second timing state and the second clock signal DCLK_b being in the first timing state; output channels N5-N6 output once in response to the first clock signal DCLK_a being in the first timing state again and the second clock signal DCLK_b being in the second timing state again; and so on. The output interval time T1 between output channels N1-N2 and output channels N3-N4 is T1, and the output interval time T2 between output channels N3-N4 and output channels N5-N6 is T2, where T1 and T2 are output delay times.
[0035] In this embodiment, the driving circuit 100 is applied to the display panel 200. The driving circuit 100 includes multiple output channels 110, and the display panel 200 includes multiple pixel columns 210. The multiple pixel columns 210 and the multiple output channels 110 are divided into m groups. The m groups of output channels output in response to a first clock signal and a second clock signal. In this case, at least two groups of output channels in each of the m groups output channels output once in response to the first clock signal and the second clock signal, and the interval between any adjacent outputs is an output delay time. The output delay of the multiple output channels 110 is controlled by the first clock signal and the second clock signal, which saves space and cost while meeting the high requirements of PPCC function of large-size panels, thereby improving product yield.
[0036] In some embodiments, the first clock signal and the second clock signal have the same period, and the timing of the first clock signal and the second clock signal are opposite but the levels are the same.
[0037] like Figure 4 As shown, the first clock signal DCLK_a and the second clock signal DCLK_b have the same period T, and their timing sequences are opposite while their levels are the same. The period T of the first clock signal DCLK_a and the second clock signal DCLK_b can refer to the width of the first clock signal DCLK_a / second clock signal DCLK_b when it is at a high level and a low level, respectively. Figure 4 (Not shown in the image).
[0038] In some embodiments, in response to the rising edge of the first clock signal and the second clock signal being at a low level, the current two output channels in the m output channels perform the current output; in response to the first clock signal being at a low level and the second clock signal being at a high level, the next two output channels in the m output channels perform the next output.
[0039] Continuing with the example of output channels N1, N2...N10, as described above... Figure 4 As shown, in response to the rising edge of the first clock signal and the second clock signal being low, the current two output channels in the m output channels perform the current output. For example, in response to the rising edge of the first clock signal DCLK_a and the second clock signal DCLK_b being low, the channel signal 1 corresponding to output channel N1-N2 is high, and output channel N1-N2 performs the current output. At this time, the data transmission of the other output channels (e.g., output channels N3-N10) is delayed.
[0040] Furthermore, in response to the first clock signal being low and the second clock signal being high, the next two output channels in the m output channels will perform the next output. For example, in the current time period, the first clock signal DCLK_a is high and the second clock signal DCLK_b is low. In the next time period, the first clock signal DCLK_a goes low and the second clock signal DCLK_b goes high. At this time, in response to the first clock signal DCLK_a going low and the second clock signal DCLK_b going high, the channel signal 2 corresponding to output channels N3-N4 is high, and output channels N3-N4 will perform the current output. At this time, the data transmission of the other output channels (e.g., output channels N1-N2, output channels N5-N10) is delayed. It can be understood that the delayed output of the m output channels can be controlled by the first clock signal DCLK_a and the second clock signal DCLK_b.
[0041] In this embodiment, in response to the rising edge of the first clock signal and the second clock signal being at a low level, the current two output channels in the m output channels perform the current output. In response to the first clock signal being at a low level and the second clock signal being at a high level, the next two output channels in the m output channels perform the next output. The delayed output of the m output channels is achieved by using the first clock signal and the second clock signal, thereby saving space and cost of the driving circuit 100 and meeting the high requirements of PPCC function for large-size panels.
[0042] In some embodiments, such as Figure 5 As shown, Figure 5This is a schematic diagram of the structure of a driving circuit according to an embodiment of this application. The driving circuit 100 further includes a delay setting module 120, which is connected to the external voltage divider circuit 300. The delay setting module 120 is used to set the output delay time based on the input voltage of the external voltage divider circuit 300.
[0043] In some examples, the delay setting module 120 can be a register in the driver circuit 100. For example, the output delay time can be determined by processing any blank register in the driver circuit 100. The delay setting module 120 is connected to the external voltage divider circuit 300. For example, the delay setting module 120 is connected to resistors R1 and R2 in the external voltage divider circuit 300. Thus, the delay setting module 120 can set the output delay time according to the input voltage of the external voltage divider circuit 300. That is, the delay setting module 120 can control the voltage level input to the delay setting module 120 through the external voltage divider resistor to control the output delay.
[0044] In some embodiments, the output delay time is related to the period of a first clock signal or a second clock signal.
[0045] For example, in response to the first clock signal DCLK_a being in the first timing state and the second clock signal DCLK_b being in the second timing state, output channels N1-N2 perform one output. In response to the first clock signal DCLK_a being in the second timing state and the second clock signal DCLK_b being in the first timing state, output channels N3-N4 perform one output. The output interval time between output channels N1-N2 and output channels N3-N4 is T1, and the output interval time between output channels N3-N4 and output channels N5-N6 is T2. Here, T1 and T2 are output delay times, which are related to the period T of the first clock signal DCLK_a or the second clock signal DCLK_b. For example, T1 = T2 = T / 2, that is, the output delay time can be half the period of the first clock signal or the second clock signal.
[0046] In some embodiments, setting the output delay time based on the input voltage of the external voltage divider circuit 300 includes: in response to the input voltage being a first value, setting the output delay time to a first preset multiple of the period of the first clock signal or the second clock signal; in response to the input voltage being a second value, setting the output delay time to a second preset multiple of the period of the first clock signal or the second clock signal; wherein, if the first value is greater than the second value, then the first preset multiple is less than the second preset multiple.
[0047] If the input voltage is a first value V1, the output delay time can be set to a first preset multiple x of the period T of the first or second clock signal. If the input voltage is a second value V2, the output delay time can be set to a second preset multiple y of the period T of the first or second clock signal. Wherein, if the first value is greater than the second value, the first preset multiple is less than the second preset multiple. For example, if V1 > V2, then x < y. That is, when the input voltage is the first value V1, the output delay time is set to x*T; when the input voltage is the second value V2, the output delay time is set to y*T, where x*T < y*T. Thus, by changing the input voltage of the external voltage divider circuit 300, the delayed output of the drive circuit 100 can be controlled.
[0048] In some examples, if the period T of the first clock signal DCLK_a or the second clock signal DCLK_b is 20ns, and the high and low level widths of the first clock signal DCLK_a and the second clock signal DCLK_b are each 10ns, then when the input voltage is 3.3V, the output delay time can be set to the width of one high level, i.e., the output delay time is 10ns; when the input voltage is 1.8V, the output delay time can be set to the width of 1.5 high levels, i.e., the output delay time is 15ns; and when the input voltage is 0.9V, the output delay time can be set to the width of two high levels, i.e., the output delay time is 20ns.
[0049] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of a panel driving system according to an embodiment of this application. The panel driving system 600 includes at least one driving circuit 100 and a timing control circuit 610. The at least one driving circuit 100 is connected to the display panel 200, and the timing control circuit 610 is connected to the at least one driving circuit 100 to generate a first clock signal and a second clock signal.
[0050] In some examples, such as Figure 6 As shown, at least one driving circuit 100 includes driving circuit 101, driving circuit 102... driving circuit 10n, wherein the timing control circuit 610 is connected to driving circuit 101, driving circuit 102... driving circuit 10n, and can generate different first clock signals and second clock signals for different driving circuits 100.
[0051] In this embodiment, the panel driving system 600 includes at least one driving circuit 100 and a timing control circuit 610. The timing control circuit 610 is connected to at least one driving circuit 100 and generates a first clock signal and a second clock signal corresponding to at least one driving circuit 100. The output delay of multiple driving circuits 100 is controlled by the first clock signal and the second clock signal, which saves space and cost while meeting the high requirements of PPCC function of large-size panels, thereby improving product yield.
[0052] In some embodiments, the timing control circuit 610 is further configured to receive output grayscale data on the display panel 200 corresponding to the corresponding driving circuit 100, and determine the target delay time corresponding to the corresponding driving circuit 100 based on the output grayscale data; at least one driving circuit 100 is further configured to adjust the output delay time of the corresponding driving circuit 100 based on the target delay time.
[0053] In some examples, such as Figure 6 As shown, at least one driving circuit 100 includes driving circuit 101, driving circuit 102...driving circuit 10n, wherein the impedances of driving circuit 101, driving circuit 102...driving circuit 10n are different, for example, R1, R2...Rn respectively. Timing control circuit 610 receives grayscale data G, which can be the actual output data of at least one driving circuit 100 on the display panel 200. Based on the output grayscale data G of driving circuit 101, driving circuit 102...driving circuit 10n, timing control circuit 610 can determine the target delay time corresponding to the respective driving circuit 100, and thus at least one driving circuit 100 can adjust its corresponding output delay time according to the determined target delay time. The target delay time corresponding to the driving circuit 100 is the interval between at least two output channels in the m output channels of the driving circuit 100 responding to the first clock signal and the second clock signal to output once.
[0054] In this embodiment, the panel driving system 600 includes at least one driving circuit 100 and a timing control circuit 610. The timing control circuit 610 is connected to at least one driving circuit 100 and generates a first clock signal and a second clock signal corresponding to at least one driving circuit 100. The timing control circuit 610 is also used to receive output grayscale data on the display panel corresponding to the corresponding driving circuit 100, and determine the target delay time corresponding to the corresponding driving circuit 100 based on the output grayscale data. Furthermore, at least one driving circuit 100 is also used to adjust the output delay time of the corresponding driving circuit 100 based on the target delay time, so as to avoid the influence of the differences between driving circuits 100 on the output delay time of the driving circuit 100.
[0055] In some embodiments, determining the target delay time corresponding to the corresponding driving circuit 100 based on the output grayscale data includes: obtaining the impedance data of the corresponding driving circuit 100 from a first preset table based on the output grayscale data; and obtaining the target delay time corresponding to the corresponding driving circuit 100 from a second preset table based on the impedance data of the corresponding driving circuit 100.
[0056] The timing control circuit 610 is used to obtain the impedance data of the corresponding driving circuit 100 from the first preset table based on the received output grayscale data, and to obtain the target delay time corresponding to the driving circuit 100 from the second preset table based on the impedance data of the corresponding driving circuit 100. The first preset table can be an impedance-grayscale data table (R / Gtable), and the second preset table can be an impedance-time data table (R / T table).
[0057] by Figure 6 Taking the driving circuit 10n as an example, the timing control circuit 610 receives the output grayscale data Gn of the driving circuit 10n, and obtains the impedance data Rn of the driving circuit 10n from the R / G table based on the output grayscale data Gn. Furthermore, based on the impedance data Rn of the driving circuit 101, the target delay time Tn corresponding to the driving circuit 101 can be obtained from the R / T table, that is, the interval Tn between at least two output channels in the m output channels of the driving circuit 10n responding to the first clock signal and the second clock signal to output once.
[0058] In some examples, at least one driving circuit 100 includes driving circuit 101, driving circuit 102... driving circuit 10n, and the impedances of each driving circuit 100 are different, for example, R1, R2... Rn respectively. The output delay time of at least one driving circuit 100 can be set to T0. After the output of at least one driving circuit 100, the brightness under the current setting is tested using an optical measuring instrument. At the same time, the actual output grayscale G corresponding to the feedback measurement point pulled back from the position of at least one driving circuit 100 is tested. Then, the output delay time of at least one driving circuit 100 is adjusted. The optical instrument is used to confirm that the actual display brightness is consistent with the preset brightness, so that impedance-grayscale data table and impedance-time data table can be obtained.
[0059] Furthermore, the impedance-grayscale data table and the impedance-time data table can be compiled into the timing control circuit 610. During in-plane architecture design, the outputs of different driving circuits 100 are pulled back to the driving circuit 100 and synchronously fed back to the timing control circuit 610. The algorithm controller in the timing control circuit 610 receives the actual output grayscale G fed back at this time, substitutes it into the impedance-grayscale data table to obtain the corresponding R of the driving circuit 100, and substitutes R into the impedance-time data table to obtain the target delay time T of the driving circuit 100. The timing control circuit 610 inputs the target delay time T to the delay setting module 120 of the driving circuit 100. The delay setting module 120 adjusts the actual output delay time of the corresponding driving circuit 100 according to the input target delay time T, thereby adjusting the actual output delay time of the PPCC of different driving circuits 100 to ensure that the output completely avoids the influence of different impedances.
[0060] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of a display device according to an embodiment of this application. The display device 700 includes a display panel 200 and a driving circuit 100 as described above, or the display device 700 includes a display panel 200 and a panel driving system 600 as described above. The display panel 200 includes a plurality of pixel columns 210, which are divided into m groups. The panel driving system 600 includes at least one driving circuit 100 and a timing control circuit 610. The driving circuit 100 includes a plurality of output channels 110, which are divided into m groups. The m groups of output channels sequentially output in response to a first clock signal and a second clock signal, and at least two groups of output channels in each of the m groups output channels output once in response to the first clock signal and the second clock signal, with any adjacent outputs separated by an output delay time.
[0061] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.
[0062] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.
[0063] In the several embodiments provided in this application, it should be understood that the disclosed methods and related devices can be implemented in other ways. For example, the related device implementations described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication disconnection shown or discussed may be indirect coupling or communication disconnection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.
[0064] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0065] Those skilled in the art will readily recognize that numerous modifications and variations can be made to the apparatus and method while maintaining the teachings of this application. Therefore, the above disclosure should be considered limited only by the scope of the appended claims.
Claims
1. A driving circuit, characterized in that, Applied to a display panel, the display panel comprising multiple columns of pixels, the multiple columns of pixels being divided into m groups, including: Multiple output channels, the multiple output channels are divided into m groups, and each group of output channels is connected to a group of pixel columns; The m output channels respond to the first clock signal and the second clock signal in sequence to output; In the m sets of output channels, at least two sets of output channels respond to the first clock signal and the second clock signal to output once, and the interval between any adjacent outputs is an output delay time. The driving circuit further includes a delay setting module connected to resistors R1 and R2 in the external voltage divider circuit, used to set the output delay time according to the input voltage of the external voltage divider circuit. The delay setting module is also used to adjust the output delay time according to the target delay time input by the timing control circuit, wherein the target delay time is determined by the timing control circuit receiving the output grayscale data on the display panel corresponding to the driving circuit and based on the output grayscale data, and the output grayscale data is the actual output data of the driving circuit on the display panel.
2. The driving circuit according to claim 1, characterized in that, The first clock signal and the second clock signal have the same period, and the timing of the first clock signal and the second clock signal are opposite but the levels are the same.
3. The driving circuit according to claim 2, characterized in that, In response to the rising edge of the first clock signal and the second clock signal being at a low level, the current two output channels in the m output channels perform the current output; In response to the first clock signal being at a low level and the second clock signal being at a high level, the next two output channels in the m output channels will perform the next output.
4. The driving circuit according to claim 1, characterized in that, The output delay time is related to the period of the first clock signal or the second clock signal.
5. The driving circuit according to claim 4, characterized in that, Setting the output delay time based on the input voltage of the external voltage divider circuit includes: In response to the input voltage being a first value, the output delay time is set to a first preset multiple of the period of the first clock signal or the second clock signal; In response to the input voltage being a second value, the output delay time is set to a second preset multiple of the period of the first clock signal or the second clock signal; Wherein, if the first value is greater than the second value, then the first preset multiple is less than the second preset multiple.
6. A panel driving system, characterized in that, include: At least one driving circuit is connected to the display panel, wherein each of the driving circuits is a driving circuit as described in any one of claims 1-5; A timing control circuit, connected to the at least one driving circuit, is used to generate the first clock signal and the second clock signal; The timing control circuit is also used to receive the output grayscale data on the display panel corresponding to the corresponding driving circuit, and determine the target delay time corresponding to the corresponding driving circuit based on the output grayscale data. The at least one driving circuit is further configured to adjust the output delay time of the corresponding driving circuit according to the target delay time.
7. The system according to claim 6, characterized in that, Determining the target delay time corresponding to the corresponding driving circuit based on the output grayscale data includes: Based on the output grayscale data, the impedance data of the corresponding driving circuit is obtained from the first preset table; Based on the impedance data of the corresponding driving circuit, the target delay time corresponding to the corresponding driving circuit is obtained from the second preset table.
8. A display device, characterized in that, It includes a display panel and a driving circuit as described in any one of claims 1-5, or it includes the display panel and a panel driving system as described in any one of claims 6-7.