Display panel and display device

Abstract

The application discloses a display panel and a display device, and relates to the technical field of display panels, and specifically discloses a display panel comprising a first driving circuit, wherein the first driving circuit comprises a multi-stage shift register; the shift register comprises a shift control module and a shift output module, which are used for controlling a first node, a second node and a shift output end, and controlling the shift output end to output a shift signal; a first control module is used for controlling a signal of a fourth node; a second control module is used for adjusting the signal of the fourth node; and a refresh output module is used for controlling a scanning output end to output a gate driving signal. In the application, the second control module is additionally arranged, so that the potential stability of the fourth node of the shift register and the output stability of the gate driving signal are improved, the output effectiveness, accuracy and stability of the shift register are ensured, and the display quality of the display panel is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the rapid development of display technology, a display screen based on multi-zone dynamic refresh technology appears. The display adopting the multi-zone dynamic refresh technology can perform different refresh rates in the dynamic picture zone and the static picture zone of the display area, or can present different refresh rates in the eye observation zone and the non-eye observation zone of the display area, so as to realize the partition display control of the display area. In this way, the refresh rate requirement and the low power consumption requirement can be considered.

[0003] However, the display screen with the partition refresh function has the problems of poor stability and the like, which affects the display effect. SUMMARY

[0004] The present application provides a display panel and a display device to solve the problem of poor stability of the display screen with the partition refresh function.

[0005] According to an aspect of the present application, a display panel is provided, comprising: a first driving circuit, the first driving circuit comprising a multi-stage shift register;

[0006] The shift register comprises:

[0007] a shift control module electrically connected to the input end, the first clock end, the second clock end, the first power supply end, the second power supply end, the first node and the second node, for controlling the signal of the first node and the signal of the second node;

[0008] a shift output module electrically connected to the first node, the second node, the first power supply end, the second power supply end and the shift output end, for controlling the shift output end to output a shift signal;

[0009] a first control module electrically connected to the first node, a third node and a fourth node, for controlling the signal of the fourth node; the third node is used for receiving a first refresh control signal provided by a first refresh signal line;

[0010] a second control module electrically connected to the third node and the fourth node, for adjusting the signal of the fourth node; the second control module is also electrically connected to the first node, and / or the first control module is electrically connected to the fourth node through the second control module;

[0011] a refresh output module electrically connected to the second node, the fourth node, a third power supply end, a fourth power supply end and a scan output end, for controlling the scan output end to output a gate driving signal.

[0012] According to another aspect of the present application, there is provided a display device comprising the display panel as described above.

[0013] In the present application, the second control module is added in the shift register, so that the potential of the fourth node is not only affected by the first control module, but also affected by the second control module. Under the joint action of the first control module and the second control module, the added second control module can stabilize the potential of the fourth node. Specifically, if the potential of the fourth node is low, the second control module controls the potential of the fourth node to remain at low; if the potential of the fourth node is high, the second control module controls the potential of the fourth node to remain at high, especially when the first node is low and the first control module is off, the added second control module can control the potential of the fourth node to remain at high, reducing the leakage current of the fourth node to the first node due to the interference of the first control module, and further avoiding the problem of gradually reducing the potential of the fourth node due to the leakage current of the fourth node and erroneously controlling the refresh output module. Based on this, the second control module is added in the present application, which can improve the potential stability of the fourth node of the shift register and the output stability of the gate drive signal, and is conducive to ensuring the output effectiveness, accuracy and stability of the shift register, and further conducive to improving the display quality of the display panel.

[0014] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0016] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present application;

[0017] Figure 2 is a schematic diagram of a first drive circuit provided by an embodiment of the present application;

[0018] Figure 3 is a schematic diagram of a shift register provided by an embodiment of the present application;

[0019] Figure 4 is a schematic diagram of another shift register provided by an embodiment of the present application;

[0020] Figure 5is a schematic diagram of another shift register provided by an embodiment of the present application;

[0021] Figure 6 is a schematic diagram of a shift output provided by an embodiment of the present application;

[0022] Figure 7 is a schematic diagram of another shift output provided by an embodiment of the present application;

[0023] Figure 8 is a schematic diagram of another shift register provided by an embodiment of the present application;

[0024] Figure 9 is Figure 8 a low-frequency working timing diagram of the shift register in the first display partition shown in FIG. 8;

[0025] Figure 10 is Figure 8 a high-frequency working timing diagram of the shift register in the second display partition shown in FIG. 8;

[0026] Figure 11 is a schematic diagram of another shift register provided by an embodiment of the present application;

[0027] Figure 12 is a schematic diagram of another shift register provided by an embodiment of the present application;

[0028] Figure 13 is a schematic diagram of another shift register provided by an embodiment of the present application;

[0029] Figure 14 is a schematic diagram of another shift register provided by an embodiment of the present application;

[0030] Figure 15 is a schematic diagram of another shift register provided by an embodiment of the present application;

[0031] Figure 16 is a schematic diagram of another shift register provided by an embodiment of the present application;

[0032] Figure 17 is a schematic diagram of another shift register provided by an embodiment of the present application;

[0033] Figure 18 is a schematic diagram of another shift register provided by an embodiment of the present application;

[0034] Figure 19 is a schematic diagram of another shift register provided by an embodiment of the present application;

[0035] Figure 20 is a schematic diagram of another shift register provided by an embodiment of the present application;

[0036] Figure 21 is a schematic diagram of another shift register provided by an embodiment of the present application;

[0037] Figure 22 is a low-frequency operation timing diagram of the shift register in the first display partition shown in Figure 21

[0038] Figure 23 is a high-frequency operation timing diagram of the shift register in the second display partition shown in Figure 21

[0039] Figure 24 is a structural schematic diagram of a display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should fall within the scope of protection of the present application.

[0041] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to only those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to the process, method, product, or device.

[0042] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present application, Figure 2 is a schematic diagram of a first driving circuit provided by an embodiment of the present application, Figure 3 is a schematic diagram of a shift register provided by an embodiment of the present application, Figure 4 is a schematic diagram of another shift register provided by an embodiment of the present application, Figure 5 is a schematic diagram of another shift register provided by an embodiment of the present application. Reference is made to Figures 1 to 5 ​​As shown, the display panel 10 comprises a first driving circuit 11, the first driving circuit 11 comprising a multi-stage shift register 12; the shift register 12 comprises a shift control module 110, electrically connected with an input end IN, a first clock end CK, a second clock end XCK, a first power supply end VG1, a second power supply end VG2, a first node N1 and a second node N2, for controlling signals of the first node N1 and the second node N2; a shift output module 120, electrically connected with the first node N1, the second node N2, the first power supply end VG1, the second power supply end VG2 and a shift output end NEXT, for controlling the shift output end NEXT to output a shift signal; a first control module 130, electrically connected with the first node N1, a third node N3 and a fourth node N4, for controlling a signal of the fourth node N4; the third node N3 is used for receiving a first refresh control signal Ctrl1 provided by a first refresh signal line SCL1; a second control module 140, electrically connected with the third node N3 and the fourth node N4, for adjusting the signal of the fourth node N4; the second control module 140 is further electrically connected with the first node N1, and / or the first control module 130 is electrically connected with the fourth node N4 through the second control module 140; a refresh output module 150, electrically connected with the second node N2, the fourth node N4, a third power supply end VG3, a fourth power supply end VG4 and a scan output end OUT, for controlling the scan output end OUT to output a gate driving signal Gout.

[0043] As shown in Figure 3 , the optional second control module 140 is further electrically connected with the first node N1, and the first control module 130 is electrically connected with the fourth node N4 through the second control module 140. As shown in Figure 4 , the optional second control module 140 is further electrically connected with the first node N1, and the first control module 130 is directly electrically connected with the fourth node N4. As shown in Figure 5 , the optional first control module 130 is electrically connected with the fourth node N4 through the second control module 140.

[0044] In this embodiment, the shift control module 110 is electrically connected with the input terminal IN, the first clock terminal CK, the second clock terminal XCK, the first power supply terminal VG1, the second power supply terminal VG2, the first node N1 and the second node N2. Specifically, the input terminal IN provides an input signal, the first clock terminal CK provides a first clock signal, the second clock terminal XCK provides a second clock signal, the first power supply terminal VG1 provides a first power supply signal, and the second power supply terminal VG2 provides a second power supply signal. The first clock signal is different from the second clock signal. Optionally, the frequency of the first clock signal is the same as that of the second clock signal, and the phase of the first clock signal is different from that of the second clock signal. The first power supply signal is different from the second power supply signal. One of the first power supply signal and the second power supply signal is at a low level, and the other is at a high level. The shift control module 110 controls the signal of the first node N1 and the signal of the second node N2 according to the input signal, the first clock signal, the second clock signal, the first power supply signal and the second power supply signal.

[0045] The shift output module 120 controls the shift output terminal NEXT to output a shift signal according to the signal of the first node N1, the signal of the second node N2, the first power supply signal and the second power supply signal. The shift signal includes a valid level and an invalid level.

[0046] The first control module 130 controls the signal of the fourth node N4 according to the signal of the first node N1 and the signal of the third node N3. The first refresh control signal Ctrl1 provided by the first refresh signal line SCL1 can be directly transmitted to the third node N3, that is, the signal of the third node N3 is the first refresh control signal Ctrl1 provided by the first refresh signal line SCL1. In other embodiments, a switch structure can be arranged between the first refresh signal line SCL1 and the third node N3. When the switch structure is turned on, the first refresh control signal Ctrl1 provided by the first refresh signal line SCL1 is transmitted to the third node N3.

[0047] Reference is made to FIG. 1. Figure 3 As shown in FIG. 1, the second control module 140 controls the signal of the fourth node N4 according to the signal of the third node N3, the signal of the first node N1 and the signal of the first control module 130.

[0048] Reference is made to FIG. 1. Figure 4 As shown in FIG. 1, the second control module 140 controls the signal of the fourth node N4 according to the signal of the third node N3 and the signal of the first node N1. The signal of the fourth node N4 is jointly affected by the first control module 130 and the second control module 140.

[0049] Reference is made to FIG. 1. Figure 5As shown, the second control module 140 controls the signal of the fourth node N4 according to the signal of the third node N3 and the signal of the first control module 130. The signal of the fourth node N4 is jointly affected by the first control module 130 and the second control module 140.

[0050] The refresh output module 150 controls the scan output terminal OUT to output the gate driving signal Gout according to the signal of the second node N2, the signal of the fourth node N4, the third power signal provided by the third power terminal VG3 and the fourth power signal provided by the fourth power terminal VG4. The gate driving signal Gout includes an effective level and an ineffective level. The third power signal is different from the fourth power signal, and one of the third power signal and the fourth power signal is low and the other is high.

[0051] If the second control module 140 is not added in the shift register 12, the fourth node N4 is directly electrically connected with the first control module 130, and the signal of the fourth node N4 is directly affected by the first control module 130. When the fourth node N4 is high and the first node N1 is low, if the first control module 130 is off, the high level of the fourth node N4 is easy to be interfered by the first control module 130 and to cause a leakage current to the first node N1, and accordingly, the potential of the fourth node N4 is gradually reduced due to the leakage current, which may cause the output of the shift register 12 to be invalid.

[0052] In the present application, by adding the second control module 140 in the shift register 12, the potential of the fourth node N4 is not only affected by the first control module 130, but also affected by the second control module 140. Under the joint action of the first control module 130 and the second control module 140, the added second control module 140 can stabilize the potential of the fourth node N4. Specifically, if the potential of the fourth node N4 is low, the second control module 140 controls the potential of the fourth node N4 to remain low; if the potential of the fourth node N4 is high, the second control module 140 controls the potential of the fourth node N4 to remain high, especially when the first node N1 is low and the first control module 130 is off, the added second control module 140 can control the potential of the fourth node N4 to remain high, reduce the leakage current of the high level of the fourth node N4 to the first node N1 due to the interference of the first control module 130, and further avoid the problem that the potential is gradually reduced due to the leakage current of the fourth node N4 and the refresh output module 150 is controlled incorrectly. Based on this, by adding the second control module 140 in the present application, the potential stability of the fourth node N4 of the shift register 12 and the output stability of the gate driving signal Gout can be improved, which is conducive to ensuring the output effectiveness, accuracy and stability of the shift register 12, and further conducive to improving the display quality of the display panel.

[0053] The above is the core idea of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application. The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the accompanying drawings of the embodiments of the present application.

[0054] Optionally, as shown in Figures 1 to 2 For example, the first refresh signal line SCL1 provides the first refresh control signal Ctrl1 to the shift register 12; the first clock signal line CKL1 and the second clock signal line CKL2 provide the first clock signal to the first clock terminal CK of the shift register 12 and the second clock signal to the second clock terminal XCK of the shift register 12, respectively; the first power signal line VL1 provides the first power signal to the first power terminal VG1 of the shift register 12; the second power signal line VL2 provides the second power signal to the second power terminal VG2 of the shift register 12; the third power signal line VL3 provides the third power signal to the third power terminal VG3 of the shift register 12; the fourth power signal line VL4 provides the fourth power signal to the fourth power terminal VG4 of the shift register 12; the input signal line STV provides the input signal to the input terminal IN of the at least one stage of shift register 12; and the display panel 10 can further include a plurality of other types of signal lines 15, which are not described herein again.

[0055] It can be understood that, as shown in Figure 1 As shown in

[0056] As shown in Figures 3 to 5As shown in the figure, in the display panel 10, the shift register 12 includes a shift control module 110 and a shift output module 120, the shift control module 110 and the shift output module 120 constitute a shift output part 13 of the shift register 12, the shift output part 13 includes an input end IN and a shift output end NEXT, the shift output part 13 is used for controlling the shift output end NEXT to output a shift signal, the shift signal includes a valid level and an invalid level. The shift register 12 further includes a first control module 130, a second control module 140 and a refresh output module 150, the first control module 130, the second control module 140 and the refresh output module 150 constitute a scan output part 14, the scan output part 14 includes a scan output end OUT, the scan output part 14 is further electrically connected with a first refresh signal line SCL1, the scan output part 14 controls the scan output end OUT to output a gate drive signal Gout in response to a first refresh control signal Ctrl1 provided by the first refresh signal line SCL1, the gate drive signal Gout includes a valid level and an invalid level.

[0057] Reference Figure 2 As shown in the figure, the shift output end NEXT of the optional i-th shift register 12 is electrically connected with the input end IN of the (i+m)-th shift register 12, where m=1, then the shift signal output by the shift output part 13 of the i-th shift register 12 is transmitted to the input end IN of the (i+1)-th shift register 12. In other embodiments, the shift output end NEXT of the optional i-th shift register 12 is also electrically connected with the input end IN of the (i+m)-th shift register 12, where m can be an integer greater than 1, for example, m=2, or m=3, or m=4, or m is equal to other positive integers, not limited to Figure 2 As shown in the figure, m=1.

[0058] In the display panel 10, the shift output part 13 of the shift register 12 has diversity in the setting. Exemplarily, the shift output part 13 can be “13T2C”, or can be “13T3C”, or can be “15T3C”, or can be “16T3C”, etc., where “T” represents a transistor and “C” represents a storage capacitor. The setting of the shift output part 13 is not limited to this. In the following multiple embodiments, the shift output part 13 is exemplarily taken as “16T3C” to illustrate the electrical connection relationship and working process of the shift register 12, and relevant practitioners can adaptively adjust the shift output part 13 according to the needs, not limited to “16T3C”.

[0059] Figure 6 is a schematic diagram of a shift output part provided by an embodiment of the present application, as Figure 6As shown, in the optional shift output unit 13, the shift control module 110 includes: a first shift submodule 111 electrically connected to the input end IN, the first clock end CK and the fifth node N5, configured to control the signal of the fifth node N5; a second shift submodule 112 electrically connected to the fifth node N5, the first clock end CK, the second clock end XCK, the first power supply end VG1, the second power supply end VG2 and the first node N1, configured to control the signal of the first node N1; and a third shift submodule 113 electrically connected to the fifth node N5, the second clock end XCK, the first power supply end VG1, the second power supply end VG2 and the second node N2, configured to control the signal of the second node N2.

[0060] In this embodiment, the first shift submodule 111 is electrically connected to the input end IN, the first clock end CK and the fifth node N5, and is configured to control the signal of the fifth node N5. Specifically, the input end IN of the first shift submodule 111 of the i-th shift register 12 is electrically connected to the shift output end NEXT of the (i-m)-th shift register 12, and m is an integer greater than or equal to 1. The input end IN of the first shift submodule 111 receives an input signal, and the first clock end CK of the first shift submodule 111 receives a first clock signal. The first shift submodule 111 controls the signal of the fifth node N5 in response to the input signal and the first clock signal, so that the potential of the fifth node N5 jumps between high and low levels.

[0061] The second shift submodule 112 is electrically connected to the fifth node N5, the first clock end CK, the second clock end XCK, the first power supply end VG1, the second power supply end VG2 and the first node N1. The first clock end CK of the second shift submodule 112 receives a first clock signal, the second clock end XCK of the second shift submodule 112 receives a second clock signal, and the first clock signal of the first clock end CK is different from the second clock signal of the second clock end XCK. Optionally, the frequencies of the first clock signal and the second clock signal are the same and the phases are different, but are not limited thereto. The first power supply end VG1 of the second shift submodule 112 receives a first power supply signal, the second power supply end VG2 of the second shift submodule 112 receives a second power supply signal, and the first power supply signal of the first power supply end VG1 is different from the second power supply signal of the second power supply end VG2. Optionally, one of the first power supply signal and the second power supply signal is low and the other is high. The second shift submodule 112 controls the signal of the first node N1 in response to the signal of the fifth node N5, the first clock signal, the second clock signal, the first power supply signal and the second power supply signal, so that the potential of the first node N1 jumps between high and low levels.

[0062] The third shift submodule 113 is electrically connected with the fifth node N5, the second clock terminal XCK, the first power terminal VG1, the second power terminal VG2 and the second node N2. The third shift submodule 113 controls the signal of the second node N2 in response to the signal of the fifth node N5, the second clock signal, the first power signal and the second power signal, so that the potential of the second node N2 jumps between high level and low level.

[0063] Figure 7 is another schematic diagram of the shift output unit provided by the embodiment of the present application, as shown in Figure 7 Figure 7 The shift output unit 13 is "16T3C" in the optional embodiment.

[0064] The optional first shift submodule 111 includes a transistor Ma4 and a transistor Ma13. The gate of the transistor Ma4 is electrically connected with the first clock terminal CK, the first end of the transistor Ma4 is electrically connected with the input terminal IN, and the second end of the transistor Ma4 is electrically connected with the fifth node N5. The gate of the transistor Ma13 is electrically connected with the first clock terminal CK, the first end of the transistor Ma13 is electrically connected with the input terminal IN, and the second end of the transistor Ma13 is electrically connected with the node N5a. The first clock signal provided by the first clock terminal CK controls the transistor Ma4 and the transistor Ma13 to be opened or closed at the same time, and when the transistor Ma4 and the transistor Ma13 are opened at the same time, the input signal provided by the input terminal IN is written into the fifth node N5 and the node N5a. It can be understood that the signal of the node N5a is the same as the signal of the fifth node N5. In other embodiments, the optional first shift submodule also includes one of the transistor Ma4 and the transistor Ma13.

[0065] ​The optional second shift sub-module 112 includes a transistor Ma1, a transistor Ma2, a transistor Ma3, a transistor Ma5, a transistor Ma6, a transistor Ma7, a transistor Ma8 and a capacitor Ca2. The gate of the transistor Ma1 is electrically connected with a reset signal terminal RST, the first end of the transistor Ma1 is electrically connected with a second power supply terminal VG2, and the second end of the transistor Ma1 is electrically connected with a fifth node N5. The gate of the transistor Ma2 is electrically connected with the fifth node N5, the first end of the transistor Ma2 is electrically connected with a first clock terminal CK, and the second end of the transistor Ma2 is electrically connected with a node N6a. The gate of the transistor Ma3 is electrically connected with a node N6b, the first end of the transistor Ma3 is electrically connected with a second clock terminal XCK, and the second end of the transistor Ma3 is electrically connected with a node N6c. The gate of the transistor Ma5 is electrically connected with the first clock terminal CK, the first end of the transistor Ma5 is electrically connected with a first power supply terminal VG1, and the second end of the transistor Ma5 is electrically connected with the node N6a. The gate of the transistor Ma6 is electrically connected with the fifth node N5, the first end of the transistor Ma6 is electrically connected with the second power supply terminal VG2, and the second end of the transistor Ma6 is electrically connected with a first node N1. The gate of the transistor Ma7 is electrically connected with the second clock terminal XCK, the first end of the transistor Ma7 is electrically connected with the node N6c, and the second end of the transistor Ma7 is electrically connected with the first node N1. The gate of the transistor Ma8 is electrically connected with the first power supply terminal VG1, the first end of the transistor Ma8 is electrically connected with the node N6a, and the second end of the transistor Ma8 is electrically connected with the node N6b. The first plate of the capacitor Ca2 is electrically connected with the node N6b, and the second plate of the capacitor Ca2 is electrically connected with the node N6c. In other embodiments, the types or quantities of transistors in the optional second shift sub-module can be adjusted adaptively, the connection relationship between each transistor and the signal terminal changes, and the structure of the second shift sub-module is not limited to Figure 7 as shown.

[0066] The optional third shift sub-module 113 includes transistors Ma11, Ma12, Ma14, Ma15, Ma16 and a capacitor Ca3. The gate of the transistor Ma11 is electrically connected to the node N2b, the first end of the transistor Ma11 is electrically connected to the second clock end XCK, and the second end of the transistor Ma11 is electrically connected to the node N2a. The gate of the transistor Ma12 is electrically connected to the node N6a, the first end of the transistor Ma12 is electrically connected to the second power supply end VG2, and the second end of the transistor Ma12 is electrically connected to the node N2a. The gate of the transistor Ma14 is electrically connected to the node N2b, the first end of the transistor Ma14 is electrically connected to the node N2b, and the second end of the transistor Ma14 is electrically connected to the second node N2. The gate of the transistor Ma15 is electrically connected to the first power supply end VG1, the first end of the transistor Ma15 is electrically connected to the fifth node N5, and the second end of the transistor Ma15 is electrically connected to the second node N2. The gate of the transistor Ma16 is electrically connected to the first power supply end VG1, the first end of the transistor Ma16 is electrically connected to the fifth node N5 or the node N5a, and the second end of the transistor Ma16 is electrically connected to the node N2b. The first plate of the capacitor Ca3 is electrically connected to the node N2a, and the second plate of the capacitor Ca3 is electrically connected to the node N2b. In other embodiments, the types or number of transistors in the optional third shift sub-module can be adaptively adjusted, the connection relationship between the respective transistors and the signal ends changes, and the structure of the third shift sub-module is not limited to Figure 7 as shown.

[0067] The shift output module 120 of the optional shift output unit 13 includes a transistor Ma9, a transistor Ma10 and a capacitor Ca1. The gate of the transistor Ma9 is electrically connected to the first node N1, the first end of the transistor Ma9 is electrically connected to the second power supply end VG2, and the second end of the transistor Ma9 is electrically connected to the shift output end NEXT. The gate of the transistor Ma10 is electrically connected to the second node N2, the first end of the transistor Ma10 is electrically connected to the first power supply end VG1, and the second end of the transistor Ma10 is electrically connected to the shift output end NEXT. The first plate of the capacitor Ca1 is electrically connected to the first node N1, and the second plate of the capacitor Ca1 is electrically connected to the second power supply end VG2.

[0068] Figure 7 In the optional shift output unit 13, the transistors Ma1 to Ma16 are all P-type transistors; and the first power supply end VG1 is low (marked as vgl1) and the second power supply end VG2 is high (marked as vgh1). In other embodiments, at least one transistor in the shift output unit is an N-type transistor; and the types or number of transistors in the shift output unit can be adaptively adjusted, the connection relationship between the respective transistors and the signal ends changes, and the structure of the shift output unit is not limited to Figure 7 as shown.

[0069] The shift control module 110 controls the signal of the first node N1 and the signal of the second node N2 in response to the input signal, the first clock signal, the second clock signal, the first power signal vgl1 and the second power signal vgh1, so that the signal of the first node N1 and the signal of the second node N2 jump between high and low levels. The shift output module 120 controls one of the first power signal vgl1 and the second power signal vgh1 to be transmitted to the shift output end NEXT in response to the signal of the first node N1, the signal of the second node N2, the first power signal vgl1 and the second power signal vgh1. Taking the active level of the shift signal as the high level vgh1 as an example.

[0070] If the shift control module 110 controls the signal of the first node N1 to be the low level, the transistor Ma9 in the shift output module 120 is turned on, and the second power signal vgh1 provided by the second power end VG2 is transmitted to the shift output end NEXT, and the shift signal output by the shift output end NEXT is the active level.

[0071] If the shift control module 110 controls the signal of the first node N1 to be the high level, the transistor Ma9 in the shift output module 120 is turned off, and the first power signal vgl1 provided by the first power end VG1 can be transmitted to the shift output end NEXT through the turned-on transistor Ma10, and the shift signal output by the shift output end NEXT is the inactive level.

[0072] Figure 8 FIG. 6 is a schematic diagram of another shift register provided by an embodiment of the present application, which is similar to FIG. 5, and reference can be made to the description of FIG. 5. Figure 4 and Figure 8 The optional first control module 130 includes: a first transistor Mb1; the gate of the first transistor Mb1 is electrically connected to the third node N3, the first end of the first transistor Mb1 is electrically connected to the first node N1, and the second end of the first transistor Mb1 is electrically connected to the fourth node N4. The optional second control module 140a includes: a second transistor Mb2; the gate of the second transistor Mb2 is electrically connected to the first node N1, the first end of the second transistor Mb2 is electrically connected to the third node N3, and the second end of the second transistor Mb2 is electrically connected to the fourth node N4. In the embodiment, the second end of the optional first transistor Mb1 is directly electrically connected to the fourth node N4.

[0073] The optional refresh output module 150 comprises: a first output submodule 151 electrically connected with the fourth node N4, the fourth power terminal VG4 and the scan output terminal OUT, configured to control the scan output terminal OUT to output the gate drive signal Gout; and a second output submodule 152 electrically connected with the second node N2, the third power terminal VG3 and the scan output terminal OUT, configured to control the scan output terminal OUT to output the gate drive signal Gout. The optional first output submodule 151 comprises: a sixth transistor Mb6; the gate of the sixth transistor Mb6 is electrically connected with the fourth node N4, the first end of the sixth transistor Mb6 is electrically connected with the fourth power terminal VG4, and the second end of the sixth transistor Mb6 is electrically connected with the scan output terminal OUT. The optional second output submodule 152 comprises: a seventh transistor Mb7; the gate of the seventh transistor Mb7 is electrically connected with the second node N2, the first end of the seventh transistor Mb7 is electrically connected with the third power terminal VG3, and the second end of the seventh transistor Mb7 is electrically connected with the scan output terminal OUT.

[0074] The optional shift register 12 further comprises: a fourth control module 160; the fourth control module 160 is electrically connected with the second control terminal B; the first refresh signal line SCL1 provides the first refresh control signal Ctrl1 to the third node N3 through the fourth control module 160; and the second control terminal B is one of the fifth node N5, the second node N2 and the shift output terminal NEXT. The optional fourth control module 160 comprises: a fifth transistor Mb5; the gate of the fifth transistor Mb5 is electrically connected with the second control terminal B, the first end of the fifth transistor Mb5 is electrically connected with the first refresh signal line SCL1, and the second end of the fifth transistor Mb5 is electrically connected with the third node N3.

[0075] In other embodiments, the fifth transistor Mb5 can also be a double-gate transistor. Designing the fifth transistor Mb5 as a double-gate transistor can reduce the leakage current of the third node N3. Specifically, when the fifth transistor Mb5 is off and the third node N3 is at a high level, designing the fifth transistor Mb5 as a double-gate transistor can stabilize the potential of the third node N3 at a high level near the time node when the first refresh signal line SCL1 jumps from a high level to a low level, reducing the leakage current from the high-level third node N3 to the low-level first refresh signal line SCL1, and improving the working stability of the shift register 12.

[0076] In this embodiment, the signal from the third node N3 controls the first transistor Mb1 to turn on or off. When the signal from the third node N3 controls the first transistor Mb1 to turn on, the signal from the first node N1 is transmitted to the fourth node N4 through the turned-on first transistor Mb1. The signal from the first node N1 controls the second transistor Mb2 to turn on or off. When the signal from the first node N1 controls the second transistor Mb2 to turn on, the signal from the third node N3 is transmitted to the fourth node N4 through the turned-on second transistor Mb2. It can be seen that the signal from the fourth node N4 is jointly controlled by the first control module 130 and the second control module 140a, and the signal from the fourth node N4 undergoes high-low level transitions.

[0077] The signal from the fourth node N4 controls the sixth transistor Mb6 to turn on or off. When the signal from the fourth node N4 controls the sixth transistor Mb6 to turn on, the fourth power supply signal provided by the fourth power supply terminal VG4 is transmitted to the scan output terminal OUT. The signal from the second node N2 controls the seventh transistor Mb7 to turn on or off. When the signal from the second node N2 controls the seventh transistor Mb7 to turn on, the third power supply signal provided by the third power supply terminal VG3 is transmitted to the scan output terminal OUT. If the fourth power supply signal is high (vgh2) and the third power supply signal is low (vgl2), then when the sixth transistor Mb6 is turned on, the gate drive signal Gout output by the shift register 12 is high (vgh2), and when the seventh transistor Mb7 is turned on, the gate drive signal Gout output by the shift register 12 is low (vgl2).

[0078] The signal at the second control terminal B controls the fifth transistor Mb5 to turn on or off. When the signal at the second control terminal B turns the fifth transistor Mb5 on, the first refresh signal line SCL1 provides the first refresh control signal Ctrl1 to the third node N3 through the fifth transistor Mb5. The second control terminal B is one of the fifth node N5, the second node N2, and the shift output terminal NEXT. (Reference) Figure 8 As shown, the signal of node N5a is the same as the signal of the fifth node N5, and the signal of node N2b is the same as the signal of the second node N2. Further, in the same shift register 12, the second control terminal B can be the fifth node N5, or node N5a, or the second node N2, or node N2b, or the shift output terminal NEXT. In other embodiments, the shift register 12 may not include the fourth control module 160; in this case, the first refresh signal line SCL1 is directly electrically connected to the third node N3, and the signal of the third node N3 is the first refresh control signal Ctrl1.

[0079] In this embodiment, the first transistor Mb1, the second transistor Mb2, the fifth transistor Mb5, the sixth transistor Mb6 and the seventh transistor Mb7 are all PMOS. However, they are not limited thereto, and under the premise of ensuring the normal operation of the shift register 12, the working types of the transistors in the shift register 12 can be reasonably selected to be PMOS or NMOS. Correspondingly, the third power supply signal received by the third power supply end VG3 is low (labeled as vgl2), and the fourth power supply signal received by the fourth power supply end VG4 is high (labeled as vgh2). The effective level of the gate drive signal Gout provided by the scan output end OUT is high vgh2, and the ineffective level of the gate drive signal Gout is low vgl2. The effective level of the shift signal provided by the shift output end NEXT is high vgh1, and the ineffective level of the shift signal is low vgl1. In this embodiment, the working principle of the shift register 12 is illustrated by taking the second control end B in the shift register 12 being electrically connected to the shift output end NEXT as an example.

[0080] The level signal provided by the first power supply end VG1 is different from the level signal provided by the third power supply end VG3. The level signal provided by the first power supply end VG1 is less than or equal to the level signal provided by the third power supply end VG3. Referring to Figure 8 As shown in the figure, the first power supply signal provided by the first power supply end VG1 is low vgl1, and the third power supply signal provided by the third power supply end VG3 is low vgl2. The first power supply signal vgl1 and the third power supply signal vgl2 can be different. Specifically, the first power supply signal vgl1 is less than or equal to the third power supply signal vgl2. Then, if the second node N2 leaks, the first power supply signal vgl1 is less than the third power supply signal vgl2, which can ensure that the transistor Ma10 and the seventh transistor Mb7 can normally turn on and off, avoiding the case that the second node N2 leaks and mistakenly controls the transistor Ma10 and the seventh transistor Mb7. The normal and stable operation of the shift register 12 is ensured.

[0081] The display panel has a multi-frequency refresh mode. In the multi-frequency refresh mode, the display area of the display panel includes at least a first display sub-area and a second display sub-area. The refresh frequency of the first display sub-area is a first refresh frequency, and the refresh frequency of the second display sub-area is a second refresh frequency. The first refresh frequency is less than the second refresh frequency.

[0082] Optionally, in the multi-frequency refresh mode, the frequency of the shift signal of the shift register in the first display area is greater than the frequency of the gate driving signal; in the multi-frequency refresh mode, the frequency of the gate driving signal of the shift register in the first display area is less than the frequency of the gate driving signal of the shift register in the second display area. Therefore, the first display area works at a low frequency, and the second display area works at a high frequency. Optionally, in the multi-frequency refresh mode, the frequency of the shift signal of the shift register in the second display area can be equal to the frequency of the gate driving signal, but is not limited thereto.

[0083] For example, in the multi-frequency refresh mode, the first refresh frequency of the first display area is 30 Hz, and the second refresh frequency of the second display area is 120 Hz. Taking the refresh frequency of the display panel as 120 Hz as an example. Then, in the multi-frequency refresh mode, in the first display area, the frequency of the shift signal of the shift register is 120 Hz and the frequency of the gate driving signal is 30 Hz; in the second display area, the frequency of the shift signal of the shift register is 120 Hz and the frequency of the gate driving signal is 120 Hz.

[0084] For example, in the multi-frequency refresh mode, the first refresh frequency of the first display area is 30 Hz, and the second refresh frequency of the second display area is 60 Hz. Taking the refresh frequency of the display panel as 120 Hz as an example. Then, in the multi-frequency refresh mode, in the first display area, the frequency of the shift signal of the shift register is 120 Hz and the frequency of the gate driving signal is 30 Hz; in the second display area, the frequency of the shift signal of the shift register is 120 Hz and the frequency of the gate driving signal is 60 Hz.

[0085] Optionally, the working process of the shift register 12 includes a data writing stage and a data holding stage; in the data writing stage, the first refresh control signal Ctrl1 provided by the first refresh signal line SCL1 to the shift register 12 is at an effective level; in the data holding stage, the first refresh control signal Ctrl1 provided by the first refresh signal line SCL1 to the shift register 12 is at an invalid level.

[0086] It can be understood that one data holding stage is arranged between two adjacent data writing stages of the shift register 12. In the multi-frequency refresh mode, the first refresh frequency of the first display area is less than the second refresh frequency of the second display area, so that, in one frame of picture, the data holding stage duration of the shift register 12 in the first display area is greater than the data holding stage duration of the shift register 12 in the second display area.

[0087] In the embodiment, by adding the second control module 140a, the potential of the fourth node N4 can be stabilized, the output of any shift register 12 in the first display area working at low frequency can be effectively stabilized, and the output of any shift register 12 in the second display area working at high frequency can also be effectively stabilized. Whether working at low frequency or high frequency, the shift register 12 will not have the problem of output failure or poor stability caused by the leakage of the fourth node N4 to other nodes and the decrease of the potential.

[0088] In the embodiment, the working principle of the shift register 12 is illustrated by taking the active level of the first refresh control signal Ctrl1 as the low level vgl and the inactive level of the first refresh control signal Ctrl1 as the high level vgh.

[0089] Figure 9 is Figure 8 the low-frequency working timing diagram of the shift register 12 in the first display area. Referring to Figure 8 and Figure 9 , in the first display area, the shift signal frequency of the shift register 12 is greater than the gate drive signal frequency, so when the shift signal of the shift register 12 is at the active level, the gate drive signal of the shift register 12 is at the inactive level, thereby realizing low-frequency working. Based on this, for the working condition of the shift register 12 in the first display area shown in Figure 9 , in the t11 to t13 stages, the first refresh control signal Ctrl1 is at the high level vgh, i.e., the inactive level, so that the shift register 12 meets the condition that the shift signal is at the active level and the gate drive signal is at the inactive level.

[0090] Figure 10 is Figure 8 the high-frequency working timing diagram of the shift register 12 in the second display area. Referring to Figure 8 and Figure 10 , in the optional second display area, the shift signal frequency of the shift register 12 is equal to the gate drive signal frequency, so when the shift signal of the shift register 12 is at the active level, the gate drive signal of the shift register 12 is at the active level, thereby realizing high-frequency working. Based on this, for the working condition of the shift register 12 in the second display area shown in Figure 10 , in the t21 to t23 stages, the first refresh control signal Ctrl1 is at the low level vgl, i.e., the active level, so that the shift register 12 meets the condition that the shift signal is at the active level and the gate drive signal is at the active level.

[0091] In other embodiments, the shift register includes a data writing stage and a data holding stage, the t11 to t13 stages can also be regarded as the data holding stage of the shift register independently, and the t21 to t23 stages can also be regarded as the data writing stage of the shift register independently.

[0092] Reference Figure 8 and Figure 9 As shown in the figure, the low-frequency operation process of the shift register 12 includes:

[0093] In the t11 stage, the first clock signal provided by the first clock end CK jumps from low level to high level, and the corresponding transistors Ma4 and Ma13 are synchronously turned on and then turned off. If the input signal provided by the input end IN is high level, the fifth node N5 and the node N5a are both high level, and the transistors Ma2 and Ma6 are both turned off. The transistors Ma15 and Ma16 are turned on, and the second node N2 and the node N2b are both high level, and the transistor Ma10 is turned off. The low level vgl1 is sequentially transmitted to the node N6a and the node N6b through the transistors Ma5 and Ma8, and the transistor Ma3 is turned on. The second clock signal provided by the second clock end XCK is high level, which makes the transistor Ma7 turned off, and the first node N1 keeps the high level of the previous stage, and the transistor Ma9 is turned off. The shift signal of the shift output end NEXT keeps the low level vgl1 of the previous stage, i.e. the invalid level. The transistor Mb5 is turned on, the high level vgh of the first refresh control signal Ctrl1 is transmitted to the third node N3, and the third node N3 is high level vgh. The transistor Mb1 is turned off and the transistor Mb2 is turned off. Under the coupling of the high level of the third node N3, the fourth node N4 can be stabilized to the high level vgh of the previous stage, so that the transistor Mb6 is turned off. The transistor Mb7 is turned off, and the gate drive signal Gout of the scan output end OUT keeps low level vgl2.

[0094] In the t12 to t13 stage, which is also the stage of outputting the valid level of the shift signal of the shift register 12, the fifth node N5 and the node N5a are both kept at high level, the second node N2 and the node N2b are both at high level, and the transistor Ma10 is turned off; the node N6a and the node N6b are at low level vgl1, so that the transistor Ma3 is turned on; when the second clock signal provided by the second clock end XCK is at low level, the transistor Ma7 is turned on, and the low level of the second clock signal is transmitted to the node N6c and the first node N1, so that the first node N1 is at low level; when the second clock signal provided by the second clock end XCK is at high level, the transistor Ma7 is turned off, so that the first node N1 is kept at low level; the transistor Ma9 is turned on, and the second power signal vgh1 provided by the second power supply end VG2 is transmitted to the shift output end NEXT, so that the shift signal is at high level vgh1, i.e. valid level; the transistor Mb5 is turned off, the third node N3 is kept at high level vgh of the previous stage, and the transistor Mb1 is turned off; the first node N1 is at low level, so that the transistor Mb2 is turned on; under the action of the third node N3, the fourth node N4 can be stabilized at high level vgh, so that the leakage current of the fourth node N4 to the first node N1 can be reduced, the problem that the potential of the fourth node N4 gradually decreases due to the leakage current of the fourth node N4 to the first node N1 is solved, and the transistor Mb6 is turned off; the transistor Mb7 is turned off, and the gate drive signal Gout of the scan output end OUT is kept at low level vgl2, i.e. invalid level. It can be seen that in this stage, the shift signal is at valid level and the gate drive signal Gout is at invalid level.

[0095] After the t13 stage, the fifth node N5 and the node N5a are at low level, and the second node N2 and the node N2b are both at low level correspondingly, so that the transistor Ma10 is turned on, and the shift signal of the shift output end NEXT is at low level vgl1; the transistor Ma6 is turned on, so that the first node N1 is at high level vgh1, and the transistor Ma9 is turned off; the transistor Mb5 is turned on; if the signal Ctrl1 of the first refresh signal line SCL1 jumps from high level to low level, the third node N3 jumps from high level to low level, so that the on-off state of the transistor Mb1 is switched, and the high level of the first node N1 is written into the fourth node N4 when the transistor Mb1 is turned on, so that the signal of the fourth node N4 is at high level, and the transistor Mb6 is turned off; or, if the signal Ctrl1 of the first refresh signal line SCL1 is kept at high level, the third node N3 is at high level, so that the transistor Mb1 is turned off, the transistor Mb2 is turned off, and the fourth node N4 can be stabilized at high level vgh under the coupling of the third node N3, so that the transistor Mb6 is turned off; the transistor Mb7 is turned on, and the gate drive signal Gout of the scan output end OUT is at low level vgl2.

[0096] As described above, when the shift register 12 works in the low frequency mode, the high level signal provided by the first refresh signal line SCL1 can keep the third node N3 as high level vgh, especially for the stage t12 to t13, the first node N1 is low level, the transistor Mb1 is off, then the high level of the third node N3 can write high level to the fourth node N4 through the newly added second control module 140a, keep the high level of the fourth node N4, control the transistor Mb6 to be off, prevent the problem that the transistor Mb6 is mistakenly opened due to the gradual decrease of the potential caused by the current leakage from the fourth node N4 to the first node N1, and keep the gate drive signal Gout of the scan output end OUT as low level vgl2. In this way, the circuit stability and effectiveness of the shift register 12 working in the low frequency mode are effectively enhanced.

[0097] Reference Figure 8 and Figure 10 As shown in FIG. 13, the high frequency working process of the shift register 12 includes:

[0098] In the stage t21, the first clock signal provided by the first clock end CK jumps from low level to high level, and the corresponding transistors Ma4 and Ma13 are synchronously opened and then closed. The input signal provided by the input end IN is high level, so the fifth node N5 and the node N5a are both high level, and the transistors Ma2 and Ma6 are both off. The transistors Ma15 and Ma16 are on, so the second node N2 and the node N2b are both high level, and the transistor Ma10 is off. The low level vgl1 is sequentially transmitted to the node N6a and the node N6b through the transistors Ma5 and Ma8, and the transistor Ma3 is on. The second clock signal provided by the second clock end XCK is high level, so the transistor Ma7 is off, the first node N1 keeps the high level of the previous stage, and the transistor Ma9 is off. The shift signal of the shift output end NEXT keeps the low level vgl1 of the previous stage, i.e. the invalid level. The transistor Mb5 is on, the low level vgl of the first refresh control signal Ctrl1 is transmitted to the third node N3, so the third node N3 is low level vgl, the transistor Mb1 is on and the transistor Mb2 is off, the high level of the first node N1 is transmitted to the fourth node N4, so the fourth node N4 is stable as high level, and the transistor Mb6 is off. The transistor Mb7 is off, and the gate drive signal Gout of the scan output end OUT keeps the low level vgl2 of the previous stage, i.e. the invalid level.

[0099] In the t22-t23 stage, which is also the stage of outputting the valid level of the shift signal of the shift register 12, the fifth node N5 and the node N5a are both kept at high level, the second node N2 and the node N2b are both at high level, and the transistor Ma10 is turned off; the node N6a and the node N6b are at low level vgl1, so that the transistor Ma3 is turned on; when the second clock signal provided by the second clock terminal XCK is at low level, the transistor Ma7 is turned on, and the low level of the second clock signal is transmitted to the node N6c and the first node N1, so that the first node N1 is at low level; when the second clock signal provided by the second clock terminal XCK is at high level, the transistor Ma7 is turned off, so that the first node N1 is kept at low level; the transistor Ma9 is turned on, and the second power supply signal vgh1 provided by the second power supply terminal VG2 is transmitted to the shift output terminal NEXT, so that the shift signal is at high level vgh1, i.e., the valid level; the transistor Mb5 is turned off, the third node N3 is kept at low level vgl of the previous stage, the transistor Mb1 is turned on, and the transistor Mb2 is turned on, so that the fourth node N4 is at low level, the transistor Mb6 is turned on, the transistor Mb7 is turned off, the fourth power supply signal vgh2 provided by the fourth power supply terminal VG4 is transmitted to the scan output terminal OUT, and the gate drive signal Gout is at high level vgh2, i.e., the valid level. It can be seen that in this stage, the shift signal is at the valid level, and the gate drive signal Gout is at the valid level.

[0100] After the t23 stage, the fifth node N5 and the node N5a are at low level, and the second node N2 and the node N2b are both at low level, so that the transistor Ma10 is turned on, the first power supply signal vgl1 provided by the first power supply terminal VG1 is transmitted to the shift output terminal NEXT, and the shift signal of the shift output terminal NEXT is at low level vgl1, i.e., the invalid level; the transistor Ma6 is turned on, so that the first node N1 is at high level vgh1, and the transistor Ma9 is turned off; the transistor Mb5 is turned on, and the transistor Mb2 is turned off; if the signal Ctrl1 of the first refresh signal line SCL1 remains at low level, the third node N3 is at low level, so that the transistor Mb1 is turned on, or if the signal Ctrl1 of the first refresh signal line SCL1 jumps from high level to low level, the third node N3 jumps from high level to low level, so that the on-off state of the transistor Mb1 is switched; the high level of the first node N1 is written into the fourth node N4 when the transistor Mb1 is turned on, so that the signal of the fourth node N4 is at high level, and the transistor Mb6 is controlled to be turned off; the transistor Mb7 is turned on, the third power supply signal vgl2 provided by the third power supply terminal VG3 is transmitted to the scan output terminal OUT, and the gate drive signal Gout is at low level vgl2, i.e., the invalid level.

[0101] As described above, when the shift register 12 works in the high-frequency mode, the newly added second control module 140a does not affect the normal work of the circuit, and the circuit stability and effectiveness of the shift register 12 working in the high-frequency mode are ensured.

[0102] In the embodiment, the second control module 140a is additionally arranged in the shift register 12, the second control module 140a can stabilize the potential of the fourth node N4, reduces the leakage current of the fourth node N4 to the first node N1 caused by the interference of the first control module 130, and further avoids the problem of the error control refresh output module 150 caused by the leakage current of the fourth node N4, thereby the potential stability of the fourth node N4 of the shift register 12 and the output stability of the gate drive signal Gout can be improved, the output effectiveness, accuracy and stability of the shift register 12 can be ensured, and the display quality of the display panel can be improved.

[0103] Figure 11 is another schematic diagram of the shift register provided by the embodiment of the present application, which is different from Figure 8 in that, Figure 11 the third node N3 is directly electrically connected with the first refresh signal line SCL1 in the shift register 12.

[0104] Figure 11 the low-frequency working timing of the shift register 12 in the embodiment can refer to Figure 9 . Specifically, the t12 to t13 stage is taken as an example for description, in the t12 to t13 stage, the first node N1 is at low level, the second node N2 is at high level, the second power supply signal vgh1 provided by the second power supply end VG2 is transmitted to the shift output end NEXT through the turned-on transistor Ma9, and then the shift signal is at high level vgh1, i.e. the effective level; the first refresh signal line SCL1 is directly electrically connected with the third node N3, and then the third node N3 is at high level of the first refresh control signal Ctrl1; the transistor Mb1 is turned off and the transistor Mb2 is turned on, the high level of the third node N3 is transmitted to the fourth node N4, so that the transistor Mb6 is turned off; and the gate drive signal Gout of the scan output end OUT remains at the low level vgl2 of the previous stage, i.e. the ineffective level. It can be known that the first refresh signal line SCL1 directly provides the first refresh control signal Ctrl1 for the third node N3, when the shift signal output by the shift register 12 is at the effective level, the gate drive signal Gout can be at the ineffective level, and the low-frequency working is realized.

[0105] Figure 11 the high-frequency working timing of the shift register 12 in the embodiment can refer to Figure 10As shown in FIG. 12, the first node N1 is at low level, the second node N2 is at high level, the second power signal vgh1 is transmitted to the shift output end NEXT, and the shift signal is at high level vgh1, i.e., the effective level; the low level of the first refresh control signal Ctrl1 is written to the third node N3; the transistor Mb1 is turned on and the transistor Mb2 is turned on, so that the fourth node N4 is at low level; the transistor Mb6 is turned on, the transistor Mb7 is turned off, the fourth power signal vgh2 is transmitted to the scan output end OUT, and the gate drive signal Gout is at high level vgh2, i.e., the effective level. It can be known that the first refresh signal line SCL1 directly provides the first refresh control signal Ctrl1 for the third node N3, the shift signal output by the shift register 12 is at the effective level, the gate drive signal Gout can be at the effective level, and high-frequency operation is realized.

[0106] Figure 12 FIG. 13 is a schematic diagram of another shift register provided by an embodiment of the present application, which is similar to the shift register shown in FIG. 12. Figure 5 and Figure 12 As shown in FIG. 13, the optional second control module 140b includes: a third transistor Mb3; the gate of the third transistor Mb3 is electrically connected to the third node N3, the first end of the third transistor Mb3 is electrically connected to the first control module 130, and the second end of the third transistor Mb3 is electrically connected to the fourth node N4. Specifically, the second control module 140b is electrically connected between the first control module 130 and the fourth node N4. Figure 12 The second control module 140b shown in FIG. 13 is different from the second control module 140a shown in FIG. 12. Figure 8 The second control module 140b shown in FIG. 13 is different from the second control module 140a shown in FIG. 12.

[0107] The third transistor Mb3 and the first transistor Mb1 are of the same type, and both are PMOS in the example. The signal of the third node N3 controls the third transistor Mb3 and the first transistor Mb1 to be turned on or turned off at the same time. It can be understood that the first transistor Mb1 and the third transistor Mb3 can be regarded as a double-gate transistor.

[0108] Figure 12 The low-frequency operation timing of the shift register 12 shown in FIG. 13 can refer to the low-frequency operation timing shown in FIG. 12. Figure 9As shown in the figure. Specifically, the t12-t13 stage is taken as an example for illustration. In the t12-t13 stage, the first node N1 is at a low level, the second node N2 is at a high level, and the shift output end NEXT outputs a shift signal at the second power supply signal vgh1, i.e., an effective level. The high level of the first refresh control signal Ctrl1 is written to the third node N3, so that the double-gate transistor (Mb1+Mb3) is turned off, the fourth node N4 is in a floating state and remains at the high level of the previous stage. The double-gate transistor (Mb1+Mb3) arranged between the fourth node N4 and the first node N1 can reduce the leakage current of the fourth node N4 to the first node N1. Therefore, in this stage, the second control module 140b is arranged to reduce the leakage current of the fourth node N4 to the first node N1, so that the fourth node N4 can also be stabilized at a high level to control the transistor Mb6 to be turned off. The gate drive signal Gout of the scan output end OUT remains at a low level vgl2, i.e., an ineffective level. It can be known that, in the case that the first node N1 is at a low level, the fourth node N4 is at a high level, and the first transistor Mb1 is turned off, the second control module 140b arranged between the output end of the first transistor Mb1 and the fourth node N4 can reduce the leakage current of the fourth node N4 to the first node N1, thereby improving the output stability of the shift register 12.

[0109] Figure 12 The high-frequency working timing of the shift register 12 can refer to Figure 10 As shown in the figure. Specifically, the t22-t23 stage is taken as an example for illustration. In the t22-t23 stage, the first node N1 is at a low level, the second power supply signal vgh1 is transmitted to the shift output end NEXT, and the shift signal is at a high level vgh1, i.e., an effective level. The low level of the first refresh control signal Ctrl1 is written to the third node N3, so that the double-gate transistor (Mb1+Mb3) is turned on, the fourth node N4 is at a low level, the fourth power supply signal vhg2 is transmitted to the scan output end OUT, and the gate drive signal Gout is at a high level vgh2, i.e., an effective level. It can be known that, by designing the double-gate transistor (Mb1+Mb3), when the shift signal output by the shift register 12 is at an effective level, the gate drive signal Gout can be at an effective level, thereby realizing high-frequency working.

[0110] Figure 13 is another schematic diagram of a shift register provided by an embodiment of the present application, which can refer to Figure 3 and Figure 13As shown, the optional shift register 12 includes a second control module 140a and a second control module 140b, wherein the second control module 140a includes a second transistor Mb2, and the second control module 140b includes a third transistor Mb3. The gate of the second transistor Mb2 is electrically connected to the first node N1, the first end of the second transistor Mb2 is electrically connected to the third node N3, and the second end of the second transistor Mb2 is electrically connected to the fourth node N4. The gate of the third transistor Mb3 is electrically connected to the third node N3, the first end of the third transistor Mb3 is electrically connected to the first control module 130, and the second end of the third transistor Mb3 is electrically connected to the fourth node N4.

[0111] The first transistor Mb1 and the third transistor Mb3 can be of the same type, and the second transistor Mb2 and the third transistor Mb3 can be of the same type or different types. In an example, all of them are PMOS, and the third node N3 controls the third transistor Mb3 and the first transistor Mb1 to be turned on or turned off at the same time. It can be understood that the first transistor Mb1 and the third transistor Mb3 can be regarded as a double-gate transistor. However, this is not limited, and the working types of the transistors in the shift register 12 can be reasonably selected under the premise of ensuring the normal working of the shift register 12.

[0112] Figure 13 The low-frequency working timing of the shift register 12 can refer to Figure 9 As shown, Figure 13 The high-frequency working timing of the shift register 12 can refer to Figure 10 As shown.

[0113] Figure 13 In addition, for the case that the double-gate transistor (Mb1+Mb3) is turned off, the first node N1 is at a low level, and the fourth node N4 is at a high level, the double-gate transistor (Mb1+Mb3) can reduce the leakage current of the fourth node N4 to the first node N1, and the high level of the third node N3 can further pull up the potential of the fourth node N4 through the second transistor Mb2, thereby further reducing the leakage current of the fourth node N4 to the first node N1, so that the fourth node N4 can also be stabilized at a high level in the low-frequency working to control the transistor Mb6 to be turned off, and the gate driving signal Gout of the scan output end OUT is kept at a low level vgl2, i.e., an invalid level. By simultaneously setting the second control module 140a and the second control module 140b, the leakage current of the fourth node N4 to the first node N1 can be reduced, and the output stability of the shift register 12 can be improved.

[0114] In other embodiments, Figure 12 and Figure 13 A fourth control module 160 can also be added (refer to Figure 8As shown, the third node N3 is electrically connected to the first refresh signal line SCL1 through the fourth control module 160, which further improves the output stability of the shift register 12.

[0115] In this embodiment, the added second control module 140 can stabilize the potential of the fourth node N4, improve the problem of leakage caused by interference from the first control module 130 at the high level of the fourth node N4, and thus avoid the problem of incorrect control of the refresh output module 150 caused by leakage at the fourth node N4. This can improve the potential stability of the fourth node N4 of the shift register 12 and the output stability of the gate drive signal Gout, which is beneficial to ensuring the effectiveness, accuracy and stability of the output of the shift register 12, and thus improving the display quality of the display panel.

[0116] Figure 14 This is a schematic diagram of another shift register provided in an embodiment of the present invention, as shown below. Figure 14 As shown, the optional shift register 12 further includes: a third control module 170, electrically connected to the fifth power supply terminal VG5, the first control terminal A, and the fourth node N4, used to control the signal of the fourth node N4; the first control terminal A is one of the fifth node N5, the second node N2, the shift output terminal NEXT, and the third node N3. The optional third control module 170 includes: a fourth transistor Mb4; the gate of the fourth transistor Mb4 is electrically connected to the first control terminal A, the first terminal of the fourth transistor Mb4 is electrically connected to the fifth power supply terminal VG5, and the second terminal of the fourth transistor Mb4 is electrically connected to the fourth node N4.

[0117] In this embodiment, the signal from the first control terminal A controls the fourth transistor Mb4 to turn on or off. When the signal from the first control terminal A controls the fourth transistor Mb4 to turn on, the fifth power supply signal provided by the fifth power supply terminal VG5 is transmitted to the fourth node N4 through the turned-on fourth transistor Mb4 to adjust the signal of the fourth node N4. Specifically, the signal of node N5a is the same as the signal of the fifth node N5, and the signal of node N2b is the same as the signal of the second node N2. Therefore, the first control terminal A can be the fifth node N5, or node N5a, or the second node N2, or node N2b, or the shift output terminal NEXT, or the third node N3, within the same shift register 12.

[0118] The fourth transistor Mb4 is a PMOS. The fifth power supply signal provided by the fifth power supply end VG5 is a high voltage vgh3. Correspondingly, when the signal of the fourth node N4 is a high voltage, the fifth power supply signal vgh3 provided by the fifth power supply end VG5 can stabilize the potential of the fourth node N4, so that the fourth node N4 is kept at a high voltage, the leakage current of the fourth node N4 is reduced, the leakage current problem of the fourth node N4 to the fifth power supply end VG5 is avoided, and the sixth transistor Mb6 is turned off. When the signal of the fourth node N4 is a low voltage, the first control end A controls the fourth transistor Mb4 to be turned off, and the low voltage of the fourth node N4 controls the sixth transistor Mb6 to be turned on. The third control module 170 added in the shift register 12 does not affect the normal operation of the shift register 12, and can improve the output stability and effectiveness of the shift register 12. However, the working type and signal of each transistor in the shift register 12 can be reasonably selected under the premise of ensuring the normal operation of the shift register 12.

[0119] The level signal vgh3 provided by the fifth power supply end VG5 is different from the level signal vgh2 provided by the fourth power supply end VG4. The level signal vgh3 provided by the fifth power supply end VG5 is greater than or equal to the level signal vgh2 provided by the fourth power supply end VG4.

[0120] In the working process of the shift register 12, when the fourth node N4 is a high voltage, the sixth transistor Mb6 is turned off to ensure that the scanning output end OUT outputs a low voltage. In this embodiment, the fourth power supply signal vgh2 provided by the fourth power supply end VG4 is designed to be less than the fifth power supply signal vgh3 provided by the fifth power supply end VG5. Therefore, when the fourth node N4 has a slight drop or disturbance in the high voltage due to the leakage current of the fourth node N4, external electric field interference or other signal interference, the sixth transistor Mb6 can still be kept off, thereby ensuring the output effectiveness and stability of the shift register 12.

[0121] Reference Figure 14 As shown in the figure, among the level signal provided by the second power supply end VG2, the level signal provided by the fourth power supply end VG4 and the level signal provided by the fifth power supply end VG5, at least two of them are the same signal.

[0122] In this embodiment, the second power supply signal provided by the second power supply end VG2 is a high voltage vgh1, the fourth power supply signal provided by the fourth power supply end VG4 is a high voltage vgh2, and the fifth power supply signal provided by the fifth power supply end VG5 is a high voltage vgh3.

[0123] Optionally, the same signal line is used to simultaneously provide power signals for the second power terminal VG2, the fourth power terminal VG4 and the fifth power terminal VG5, and thus the second power signal vgh1 is equal to the fourth power signal vgh2 and equal to the fifth power signal vgh3. In other embodiments, two different signal lines are used to respectively provide power signals for the second power terminal VG2, the fourth power terminal VG4 and the fifth power terminal VG5. For example, one signal line is used to provide the same power signal for the second power terminal VG2 and the fourth power terminal VG4, and another signal line is used to provide a power signal for the fifth power terminal VG5. In this way, the number of signal lines in the non-display area can be reduced, which is conducive to achieving a narrow frame.

[0124] Optionally, the shift register further comprises a first coupling module, a first end of the first coupling module is electrically connected to one of the second power terminal, the fourth power terminal and the fifth power terminal, and a second end of the first coupling module is electrically connected to the fourth node. Optionally, the first coupling module comprises a first capacitor, a first plate of the first capacitor is the first end of the first coupling module, and a second plate of the first capacitor is electrically connected to the fourth node. For reference Figure 14 As shown, the first coupling module 181 comprises a first capacitor Cb1, and the first capacitor Cb1 is electrically connected between the fourth power terminal VG4 and the fourth node N4.

[0125] Optionally, the shift register further comprises a second coupling module, a first end of the second coupling module is electrically connected to the sixth power terminal, and a second end of the second coupling module is electrically connected to the third node. Optionally, the second coupling module comprises a second capacitor, a first plate of the second capacitor is electrically connected to the sixth power terminal, and a second plate of the second capacitor is electrically connected to the third node. For reference Figure 14 As shown, the second coupling module 182 comprises a second capacitor Cb2, and the second capacitor Cb2 is electrically connected between the sixth power terminal VG6 and the third node N3.

[0126] In this embodiment, the sixth power signal provided by the sixth power terminal VG6 is a low level vgl3. Optionally, the first power signal provided by the first power terminal VG1 is a low level vgl1, and the third power signal provided by the third power terminal VG3 is a low level vgl2. Based on this, among the level signal vgl1 provided by the first power terminal VG1, the level signal vgl2 provided by the third power terminal VG3 and the level signal vgl3 provided by the sixth power terminal VG6, at least two of them are the same signal, that is, at least two of the first power terminal VG1, the third power terminal VG3 and the sixth power terminal VG6 are electrically connected to the same signal line. In this way, the number of signal lines in the non-display area can be reduced, which is conducive to achieving a narrow frame.

[0127] In other embodiments, the sixth power supply end provides a sixth power supply signal at a high level. Based on this, the level signal provided by the sixth power supply end and the level signal provided by the second power supply end are the same signal; or, the level signal provided by the sixth power supply end and the level signal provided by the fourth power supply end are the same signal. Specifically, the same signal line is used to provide the same second power supply signal vgh1 to the sixth power supply end and the second power supply end; or, the same signal line is used to provide the same fourth power supply signal vgh2 to the sixth power supply end and the fourth power supply end. In this way, the number of signal lines in the non-display area can be reduced, which is conducive to realizing a narrow frame. In other embodiments, the level signal provided by the sixth power supply end and the level signal provided by the fifth power supply end are the same signal.

[0128] The optional shift register further includes: a third coupling module; a first end of the third coupling module is electrically connected to the scan output end, and a second end of the third coupling module is electrically connected to the second node. The optional third coupling module includes: a third capacitor; a first plate of the third capacitor is electrically connected to the scan output end, and a second plate of the third capacitor is electrically connected to the second node. It is referred to Figure 14 As shown, the third coupling module 183 includes a third capacitor Cb3. The exemplary third capacitor Cb3 is electrically connected between the scan output end OUT and the second node N2.

[0129] Figure 14 In the embodiment, the optional second control end B is electrically connected to the shift output end NEXT, and the optional first control end A is electrically connected to the second node N2.

[0130] Figure 14 In the embodiment, the low-frequency working timing of the shift register 12 can refer to Figure 9 As shown. Specifically, the t12 to t13 stage is taken as an example for description.

[0131] In the t12 to t13 stage of low-frequency work, the first node N1 is at a low level, the second node N2 is at a high level, and the second power supply signal vgh1 provided by the second power supply end VG2 is transmitted to the shift output end NEXT through the turned-on transistor Ma9, so that the shift signal is at a high level vgh1, i.e., an effective level; the fifth transistor Mb5 is turned off, the third node N3 maintains the high level of the previous stage, and then the transistor Mb1 is turned off; the transistor Mb2 is turned on, the second node N2 is at a high level, the fourth transistor Mb4 is turned off, and then the high level of the third node N3 is transmitted to the fourth node N4, so that the fourth node N4 maintains a high level; the transistor Mb6 is turned off, and the gate drive signal Gout of the scan output end OUT maintains a low level vgl2, i.e., an ineffective level.

[0132] After the t13 stage of low-frequency operation, the first node N1 is at high level, the second node N2 is at low level, and the first power supply signal vgl1 provided by the first power supply end VG1 is transmitted to the shift output end NEXT through the turned-on transistor Ma10, so that the shift signal is at low level vgl1, i.e., an invalid level; the fifth transistor Mb5 is turned on, the high level of the first refresh control signal Ctrl1 is transmitted to the third node N3, so that the transistor Mb1 is turned off; the transistor Mb2 is turned off, the second node N2 is at low level, so that the fourth transistor Mb4 is turned on, and the fifth power supply signal vgh3 provided by the fifth power supply end VG5 is transmitted to the fourth node N4, so that the fourth node N4 is at high level; the transistor Mb6 is turned off and the transistor Mb7 is turned on, so that the gate drive signal Gout of the scan output end OUT is at low level vgl2, i.e., an invalid level.

[0133] Figure 14 The high-frequency operation timing of the shift register 12 can refer to FIG. 2, which will not be repeated here. Figure 10

[0134] In the embodiment, by adding the second control module 140a and the third control module 170, the potential of the fourth node N4 can be stabilized, the leakage current of the fourth node N4 to the first node N1 caused by the interference of the first control module 130 on the high level of the fourth node N4 is reduced, and the problem of incorrect control of the refresh output module 150 caused by the leakage current of the fourth node N4 is avoided, so that the potential stability of the fourth node N4 of the shift register 12 and the output stability of the gate drive signal Gout can be improved, which is beneficial to ensure the output effectiveness, accuracy and stability of the shift register 12, and further beneficial to improve the display quality of the display panel.

[0135] In other embodiments, the types of transistors in the shift register can all be NMOS, or the types of transistors in the shift register can include at least one NMOS and at least one PMOS. Exemplarily, Figure 15 is another schematic diagram of a shift register provided by an embodiment of the present application, as shown in Figure 15 ​As shown, the optional first control end A is the third node N3; the signal of the third node N3 controls the first control module 130 and the third control module 170 to be turned on at different times. Specifically, the first transistor Mb1 in the optional first control module 130 is PMOS, the fourth transistor Mb4 in the third control module 170 is NMOS, the first control end A is the third node N3, and the signal of the third node N3 controls the first control module 130 and the third control module 170 to be turned on at different times. When the signal of the third node N3 is high, the first transistor Mb1 is controlled to be turned off and the fourth transistor Mb4 is controlled to be turned on, the fifth power signal vgh3 is written to the fourth node N4, the fourth node N4 is ensured to be high, and the leakage current of the fourth node N4 to the first node N1 can be reduced. When the signal of the third node N3 is low, the first transistor Mb1 is controlled to be turned on and the fourth transistor Mb4 is controlled to be turned off, and the signal of the first node N1 is written to the fourth node N4. Figure 15 The low-frequency working timing of the shift register 12 can refer to Figure 9 As shown, Figure 15 The high-frequency working timing of the shift register 12 can refer to Figure 10 As shown, which will not be repeated here.

[0136] For the above-mentioned multiple embodiments, the shift register 12 includes the first control module 130 and the second control module 140. On this basis, the third control module 170, the fourth control module 160, the first coupling module 181, the second coupling module 182 and the third coupling module 183 are all optional items of the shift register 12, that is, the shift register 12 can not include the third control module 170, the fourth control module 160, the first coupling module 181, the second coupling module 182 and the third coupling module 183, or the shift register 12 can include at least one of the third control module 170, the fourth control module 160, the first coupling module 181, the second coupling module 182 and the third coupling module 183. On the premise of ensuring the normal working of the shift register 12, relevant practitioners can reasonably design the specific components and structure of the shift register 12 according to the needs of the product. Not limited to the above diagram.

[0137] The inventor has found through research that the scan output part 14 of the shift register 12 is not limited to the above structure, the scan output part 14 can not include the second control module 140, and the structure of the scan output part 14 in the shift register 12 can be reasonably designed to ensure the normal working, stable and effective output of the shift register 12. The following multiple embodiments provide different multiple scan output parts 14, wherein the scan output part 14 can include the second control module 140 or not include the second control module 140.

[0138] Figure 16 is another schematic diagram of a shift register provided by an embodiment of the present application, as shown inFigure 16 As shown, the scan output part 14 of the optional shift register 12 does not include the second control module. The optional scan output part 14 is a 5T3C structure, wherein the "5T" of the scan output part 14 includes the first transistor Mb1, the fourth transistor Mb4, the fifth transistor Mb5, the sixth transistor Mb6 and the seventh transistor Mb7, and the "3C" of the scan output part 14 includes the first capacitor Cb1, the second capacitor Cb2 and the third capacitor Cb3. The five transistors in the optional scan output part 14 are all PMOS, but are not limited thereto. The low-frequency working timing of the shift register 12 can refer to Figure 9 As shown, and the high-frequency working timing thereof can refer to Figure 10 As shown, which is not repeated here.

[0139] Figure 17 is a schematic diagram of still another shift register provided by an embodiment of the present application, which is different from Figure 16 . Specifically, the optional Figure 17 The scan output part 14 in the optional shift register 12 is a 5T2C structure, wherein the optional first transistor Mb1 is NMOS and the fourth transistor Mb4 is PMOS, the gate of the fourth transistor Mb4 is electrically connected to the third node N3, and the scan output part 14 can include only two capacitors, which are the second capacitor Cb2 and the third capacitor Cb3.

[0140] Figure 18 is a schematic diagram of still another shift register provided by an embodiment of the present application, which is different from Figure 16 . Specifically, the optional Figure 18 The scan output part 14 in the optional shift register 12 is a 5T2C structure, wherein the optional first transistor Mb1 is NMOS and the fourth transistor Mb4 is PMOS, the first end of the first transistor Mb1 receives a high level and the second end is electrically connected to the fourth node N4, the high level received by the first end of the first transistor Mb1 can come from the second power supply end VG2, or from the fourth power supply end VG4, or from the fifth power supply end VG5, the gate of the fourth transistor Mb4 is electrically connected to the third node N3, the first end of the fourth transistor Mb4 is electrically connected to the first node N1 and the second end is electrically connected to the fourth node N4, and the scan output part 14 can include only two capacitors, which are the second capacitor Cb2 and the third capacitor Cb3.

[0141] Figure 19 is a schematic diagram of still another shift register provided by an embodiment of the present application, which is different from Figure 16 . Specifically, the optional Figure 19 The scan output part 14 in the optional shift register 12 is a 4T2C structure, wherein the third node N3 of the shift register 12 can be directly electrically connected to the first refresh signal line SCL1 to receive the first refresh control signal Ctrl1, and the scan output part 14 can include only two capacitors, which are the first capacitor Cb1 and the third capacitor Cb3.

[0142] In combination Figure 9 And Figure 10 For Figure 19 As shown in the shift register 12, when the first refresh control signal Ctrl1 received by the third node N3 is high, the first transistor Mb1 is off, and the shift register 12 is in a low refresh rate mode. Conversely, when the first refresh control signal Ctrl1 received by the third node N3 of the shift register 12 is low, the first transistor Mb1 is on, and the electrical signal of the first node N1 is written to the fourth node N4, then the shift register 12 is in a high refresh rate mode. Therefore, the high and low level transition position of the first refresh control signal Ctrl1 is the boundary between the low refresh rate display area and the high refresh rate display area.

[0143] In this embodiment, a plurality of refresh signal lines can be used, and each refresh signal line is electrically connected to a plurality of consecutive shift registers. Therefore, the transition of the refresh control signal of each refresh signal line will not affect the output validity of the shift register 12.

[0144] For the above-mentioned multiple embodiments, under the premise of ensuring the normal operation of the shift register 12, the structure of the scan output part 14 can be adjusted, and the structure of the scan output part 14 can be “5T3C”, or “5T2C”, or “4T2C”, or other, and relevant practitioners can reasonably design the specific components and structure of the shift register 12 according to the needs of the product. Not limited to the above diagram.

[0145] Figure 20 is another schematic diagram of a shift register provided by an embodiment of the present application, Figure 21 is another schematic diagram of a shift register provided by an embodiment of the present application, which is different from any of the above-mentioned embodiments in that, Figure 20 And Figure 21 The shift register 12 in the figure is electrically connected to two refresh signal lines.

[0146] As shown in the figure, Figure 20 And Figure 21 As shown in the figure, the optional shift register 12 further includes a fifth control module 190; the fifth control module 190 is electrically connected to the second control end B, the second refresh signal line, the fifth power supply end VG5 and the fourth node N4, and is used for controlling the signal of the fourth node N4; the second control end B is one of the fifth node N5, the second node N2 and the shift output end NEXT.

[0147] In this embodiment, the display panel includes a second refresh signal line and a first refresh signal line. The first refresh signal line provides a first refresh control signal Ctrl1 to the shift register 12, and the second refresh signal line provides a second refresh control signal Ctrl2 to the shift register 12. The first refresh control signal Ctrl1 provided by the first refresh signal line can be transmitted to the third node N3 through the fourth control module 160; in other embodiments, the first refresh control signal Ctrl1 provided by the first refresh signal line can also be directly transmitted to the third node N3.

[0148] Combination Figure 7 , Figure 20 and Figure 21 As shown, the second control terminal B can be the fifth node N5, or node N5a, or the second node N2, or node N2b, or the shift output terminal NEXT.

[0149] The optional fifth control module 190 includes: a first control submodule 191, electrically connected to the second control terminal B, the second refresh signal line, and the first sub-node N3a, used to control the signal of the first sub-node N3a; and a second control submodule 192, electrically connected to the first sub-node N3a, the fifth power supply terminal VG5, and the fourth node N4, used to control the signal of the fourth node N4. The optional first control submodule 191 includes: an eighth transistor Mb8, the gate of which is electrically connected to the second control terminal B, the first terminal of which is electrically connected to the second refresh signal line, and the second terminal of which is electrically connected to the first sub-node N3a; the second control submodule 192 includes: a ninth transistor Mb9, the gate of which is electrically connected to the first sub-node N3a, the first terminal of which is electrically connected to the fifth power supply terminal VG5, and the second terminal of which is electrically connected to the fourth node N4.

[0150] In this embodiment, the first terminal of the eighth transistor Mb8 in the first control submodule 191 receives the second refresh control signal Ctrl2 provided by the second refresh signal line. The signal from the second control terminal B controls the on / off state of the first control submodule 191. Specifically, when the signal from the second control terminal B controls the eighth transistor Mb8 to turn on, the second refresh control signal Ctrl2 is transmitted to the first subnode N3a. When the signal from the second control terminal B controls the eighth transistor Mb8 to turn off, the first subnode N3a remains at the level of the previous stage.

[0151] The gate of the ninth transistor Mb9 in the second control submodule 192 is electrically connected with the first sub-node N3a. The signal of the first sub-node N3a controls the on-off state of the second control submodule 192. Specifically, when the ninth transistor Mb9 is turned on, the signal of the first sub-node N3a controls the fifth power supply signal provided by the fifth power supply end VG5 to be transmitted to the fourth node N4. When the ninth transistor Mb9 is turned off, the fourth node N4 keeps the level of the previous stage or is adjusted by other nodes.

[0152] As shown in Figure 21 , the optional fifth control module 190 further includes a coupling submodule 193. The first end of the coupling submodule 193 is electrically connected with the sixth power supply end VG6, and the second end of the coupling submodule 193 is electrically connected with the first sub-node N3a. The optional coupling submodule 193 includes a fourth capacitor Cb4. The first plate of the fourth capacitor Cb4 is electrically connected with the sixth power supply end VG6, and the second plate of the fourth capacitor Cb4 is electrically connected with the first sub-node N3a.

[0153] The control signal Ctrl2 provided by the optional second refresh signal line is different from the control signal Ctrl1 provided by the first refresh signal line. The control signal Ctrl2 provided by the optional second refresh signal line and the control signal Ctrl1 provided by the first refresh signal line are both high-low level jump signals, and the two are opposite phases.

[0154] In this embodiment, the effective level of the first refresh control signal Ctrl1 is taken as the low level vgl, and the invalid level of the first refresh control signal Ctrl1 is taken as the high level vgh, to illustrate the working principle of the shift register 12. Correspondingly, when the first refresh control signal Ctrl1 provided by the first refresh signal line is at the low level vgl, the second refresh control signal Ctrl2 provided by the second refresh signal line is at the high level vgh; on the contrary, when the first refresh control signal Ctrl1 is at the high level vgh, the second refresh control signal Ctrl2 is at the low level vgl. The optional first control end A is electrically connected with the second node N2, and the second control end B is electrically connected with the shift output end NEXT.

[0155] In this embodiment, the effective level of the first refresh control signal Ctrl1 is taken as the low level vgl, and the invalid level of the first refresh control signal Ctrl1 is taken as the high level vgh, to illustrate the working principle of the shift register 12. Correspondingly, when the first refresh control signal Ctrl1 provided by the first refresh signal line is at the low level vgl, the second refresh control signal Ctrl2 provided by the second refresh signal line is at the high level vgh; on the contrary, when the first refresh control signal Ctrl1 is at the high level vgh, the second refresh control signal Ctrl2 is at the low level vgl. The optional first control end A is electrically connected with the second node N2, and the second control end B is electrically connected with the shift output end NEXT. Figure 21 Figure 22 is Figure 21 shown in FIG. 7 is a low-frequency working timing diagram of the shift register 12 in the first display partition. Referring to Figure 21 and Figure 22 , in the first display partition, the shift signal frequency of the shift register 12 is greater than the gate drive signal frequency, so that the shift register 12 exists in the case that the shift signal is at the effective level and the gate drive signal is at the invalid level in the low-frequency working, so as to realize the low-frequency working.

[0156] Figure 23 is​Figure 21 The high-frequency working timing diagram of the shift register 12 in the second display partition is shown in FIG. 6. Referring to FIG. 6, Figure 21 and Figure 23 As shown in FIG. 6, in the optional second display partition, the shift signal frequency of the shift register 12 is equal to the gate drive signal frequency, and then the shift register 12 exists the case that the shift signal is at the active level and the gate drive signal is at the active level in the high-frequency working, so as to realize the high-frequency working.

[0157] Referring to FIG. 7, Figure 21 and Figure 22 As shown in FIG. 7, the low-frequency working process of the shift register 12 includes:

[0158] In the t31 stage, the second node N2 is at the high level, the first node N1 remains at the high level of the previous stage, and the shift signal of the shift output end NEXT remains at the low level vgl1, i.e., the inactive level of the previous stage; the transistor Mb5 and the transistor Mb8 are both turned on, the third node N3 is at the high level vgh of the first refresh control signal Ctrl1, the transistor Mb1 is turned off, the first sub-node N3a is at the low level vgl of the second refresh control signal Ctrl2, and the transistor Mb9 is turned on; the fifth power supply signal vgh3 of the fifth power supply end VG5 is written into the fourth node N4, and the fourth node N4 is at the high level; the transistor Mb6 is turned off and the transistor Mb7 is turned off, and the gate drive signal Gout of the scan output end OUT remains at the low level vgl2.

[0159] In the t32 to t33 stages, which are also the active level output stages of the shift signal of the shift register 12, the second node N2 is at the high level, the first node N1 is at the low level, the second power supply signal vgh1 provided by the second power supply end VG2 is transmitted to the shift output end NEXT, and the shift signal is at the high level vgh1, i.e., the active level; the transistor Mb5 and the transistor Mb8 are both turned off, the third node N3 remains at the high level vgh of the previous stage, and the fourth node N4 remains at the high level vgh3 of the previous stage; the transistor Mb6 is turned off and the transistor Mb7 is turned off, and the gate drive signal Gout of the scan output end OUT remains at the low level vgl2, i.e., the inactive level. It can be seen that in this stage, the shift signal is at the active level and the gate drive signal Gout is at the inactive level.

[0160] After the t33 stage, the second node N2 is at the low level, the first node N1 is at the high level vgh1, and the shift signal of the shift output end NEXT is at the low level vgl1; the transistor Mb5 and the transistor Mb8 are both turned on, the third node N3 is at the high level vgh, the first sub-node N3a is at the low level vgl so that the transistor Mb9 is turned on, the fifth power supply signal vgh3 is written into the fourth node N4, the transistor Mb6 is turned off and the transistor Mb7 is turned on, and the gate drive signal Gout of the scan output end OUT is at the low level vgl2.

[0161] Reference Figure 21 and Figure 23 As shown in the figure, the high-frequency operation process of the shift register 12 includes:

[0162] In the t41 stage, the second node N2 is at high level, the first node N1 remains at the high level of the previous stage, and thus the shift signal of the shift output end NEXT remains at the low level vgl1 of the previous stage, i.e., the invalid level; the transistor Mb5 and the transistor Mb8 are both turned on, the third node N3 is at the low level vgl of the first refresh control signal Ctrl1, the transistor Mb1 is turned on, the first sub-node N3a is at the high level vgh of the second refresh control signal Ctrl2, and the transistor Mb9 is turned off; the high level of the first node N1 is written into the fourth node N4, and the fourth node N4 is at high level; the transistor Mb6 is turned off, the transistor Mb7 is turned off, and the gate drive signal Gout of the scan output end OUT remains at low level vgl2.

[0163] In the t42 to t43 stage, the second node N2 is at high level, the first node N1 is at low level, the second power signal vgh1 is transmitted to the shift output end NEXT, and the shift signal is at high level vgh1, i.e., the valid level; the transistor Mb5 and the transistor Mb8 are both turned off, the third node N3 remains at the low level vgl of the previous stage, the transistor Mb1 is turned on, and the low level vgl of the first node N1 is written into the fourth node N4; the first sub-node N3a remains at the high level vgh of the previous stage, and the transistor Mb9 is turned off; the transistor Mb6 is turned on, the transistor Mb7 is turned off, the fourth power signal vgh2 is written into the scan output end OUT, and the gate drive signal Gout is at high level vgh2, i.e., the valid level. It can be seen that in this stage, the shift signal is at the valid level and the gate drive signal Gout is at the valid level.

[0164] After the t43 stage, the second node N2 is at low level, the first node N1 is at high level vgh1, the first power signal vgl1 is transmitted to the shift output end NEXT, and the shift signal is at low level vgl1, i.e., the invalid level; the transistor Mb5 and the transistor Mb8 are both turned on, the third node N3 is at the low level vgl of the first refresh control signal Ctrl1, the transistor Mb1 is turned on, the first sub-node N3a is at the high level vgh of the second refresh control signal Ctrl2, and the transistor Mb9 is turned off; the high level of the first node N1 is written into the fourth node N4; the transistor Mb6 is turned off, the transistor Mb7 is turned on, the third power signal vgl2 is written into the scan output end OUT, and the gate drive signal Gout is at low level vgl2.

[0165] As described above, when the shift register 12 works in the low frequency mode or the high frequency mode, the potential of the fourth node N4 is stable, and the sixth transistor Mb6 is not triggered by mistake, which ensures the stability and effectiveness of the circuit in which the shift register 12 works. Based on the shift register structure, the display panel can realize the partition refresh at any position, can save power consumption, and improve the output stability and effectiveness of the partition refresh, especially the output effectiveness of the low brush display area.

[0166] It should be noted that the structure of the shift register in the embodiment of the present application is not limited to this, and the shift register with the corresponding transistors and other structures added or reduced is suitable for the embodiment of the present application, and the embodiment of the present application will not be repeated here. For example, another shift register can delete the transistor Mb4 based on the structure shown in Figure 20 , and the working process is similar to other shift registers, which will not be repeated here. Obviously, the structure of the shift register in the embodiment of the present application can be various, and is not limited to this.

[0167] Based on the same inventive concept, the embodiment of the present application also provides a display device, which comprises the display panel provided by the embodiment of the present application. Therefore, the display device has the technical features of the display panel and the driving process provided by the embodiment of the present application, and can achieve the beneficial effects of the display panel provided by the embodiment of the present application. The same parts can be referred to the description of the display panel provided by the embodiment of the present application, and will not be repeated here.

[0168] For example, Figure 24 is a structural schematic diagram of a display device provided by the embodiment of the present application, as Figure 24 shown, the display device 1 comprises the display panel 10 provided by the embodiment of the present application. The display device 1 provided by the embodiment of the present application can be any electronic product with display function, including but not limited to the following categories: mobile phone, television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interactive terminal, etc. The embodiment of the present application does not make special limitation here.

[0169] It should be understood that the steps can be reordered, added or deleted using the various forms of flow shown above. For example, the steps described in the present application can be executed in parallel, sequentially or in different order, as long as the desired results of the technical solutions of the present application can be achieved, which is not limited herein.

[0170] The above detailed description does not limit the scope of the application. Various modifications, combinations, sub-combinations and alternatives can be made to the detailed embodiment within the scope of the application. Any modification, equivalent replacement and improvement made without departing from the spirit and principle of the application shall fall within the scope of the application.

Claims

1. A display panel, characterized by, include: A first driving circuit, the first driving circuit including a multi-stage shift register; The shift register includes: The shift control module is electrically connected to an input terminal, a first clock terminal, a second clock terminal, a first power supply terminal, a second power supply terminal, a first node, and a second node, and is used to control the signals of the first node and the second node. The shift output module is electrically connected to the first node, the second node, the first power supply terminal, the second power supply terminal, and the shift output terminal, and is used to control the shift output terminal to output a shift signal; A first control module and a second control module, wherein the first control module is electrically connected to the first node and the third node, and the second control module is electrically connected to the third node and the fourth node; The first control module is electrically connected to the fourth node and the second control module is electrically connected to the first node; or, the first control module is electrically connected to the fourth node through the second control module; or, the first control module is electrically connected to the fourth node through the second control module and the second control module is electrically connected to the first node. The first control module is used to control the signal of the fourth node; the third node is used to receive the first refresh control signal provided by the first refresh signal line; the second control module is used to adjust the signal of the fourth node. The refresh output module is electrically connected to the second node, the fourth node, the third power supply terminal, the fourth power supply terminal, and the scan output terminal, and is used to control the scan output terminal to output a gate drive signal.

2. The display panel of claim 1, wherein, The first control module includes: a first transistor; The gate of the first transistor is electrically connected to the third node, the first terminal of the first transistor is electrically connected to the first node, and the second terminal of the first transistor is electrically connected to the fourth node.

3. The display panel of claim 1, wherein, The second control module includes: a second transistor; The gate of the second transistor is electrically connected to the first node, the first terminal of the second transistor is electrically connected to the third node, and the second terminal of the second transistor is electrically connected to the fourth node.

4. The display panel of claim 1, wherein, The second control module includes: a third transistor; The gate of the third transistor is electrically connected to the third node, the first terminal of the third transistor is electrically connected to the first control module, and the second terminal of the third transistor is electrically connected to the fourth node.

5. The display panel of claim 1, wherein, The shift control module includes: The first shift submodule is electrically connected to the input terminal, the first clock terminal, and the fifth node, and is used to control the signal of the fifth node; The second shift submodule is electrically connected to the fifth node, the first clock terminal, the second clock terminal, the first power supply terminal, the second power supply terminal, and the first node, and is used to control the signal of the first node; The third shift submodule is electrically connected to the fifth node, the second clock terminal, the first power supply terminal, the second power supply terminal, and the second node, and is used to control the signal of the second node.

6. The display panel of claim 5, wherein, The shift register further includes: a third control module, electrically connected to the fifth power supply terminal, the first control terminal and the fourth node, used to control the signal of the fourth node; The first control end is one of the fifth node, the second node, the shift output end and the third node.

7. The display panel of claim 6, wherein, The third control module comprises a fourth transistor. The gate of the fourth transistor is electrically connected to the first control end, the first end of the fourth transistor is electrically connected to the fifth power supply end, and the second end of the fourth transistor is electrically connected to the fourth node.

8. The display panel of claim 6, wherein, The level signal provided by the fifth power supply end is different from the level signal provided by the fourth power supply end.

9. The display panel of claim 6, wherein, The level signal provided by the fifth power supply end is greater than or equal to the level signal provided by the fourth power supply end.

10. The display panel of claim 6, wherein, Among the level signal provided by the second power supply end, the level signal provided by the fourth power supply end and the level signal provided by the fifth power supply end, at least two are the same signal.

11. The display panel of claim 6, wherein, The first control end is the third node. The signal of the third node controls the first control module and the third control module to be turned on at different times.

12. The display panel of claim 6, wherein, The shift register further comprises a first coupling module. The first end of the first coupling module is electrically connected to one of the second power supply end, the fourth power supply end and the fifth power supply end, and the second end of the first coupling module is electrically connected to the fourth node.

13. The display panel of claim 12, wherein, The first coupling module comprises a first capacitor. The first plate of the first capacitor is the first end of the first coupling module, and the second plate of the first capacitor is electrically connected to the fourth node.

14. The display panel of claim 5, wherein, The shift register further comprises a fourth control module. The fourth control module is electrically connected to a second control end. The first refresh signal line provides the first refresh control signal to the third node through the fourth control module. The second control end is one of the fifth node, the second node and the shift output end.

15. The display panel of claim 14, wherein, The fourth control module comprises a fifth transistor. The gate of the fifth transistor is electrically connected to the second control end, the first end of the fifth transistor is electrically connected to the first refresh signal line, and the second end of the fifth transistor is electrically connected to the third node.

16. The display panel of claim 15, wherein, The fifth transistor is a double-gate transistor.

17. The display panel of claim 1, wherein, The shift register further comprises a second coupling module. The first end of the second coupling module is electrically connected to a sixth power supply end, and the second end of the second coupling module is electrically connected to the third node.

18. The display panel of claim 17, wherein, The second coupling module comprises a second capacitor. The first plate of the second capacitor is electrically connected to the sixth power supply end, and the second plate of the second capacitor is electrically connected to the third node.

19. The display panel of claim 17, wherein, Among the level signal provided by the first power supply end, the level signal provided by the third power supply end and the level signal provided by the sixth power supply end, at least two are the same signal.

20. The display panel of claim 17, wherein, The level signal provided by the sixth power supply end is the same as the level signal provided by the second power supply end, or the level signal provided by the sixth power supply end is the same as the level signal provided by the fourth power supply end.

21. The display panel of claim 1, wherein, The refresh output module comprises: A first output sub-module electrically connected to the fourth node, the fourth power supply end and the scan output end, for controlling the scan output end to output the gate drive signal. The second output sub-module is electrically connected with the second node, the third power supply end and the scan output end, and is configured to control the scan output end to output the gate drive signal.

22. The display panel of claim 21, wherein, The first output sub-module comprises a sixth transistor. The gate of the sixth transistor is electrically connected with the fourth node, the first end of the sixth transistor is electrically connected with the fourth power supply end, and the second end of the sixth transistor is electrically connected with the scan output end.

23. The display panel of claim 21, wherein, The second output sub-module comprises a seventh transistor. The gate of the seventh transistor is electrically connected with the second node, the first end of the seventh transistor is electrically connected with the third power supply end, and the second end of the seventh transistor is electrically connected with the scan output end.

24. The display panel of claim 1, wherein, The first power supply end provides a level signal different from a level signal provided by the third power supply end.

25. The display panel of claim 1, wherein, The level signal provided by the first power supply end is less than or equal to the level signal provided by the third power supply end.

26. The display panel of claim 1, wherein, The shift register further comprises a third coupling module. The first end of the third coupling module is electrically connected with the scan output end, and the second end of the third coupling module is electrically connected with the second node.

27. The display panel of claim 26, wherein, The third coupling module comprises a third capacitor. The first plate of the third capacitor is electrically connected with the scan output end, and the second plate of the third capacitor is electrically connected with the second node.

28. The display panel of claim 5, wherein, The shift register further comprises a fifth control module. The fifth control module is electrically connected with a second control end, a second refresh signal line, a fifth power supply end and the fourth node, and is configured to control a signal of the fourth node. The second control end is one of the fifth node, the second node and the shift output end.

29. The display panel of claim 28, wherein, The fifth control module comprises: A first control sub-module electrically connected with the second control end, the second refresh signal line and a first sub-node, and configured to control a signal of the first sub-node; A second control sub-module electrically connected with the first sub-node, the fifth power supply end and the fourth node, and configured to control a signal of the fourth node.

30. The display panel of claim 29, wherein, The first control sub-module comprises an eighth transistor, the gate of the eighth transistor is electrically connected with the second control end, the first end of the eighth transistor is electrically connected with the second refresh signal line, and the second end of the eighth transistor is electrically connected with the first sub-node. The second control sub-module comprises a ninth transistor, the gate of the ninth transistor is electrically connected with the first sub-node, the first end of the ninth transistor is electrically connected with the fifth power supply end, and the second end of the ninth transistor is electrically connected with the fourth node.

31. The display panel of claim 29, wherein, The fifth control module further comprises a coupling sub-module. The first end of the coupling sub-module is electrically connected with a sixth power supply end, and the second end of the coupling sub-module is electrically connected with the first sub-node.

32. The display panel of claim 31, wherein, The coupling sub-module comprises a fourth capacitor. The first plate of the fourth capacitor is electrically connected with the sixth power supply end, and the second plate of the fourth capacitor is electrically connected with the first sub-node.

33. The display panel of claim 28, wherein, The second refresh signal line provides a control signal different from a control signal provided by the first refresh signal line.

34. The display panel of claim 28, wherein, The control signal provided by the second refresh signal line and the control signal provided by the first refresh signal line are both high-low level jump signals, and the two are opposite phases.

35. The display panel of claim 1, wherein, The display panel has a multi-frequency refresh mode; In the multi-frequency refresh mode, a display area of the display panel includes at least a first display sub-area and a second display sub-area, a refresh frequency of the first display sub-area is a first refresh frequency, and a refresh frequency of the second display sub-area is a second refresh frequency, the first refresh frequency being less than the second refresh frequency.

36. The display panel of claim 35, wherein, In the multi-frequency refresh mode, a frequency of a shift signal of the shift register in the first display sub-area is greater than a frequency of a gate drive signal. In the multi-frequency refresh mode, a frequency of a gate drive signal of the shift register in the first display sub-area is less than a frequency of a gate drive signal of the shift register in the second display sub-area.

37. A display device comprising: Comprising: The display panel of any one of claims 1-36.

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