Low-power-consumption power management module and test equipment

Abstract

The invention discloses a low-power-consumption power management module and test equipment. The low-power-consumption power management module comprises a timing circuit, a trigger circuit, a first switching circuit and a second switching circuit, the timing switch circuit is connected with the first switch circuit, the first switch circuit is connected with the second switch circuit, the trigger circuit is connected with the second switch circuit, and the output end of the second switch circuit is connected with the FPGA. According to the invention, through the RS5C372A clock chip and the delay button switch, in combination with the NMOS transistor and the PMOS transistor, two working modes of automatic starting and manual starting are realized in a test scene, and long-time low-power-consumption management of an external power supply is carried out, so that the problem of overlarge quiescent current of the power supply management module under a long-time working condition is solved, and test result errors are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of power management, and in particular to a low-power consumption power management module and testing equipment. Background Art

[0002] Power management refers to the effective management and control of the power supply of the test equipment to achieve higher energy efficiency and longer battery life. It is widely used in many fields such as industry, energy, transportation, information, aviation, national defense, education, culture, etc. Existing power management includes direct power supply or indirect power supply, but its working mode is single, and there is a problem of excessive static current under long-term working conditions, which leads to large errors in test results. Summary of the invention

[0003] The main purpose of the present invention is to provide a low-power power management module, aiming to solve the problem that the power management module has a single working mode and has excessive static current under long-term working conditions, resulting in large errors in test results.

[0004] In order to achieve the above object, the present invention proposes a low-power power management module, the low-power power management module includes a timing circuit, a trigger circuit, a first switch circuit and a second switch circuit, the timing switch circuit is connected to the first switch circuit, the first switch circuit is connected to the second switch circuit, the trigger circuit is connected to the second switch circuit, and the output end of the second switch circuit is connected to the FPGA; The timing circuit is used to output a corresponding start signal after reaching a set start time, turn on the first switch circuit and the second switch circuit, and output an external power supply to the FPGA; The trigger circuit is used to output a delayed trigger signal when triggered, turn on the second switch circuit, and output an external power supply to the FPGA.

[0005] In one embodiment, the first switch circuit includes an NMOS transistor, and the second switch circuit includes a PMOS transistor.

[0006] In one embodiment, the timing circuit includes an RS5C372A clock chip.

[0007] In one embodiment, the trigger circuit includes a time-delay push button switch.

[0008] In one embodiment, the low power consumption power management module further includes a lithium battery, the lithium battery is connected to the timing circuit, and the lithium battery is used to provide working power to the timing circuit.

[0009] The present invention also provides a testing device, which includes an FPGA and the above-mentioned low-power power management module.

[0010] The technical solution of the present invention uses an RS5C372A clock chip and a delay button switch in combination with an NMOS tube and a PMOS tube to realize two working modes, automatic start and manual start, in a test scenario, and perform long-term low-power consumption management of an external power supply to solve the problem of excessive static current of a power management module under long-term working conditions and reduce the error of test results. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 The overall circuit diagram of the low-power power management module of the present invention; In the picture: U1-RS5C372A clock chip, S1-delay button switch, BT1-lithium battery, BT2-external power supply, Q1-NMOS tube, Q2-PMOS tube. DETAILED DESCRIPTION

[0012] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0013] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0014] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0015] In the description of the present invention, it should be understood that the terms "upper", "lower", "inside", "outside", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are directions or positional relationships in which the product of the invention is usually placed when in use, or are directions or positional relationships commonly understood by those skilled in the art. These directions or positional relationships are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0016] Furthermore, the terms “first”, “second”, etc. are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0017] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms such as "setting" and "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0018] Existing power management includes multiple methods such as direct power supply or indirect power supply, but its working mode is single and there is a problem of excessive static current under long-term working conditions, which leads to large errors in test results.

[0019] In order to solve the above problems, the present invention proposes a low-power consumption power management module, which is applied to a test device. The specific implementation of the present invention is described in detail below with reference to the accompanying drawings.

[0020] like Figure 1 As shown, the low power consumption power management module includes: A timing circuit, a trigger circuit, a first switch circuit, and a second switch circuit, wherein the timing switch circuit is connected to the first switch circuit, the first switch circuit is connected to the second switch circuit, the trigger circuit is connected to the second switch circuit, and an output end of the second switch circuit is connected to the FPGA; The timing circuit is used to output a corresponding start signal after reaching a set start time, turn on the first switch circuit and the second switch circuit, and output an external power supply BT2 to the FPGA; The trigger circuit is used to output a delayed trigger signal when triggered, turn on the second switch circuit, and output the external power supply BT2 to the FPGA.

[0021] In one embodiment, the first switch circuit includes an NMOS transistor Q1 , and the second switch circuit includes a PMOS transistor Q2 .

[0022] In one embodiment, the timing circuit includes an RS5C372A clock chip U1.

[0023] In one embodiment, the trigger circuit includes a delay button switch S1.

[0024] In one embodiment, the low power consumption power management module further includes a lithium battery BT1, wherein the lithium battery BT1 is connected to the timing circuit, and the lithium battery BT1 is used to provide working power to the timing circuit.

[0025] In this embodiment, the timing circuit can be implemented by any circuit with a timing function, such as the RS5C372A clock chip U1; the first switch circuit can be implemented by an NMOS tube Q1, and the second switch circuit can be implemented by a PMOS tube Q2; the trigger circuit can be implemented by a delay button switch S1; wherein, the RS5C372A clock chip U1 is independently powered by a lithium battery BT1, which is used to record time in real time and time-control the external power supply BT2 to power on the FPGA.

[0026] In practical applications, the power management module is in standby state most of the time, that is, the delay button switch S1 is disconnected and the RS5C372A clock chip has not reached the start time, the standby static current is less than 0.001mA, the lithium battery BT1 is connected to the G pole of the NMOS tube Q1, and the NMOS is always in the on state. At this time, the output end of the RS5C372A clock chip (the S pole of the NMOS tube Q1) is at a high level, so the output end D pole of the NMOS tube Q1 is at a high level; at this time, the delay button switch S1 is in the off state, the G pole of the PMOS tube Q2 is at a high level, the PMOS tube Q2 is in the off state, and the power management module is in the off state.

[0027] In this embodiment, when the RS5C372A clock chip U1 reaches the start time, its output end (S pole of NMOS tube Q1) is at a low level, so the D pole of the output end of NMOS tube Q1 is also at a low level. At this time, the delay button switch S1 is in the disconnected state, the G pole of PMOS tube Q2 is at a low level, PMOS tube Q2 is in the on state, the power management module is in the on state, and the external power supply BT2 can normally power the test equipment. Among them, the start time can be set according to the actual situation; the external power supply BT2 can be selected as a municipal power supply or a battery. In this embodiment, the timing circuit can use two RS5C372A clock chips U1, that is, any RS5C372A clock chip U1 reaches the preset start time, which will cause the external power supply BT2 to power on the FPGA. After the test is completed, the FPGA resets the timing chip RS5C372A, and the external power supply BT2 stops powering on the FPGA.

[0028] In this embodiment, when the delay button switch S1 is in the closed state, the delay trigger signal is output, that is, the output end is at a low level, at this time, the G pole of the PMOS tube Q2 is also at a low level, the PMOS tube Q2 is in the on state, the power management module is in the open state, and the external power supply BT2 can normally power the external device; after the 10-minute delay time ends, the delay button switch S1 is automatically disconnected, the G pole of the PMOS tube Q2 returns to a high level, and the power management module returns to the standby state; the button switch can also be manually disconnected during the delay period. Among them, the delay time can be set according to actual conditions.

[0029] The low-power power management module of the present invention realizes two working modes, automatic start and manual start, in a test scenario through the RS5C372A clock chip U1 and the delay button switch S1, combined with the NMOS tube Q1 and the PMOS tube Q2, and performs long-term low-power management of the external power supply BT2 to solve the problem of excessive static current of the power management module under long-term working conditions and reduce the error of the test result.

[0030] The present invention also proposes a test device, which includes an FPGA and the above-mentioned low-power power management module; the specific structure of the low-power power management module refers to the above-mentioned embodiment. Since this test device adopts all the technical solutions of all the above-mentioned embodiments, it at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here one by one.

[0031] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A low-power power management module, applied to a test device, wherein the test device includes an FPGA, characterized in that: The low-power power management module includes a timing circuit, a trigger circuit, a first switch circuit and a second switch circuit, the timing switch circuit is connected to the first switch circuit, the first switch circuit is connected to the second switch circuit, the trigger circuit is connected to the second switch circuit, and the output end of the second switch circuit is connected to the FPGA; The timing circuit is used to output a corresponding start signal after reaching a set start time, turn on the first switch circuit and the second switch circuit, and output an external power supply to the FPGA; The trigger circuit is used to output a delayed trigger signal when triggered, turn on the second switch circuit, and output an external power supply to the FPGA.

2. The low power consumption power management module according to claim 1, characterized in that: The first switch circuit includes an NMOS transistor, and the second switch circuit includes a PMOS transistor.

3. The low power consumption power management module according to claim 1, characterized in that: The timing circuit includes an RS5C372A clock chip.

4. The low power consumption power management module according to claim 1, characterized in that: The trigger circuit includes a time-delay switch button.

5. The low power consumption power management module according to claim 1, characterized in that: The low-power consumption power management module further comprises a lithium battery, which is connected to the timing circuit and is used to provide working power to the timing circuit.

6. A testing device, characterized in that: The testing device comprises an FPGA and a low-power power management module as described in any one of claims 1-5.

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