Method and system for enabling PC to debug multiple FPGAs based on UDP / IP protocol

Abstract

The invention provides a method and system for enabling a PC to debug multiple FPGAs based on a UDP / IP protocol, and the method comprises the steps: respectively setting a receiving synchronous number and a sending synchronous number at an FPGA end, enabling a PC end to obtain the synchronous number through querying, storing the synchronous number, packaging the received synchronous number and a debugging command or the sent synchronous number and a debugging result into a network message when the debugging command or the debugging result is sent, and transmitting the network message to the PC end. Whether messages are lost or not is judged by judging whether receiving and sending synchronous numbers at the two ends are legal or not, when a debugging command message is legal, the debugging command message in a network message is converted into a debugging command, the FPGA is debugged, communication reliability is ensured, and due to the fact that UDP / IP and an upper layer protocol are completely achieved on the FPGA, the reliability of communication is improved. The whole debugging process does not need assistance of other processors, and debugging resources are saved.

Description

Technical Field

[0001] The invention belongs to the field of FPGA debugging, and in particular relates to a method and a system for enabling a PC to debug multiple FPGAs based on a UDP / IP protocol. Background Art

[0002] During FPGA development and use, online debugging, monitoring, and control functions are very important. During development, online debugging facilitates problem location. During use, the working status of the FPGA needs to be monitored.

[0003] The most common debugging method is to use the JTAG bus. You can debug by connecting the PC and FPGA using the JTAG line and debugging tools. You can also use the JTAG line to connect multiple FPGAs in series for debugging.

[0004] You can also use Xilinx's XVC tool, which is based on TCP and can debug FPGA over the network.

[0005] However, JTAG lines are not suitable for networking, dynamic addition and subtraction of devices, and when the FPGA of the entire chassis needs to be debugged, JTAG cannot meet the needs.

[0006] The XVC tool requires a processor to work. The processor runs the TCP protocol stack and the XVC protocol stack. This solution increases the cost. It is not suitable for FPGAs without embedded processors.

[0007] The open source solution github Alexforencich / xfcp can realize network debugging of FPGA. This solution is based on UDP and the message length is variable. This solution only needs FPGA to work and does not require an additional processor. However, this solution is based on UDP and does not guarantee reliable communication. The solution consumes a lot of resources. For debugging functions, excessive use of FPGA resources is not worth the loss. Summary of the invention

[0008] The main problem solved by the present invention is how to debug FPGA reliably with fewer resources, and provides a method and system for enabling PC to debug multiple FPGAs based on UDP / IP protocol.

[0009] In order to solve the above technical problems, the technical solution adopted is: A method for enabling a PC to debug multiple FPGAs based on a UDP / IP protocol comprises the following steps: Step 1: The PC and multiple FPGAs to be debugged communicate over a network based on the UDP / IP protocol, and each FPGA has an independent device number. Step 2: A receiving synchronization number counter and a sending synchronization number counter are set on the FPGA end to count the debugging command messages received through the network or the debugging result messages sent; Step 3: When the PC is connected to the FPGA to be debugged, the PC sends a message to query the device number, receiving synchronization number, and sending synchronization number of the FPGA. When the queried device number is consistent with the device number saved on the PC, the connection is successful, and the queried receiving synchronization number and sending synchronization number are stored on the PC. Step 4: After the connection is successful, the PC sends a debugging command, packages the debugging command and the receiving synchronization number into a network message, and transmits the network message to the FPGA to be debugged through the network based on the network protocol; Step 5: After checking that the network message is correct according to the transmission protocol, the FPGA also needs to check whether the receiving synchronization number in the network message is legal. If it is legal, the debugging command in the network message is converted into the debugging command of the FPGA internal debugging bus to debug the FPGA; Step 6: Pack the debugging result returned by the FPGA internal debugging bus together with the sending synchronization number into a network message, and transmit the network message to the PC through the network based on the UDP / IP protocol; Step 7: After checking that the network message is correct according to the transmission protocol, the PC side also needs to check the legitimacy of the sending synchronization number in the network message. If it is legal, the debugging is successful.

[0010] Furthermore, the method by which the FPGA checks whether the received synchronization number in the network message is legal is: When the PC sends a debug command message, the value of the receive synchronization number saved by the PC plus 1 is packaged together with the debug command into a message and sent to the FPGA. The FPGA checks whether the receive synchronization number in the message is the same as the value of the receive synchronization number inside the FPGA plus 1. If they are the same, it is a legal message. For legal messages, the receive synchronization number of the FPGA is increased by 1, and the debug command in the message is used to debug the FPGA.

[0011] Furthermore, the method for the PC to check the legitimacy of the sending synchronization number in the network message and the sending synchronization number of the PC is: when the FPGA sends the debugging result message, the internal sending synchronization number of the FPGA is increased by 1, and then the sending synchronization number of the FPGA and the debugging result are combined into a message and sent to the PC. The PC checks whether the value of the sending synchronization number in the message is the same as the value of the sending synchronization number of the PC plus 1. If they are the same, it is a legal message.

[0012] Further, the types of the network messages include: query node information message, node response information message, debugging command message, debugging result message, and resend debugging result instruction message; The query node information message includes a message type field; The node response information message includes: message type field, sending synchronization number, receiving synchronization number, device number, UDP checksum correction; The debugging command message includes: a message type field, a receiving synchronization number, debugging command data, and UDP checksum correction; The debugging result message includes: message type field, sending synchronization number, debugging command result, UDP checksum correction; The resending debugging result instruction message includes: a message type field, a UDP checksum and a correction.

[0013] Furthermore, when transmitting messages via UDP, the length of the messages is set to a fixed value, and messages of each type that are less than the fixed length are padded with zeros.

[0014] Furthermore, after the PC sends the debugging command message, the PC enters a waiting state. If the PC does not receive the debugging result message given by the FPGA within the specified time, the PC sends a query node information message. After receiving the node response information message from the FPGA, the PC determines the error location based on the consistency of the receiving synchronization number and sending synchronization number in the node response information message with the receiving synchronization number and sending synchronization number of the PC.

[0015] Further, the method for determining the error location based on the consistency of the receiving synchronization number and the sending synchronization number in the node response information message with the receiving synchronization number and the sending synchronization number of the PC end is: If the receiving synchronization number in the node response information message is the same as the receiving synchronization number of the PC, the debugging command message sent by the PC to the FPGA is lost, and the PC resends the debugging command message; If the send synchronization number in the node response information message is the same as the send synchronization number on the PC side, the FPGA does not send the debugging result message and the FPGA works abnormally; If the sending synchronization number in the node response information message is the same as the sending synchronization number of the PC side plus 1, the debugging result message from the FPGA side to the PC side is lost, and the PC side sends a resend debugging result instruction message. The FPGA side resends the debugging result message to the PC side. When the PC side sends the resend debugging result instruction message, the receiving synchronization numbers of the PC side and the FPGA side do not change. When the FPGA side resends the debugging result message, its sending synchronization number does not change.

[0016] Furthermore, after the PC and FPGA are successfully connected, the PC periodically sends a query node information message, and confirms the connection status based on whether the device number in the responded node information message is consistent; When the PC sends a node information query message but does not receive a node information message in response from the FPGA, it repeatedly sends the node information query message and executes the above steps until the upper limit of the number of repeated transmissions is reached, and then sends a network abnormality notification message.

[0017] Furthermore, the method by which the FPGA checks whether the network message is correctly verified according to the transmission protocol is: IP checksum is correct, UDP checksum is correct, and Ethernet CRC checksum is correct.

[0018] The present invention also provides a system for enabling a PC to debug multiple FPGAs based on a UDP / IP protocol, and implements each step of a method for enabling a PC to debug multiple FPGAs based on a UDP / IP protocol.

[0019] By adopting the above technical solution, the present invention has the following beneficial effects: The present invention provides a method and system for enabling a PC to debug multiple FPGAs based on a UDP / IP protocol. The method comprises the following steps: respectively setting receiving and sending synchronization numbers on an FPGA end and obtaining and saving the synchronization numbers on a PC end through query. When sending a debugging command or a debugging result, the receiving synchronization number and the debugging command or the sending synchronization number and the debugging result are packaged into a network message. By judging whether the receiving and sending synchronization numbers at both ends are legal, it is judged whether the message is lost. When the debugging command message is legal, the debugging command message in the network message is converted into a debugging command to debug the FPGA, thereby ensuring reliable communication. Since the UDP / IP and upper layer protocols are completely implemented on the FPGA, the entire debugging process does not require assistance from other processors, thereby saving debugging resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a schematic diagram of the connection process between PC and FPGA of the present invention; Figure 2 This is a schematic diagram of the data reading operation flow; Figure 3 This is a schematic diagram of the data writing operation flow. DETAILED DESCRIPTION

[0021] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] Figures 1 to 3 A specific embodiment of a method for enabling a PC to debug multiple FPGAs based on a UDP / IP protocol is shown, including the following steps: Step 1: The PC and multiple FPGAs to be debugged communicate over a network based on the UDP / IP protocol, and each FPGA has an independent device number.

[0023] In this embodiment, by using UDP / IP protocol networking, the PC end is connected to multiple FPGAs, and multiple FPGAs can be debugged. By making each FPGA end have an independent device number, it is convenient to confirm which FPGA is connected through the network.

[0024] Step 2: A receiving synchronization number counter and a sending synchronization number counter are set on the FPGA side to count the debugging command messages received through the network or the debugging result messages sent.

[0025] In this embodiment, by setting a receiving synchronization number counter and a sending synchronization number counter on the FPGA side, it is convenient to count the debugging commands received or the debugging results sent by the FPGA side.

[0026] Step 3: When the PC establishes a connection with the FPGA to be debugged, the PC sends a message to query the device number, receive synchronization number, and send synchronization number of the FPGA. When the queried device number is consistent with the device number saved on the PC, the connection is successful, and the queried receive synchronization number and send synchronization number are stored on the PC.

[0027] In this embodiment, the PC establishes a connection with the FPGA to be debugged by sending a query message from the PC, and the FPGA responds to the device number, receiving synchronization number and sending synchronization number of the current FPGA. When the device number in the node information of the response is consistent with the device number to be connected by the PC, the connection is successful. The queried receiving synchronization number and sending synchronization number are stored on the PC, so that the synchronization number can be used to determine whether the message is sent successfully when the debugging command is sent next.

[0028] Step 4: After the connection is successful, the PC sends a debugging command, packages the debugging command and the receiving synchronization number into a network message, and transmits the network message to the FPGA to be debugged through the network based on the network protocol.

[0029] In this embodiment, the types of network messages include: query node information message, node response information message, debugging command message, debugging result message, and resend debugging result instruction message; The query node information message includes a message type field; The node response information message includes: message type field, sending synchronization number, receiving synchronization number, device number, UDP checksum correction; The debugging command message includes: a message type field, a receiving synchronization number, debugging command data, and UDP checksum correction; The debugging result message includes: message type field, sending synchronization number, debugging command result, UDP checksum correction; The resending debugging result instruction message includes: a message type field, a UDP checksum and a correction.

[0030] The PC and FPGA can establish a connection by querying the node information message and the node response message. The UDP checksum correction bit can verify the accuracy of the message transmission process. By packaging the debug command data and the receiving synchronization number together into a message, it is convenient for the PC and FPGA to verify the legitimacy of the message. The message type field can be used to know the type of the transmitted message so as to make a corresponding information response. By setting the resend debug result command message, the last debug result message information can be re-sent when the debug result message sent by the FPGA is lost.

[0031] The debugging command data is used to operate the internal debugging of the FPGA, and the debugging result is used to feed back the debugging result obtained by the FPGA using the debugging data.

[0032] In this embodiment, when transmitting a message via UDP, the length of the message is set to a fixed value, and messages of each type that are less than the fixed length are padded with 0. In this embodiment, the length of the message, i.e., the upper layer protocol, is fixed to 18 bytes, a UDP checksum correction bit is set at the end of the upper layer protocol stack in 2 bytes, and the UDP checksum bit of the response message is set to a fixed value. By fixing the length and the last correction bit, the UDP / IP protocol can be tailored, and fewer LUT and register resources are required when implemented on an FPGA.

[0033] Since UDP and IP support packetization and other features, the complete implementation of the UDP / IP protocol on the FPGA consumes a lot of resources. By fixing the length of the upper layer protocol, the unnecessary UDP / IP features can be trimmed, and then a usable protocol stack that complies with the UDP / IP specification can be implemented with a small amount of resources. In this embodiment, the fixed length and checksum correction bits are used to facilitate the trimming of the protocol, making the protocol stack as small as possible.

[0034] Step 5: After checking that the network message is correct according to the transmission protocol, the FPGA also needs to check whether the receiving synchronization number in the network message is legal. If it is legal, the debugging command in the network message is converted into the debugging command of the FPGA internal debugging bus to debug the FPGA.

[0035] In this embodiment, when the FPGA receives a network message, it checks that the CRC, IP checksum, and UDP checksum set in the transmission protocol message are correct, and then checks the legitimacy of the receiving synchronization number and the receiving synchronization number in the FPGA.

[0036] In this embodiment, the method by which the FPGA checks the legitimacy of the receiving synchronization number in the network message and the receiving synchronization number in the FPGA is as follows: When the PC sends a debug command message, the value of the received synchronization number saved by the PC plus 1 is packaged together with the debug command into a message and sent to the FPGA. The FPGA checks whether the received synchronization number in the message is the same as the value of the received synchronization number inside the FPGA plus 1. If they are the same, it is a legal message. For legal messages, the received synchronization number of the FPGA is increased by 1, and the debug command in the message is used to debug the FPGA. By setting the synchronization number, the legitimacy is judged, which is simple, convenient and reliable, and ensures the accuracy of the debug command transmission. If they are not the same, it is an illegal message, indicating that the message is lost.

[0037] Step 6: Pack the debugging result returned by the FPGA internal debugging bus together with the sending synchronization number into a network message, and transmit the network message to the PC through the network based on the network protocol.

[0038] In this embodiment, the debugging command data and the receiving synchronization number are packaged together in the debugging command message, and the sending synchronization number and the debugging command result are packaged together into a message in the debugging result message, which can not only realize the transmission of the message, but also verify the legitimacy of the message through the synchronization number in the message.

[0039] Step 7: After checking that the network message is correct according to the transmission protocol, the PC side also needs to check the legitimacy of the sending synchronization number in the network message. If it is legal, the debugging is successful.

[0040] In this embodiment, the method for the PC end to check the legitimacy of the sending synchronization number in the network message and the sending synchronization number of the PC end is: when the FPGA end sends the debugging result message, the internal sending synchronization number of the FPGA is increased by 1, and then the sending synchronization number of the FPGA end and the debugging result are combined into a message and sent to the PC end. The PC end checks whether the value of the sending synchronization number in the message is the same as the value of the sending synchronization number of the PC end increased by 1. If they are the same, it is a legal message.

[0041] In this embodiment, after the PC sends the debugging command message, the PC enters a waiting state. If the PC does not receive the debugging result message given by the FPGA within the specified time, the PC sends a query node information message. After receiving the node response information message from the FPGA, the PC determines the error location based on the consistency between the receiving synchronization number and the sending synchronization number in the node response information message and the receiving synchronization number and the sending synchronization number of the PC. The method for determining the error location is: If the receiving synchronization number in the node response information message is the same as the receiving synchronization number of the PC, the debugging command message sent by the PC to the FPGA is lost, and the PC resends the debugging command message; If the send synchronization number in the node response information message is the same as the send synchronization number on the PC side, the FPGA does not send the debugging result message and the FPGA works abnormally; If the sending synchronization number in the node response information message is the same as the sending synchronization number of the PC side plus 1, the debugging result message from the FPGA side to the PC side is lost, and the PC side sends a resend debugging result instruction message. The FPGA side resends the debugging result message to the PC side. When the PC side sends the resend debugging result instruction message, the receiving synchronization numbers of the PC side and the FPGA side do not change. When the FPGA side resends the debugging result message, its sending synchronization number does not change.

[0042] This embodiment queries the node message information, sends the synchronization number and receives the synchronization number, so that the PC can judge the current communication situation according to the synchronization number information stored locally and the synchronization number information obtained on the FPGA, and executes the corresponding remedial operation according to the location of the communication failure so that the data can be correctly transmitted. The synchronization number is counted when the FPGA receives the debugging command and sends the debugging result, and the PC determines the error location by the consistency between the queried synchronization number and the saved synchronization number. By checking the sending synchronization number at both ends, it can be confirmed whether the FPGA has sent the message. By setting the receiving and sending synchronization numbers, each message sent and received is verified, ensuring the correctness of the message. By receiving the synchronization number and sending the synchronization number, the reliability of communication can be guaranteed, one is to ensure that the data arrives at the FPGA and PC, and the other is to ensure that the order of data arrival is correct. The simple UDP protocol cannot guarantee the arrival of data, nor can it guarantee that the data arrives in the order of sending.

[0043] In this embodiment, after the PC end is successfully connected to the FPGA, the PC end periodically sends a query node information message, and confirms the connection status based on whether the device number in the responded node information message is consistent; when the PC end sends the query node information message and does not receive the node information message responded by the FPGA, the query node information message is repeatedly sent and the above steps are performed until the upper limit of the number of repeated transmissions is reached, and a notification message of network abnormality is issued. By periodically sending the query node information message, it can be determined whether the FPGA is connected normally.

[0044] For example, the debug command message on the PC side is lost after being sent. The PC sends the debug command message, and after the message is lost, the FPGA side does not receive the message (receive synchronization number 0, send synchronization number 0), and the FPGA side does not respond. The PC side sends a query node information message, and the FPGA returns the node information message (receive synchronization number 0, send synchronization number 0). The PC side compares and finds that the receive synchronization number has not increased, indicating that the message from the PC to the FPGA is lost. The PC resends the debug command message, and the FPGA receives a legal message (receive synchronization number 1, send synchronization number 0). The FPGA debug function processes and sends the result. The FPGA sends the debug result message (receive synchronization number 1, send synchronization number 1). The PC receives the debug result message, and the debug operation is completed.

[0045] For another example, the debugging result message sent by FPGA is lost. First, PC sends a debugging command message, and the current state of FPGA is (receive synchronization number 0, send synchronization number 0). FPGA receives a legal message (receive synchronization number 1, send synchronization number 0). FPGA debug function processing, FPGA sends a debugging result message (receive synchronization number 1, send synchronization number 1). At this time, the message is lost, and PC does not receive the message. PC sends a query node information message, and FPGA returns a node response information message (receive synchronization number 1, send synchronization number 1). PC compares and finds that the send synchronization number is 1, indicating that the message is lost when FPGA to PC. PC sends a resend debugging result instruction message, and the current state of FPGA is (receive synchronization number 1, send synchronization number 1). FPGA receives the resend debugging result instruction message (receive synchronization number 1, send synchronization number 1. Because it is a resend debugging result instruction message, the receive synchronization number and the send synchronization number do not change). FPGA repeats the debugging result message sent before (receive synchronization number 1, send synchronization number 1). PC receives the debugging result message, and debugging is completed.

[0046] From the above two examples, we can know that by setting the receiving synchronization number and the sending synchronization number respectively, the PC side can determine at which link the message is lost. By setting the resending node information message in the message, the node information and synchronization number of the FPGA side can be known. By resending the data message, it can be sent again when the message is lost.

[0047] In this embodiment, for multiple FPGAs, by setting IP addresses and IP port interfaces, the PC accesses the corresponding FPGAs through the network. By connecting multiple FPGAs to the PC through the network, when the PC accesses the FPGA to be debugged, the corresponding FPGA can be connected through the IP address and IP PORT, without the need to use additional equipment.

[0048] The present invention also provides a system for enabling a PC to debug multiple FPGAs based on a UDP / IP protocol, and implements each step of a method for enabling a PC to debug multiple FPGAs based on a UDP / IP protocol.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for debugging multiple FPGAs using a PC based on UDP / IP protocol, characterized in that: The following steps are involved: Step 1: The PC and multiple FPGAs to be debugged communicate over a network based on the UDP / IP protocol, and each FPGA has an independent device number. Step 2: A receiving synchronization number counter and a sending synchronization number counter are set on the FPGA end to count the debugging command messages received through the network or the debugging result messages sent; Step 3: When the PC is connected to the FPGA to be debugged, the PC sends a message to query the device number, receiving synchronization number, and sending synchronization number of the FPGA. When the queried device number is consistent with the device number saved on the PC, the connection is successful, and the queried receiving synchronization number and sending synchronization number are stored on the PC. Step 4: After the connection is successful, the PC sends a debugging command, packages the debugging command and the receiving synchronization number into a network message, and transmits the network message to the FPGA to be debugged through the network based on the network protocol; Step 5: After checking that the network message is correct according to the transmission protocol, the FPGA also needs to check whether the receiving synchronization number in the network message is legal. If it is legal, the debugging command in the network message is converted into the debugging command of the FPGA internal debugging bus to debug the FPGA; Step 6: Pack the debugging result returned by the FPGA internal debugging bus together with the sending synchronization number into a network message, and transmit the network message to the PC through the network based on the UDP / IP protocol; Step 7: After checking that the network message is correct according to the transmission protocol, the PC side also needs to check the legitimacy of the sending synchronization number in the network message. If it is legal, the debugging is successful.

2. The method for enabling a PC to debug multiple FPGAs based on UDP / IP protocol according to claim 1, characterized in that: The method by which FPGA checks whether the received synchronization number in the network message is legal is: When the PC sends a debugging command message, the value of the received synchronization number saved by the PC plus 1 is packaged together with the debugging command into a message and sent to the FPGA. The FPGA checks whether the received synchronization number in the message is the same as the value of the received synchronization number inside the FPGA plus 1. If they are the same, it is a legal message. For legal messages, the receiving synchronization number of the FPGA side is increased by 1, and the debugging command in the message is used to debug the FPGA.

3. The method for enabling a PC to debug multiple FPGAs based on UDP / IP protocol according to claim 2, characterized in that: The method for the PC to check the legitimacy of the send synchronization number in the network message and the send synchronization number of the PC is: when the FPGA sends the debugging result message, the FPGA internal send synchronization number is increased by 1, and then the send synchronization number of the FPGA and the debugging result are combined into a message and sent to the PC. The PC checks whether the value of the send synchronization number in the message is the same as the value of the send synchronization number of the PC plus 1. If they are the same, it is a legal message.

4. The method for enabling a PC to debug multiple FPGAs based on UDP / IP protocol according to claim 3, characterized in that: The types of network messages include: query node information message, node response information message, debugging command message, debugging result message, and resend debugging result instruction message; The query node information message includes a message type field; The node response information message includes: message type field, sending synchronization number, receiving synchronization number, device number, UDP checksum correction; The debugging command message includes: a message type field, a receiving synchronization number, debugging command data, and UDP checksum correction; The debugging result message includes: message type field, sending synchronization number, debugging command result, UDP checksum correction; The resending debugging result instruction message includes: a message type field, a UDP checksum and a correction.

5. The method for enabling a PC to debug multiple FPGAs based on UDP / IP protocol according to claim 4, characterized in that: When transmitting messages through UDP, the length of the message is set to a fixed value, and messages of each type that are less than the fixed length are padded with 0.

6. The method for enabling a PC to debug multiple FPGAs based on UDP / IP protocol according to claim 5, characterized in that: After the PC sends the debugging command message, the PC enters a waiting state. If the PC does not receive the debugging result message given by the FPGA within the specified time, the PC sends a query node information message. After receiving the node response information message from the FPGA, the error is determined based on the consistency of the receiving synchronization number and sending synchronization number in the node response information message with the receiving synchronization number and sending synchronization number of the PC.

7. The method for enabling a PC to debug multiple FPGAs based on UDP / IP protocol according to claim 6, characterized in that: The method to determine the error location based on the consistency of the receive synchronization number and send synchronization number in the node response information message with the receive synchronization number and send synchronization number on the PC side is: If the receiving synchronization number in the node response information message is the same as the receiving synchronization number of the PC, the debugging command message sent by the PC to the FPGA is lost, and the PC resends the debugging command message; If the send synchronization number in the node response information message is the same as the send synchronization number on the PC side, the FPGA does not send the debugging result message and the FPGA works abnormally; If the sending synchronization number in the node response information message is the same as the sending synchronization number of the PC side plus 1, the debugging result message from the FPGA side to the PC side is lost, and the PC side sends a resend debugging result instruction message. The FPGA side resends the debugging result message to the PC side. When the PC side sends the resend debugging result instruction message, the receiving synchronization numbers of the PC side and the FPGA side do not change. When the FPGA side resends the debugging result message, its sending synchronization number does not change.

8. The method for enabling a PC to debug multiple FPGAs based on UDP / IP protocol according to claim 7, characterized in that: After the PC and FPGA are successfully connected, the PC periodically sends a query node information message and confirms the connection status based on whether the device number in the response node information message is consistent; When the PC sends a node information query message but does not receive a node information message in response from the FPGA, it repeatedly sends the node information query message and executes the above steps until the upper limit of the number of repeated transmissions is reached, and then sends a network abnormality notification message.

9. A method for enabling a PC to debug multiple FPGAs based on UDP / IP protocol according to any one of claims 1 to 8, characterized in that: The method by which FPGA checks whether the network message is correctly verified according to the transmission protocol is: IP checksum is correct, UDP checksum is correct, and Ethernet CRC checksum is correct.

10. A system for PC debugging multiple FPGAs based on UDP / IP protocol, characterized in that: Each step of the method for enabling a PC to debug multiple FPGAs based on the UDP / IP protocol as described in any one of claims 1 to 9 is implemented.

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