Method for generating network-on-chip model, electronic equipment and storage medium

Abstract

The invention discloses a method for generating a network-on-chip model, electronic equipment and a storage medium. The method comprises the following steps: reading a user-defined template; wherein the self-defined template comprises on-chip network topology structure information filled in a set format; the network-on-chip topological structure information at least comprises identification information of a plurality of routing nodes and path configuration information between the routing nodes; based on an analysis mode matched with a set format, analyzing the network-on-chip topological structure information in the self-defined template to obtain network-on-chip routing information; and generating a network-on-chip model based on the network-on-chip routing information. Through the scheme disclosed by the invention, the network-on-chip topological structure information can be automatically converted into the network-on-chip routing information which can be identified by a machine and is required for generating the network-on-chip model without excessive manual intervention. Therefore, a large amount of manpower and time cost is saved, and the generation efficiency of the model is effectively improved.

Description

Technical Field

[0001] The present disclosure generally relates to the field of computer technology. More specifically, the present disclosure relates to a method for generating an on-chip network model, and an electronic device and a computer-readable storage medium for executing the aforementioned method. Background Art

[0002] Network-on-Chip (NoC) is a network-based communication subsystem on an integrated circuit, which can usually be applied to system-on-chip (SoC) chips. Since the functions of traditional SoC chips are relatively simple, NoCs mostly use the Advanced Microcontroller Bus Architecture (AMBA). However, for some special scenarios (for example, for large chips, especially large chips for multi-core data processing), there are certain requirements for bandwidth and latency, which can no longer be met by AMBA bus interconnection alone. Therefore, it is necessary to explore a more complex NoC architecture to solve this problem.

[0003] In related technologies, considering the complexity of some chip designs (such as large chips) and the high trial and error costs, when defining the architecture, a NoC model is developed to simulate various NoC structures as a reference for architecture definition. However, currently, manual programming is mostly used to develop NoC models. This manual programming method requires relevant personnel to use their own experience and programming languages ​​to write the required models, which consumes a lot of manpower and time costs and cannot meet the needs of fast and efficient NoC model development.

[0004] In view of this, there is an urgent need to provide a solution for generating a network on chip model so that the NoC model can be generated efficiently. Summary of the invention

[0005] In order to at least solve one or more technical problems mentioned above, the present disclosure proposes a method, an electronic device and a storage medium for generating an on-chip network model in multiple aspects.

[0006] In a first aspect, the present disclosure provides a method for generating an on-chip network model, comprising: reading a custom template; wherein the custom template includes on-chip network topology information filled in a set format; the on-chip network topology information includes at least: identification information of multiple routing nodes, path configuration information between routing nodes; based on a parsing method matching the set format, parsing the on-chip network topology information in the custom template to obtain on-chip network routing information; based on the on-chip network routing information, generating an on-chip network model.

[0007] In some embodiments, the on-chip network topology information also includes: path delay configuration information between routing nodes.

[0008] In some embodiments, parsing the on-chip network topology information within the custom template to obtain the on-chip network routing information includes: generating a local routing lookup table for each routing node based on the identification information of multiple routing nodes parsed from the custom template and the path configuration information between the routing nodes, wherein the local routing lookup table for each routing node includes the identification information of the current node, the identification information of the destination node associated with the current routing node for communication, and the communication channel information between the current node and its corresponding destination node.

[0009] In some embodiments, parsing the on-chip network topology information within the custom template to obtain the on-chip network routing information also includes: generating a routing path information table containing path delay configuration information between routing nodes based on identification information of multiple routing nodes and path configuration information between routing nodes parsed from the custom template.

[0010] In some embodiments, the routing path information table includes identification information of communication-related routing nodes and their corresponding path delay configuration information, wherein the path delay configuration information includes default configuration information or custom configuration information.

[0011] In some embodiments, the method also includes: visually displaying the routing path information table, wherein the routing path information table includes an information configuration area that supports customized configuration of path delay configuration information; and in response to obtaining a user's configuration operation for the information configuration area, determining the path delay configuration information corresponding to the communication-related routing node according to the configuration operation.

[0012] In some embodiments, the setting format includes an Excel table format, and the Excel table includes an editing area for identification information of routing nodes and an editing area for path configuration information between routing nodes.

[0013] In some embodiments, the method further includes: performing performance simulation verification on the on-chip network model to obtain verification data; determining whether the verification data meets predetermined performance requirements; and adjusting the on-chip network model in response to determining that the verification data does not meet the predetermined performance requirements.

[0014] In some embodiments, wherein the on-chip network routing information includes a routing path information table containing path delay configuration information between routing nodes, adjusting the on-chip network model includes: adjusting the path delay configuration information in the routing path information table or the on-chip network topology information in the custom template to generate a new on-chip network model.

[0015] In some embodiments, the method also includes: pre-building the custom template, wherein the custom template includes a filling area for the on-chip network topology information, and the filling area includes at least a first area supporting information editing of the source node in the routing node, a second area supporting information editing of the destination node in the routing node, and a third area supporting information editing of the path node between the source node and the destination node.

[0016] In some embodiments, the method further includes: in response to a user's information input operation for the custom template, editing the information of the source node in the first area of ​​the filling area according to the information input operation, editing the information of the destination node in the second area of ​​the filling area, and editing the information of the path node in the second area of ​​the filling area.

[0017] In a second aspect, the present disclosure provides an electronic device, comprising: a processor; and a memory storing computer instructions for generating an on-chip network model, wherein when the computer instructions are executed by the processor, the electronic device executes the method described in the foregoing and following embodiments.

[0018] In a third aspect, the present disclosure provides a computer-readable storage medium, comprising program instructions for generating an on-chip network model, and when the program instructions are executed by a processor, the method according to the above and the following embodiments is implemented.

[0019] Through the method, electronic device and storage medium for generating an on-chip network model as provided above, the embodiment of the present disclosure reads and parses the on-chip network topology information in the custom template to generate an on-chip network model according to the on-chip network routing information obtained by parsing. It can be seen that the scheme disclosed herein can automatically convert the on-chip network topology information into the on-chip network routing information required for generating the on-chip network model that can be recognized by the machine without too much manual intervention in the process of generating the on-chip network model. As a result, not only a large amount of manpower and time costs are saved, but also the generation efficiency of the model is effectively improved. In addition, in the automatic generation process of the on-chip network model, the user is only required to provide the on-chip network topology information that is what you see is what you get, which does not require a high technical background for the user (such as relevant R&D personnel), effectively reducing the design threshold of the on-chip network model, making the generation scheme of the entire on-chip network model more universal.

[0020] In some embodiments, the scheme disclosed herein also proposes that after the on-chip network model is generated, the on-chip network model can be subjected to performance simulation verification to obtain verification data of the on-chip network model, and the verification data can be used to determine whether the on-chip network model needs to be adjusted, so that the obtained on-chip network model can be more in line with the chip design requirements.

[0021] In addition, the disclosed solution can also update the on-chip network model by adjusting the path delay configuration information or the on-chip network topology information in the custom template, so that users can adjust or regenerate NoC models of various topologies according to actual needs. The generation scheme of the entire on-chip network model is highly reusable and forms a closed-loop generation scheme for the NoC model. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] By reading the detailed description below with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0023] Figure 1 A flow chart showing a method for generating an on-chip network model according to an embodiment of the present disclosure is shown;

[0024] Figure 2 A flow chart showing a method for generating an on-chip network model according to another embodiment of the present disclosure is shown;

[0025] Figure 3 A schematic flow chart of a method for generating an on-chip network model according to another embodiment of the present disclosure is shown;

[0026] Figure 4 A schematic flow chart showing a method for generating an on-chip network model according to another embodiment of the present disclosure;

[0027] Figure 5 A schematic diagram of a visualization interface of a custom template according to an embodiment of the present disclosure is shown;

[0028] Figure 6 A schematic diagram of a visualization interface of a local routing lookup table according to an embodiment of the present disclosure is shown;

[0029] Figure 7 A schematic diagram showing a visualization interface of a routing path information table according to an embodiment of the present disclosure; and

[0030] Figure 8 A schematic structural block diagram of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0032] It should be understood that the terms "include" and "comprising" used in the specification and claims of the present disclosure indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0033] It should also be understood that the terms used in this disclosure are only for the purpose of describing specific embodiments and are not intended to limit the disclosure. As used in this disclosure and claims, the singular forms of "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" used in this disclosure and claims refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations.

[0034] As used in this specification and claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0035] Exemplary application scenarios

[0036] As it becomes increasingly difficult to reduce the size of transistors, one feasible way to integrate more functional units is to increase the chip area. However, an important obstacle that may appear when expanding the area of ​​a single chip is the "area wall". The area wall refers to the area limit of a single chip due to manufacturing technology and cost constraints. In order to design a chip that breaks through the area wall limit, the relevant technology proposes a novel chip form called "big chip". The term "big chip" refers to a chip with an area larger than the maximum exposure area of ​​the most advanced lithography machine currently. Big chips have two characteristics: First, the big chip has a large area, breaking the area limit of the stepper lithography machine, integrating a large number of transistors into one chip, and can exceed the number of transistors integrated on a single chip under current manufacturing technology. Second, the big chip consists of multiple functional bare cores, and several emerging semiconductor manufacturing technologies are used to integrate prefabricated bare cores into the big chip.

[0037] However, a large chip composed of more functional units means that a more complex NoC design is needed to connect the various functional units in series to ensure that the functional units of the chip can communicate normally. In this regard, as described in the background technology above, based on the complexity of the large chip design itself and the high trial and error cost, when defining the chip architecture, we have to consider in advance how to quickly select a more efficient and more suitable NoC architecture for the current design. In the related art, the NoC model is mostly designed by manual programming to simulate various NoC structures through the NoC model. However, this manual programming method usually uses C or System C language to develop NoC models, which not only requires the relevant personnel to have a strong technical background but also requires pure manual writing of the required models, which consumes a lot of manpower and time costs.

[0038] In order to solve the problems in the above scenarios, the inventors proposed a solution for generating an on-chip network model, which can use the on-chip network topology information in a custom template to automatically generate the required NoC model without too much manual intervention. This not only saves a lot of manpower and time costs, but also effectively improves the model generation efficiency.

[0039] The following combination Figure 1 to Figure 7 The scheme of the present disclosure is described in detail.

[0040] Figure 1 FIG. 1 is a flow chart of a method 100 for generating a network on chip model according to an embodiment of the present disclosure.

[0041] like Figure 1 As shown, at step S101, a custom template may be read, wherein the custom template includes network on chip topology information filled in a set format, and the network on chip topology information at least includes identification information of multiple routing nodes, path configuration information between routing nodes, and the like.

[0042] At step S102, the NoC topology information in the custom template may be parsed based on the aforementioned parsing method of setting format matching to obtain NoC routing information.

[0043] At step S103, a network on chip model may be generated based on the aforementioned network on chip routing information.

[0044] It should be noted that the on-chip network model in the disclosed scheme may include an on-chip network model applicable to any topology structure on the SoC chip, such as an on-chip network model of a mesh topology structure (referred to as Mesh structure), an on-chip network model of a torus topology structure, an on-chip network model of a butterfly topology structure, an on-chip network model of a binary tree topology structure, or an on-chip network model of other regular or irregular topology structures.

[0045] In practical applications, whether it is a regular or irregular topology structure of the on-chip network, it can essentially be regarded as a packet switching network based on routers, that is, the on-chip networks of various topologies can be understood as networks built based on routers. Therefore, after knowing the topology information of the on-chip network, the on-chip network topology information can be used to automatically build the on-chip network model.

[0046] Among them, the on-chip network topology information may specifically include but is not limited to the identification information of multiple routing nodes (such as the identification information of the source node, the identification information of the destination node, etc.), the path configuration information between the routing nodes (such as whether there are intermediate nodes between the source node and the destination node, the identification information of these intermediate nodes, etc.), and of course, some other information that can reflect the topological structure. These on-chip network topology information are relatively easy to obtain for relevant personnel (users). When the user needs to build a network-on-chip model to be generated (such as the network-on-chip model of the various topological structures mentioned above), the on-chip network topology information about the on-chip network model can be obtained first, and then the on-chip network topology information can be carried by a custom template. In the process of generating the on-chip network model, the custom template can be automatically read, and the corresponding parsing method can be used to parse the on-chip network topology information, so as to obtain machine-recognizable and understandable on-chip network routing information based on the on-chip network topology information, and then the on-chip network routing information is used to realize the automatic construction of the on-chip network model.

[0047] In addition, it should be noted that the scheme disclosed herein does not limit the specific structure of the custom template, and any information carrier that can save, record or visually present the on-chip network topology information can be used. For example, the custom template can be in a table form, a file form, a drawing board form, a dialog box form, etc. In the actual application process, the custom template can be manually configured in real time or in advance, or it can be configured in an automated manner (for example, automatically configured by some programs or scripts, or configured by a large language model according to user needs, etc.). After completing the custom template configuration, when the on-chip network model to be generated needs to be constructed later, the on-chip network topology information of the on-chip network model can be carried by the custom template. Specifically, the on-chip network topology information can be input to the custom template in a format supported by the custom template (i.e., a setting format). Among them, the setting format may include but is not limited to a combination of any one or more of the text input format, the voice input format, and the picture input format. When different setting formats are used to fill in the on-chip network topology information to the custom template, the subsequent need to use a parsing method matching the setting format to parse these on-chip network topology information.

[0048] Therefore, in the process of generating the on-chip network model, the on-chip network topology information can be automatically converted into on-chip network routing information that can be recognized and understood by the machine without too much human intervention. Compared with the traditional way of manually creating on-chip network models, it not only saves a lot of manpower and time costs, but also effectively improves the efficiency of model generation. In addition, the user is only required to provide the on-chip network topology information in a WYSIWYG manner, which does not require a high technical background from the user, effectively lowering the design threshold of the on-chip network model and making the entire on-chip network model generation scheme more universal.

[0049] Figure 2 FIG. 2 is a flow chart of a method 200 for generating an on-chip network model according to another embodiment of the present disclosure. It should be noted that the method 200 can be understood as Figure 1 Therefore, the above combined with Figure 1 The relevant description also applies to the following.

[0050] like Figure 2As shown, at step S201, a custom template including on-chip network topology information is read. As described above, the on-chip network topology information may include, but is not limited to, identification information of multiple routing nodes, path configuration information between routing nodes, etc. Among them, the identification information of multiple routing nodes may include identification information of source nodes and identification information of destination nodes, and the path configuration information between routing nodes may include path information between the source node and the destination node, such as identification information of all intermediate nodes that the source node needs to pass through to reach the destination node, etc.

[0051] In actual application, the custom template may be pre-built before step S201. The custom template may include multiple forms such as table form, file form, dialog form, etc., and the specific layout of each form may also include multiple forms. The forms of the custom templates are different and the setting formats (such as text, picture, voice, etc.) supported by each form of the custom template may be the same or different.

[0052] In one embodiment, the custom template may specifically include a fill-in area for the on-chip network topology information, and the fill-in area includes at least a first area for supporting the information editing of the source node in the routing node, a second area for supporting the information editing of the destination node in the routing node, and a third area for supporting the information editing of the path node between the source node and the destination node. In this implementation scenario, the user can input the on-chip network topology information into the custom template. Specifically, in response to the user's information input operation for the custom template (such as a text input operation, a voice input operation, or a picture input operation, etc.), according to the information input operation, the information of the source node is edited in the first area of ​​the above-mentioned fill-in area, the information of the destination node is edited in the second area of ​​the fill-in area, and the information of the path node is edited in the second area of ​​the fill-in area. So far, the input of the on-chip network topology information is completed. In this embodiment, the custom template is provided with a fill-in area for various information, so as to guide the user to fill in the relevant information in a standardized manner based on different fill-in areas, so as to facilitate the subsequent machine to efficiently extract and parse information from the custom template. Of course, the fill-in area of ​​the custom template is not limited to the first to third areas mentioned above, and can also include a fill-in area for the path delay configuration information, and the specific layout of the custom template can be adjusted according to the application requirements.

[0053] As an example, a custom template may include an Excel table, and the corresponding setting format may include an Excel table format. In this case, the Excel table may include, but is not limited to, an editing area for the identification information of the routing node and an editing area for the path configuration information between the routing nodes. The user can directly input the on-chip network topology information in the Excel table. Among them, the editing area for the identification information of the routing node supports the editing of the source node and the destination node in the routing node, and the editing area for the path configuration information supports the editing of the intermediate nodes between the source node and the destination node. Compared with other forms of templates, the Excel table has a simpler and clearer structure, which is convenient for user operation and facilitates the effective collection of information.

[0054] In another embodiment, a predefined topology structure template is also displayed on the custom template, and the on-chip network topology structure information is generated according to the interactive information for the topology structure template input by the user. In this embodiment, considering that some topologies commonly used in the on-chip network model are very regular network structures, these regular topologies may only differ in size or size, and some commonly used topologies can be set in advance on the custom template, and the user only needs to adjust the specific size, and the user does not need to enter the specific structural information of these topologies one by one (for example, which routing nodes are included, which nodes are connected between these routing nodes, etc.), and the user only needs to set some interactive information such as size and size for the topology structure template, and the background can generate topology structure information based on these interactive information, thereby greatly simplifying user operations and improving user experience.

[0055] As an example, the interface of the custom template can display "options" of on-chip network models of several different topological structures (i.e., topological structure templates) such as mesh structure, torus topology structure, binary tree structure, etc. When the user clicks on any on-chip network model in the "options", the interactive information input by the user through the clicking operation (i.e., the selection result information of the on-chip network model in the options) can be obtained.

[0056] For another example, the custom template (e.g., a custom template in the form of a dialog box) may also display an information input bar, through which the user may input keywords about the type of the on-chip network model (e.g., a Mesh structure), or directly input the type of model to be built (e.g., describing the specific structure of the model, the number of nodes, etc.), or directly input the on-chip network topology information, etc. The information input bar may support input methods in the form of text, voice, or pictures. Thus, the interactive information input by the user may be obtained through the information input bar.

[0057] For example, the interface of the above-mentioned custom template can also simultaneously display an information input bar and "options" containing several on-chip network models with different topologies. The user can directly select the desired on-chip network model through the options, or when none of the models in the "options" meet the user's needs, the interactive information can be entered through the information input bar. Of course, you can also ignore the "options" on the interface and directly enter the interactive information through the information input bar. It should be noted that the description of the interface of the custom template here is only an exemplary description. The scheme disclosed in this disclosure does not limit the specific layout and display content of the interface of the custom template, and it can be set in combination with the actual application scenario and interaction needs.

[0058] When the interactive information input by the user for the aforementioned custom template interface is obtained, the on-chip network topology information can be determined based on the interactive information. As mentioned above, the interactive information may include the selection result of the on-chip network model in the "Options", the type keyword of the on-chip network model, or the information that can be included in the information input field, etc. At this time, the on-chip network topology information needs to be determined based on the interactive information.

[0059] In actual applications, some information entered in the custom template (such as relevant information entered in the first area to the third area of ​​the custom template or the on-chip network topology information entered in the information input bar) can be directly used as the on-chip network topology information, while other interactive information entered by the user in the custom template (such as the selection results of the on-chip network model in the "Options", the type keywords of the on-chip network model, etc.) needs to be further processed to obtain the on-chip network topology information.

[0060] Specifically, in some embodiments, the type of the on-chip network model can be determined according to the interactive information input in the aforementioned custom template, and then the acquisition path of the on-chip network topology information can be determined according to the type of the on-chip network model, and then the on-chip network topology information is acquired based on the acquisition path of the on-chip network topology information. This embodiment distinguishes the acquisition path based on the type of the on-chip network model. Generally speaking, on-chip network models can be divided into regular models and irregular models, among which regular models such as Mesh structures are easy to obtain through some public information, while irregular models mostly require user customization. Therefore, the acquisition path of the on-chip network topology information can be divided according to the type of the on-chip network model, which can meet the different input requirements of users and help improve the efficiency of acquiring the on-chip network topology information.

[0061] As an example, in response to determining that the on-chip network model to be generated is a rule model, it is searched whether the topology structure information of the model of the same scale as the on-chip network model is pre-stored. In this embodiment, the network structure of the rule model is usually fixed and variable, and some commonly used rule models (such as Mesh structure models, etc.) and corresponding topology structure information can be pre-stored. When the on-chip network model to be generated belongs to these commonly used rule models, the topology structure information of the model of the same scale as the on-chip network model can be directly searched at the remote and / or local ends, and the found topology structure information is determined as the topology structure information of the on-chip network model. In this implementation scenario, the user does not need to enter the specific on-chip network topology structure information, but only needs to simply enter the type keyword (such as Mesh structure) and other information of the on-chip network model in the custom template, while simplifying the user operation, the required on-chip network topology structure information can be efficiently obtained.

[0062] In response to not finding the on-chip network topology information of a model of the same scale as the on-chip network model or determining that the on-chip network model is an irregular model, the information input bar located in the custom template is visually displayed to input the topology information of the on-chip network model based on the information input bar. In this embodiment, if the topology information of a model of the same scale as the on-chip network model is not found at the local end and / or the remote end, or the on-chip network model is an irregular model, the user is required to customize the on-chip network model. At this time, an information input bar can be displayed to the user, and the information input bar can guide the user to input the topology information of the on-chip network model. In this implementation scenario, the user can input the required on-chip network topology information through the information input bar, realize the customization of on-chip network models of various topologies, and meet the different usage needs of users.

[0063] At this point, the reading of the custom template is completed to obtain the on-chip network topology information. It should be noted that the above description of the custom template and the on-chip network topology information is only an exemplary description, and the scheme disclosed herein is not limited to this. For example, it is also possible to combine web crawler technology to search online in real time for the topology information of a model of the same scale as the on-chip network model, or combine artificial intelligence dialogue and large language model technology to output the topology information of a model of the same scale as the on-chip network model.

[0064] After obtaining the on-chip network topology information, the on-chip network topology information in the custom template may be parsed according to steps S202 and S203 to obtain the on-chip network routing information.

[0065] In step S202, a local routing lookup table for each routing node is generated based on the identification information of multiple routing nodes parsed from the custom template and the path configuration information between the routing nodes. The local routing lookup table for each routing node includes the identification information of the current node, the identification information of the destination node associated with the current routing node, and the communication channel information between the current node and the destination node corresponding to the current node.

[0066] In this embodiment, a local routing lookup table about each routing node can be generated for the routing node, so as to store the current routing node, the next node or neighbor node connected to the current routing node, and the exit information of the current routing node (that is, the communication channel information) through the local routing lookup table. Each routing node can build a local network based on its own corresponding local routing lookup table, and the local networks corresponding to all routing nodes can eventually form a complete topology network. Compared with the need to store a complete routing lookup table (or a global routing lookup table) at each node in the related art, the solution of this embodiment can effectively reduce the area and power consumption of the topology network by storing the local routing lookup table of the node at each routing node.

[0067] In step S203, a routing path information table including path delay configuration information between routing nodes is generated according to identification information of multiple routing nodes and path configuration information between routing nodes parsed from the custom template.

[0068] In this embodiment, the on-chip network topology information is not limited to the identification information of multiple routing nodes and the path configuration information between routing nodes, but also includes the path delay configuration information between routing nodes. Among them, the routing path information table may include the identification information of the communication-related routing nodes and their corresponding path delay configuration information, and the path delay configuration information includes default configuration information or custom configuration information.

[0069] After the identification information of multiple routing nodes and the path configuration information between routing nodes are parsed from the custom template, a routing path information table can be generated based on the identification information of multiple routing nodes and the path configuration information between routing nodes. For example, when the routing path information table is obtained, the routing path information table can be visually displayed to the user, wherein the routing path information table contains the initial value of the path delay configuration information, and supports editing operations such as modification and filling of the initial value. The initial value can be a default value (that is, default configuration information) or blank, and the user can selectively adjust the initial value according to needs (that is, custom configuration information).

[0070] In some embodiments, when the path delay configuration information needs to be customized, a routing path information table can be visually displayed, wherein the routing path information table includes an information configuration area that supports customized configuration of the path delay configuration information. Then, in response to obtaining a configuration operation (such as modification, filling, etc.) of the user for the information configuration area, the path delay configuration information corresponding to the routing node related to the communication is determined according to the configuration operation.

[0071] At this point, the parsing of the on-chip network topology information is completed to obtain the on-chip network routing information. The on-chip network routing information may specifically include information in the local routing lookup table of each routing node and information in the routing path information table.

[0072] At step S204, a network on chip model is generated based on the network on chip routing information, that is, the network on chip model is generated according to the information in the local routing lookup table of each routing node and the information in the routing path information table.

[0073] In practical applications, the above steps S201 to S204 can all be specifically executed by a predefined model generator. That is, the predefined model generator can read the custom template, and based on the parsing method of setting format matching, parse the on-chip network topology information in the custom template to obtain the on-chip network routing information, and then generate the on-chip network model based on the on-chip network routing information. In this embodiment, the predefined model generator can be understood as a "modular" script that can support model generation, or it can be understood as a script written in machine language that can generate an on-chip network model. In some embodiments, the model generator can be specifically designed using a high-level machine language such as Python.

[0074] In practical applications, the generated on-chip network model needs to be verified to determine whether its performance meets the design requirements, and if it does not meet the design requirements, it needs to be further optimized or adjusted. Specifically, the performance parameters of the aforementioned on-chip network model can be obtained, and then the on-chip network model can be selectively adjusted according to the performance parameters. Figure 3 The process of optimizing or adjusting the generated on-chip network model is described.

[0075] Figure 3 FIG. 3 is a flow chart of a method 300 for generating an on-chip network model according to another embodiment of the present disclosure. It should be noted that the method 300 can be understood as Figure 1 Method 100 or Figure 2 Therefore, the above combined with the method 200 Figure 1 and Figure 2 The relevant description in also applies to the following.

[0076] like Figure 3 As shown, at step S301, a network on chip model may be generated. In this embodiment, topology information about the network on chip model to be generated may be obtained, and then the model generator determines routing information of the network on chip model according to the topology information, and then generates the network on chip model according to the routing information. For the specific generation process of the network on chip model, please refer to Figure 1 as well as Figure 2 The relevant description in will not be repeated here.

[0077] In step S302, a performance simulation is performed on the above-mentioned network on chip model to obtain verification data.

[0078] In some embodiments, the aforementioned on-chip network model may specifically include an on-chip network model simulated by a hardware description language (such as Verilog language, etc.). In this embodiment, the on-chip network model simulated by the hardware description language can better simulate the essence of the circuit, so that the performance parameters obtained after subsequent verification are closer to the actual circuit structure, ensuring the accuracy of the performance parameters. In some embodiments, the hardware description language is not limited to the Verilog language, and may also include languages ​​such as HDL and VHDL. Of course, the scheme disclosed in this disclosure does not limit the specific simulation language of the on-chip network model, and may also use C or System C language, etc. according to the requirements for model design.

[0079] When the generated network-on-chip model adopts a network-on-chip model simulated by a hardware description language, the network-on-chip model simulated by the hardware description language can be subjected to performance simulation verification to obtain verification data. For example, the network-on-chip model can be subjected to UVM (Universal Verification Methodology) simulation and testing to obtain simulation data of the network-on-chip model.

[0080] At step S303, it can be determined whether the verification data meets the predetermined performance requirements. In some embodiments, performance parameters are extracted from the aforementioned verification data. For example, the verification data can be screened, analyzed, etc. to extract performance parameters such as path delay, port delay, path bandwidth utilization, and port bandwidth utilization from the verification data. Then, it is determined whether these performance parameters meet the predetermined performance requirements. When these performance parameters meet the predetermined performance requirements, it is determined that the verification data meets the predetermined performance requirements, otherwise, it is determined that the verification data does not meet the predetermined performance requirements.

[0081] At step S304, in response to determining that the verification data does not meet the predetermined performance requirements, the on-chip network model can be adjusted. If the performance parameters in the verification data meet the predetermined performance requirements, it means that the generated on-chip network model meets the user requirements and does not need to be adjusted. In response to the performance parameters in the verification data not meeting the predetermined performance requirements, the path delay configuration information in the routing path information table or the on-chip network topology information in the custom template can be adjusted to generate a new on-chip network model. In the related art, the user needs to develop the on-chip network model through manual programming, and once it is found that the on-chip network model does not meet the expected design requirements, it is necessary to manually rewrite the required model. The whole process is very cumbersome and has poor reusability. However, this embodiment can update the on-chip network model by adjusting the path delay configuration information or the on-chip network topology information, so that the user can adjust or regenerate the NoC model of various topological structures according to actual needs, which not only effectively simplifies the user operation, but also the generation scheme of the entire on-chip network model has strong reusability, forming a closed-loop generation scheme of the NoC model.

[0082] Figure 4 FIG. 4 is a flow chart of a method 400 for generating an on-chip network model according to another embodiment of the present disclosure. It should be noted that the method 400 can be understood as Figure 1 to Figure 3 Therefore, the above combined Figure 1 to Figure 3 The relevant description also applies to the following.

[0083] like Figure 4 As shown, at step S401, the topology information table (i.e., custom template) of the on-chip network model (referred to as NoC model) can be filled in. As mentioned above, the custom template can be visually displayed to the user, and the "options" of several on-chip network models with different topological structures such as Mesh structure, torus topology structure, binary tree structure, etc. can be displayed on the interface of the custom template (i.e., multiple predefined topology templates are displayed). After the user clicks on any on-chip network model in the "options", the topology information of the model of the same scale as the on-chip network model can be searched from the local end or remote end, so as to obtain the on-chip network topology information in a "one-click" manner. For another example, the custom template can also be visually displayed to the user, and the user can be guided to input the topology information of the on-chip network model through the custom template.

[0084] As an example, a custom template can use a table structure, such as Figure 5 The topology information table in Excel format is shown. Figure 5 In the topology information table shown, the routing node information of the on-chip network model to be generated can be filled in (for example Figure 5M0, M1, M2, S1, S2, ... in ), path information of routing nodes (e.g. Figure 5 "X" in the figure). Among them, the area where "M0, M1, M2, S1, S2, ..." is located is the routing node filling area, and the area where "X" is located is the path filling area. All routing nodes involved in the topological network (such as source nodes, destination nodes) can be filled in the routing node filling area, and the path configuration information between the source node and the destination node (such as information of each intermediate node) can be filled in the path filling area. As an example, assuming that "M0" is the source node and "S2" is the destination node, the path configuration information between "M0" and "S2" can be expressed by "0 / 1 / 2" and other methods, where "0 / 1 / 2" means that the "M0" node needs to pass through the path node "M1" to reach "S2". The description of the way to fill in the routing nodes and the way to fill in the paths here is only an exemplary description, and can be adjusted according to needs in actual applications. It should be understood that no matter how the routing node and path configuration information is filled in or how the identification information of the routing node and path configuration information is represented, it is to indicate which routing nodes are included in the required on-chip network topology information, and which intermediate nodes need to be passed between the source node and the destination node in the routing node, etc. It should be noted that the description of the information input template in this embodiment is only an exemplary description, and the solution disclosed herein is not limited thereto.

[0085] return Figure 4 At step S402, the on-chip topology information can be used as input information of the model generator, and the model generator is used to parse the on-chip topology information to generate a local routing lookup table for each routing node and a routing path information table including path delays. As an example, Figure 6The local route lookup table stored at a certain routing node is shown. Among them, A, B, and C in the local route lookup table represent different columns of the local route lookup table, "Src" represents the source node, and "Des" represents the destination node. For example, the local route lookup table of the routing node is stored at any routing node (such as "M0"), and the local route lookup table may contain the current node information (such as the current node number or identification, etc.), the next node or neighbor node information that has a communication connection relationship with the current node (such as the label of the next node or neighbor node), and the exit information (or communication channel information) of the current node. For example, the current node is "M0", the next node is "S1", "S2", "S3", etc., and the current node "M0" has a total of 5 exits or communication channels (such as a / b / c / d / e), and can reach "S1" through channel a, reach "S2" through channel c, reach "S3" through channel e, etc. That is, the local route lookup table at the current node "M0" only needs to record the node information of the current node itself and related path information (such as the next node of the communication connection and the exit information, etc.), and does not need to record other nodes that have no communication relationship. It should be noted that the description of the local route lookup table here is only an exemplary description.

[0086] return Figure 4 At step S403, the routing node path delay may be initialized. In some embodiments, the routing path information table may display an initial value of the path delay, and support editing of the initial value.

[0087] As an example, Figure 7 A specific form of a routing path information table is shown. A, B, and C in the routing path information table represent different columns of the local routing lookup table, "Src" represents the source node, "Des" represents the destination node, and "Pipe" represents the path delay configuration information. Specifically, the routing path information table can be visually displayed to the user. The "Pipe" column in the routing path information table gives the initial value of the path delay. The user can initialize these initial values, such as keeping the initial value unchanged or editing the initial value that needs to be adjusted. For example, in Figure 7In the routing path information table, the source nodes (e.g., M0, M1, M10, ...), destination nodes (R0, R1, R10, ...) and path delay values ​​(0, 4, 2, ...) involved in the topological network can be recorded. Among them, the source nodes and destination nodes can be stored in the table in the form of node numbers, which can be specifically extracted from the acquired topological structure information. The initial value of the path delay value can be generated by default, for example, the path delays between all nodes can be defaulted to be the same (such as all "1"). Of course, the path delay value can be edited, and the user can adjust the path delay value according to actual needs to meet customized needs. It should be noted that the description of the routing path information table here is only an exemplary description, and the scheme disclosed herein is not limited to this. The specific format of the routing path information table can be set according to application or interaction requirements.

[0088] return Figure 4 At step S404, the NoC model is generated using the information in the local routing lookup table of each routing node and the routing path information table. In this embodiment, any language can be used to simulate the NoC model according to the model design requirements, for example, the NoC model can be simulated using Verilog language, VHDL language, C language, etc.

[0089] At step S405, the generated NoC model can be simulated and tested. In some embodiments, a NoC model simulated by a hardware description language such as Verilog language can be generated. For this type of NoC model, at step S406, UVM simulation verification and testing can be performed to obtain test results (such as verification data), and then the verification data is processed to extract performance parameters of the current NoC model. For example, performance parameters such as path delay, port delay, path bandwidth utilization, port bandwidth utilization, etc.

[0090] Next, at step S407, it can be determined whether the obtained performance parameters meet the design requirements. For example, it can be determined manually whether the performance parameters meet the design requirements, or it can be determined by presetting corresponding design standard data to automatically compare whether the performance parameters meet the design standard data. When the obtained performance parameters do not meet the design requirements, the NoC model can be modified through step S408 or S409.

[0091] At step S408, the NoC model can be modified by modifying the path delay between routing nodes. For example, a routing path information table can be displayed to the user, and the user can adjust the value of the path delay configuration information in the routing path information table to modify the path delay between routing nodes. After the modification of the path delay between routing nodes is completed, a new NoC model can be regenerated using the information in the local routing lookup table and the adjusted routing path information table, and subsequent verification operations can be continued until a NoC model that meets the design requirements is obtained.

[0092] At step S409, the NoC model may be modified by modifying the NoC model's on-chip network topology information. For example, the NoC model may be displayed to the user. Figure 5 In the topology information table shown, the user re-fills or adjusts the on-chip network topology information. After completing the re-filling or adjustment of the on-chip network topology information, the subsequent NoC model generation and verification operations can be continued until a NoC model that meets the design requirements is obtained.

[0093] The above-mentioned scheme disclosed herein can quickly generate a NoC model of the desired topology structure based on the on-chip network topology information filled in the Excel table, so that the NoC model generation scheme has a high degree of reusability and flexibility, and can quickly respond to changes in the NoC scheme, so that in the chip scheme formulation stage, the designer can obtain performance information through model simulation in advance to assist in the decision-making of the NoC scheme, which provides a good pre-research function for the designer. In addition, the performance indicators of the later design can be perceived in advance in the chip architecture definition stage to facilitate the definition of a more suitable architecture scheme, reduce the difficulty of determining the chip architecture, and further reduce the uncertainty caused by inappropriate architecture schemes in the subsequent chip design process. In addition, the NoC model generation scheme is mainly completed by script automation, which can reduce the workload of manpower, avoid a large amount of repetitive manpower work, and at the same time reduce the uncertainty errors introduced by human factors, and reduce the development time and manpower and material investment of chip design.

[0094] Figure 8 Schematically shows a schematic block diagram of an electronic device 800 according to an embodiment of the present disclosure. Figure 8As shown, the electronic device 800 may include a processor 801 and a memory 802. The memory 802 stores computer instructions for generating an on-chip network model. When the computer instructions are executed by the processor 801, the electronic device 800 executes: reading a custom template; wherein the custom template includes on-chip network topology information filled in a set format; the on-chip network topology information at least includes: identification information of multiple routing nodes, and path configuration information between routing nodes; based on the parsing method matching the set format, the on-chip network topology information in the custom template is parsed to obtain the on-chip network routing information; based on the on-chip network routing information, the on-chip network model is generated.

[0095] Optionally, the on-chip network topology information also includes: path delay configuration information between routing nodes.

[0096] Optionally, parsing the on-chip network topology information within the custom template to obtain the on-chip network routing information includes: generating a local routing lookup table for each routing node based on the identification information of multiple routing nodes parsed from the custom template and the path configuration information between the routing nodes, wherein the local routing lookup table for each routing node includes the identification information of the current node, the identification information of the destination node associated with the current routing node for communication, and the communication channel information between the current node and its corresponding destination node.

[0097] Optionally, parsing the on-chip network topology information within the custom template to obtain the on-chip network routing information also includes: generating a routing path information table containing path delay configuration information between routing nodes based on identification information of multiple routing nodes and path configuration information between routing nodes parsed from the custom template.

[0098] Optionally, the routing path information table includes identification information of communication-related routing nodes and their corresponding path delay configuration information, wherein the path delay configuration information includes default configuration information or custom configuration information.

[0099] Optionally, the method also includes: visually displaying the routing path information table, wherein the routing path information table includes an information configuration area that supports customized configuration of path delay configuration information; and in response to obtaining a user's configuration operation for the information configuration area, determining the path delay configuration information corresponding to the communication-related routing node according to the configuration operation.

[0100] Optionally, the setting format includes an Excel table format, and the Excel table includes an editing area for identification information of routing nodes and an editing area for path configuration information between routing nodes.

[0101] Optionally, the method further includes: performing performance simulation verification on the on-chip network model to obtain verification data; determining whether the verification data meets predetermined performance requirements; and adjusting the on-chip network model in response to determining that the verification data does not meet the predetermined performance requirements.

[0102] Optionally, the on-chip network routing information includes a routing path information table containing path delay configuration information between routing nodes, and adjusting the on-chip network model includes: adjusting the path delay configuration information in the routing path information table or the on-chip network topology information in the custom template to generate a new on-chip network model.

[0103] Optionally, the method also includes: pre-building the custom template, wherein the custom template includes a filling area for the on-chip network topology information, and the filling area includes at least a first area supporting information editing of the source node in the routing node, a second area supporting information editing of the destination node in the routing node, and a third area supporting information editing of the path node between the source node and the destination node.

[0104] Optionally, the method also includes: in response to a user's information input operation for the custom template, editing the information of the source node in the first area of ​​the filling area according to the information input operation, editing the information of the destination node in the second area of ​​the filling area, and editing the information of the path node in the second area of ​​the filling area.

[0105] Through the above implementation, the electronic device can automatically generate the required on-chip network model by using various on-chip network topology information without too much manual intervention in the process of generating the on-chip network model. As a result, not only a lot of manpower and time costs are saved, but also the generation efficiency of the model is effectively improved. In addition, only the on-chip network topology information needs to be provided, which does not require a high technical background from the user, effectively lowering the design threshold of the on-chip network model, making the generation scheme of the entire on-chip network model more universal.

[0106] It should be noted that the specific contents of the method steps of the electronic device are combined with the above Figure 1 to Figure 4 The specific implementation of the method for generating an on-chip network model described is the same or similar, so it will not be repeated here.

[0107] In addition, the present disclosure also provides a computer-readable storage medium in which program instructions are stored, and the program instructions are configured to be executed at runtime. Figure 1 to Figure 4 The method for generating a network-on-chip model is shown.

[0108] Specifically, in this embodiment, the above-mentioned storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store computer programs.

[0109] Although multiple embodiments of the present disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art may think of many changes, modifications, and alternatives without departing from the thought and spirit of the present disclosure. It should be understood that in the process of practicing the present disclosure, various alternatives to the embodiments of the present disclosure described herein may be adopted. The attached claims are intended to define the scope of protection of the present disclosure, and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for generating a network-on-chip model, characterized in that: include: Reading a custom template; wherein the custom template includes on-chip network topology information filled in a set format; the on-chip network topology information at least includes: identification information of multiple routing nodes, and path configuration information between routing nodes; Based on the parsing method matched with the set format, the on-chip network topology information in the custom template is parsed to obtain the on-chip network routing information; Based on the on-chip network routing information, a on-chip network model is generated.

2. The method according to claim 1, characterized in that: The on-chip network topology information also includes: path delay configuration information between routing nodes.

3. The method according to claim 1, characterized in that Parsing the on-chip network topology information in the custom template to obtain on-chip network routing information includes: Based on the identification information of multiple routing nodes parsed from the custom template and the path configuration information between the routing nodes, a local routing lookup table for each routing node is generated, wherein the local routing lookup table for each routing node includes the identification information of the current node, the identification information of the destination node associated with the current routing node for communication, and the communication channel information between the current node and its corresponding destination node.

4. The method according to claim 3, characterized in that Parsing the on-chip network topology information in the custom template to obtain on-chip network routing information also includes: A routing path information table including the path delay configuration information between the routing nodes is generated according to the identification information of the multiple routing nodes and the path configuration information between the routing nodes parsed from the custom template.

5. The method according to claim 4, characterized in that The routing path information table includes identification information of communication-related routing nodes and their corresponding path delay configuration information, wherein the path delay configuration information includes default configuration information or custom configuration information.

6. The method according to claim 5, characterized in that The method further comprises: Visually displaying the routing path information table, wherein the routing path information table includes an information configuration area that supports custom configuration of path delay configuration information; and In response to obtaining a configuration operation of the user for the information configuration area, path delay configuration information corresponding to a communication-related routing node is determined according to the configuration operation.

7. The method according to claim 1, characterized in that The setting format includes an Excel table format, and the Excel table includes an editing area for identification information of routing nodes and an editing area for path configuration information between routing nodes.

8. The method according to any one of claims 1 to 7, characterized in that: The method further comprises: Performing performance simulation verification on the on-chip network model to obtain verification data; Determining whether the verification data meets predetermined performance requirements; and In response to determining that the verification data does not meet a predetermined performance requirement, the network-on-chip model is adjusted.

9. The method according to claim 8, characterized in that The on-chip network routing information includes a routing path information table including path delay configuration information between routing nodes, and adjusting the on-chip network model includes: The path delay configuration information in the routing path information table or the on-chip network topology information in the custom template is adjusted to generate a new on-chip network model.

10. The method according to any one of claims 1 to 7, characterized in that: The method further comprises: The custom template is pre-constructed, wherein the custom template includes a filling area for the on-chip network topology information, and the filling area includes at least a first area for supporting information editing of a source node in a routing node, a second area for supporting information editing of a destination node in a routing node, and a third area for supporting information editing of a path node between the source node and the destination node.

11. The method according to claim 10, characterized in that The method further comprises: In response to the user's information input operation for the custom template, the information of the source node is edited in the first area of ​​the filling area according to the information input operation, the information of the destination node is edited in the second area of ​​the filling area, and the information of the path node is edited in the second area of ​​the filling area.

12. An electronic device, characterized in that: Also includes: processor; as well as A memory storing computer instructions for generating an on-chip network model, wherein when the computer instructions are executed by the processor, the electronic device executes the method according to any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that: The invention comprises program instructions for generating an on-chip network model, and when the program instructions are executed by a processor, the method according to any one of claims 1 to 10 is implemented.

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