Ethernet data transmission method and system based on single-phase CMC network transformer

Abstract

The invention discloses an Ethernet data transmission method based on a single-phase CMC network transformer, and aims to improve signal integrity and reduce electromagnetic interference. The method comprises the following steps: receiving a feedback differential signal from an RJ45 connector through an MAC layer main control module, decoding the feedback differential signal through a PHY chip, and recovering the decoded feedback differential signal into a digital signal; and after the MAC layer checks the data integrity, if data needs to be sent, transmitting a data packet to the PHY chip, and carrying out serialization and physical layer coding on parallel data. Coil current of the CMC in the network transformer is monitored in real time, common-mode impedance and common-mode voltage are calculated, and differential signal voltage and electromagnetic interference PSD thereof are further obtained. If the PSD is lower than a set threshold value, outputting a signal; and otherwise, adjusting the signal voltage by adopting a gradient descent optimization method to ensure that the signal voltage meets the standard. According to the invention, the common-mode noise can be effectively reduced, the signal stability is improved, the Ethernet communication quality is optimized, and the method is suitable for high-speed and low-bit-error-rate network equipment.

Description

Technical Field

[0001] The invention belongs to the technical field of Ethernet network data exchange communication, and in particular relates to an Ethernet data transmission method and system based on a single-phase CMC network transformer. Background Art

[0002] With the rapid development of information technology and the Internet, Ethernet has become one of the most widely used wired communication technologies in the world, and is widely used in computer networks, industrial automation, smart homes, data centers, embedded devices, and other fields. For example, in the prior art, the Chinese invention patent application with the publication number CN116319605A discloses an Ethernet data exchange module, a circuit board, and an electronic device, which includes a first shell, a first end of which is provided with at least two network cable connection ports, a metal spring, a network transformer, a PHY chip, and an embedded microcontroller are arranged in the first shell, each network transformer is connected to a corresponding PHY chip, and each PHY chip is connected to the first end of the embedded microcontroller, which can realize both 100M network reception and 1G network reception.

[0003] Another example is the Chinese utility model patent with publication number CN214627012U, which discloses a one-master-multiple-slave real-time communication system based on Ethernet PHY, which includes a master node and a slave node. The master node includes an industrial control computer and a NIC network card unit, and the slave node includes an FPGA main control unit, a PHY unit, a network transformer unit, and an RJ45 network port. The master node connects the network card NIC to the input network port of the slave node through a network cable, and the output network port of the slave node is connected to the input network port of the next slave node, forming a one-master-multiple-slave communication network in turn. With the help of the physical layer communication link provided by the Gigabit Ethernet PHY, by writing the FPGA control logic, data transmission with strong real-time performance, high throughput, and high reliability can be achieved.

[0004] In modern high-speed Ethernet (such as 100Base-TX, 1000Base-T and 10GBase-T), the signal frequency is usually above 100MHz. In the process of Ethernet data communication, the network transformer (Ethernet Transformer) such as the publication number CN208045213U, as an important component of signal transmission, undertakes key functions such as signal isolation, common mode noise suppression, impedance matching, etc., to ensure that the data maintains integrity and reliability during the transmission process. Its working principle is to convert the electrical signal of the sending end into magnetic flux through electromagnetic induction, and then convert the magnetic flux into electrical signals at the receiving end to achieve lossless transmission of data, and transmit through differential signals, thereby suppressing common mode noise to improve communication quality. However, the Ethernet data transmission system and method in the prior art do not provide a specific technical solution for how to dynamically optimize and adjust the differential signal of the network transformer to achieve high-speed, lossless and effective anti-electromagnetic interference data transmission. Summary of the invention

[0005] In view of the above-mentioned defects, the present invention provides an Ethernet data transmission method and system based on a single-phase CMC (common mode choke) network transformer. The present invention adopts an Ethernet data transmission system that combines a MAC layer, a PHY chip, a network transformer, and a single-phase common mode choke (CMC), and uses a gradient descent optimization algorithm to continuously optimize multiple pairs of differential signal pairs of parallel serial stream data converted from digital signals received by the PHY chip, thereby achieving high-efficiency, low-interference, and low-bit-error-rate Ethernet data transmission.

[0006] The present invention provides the following technical solution: an Ethernet data transmission method based on a single-phase CMC network transformer, the method dynamically optimizes electromagnetic interference during Ethernet data transmission based on a network transformer with a single-phase common mode choke, and the method comprises the following steps:

[0007] S1: The MAC layer main control module receives a feedback differential signal pair from an external network device such as an RJ45 connector through an Ethernet cable, and the feedback differential signal pair is processed by a corresponding network transformer and transmitted to a feedback differential signal pair receiving first pin and a feedback differential signal pair receiving second pin of the PHY chip;

[0008] S2: The PHY chip decodes the feedback differential signal pair and restores the digital signal to the MAC layer main control module; the MAC layer main control module verifies the feedback differential signal pair restored to the digital signal, and transmits the processed data to a higher layer for further data analysis and processing;

[0009] S3: The MAC layer main control module sends the data to be sent to the PHY chip according to the situation. After receiving the digital signal input from the MAC main control module, the PHY chip converts the received parallel data into serial stream data, encodes the serial stream data according to the encoding rules of the physical layer, and controls the differential signal pair of the PHY chip to send the first pin and the differential signal pair to send the second pin to the network transformer; at the same time, real-time monitoring of the real-time current I in the first coil of the single-phase common mode choke coil as the K component in the nth signal sending network transformer 1，n (t), real-time current I in the second coil 2，n (t);

[0010] S4: Calculate the impedance Z of the single-phase common mode choke as K component in the corresponding nth transmission signal network transformer K，n , according to the voltage level of the input analog voltage signal V in，n (t), calculate the common mode voltage V of the single-phase common mode choke com，n (t);

[0011] S5: Calculate the differential signal voltage V output from the first port corresponding to the single-phase common-mode choke in the nth signal transmission network transformer 1，n (t), differential signal voltage V output from the second port 2，n (t) and the differential mode voltage V diff，n (t);

[0012] S6: Calculate the power spectral density S of the total electromagnetic interference of the differential signal generated by the single-phase common mode choke in the nth signal transmission network transformer total，n , determine whether it is lower than the differential signal output PSD threshold S thr，n If so, the differential signal pair of the PHY chip is controlled to transmit the first pin and the differential signal pair to transmit the second pin to transmit V 1，n (t) and V 2，n (t) to the RJ45 connector, and further output to the external network device; otherwise, the MAC layer main control module continues to use the gradient descent optimization method to optimize V 1，n (t) and V 2，n (t).

[0013] Furthermore, the S3 step includes:

[0014] S31: Collect the received parallel data to obtain a parallel data set D: D = {D I-1 , D I-2 , ..., D i , ..., D2, D1, D0}, where D i is the i+1th binary parallel data, Di =0 or 1; I is the total number of binary parallel data in the parallel data set D; I=4 or 8;

[0015] S32: The PHY chip processes the data in the parallel data set D in step S11 according to the most significant bit D I-1 Arrange the bits from front to back to the least significant bit D0 and then output them bit by bit in the order of arrangement;

[0016] S33: According to the NRZ encoding rule, the binary parallel data D outputted bit by bit in step S12 is i Convert to analog voltage signal according to the following mapping rules:

[0017] Among them, U0 and U1 are respectively the high voltage level and the low voltage level after the digital signal is converted, U1 = 3.3V or 5V, and U0 = 0V.

[0018] Furthermore, the S4 step includes:

[0019] S41: Calculate the total impedance Z of the first coil of the K component in the nth signal transmission network transformer k1，n The total impedance Z of the second coil k2，n ; Z kq，n =R wire，q，n +jωL self，q，n +jωL leak，q，n +Z core，n ; q = 1 or 2; R wire，q，n , L self，q，n , L leak，q，n and Z core，n are the resistance, self-inductance, leakage inductance of the qth coil of the K-component in the nth signal transmission network transformer and the impedance of the nth magnetic core, q=1 or 2;

[0020] S42: According to the result of step S42, calculate the total impedance Z generated by the two coils of the single-phase common mode choke as the K element in the nth signal transmission network transformer. K，n :

[0021]

[0022] S43: Calculate the common mode voltage of the single-phase common mode choke as the K component in the nth transmission signal network transformer:

[0023] Among them, C3 is the capacitance value of the third capacitor C3 commonly connected before N signal transmission network transformers and the RJ45 connector are grounded; N is the total number of signal transmission network transformers included in the system, N=1 or 2, n=1, 2, ..., N; R1, R2, R3 and R4 are the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4; j is an imaginary number; ω is the angular frequency of the input digital signal, ω=2πf, f is the frequency of the input digital signal, f=125MHz.

[0024] Furthermore, the step S5 includes:

[0025] S51: Calculate the stray capacitance C of each coil in the nth signal transmission network transformer tt，n , the stray capacitance C between the qth coil and the magnetic core tc，q，n :

[0026]

[0027] Among them, δ r is the dielectric constant of the coil insulation layer; r win is the circular cross-sectional radius of the coil wire, δ0 is the vacuum dielectric constant of the coil, δ0=8.854×10 -12 F / m; r wo The outer diameter of the coil wire after it is surrounded by a circle of insulating medium; d coil A is the horizontal winding distance between the inner and outer cores of each coil of a K-piece, coil A is the effective capacitance area between the two coils of a K-piece; tc，q is the effective capacitance area between the qth coil and the magnetic core in a K-piece, h tc A is the height difference between the center point of the cross section of a coil wire in a K part and the surface of the magnetic core; tc，q =D c，q ×(h c (r cin -r co )),h c is the vertical height of the coil when it is wrapped around the core, r cin is the inner diameter of the core, r co is the outer diameter of the core; D c，q is the average path length of the qth coil wound around the toroidal core in a K-piece;

[0028] S52: Calculate the self-inductance L of the qth coil in the nth signal transmission network transformer self，q，n , the leakage inductance L of the qth coil leak，q，n :

[0029]

[0030]

[0031] Where Mq is the number of times the qth coil is wound around the magnetic core;

[0032] Among them, θ q is the angle that the qth coil passes through when it is wound around the toroidal core;

[0033] S53: Calculate the resistance R of the i-th coil wire，q，n 、The resistance R of the magnetic core in the single-phase common mode choke as the K element in the nth transmission signal network transformer core，n Its impedance Z core，n :

[0034] Among them, ρ w is the density of the coil, ρ w =8.9g / cm 3 ; γ is the skin depth of the coil material, ξ w is the resistivity of the coil, ξ w =1.68×10-8Ω·m; μ Copper is the relative magnetic permeability of the enameled copper wire coil, μ Copper =1; μ0 is the vacuum magnetic permeability, μ0=4π×10 -1 H / m:

[0035] Among them, A e is the cross-sectional area of ​​the core, η core , a and b are the first, second and third Steinmetz coefficients of the magnetic core respectively, η core It is related to the material of the magnetic core, a=1.5~2, b=2~2.5; I rms，n is the equivalent RMS current in the magnetic core of the single-phase common-mode choke in the nth signal transmission network transformer, For I 1，n (t) and I 2，n (t) phase difference;

[0036]

[0037] Among them, μ r is the relative magnetic permeability of the core material;

[0038] S54: Calculate the differential signal voltage V outputted from the first port corresponding to the single-phase common-mode choke in the nth signal transmission network transformer 1，n(t), differential signal voltage V output from the second port 2，n (t):

[0039]

[0040] Among them, I DM，1，n (t), I DM，2，n (t) are the differential signal currents flowing through the first and second coils of the single-phase common-mode choke in the nth transmitting signal network transformer, I DM，1，n (t) = I 1，n (t)-I CM，1，n (t), I DM，2，n (t) = I 2，n (t)-I CM，2，n (t), I CM，1，n (t) = I CM，2，n (t)=0.5V com，n (t) / Z K，n ;I CM，1，n (t), I CM，2，n (t) are the common mode signal currents flowing through the first coil and the second wire of the single-phase common mode choke in the nth transmitting signal network transformer;

[0041] S55: Further calculate the differential mode voltage V diff，n (t):

[0042] V diff，n (t) = V 1，n (t)-V 2，n (t).

[0043] Furthermore, when the Ethernet is Gigabit Ethernet (1000BASE-T), the differential voltage V of the analog signal converted by the PHY chip is diFf (t) is in the range of 0.4V to 2V; when the Ethernet is 100M Ethernet (100BASE-TX), the differential voltage V of the analog signal converted by the PHY chip diff，n (t) is in the range of 0.2V to 2.5V.

[0044] Furthermore, in the step S6, the power spectrum density S of the total electromagnetic interference of the differential signal generated by the single-phase common mode choke in the nth signal transmission network transformer is calculated. total，n The formula is as follows:

[0045]

[0046] in, is the differential mode voltage V diff，n (t) the power spectral density of the electromagnetic interference generated; is the common mode voltage V com，n (t) the power spectral density of the electromagnetic interference generated;

[0047]

[0048] The differential signal output PSD threshold S thr，n Adopt CISPR32 international standard, S thr，n =43.5dBμV / m.

[0049] Furthermore, in step S6, the gradient descent optimization method is used to optimize V 1，n (t) and V 2，n The steps of (t) are as follows:

[0050] S61: Construct optimization objective function:

[0051] S62: Constructing the gradient function of the objective function

[0052] is the expected electromagnetic interference value of the differential mode voltage signal, is the expected common mode voltage signal electromagnetic interference value;

[0053] S63: The p-th generation optimization value of the differential signal voltage outputted from the first port corresponding to the single-phase common mode choke in the n-th transmission signal network transformer at the learning rate α The pth generation optimized value of the differential signal voltage output from the second port corresponding to the single-phase common mode choke in the nth transmission signal network transformer Perform target gradient update:

[0054]

[0055]

[0056] in, are the p+1th generation optimized values ​​of the differential signal voltage outputted from the first port and the second port corresponding to the single-phase common mode choke in the nth transmitting signal network transformer; α=0.215;

[0057] S64: Determine the modulus of the gradient function of the ρ+1th generation objective function Is it less than the gradient optimization stop threshold 0.005? If so, stop the iteration; otherwise, repeat S61-S63.

[0058] The present invention also provides an Ethernet data transmission system based on a single-phase CMC network transformer using the above method, the system comprising a MAC layer main control module, a PHY chip, a plurality of feedback signal transformers, a plurality of transmission signal network transformers and an RJ45 connector, and also comprising a device for real-time monitoring of the real-time current I of two coils of each network transformer. 1，n (t) and I 2，n (t) coil current monitoring module;

[0059] The MAC layer main control module is used to receive a feedback differential signal pair from an external network device such as an RJ45 connector through an Ethernet cable, and the feedback differential signal pair is processed by a corresponding network transformer and transmitted to a feedback differential signal pair receiving first pin and a feedback differential signal pair receiving second pin of the PHY chip; and to verify the feedback differential signal pair restored to a digital signal, and transmit the processed data to a higher layer for further data analysis and processing;

[0060] The PHY chip is used to process the conversion between the input digital signal and the analog signal transmitted from the physical network line fed back by the RJ45 connector; the PHY chip decodes the feedback differential signal pair and restores it to the digital signal and transmits it to the MAC layer main control module, and is used to receive the digital signal input from the MAC main control module, convert the received parallel data into serial stream data, and encode the serial stream data according to the encoding rules of the physical layer; and monitor the real-time current I in the first coil of the single-phase common mode choke coil as the K component in the nth signal transmission network transformer in real time 1，n (t), real-time current I in the second coil 2，n (t);

[0061] The MAC layer main control module is also used to calculate the impedance Z of the single-phase common mode choke coil as the K component in the corresponding nth signal transmission network transformer K，n , according to the voltage level of the input analog voltage signal V in，n (t), calculate the common mode voltage V of the single-phase common mode choke com，n (t);

[0062] And calculate the differential signal voltage V output from the first port corresponding to the single-phase common mode choke in the nth signal transmission network transformer 1，n (t), differential signal voltage V output from the second port 2，n (t) and the differential mode voltage V diff，n (t); and calculate the power spectral density S of the total electromagnetic interference of the differential signal generated by the single-phase common mode choke in the nth signal transmission network transformer total，n , determine whether it is lower than the differential signal output PSD threshold Sthr，n If so, the differential signal pair of the PHY chip is controlled to transmit the first pin and the differential signal pair to transmit the second pin to transmit V 1，n (t) and V 2，n (t) to the RJ45 connector, and further output to the external network device; otherwise, the MAC layer main control module continues to use the gradient descent optimization method to optimize V 1，n (t) and V 2，n (t).

[0063] Furthermore, the sending signal network transformer includes a transformer as a T-piece and a single-phase common-mode choke as a K-piece, the coil ratio of the transformer as a T-piece is 1:1, the center tap of the left coil and the center tap of the right coil of the transformer as a T-piece are both grounded, and the two ends of the right coil are respectively connected in series with the first coil and the second coil of the single-phase common-mode choke as the K-piece.

[0064] Furthermore, the PHY chip is a voltage-driven chip.

[0065] The beneficial effects and advantages of the present invention over the prior art are as follows:

[0066] 1. The present invention receives the feedback differential signal of the external device from the RJ45 interface through the S1-S2 step control system, and ensures the integrity of the data through the network transformer, PHY chip and MAC layer main control module, specifically by decoding and recovering the digital signal through PHY, ensuring that the bit error rate during data transmission is reduced. The digital signal obtained by decoding and recovering the PHY chip is further transmitted to the MAC layer main control module, and the MAC layer performs a frame check (CRC) to detect and correct possible transmission errors and improve the accuracy of the data. The data after the integrity check is then uploaded to the IP layer and the transport layer for further processing, thereby ensuring that the data can be stably transmitted to a higher-level protocol layer, achieving efficient communication while improving the integrity of the signal and the accuracy of the data.

[0067] 2. The present invention controls the system through the S3 step. When the upper layer data (IP layer, application layer) needs to transmit data to the network device connected to the RJ45 connector, the MAC layer main control module encapsulates and sends it to the PHY chip physical layer, and then encodes the serial stream data (such as PAM-5 encoding of 1000Base-T) according to the encoding rules of the PHY chip physical layer, thereby reducing signal loss and optimizing the stability of high-speed signal transmission; at the same time, the real-time current in the two coils in the K-piece single-phase common mode choke (CMC) of the network transformer with a T-piece + K-piece structure is monitored in real time to ensure that the coils in the network transformer can then calculate the differential signal V output by the two coils in real time. 1，n (t) and V 2，n(t), reduce signal distortion and error accumulation, and improve signal quality.

[0068] 3. The present invention introduces the calculation of the common mode voltage generated by the differential signal output by each network transformer through steps S4-S6, the calculation of the differential signal, and the calculation of the common mode electromagnetic interference EMI value and the differential mode electromagnetic interference EMI value generated by the common mode voltage, and further through PSD (power spectrum density) analysis, ensures that the output differential signal is dynamically regulated to make the common mode electromagnetic interference EMI value And differential mode electromagnetic interference EMI value Sum of: Power spectral density S of total electromagnetic interference total，n Below the differential signal output PSD threshold S thr，n , thereby achieving effective control of the EMI of the output differential signal.

[0069] 4. In step S6 of the present invention, the differential signal voltage V output by the network transformer is 1，n (t) and V 2，n The common mode electromagnetic interference EMI value obtained by the calculation result of (t) And differential mode electromagnetic interference EMI value Its ideal value gap, and then construct a dynamic optimization V 1，n (t) and V 2，n The objective function of (t): Then, V 1，n (t) and V 2，n (t) Gradient optimization is performed to minimize electromagnetic interference while maintaining signal integrity. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] The present invention will be described in more detail below based on embodiments and with reference to the accompanying drawings, wherein:

[0071] Figure 1 A schematic flow chart of an Ethernet data transmission method based on a single-phase CMC network transformer provided by the present invention;

[0072] Figure 2 A comparison chart of simulation results and actual detection results of encoding the signal to be sent by the MAC layer main control module using the method provided by the present invention and the 4B / 5B encoding method;

[0073] Figure 3 A structural diagram of a single-phase common-mode choke as a K component in a network transformer in the method and system provided by the present invention;

[0074] Figure 4It is a schematic diagram of the equivalent circuit structure of the network transformer in an embodiment of the present invention and the electromagnetic interference and differential signal generated by it changing with time;

[0075] Figure 5 In the embodiment of the present invention, Figure 3 The direction of the electromagnetic interference magnetic field, the common mode signal current and the differential signal current in the single-phase common mode choke;

[0076] Figure 6 In the embodiment of the present invention, Figure 3 Schematic diagram of calculation parameters of the stray capacitance of a coil itself and the stray capacitance between it and the magnetic core in a single-phase common mode choke;

[0077] Figure 7 In the embodiment of the present invention, Figure 3 Another schematic diagram of the calculation parameters of the stray capacitance of a coil itself and the stray capacitance between it and the magnetic core in a single-phase common mode choke;

[0078] Figure 8 A schematic diagram for introducing the coil winding magnetic core and related parameters in a single-phase common mode choke in an embodiment of the present invention;

[0079] Fig. 9 It is a schematic diagram comparing the total electromagnetic interference EMI noise level of the method of the present invention and two other comparative methods omitting some steps of the present invention with the monitoring time and the number of iterations in the embodiment of the present invention;

[0080] Fig.10 An Ethernet data transmission system based on a single-phase CMC for 100M Ethernet data transmission provided by an embodiment of the present invention;

[0081] Fig.11 An Ethernet data transmission system based on a single-phase CMC for Gigabit Ethernet data transmission is provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0082] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0083] The present invention provides an Ethernet data transmission method based on a single-phase CMC network transformer, where CMC is the abbreviation of common mode choke, and the single-phase CMC is a single-phase common mode choke, which is used as a K component and a T component to form a network transformer. The method is based on the dynamic optimization of electromagnetic interference (EMI) in the Ethernet data transmission process by a network transformer with a single-phase common mode choke, so as to improve the reliability and anti-interference ability of Ethernet data transmission, such as Figure 1 As shown, the method of the present invention comprises the following steps:

[0084] S1: The MAC layer main control module receives a feedback differential signal pair from an external network device such as an RJ45 connector through an Ethernet cable (such as Cat5e, Cat6), and the feedback differential signal pair is processed by a corresponding feedback signal network transformer and transmitted to the feedback differential signal pair receiving first pin (positive end) and the feedback differential signal pair receiving second pin (negative end) of the PHY chip;

[0085] S2: The PHY chip decodes the feedback differential signal pair (analog signal) and restores it to a digital signal and transmits it to the MAC layer main control module; the MAC layer main control module verifies the feedback differential signal pair restored to the digital signal (generally, it parses the Ethernet frame of the feedback differential signal pair restored to the digital signal and checks the integrity of the data (such as CRC check)), and transmits the processed data to a higher layer (such as the IP layer and the transport layer) for further data analysis and processing;

[0086] S3: If there is data to be sent (such as data from an upper layer application), the MAC will prepare the data packet and transmit it to the PHY chip for physical layer encoding and transmission; the MAC layer main control module will send the data to be sent to the PHY chip according to the situation. After the PHY chip receives the digital signal input from the MAC main control module, it will convert the received parallel data into serial stream data, encode the serial stream data according to the encoding rules of the physical layer (i.e., perform digital-to-analog conversion to obtain a voltage change signal suitable for physical transmission), and control the differential signal pair of the PHY chip to send the first pin and the differential signal pair to send the second pin to the network transformer; at the same time, the real-time current I in the first coil of the single-phase common-mode choke as the K component in the nth signal transmission network transformer is monitored in real time. 1，n (t), real-time current I in the second coil 2，n (t);

[0087] S4: Calculate the impedance Z of the single-phase common mode choke as K component in the corresponding nth transmission signal network transformer K，n , according to the voltage level of the input analog voltage signal V in，n (t), calculate the common mode voltage V of the single-phase common mode choke com，n (t);

[0088] S5: Calculate the differential signal voltage V output from the first port corresponding to the single-phase common-mode choke in the nth signal transmission network transformer 1，n (t), differential signal voltage V output from the second port 2，n (t) and the differential mode voltage V diff，n (t);

[0089] S6: Calculate the power spectral density S of the total electromagnetic interference of the differential signal generated by the single-phase common mode choke in the nth signal transmission network transformer total，n , determine whether it is lower than the differential signal output PSD threshold S thr，n If so, the differential signal pair of the RJ45 connector is controlled to receive the first pin and the differential signal pair to receive the second pin to receive the V of the differential signal pair respectively. 1，n (t) and V 2，n (t), and further output to the external network device; otherwise, the MAC layer main control module continues to use the gradient descent optimization method to optimize V 1，n (t) and V 2，n (t).

[0090] The MAC layer main control module works with the PHY chip in network devices (such as Ethernet cards (NICs), routers, switches, etc.). Specifically, the MAC layer usually exists as a part of the network controller, responsible for the address management, data frame management, and flow control and collision detection of the following data transmission. In address management, the MAC address is the unique identifier of the physical layer device, and the MAC layer uses the MAC address to communicate between devices. The MAC layer is responsible for converting upper-layer data into frame format, transmitting or receiving, and verifying the integrity of the data. In a shared media network, the MAC layer is responsible for managing how devices access data in a shared transmission channel and avoiding data collisions (such as Ethernet's CSMA / CD).

[0091] RJ45 connector is a standardized connection interface, commonly used for physical connection between Ethernet devices. RJ45 connector is a plug interface used to connect devices with Ethernet ports, such as computers, routers, switches, printers, smart TVs, industrial equipment and embedded devices. It is generally used for twisted pair cables (such as Cat5e, Cat6) for network communication.

[0092] The present invention provides a stable, low-interference, high-speed data transmission method for high-performance Ethernet by combining signal monitoring, EMI optimization, and adaptive gradient descent algorithm. Therefore, the method of the present invention is particularly suitable for applications with strict requirements on network signal quality, such as industrial Ethernet, data centers, smart homes, and in-vehicle Ethernet.

[0093] In the Ethernet communication architecture, data transmission between the MAC layer and the physical layer of the PHY chip is usually parallel, while the transmission of physical signals is usually serial. The MAC layer main control module processes data frames (Ethernet frames) and usually sends 8-bit or 16-bit parallel data to the PHY chip through the MII, GMII or RGMII interface. If the unencoded digital signal is directly output, the receiving end will not be able to accurately extract the clock signal from the data stream, and the clock recovery will be difficult, which will lead to data synchronization difficulties. At the same time, if there is a long period of "0" or "1" in the data stream, it may cause signal deviation (DC bias), unstable signal transmission, and affect the transmission quality. Therefore, the physical layer of the PHY chip needs to convert these parallel data into serial streams to meet the serial transmission requirements of the physical medium (twisted pair). As a preferred embodiment of the present invention, step S3 includes:

[0094] S31: When the PHY chip receives parallel data from the MAC layer, these data are usually transmitted according to a fixed bit width (such as 8 bits, 16 bits, etc.). The PHY chip needs to convert these parallel data into serial streams for physical transmission; collect the received parallel data to obtain a parallel data set D: D = {D I-1 , D I-2 , ..., D i , ..., D2, D1, D0}, where D i is the i+1th binary parallel data, D i = 0 or 1; I is the total number of binary parallel data in the parallel data set D, D I-1 D0 is the most significant bit (MSB), D1 is the least significant bit (LSB); I = 4 or 8; when 100M Ethernet data is transmitted, I = 4, when Gigabit Ethernet is transmitted, I = 8;

[0095] This step ensures that data is serially output from the PHY chip in the correct order, in compliance with Ethernet protocol requirements. It reduces the interface bandwidth requirements of the MAC layer main control module and the PHY layer, and the conversion of data streams from parallel to serial reduces the demand for high-speed data buses;

[0096] S32: The PHY chip converts the data in the parallel data set D in step S11 into the most significant bit D I-1 The least significant bit D0 is arranged from front to back and then output bit by bit in the order of arrangement; that is, according to D I-1 , D I-2 The number of effective bits is gradually reduced and output bit by bit until D0 is output last;

[0097] S33: According to the NRZ encoding rule, the binary parallel data D outputted bit by bit in step S12 is i Convert to analog voltage signal according to the following mapping rules:

[0098] Among them, U0 and U1 are respectively the high voltage level and the low voltage level after the digital signal is converted, U1 = 3.3V or 5V, and U0 = 0V.

[0099] The functions of the PHY chip include converting the parallel digital signals from the MAC layer into a serial data stream and encoding the serial data according to the encoding rules of the physical layer (such as non-return-to-zero encoding, NRZ encoding). Non-return-to-zero encoding (NRZ encoding) is a common physical layer encoding method that converts each binary parallel data D of the digital signal received by the PHY chip into a serial data stream. i Directly mapped to a high voltage level or a low voltage level state. Through the NRZ encoding rule, the PHY chip can convert the input parallel data stream into a serial voltage signal and process it through the encoding rules of the physical layer. NRZ encoding is simple and efficient. It ensures that data can be transmitted stably on the physical layer by directly mapping each data bit to a fixed level. The core of the whole process is to convert the input parallel data into a serial format. After the parallel data is converted into a serial stream, the PHY chip can process data faster and improve throughput.

[0100] 100M Ethernet e -TX) and Gigabit Ethernet (1000Bas e -T) all support NRZ encoding as the basic physical layer encoding method. Therefore, full-duplex communication is supported and it is suitable for high-speed Ethernet transmission. The encoding method of the present invention is directly compatible with the current mainstream PHY chip without the need for additional decoding or conversion steps, and has strong versatility.

[0101] In order to verify the accuracy of data transmission by encoding serial data using the NRZ encoding method in the steps S31-S33 provided by the present invention, the following is used: Fig.10 The Ethernet data transmission system shown in the figure performs Ethernet data transmission. Comparative Example 1 uses a 4B / 5B encoding method to replace the NRZ encoding method of steps S31-S33 of the present invention, such as Figure 2 As shown, Figure 2 The red × dots and blue × dots in the figure are the real-time monitoring results of the method of the present invention and the 4B / 5B method as the monitoring frequency changes, respectively. The yellow dotted line is the DC bias rate of the simulation results of the 4B / 5B encoding method as the monitoring frequency changes, and the green solid line is the DC bias rate of the simulation results of the NRZ encoding method of the steps S31-S33 of the present invention as the monitoring frequency changes. Figure 2By comparing the red × dots in the figure with the green solid line, it can be seen that the difference between the simulation results of the method of the present invention and the actual real-time monitoring results is very small. When the monitoring frequency is low, the DC bias rate is about 0.02, and as the monitoring frequency increases, gradually approaching the transmission data frequency of 100M Ethernet and Gigabit Ethernet 125MHz, the red × dots and the green solid line are almost coincident, and the DC bias rate is close to 0. Figure 2 The real-time monitoring result represented by the blue × point in the figure is quite different from the simulation result represented by the yellow dotted line. Although the difference gradually decreases with the increase of the monitoring frequency, the difference between the two is still quite large, which proves that the 4B / 5B encoding method is not good for the serial stream data conversion effect when the single-phase common mode choke network transformer based Ethernet data transmission is applied to the present invention, and has a large bit error rate. For the 4B / 5B encoding method, whether it is the simulation result or the real-time monitoring result, its DC bias rate is always higher than the NRZ encoding method of the present invention. It can be seen that the present invention uses NRZ encoding to output the corresponding level signal according to the NRZ encoding rule for the input digital signal, which can ensure data accuracy and reduce the signal transmission bit error rate (BER). At the same time, it can reduce signal switching loss, improve signal integrity, and reduce the complexity of the PHY transmitter, so that it can focus on signal amplification, equalization and transmission optimization.

[0102] The network transformer used in the present invention is as follows Figure 4 The network transformer with a T-piece + K-piece structural equivalent circuit shown on the left plays a role in signal isolation, impedance matching and EMI suppression during Ethernet data transmission. However, in the differential signal output calculation of the network transformer in the prior art, the impedance calculation of the single-phase common-mode choke as the K-piece is usually fixed, but different transmission environments (such as different network cable lengths, electromagnetic interference environments) will affect the common-mode impedance, thereby affecting EMI and signal quality. In addition, the impedance of the K-piece is not accurately calculated, resulting in unstable common-mode noise suppression capabilities, affecting the data transmission of the PHY chip. At the same time, the common-mode voltage calculation lacks a dynamic optimization mechanism, which is difficult to adapt to high-speed signal transmission environments, and may lead to an increase in the bit error rate (BER). Therefore, it is necessary to dynamically calculate the impedance and common-mode voltage of the K-piece to ensure that the network transformer can provide optimal signal quality and minimize EMI in different environments. As another preferred embodiment of the present invention, step S4 includes:

[0103] S41: Calculate the total impedance Z of the first coil of the K component in the nth signal transmission network transformer k1，n The total impedance Z of the second coil k2，n ; Z kq，n =R wire，q，n +jωL self，q，n +jωL leak，q，n +Z core，n; q = 1 or 2; R wire，q，n , L self，q，n , L leak，q，n and Z core，n They are the resistance, self-inductance, leakage inductance of the qth coil of the K-component in the nth signal transmission network transformer and the impedance of the nth magnetic core, q = 1 or 2; Figure 3 As shown, the windings of the first coil and the second coil of each network transformer are wound on the magnetic core to form a single-phase common-mode choke. The first coil is the first winding, and the second coil is the second winding. The two coils form a coupled winding, and the common-mode current of the first coil; K is set in the network transformer because K is important for the useful data voltage signal V 1，n (t) and V 1，n (t)(i.e., differential signal V 1，n (t) and V 1，n (t)) has no attenuation effect, but can attenuate electromagnetic interference EMI; adding K can further block the mutual propagation of EMI between the primary and secondary coils;

[0104] like Figure 4 As shown, the orange sine wave solid lines on the right are the common mode data voltage signals V CM，A 、V CM，B The waveform of the common-mode electromagnetic interference generated. The blue solid line on the right is the differential data voltage differential signal V DM，A 、V DM，B The periodic variation diagram of Figure 4 In the network transformer equivalent circuit on the left, a differential data pair in the encoded serial data stream obtained from the MAC layer main control module enters the T-piece coil and then enters the K-piece. The orange arrow represents the common-mode data voltage signal V com，n (t) is divided into two common-mode current signals I CM，A ,I CM，B From Pin4, the current flows through the first coil (I CM，A from Figure 3 as well as Figure 5 The current flows from the A1 end to the A2 end of the K component) and from Pin6 through the second coil (I CM，B from Figure 3 as well as Figure 5 The current flows from the B1 end to the B2 section), and then enters the T-piece coil in the direction of the current; Figure 4 In the network transformer equivalent circuit on the left, the blue arrows represent two differential mode current signals I DM，A ,I DM，B From Pin4, the current flows through the first coil (I DM，A from Figure 3 as well as Figure 5The current flows from the A1 end to the A2 end of the K component) and from Pin6 through the second coil (I DM，B from Figure 3 as well as Figure 5 The B2 end flows to the B1 section).

[0105] Then in Figure 5 As shown by the blue solid arrows in J-2, when the data voltage signal flows through the upper and lower coils of the K-piece and flows out from Pin4 and Pin6 respectively, the currents are equal in magnitude and opposite in direction. The magnetic flux of the first coil inside the magnetic ring of the K-piece is φ DM , A 1 A 2. The magnetic flux in the second coil is φ DM , B1 B 2. The changes in magnetic flux caused by the two electrodes cancel each other out. Ideally, the magnetic flux change is zero (φ DM，A1A2 -φ DM，B1B2 =0), which means that the common mode impedance presented by the first coil on the top and the second coil on the bottom of the K component is zero. The differential mode EMI of the K component to the data voltage signal depends on the differential mode signal magnetic flux difference |φ generated by the two coils of the K component DM，A1A2 -φ DM，B1B2 |.

[0106] like Figure 4 The orange solid arrows show that when two common-mode current signals I CM，A ,I CM，B When flowing through the upper and lower coils of the K-piece, the currents generated are equal in magnitude and direction. The magnetic flux of the first coil inside the magnetic ring of the K-piece is φ CM，A1A2 , the magnetic flux of the second coil is φ CM，B1B2 , the magnetic flux of the common-mode signal is superimposed on each other, so the EMI value of the common-mode signal formed at the K part depends on φ CM，A1A2 +φ CM，B1B2 , the inductive reactance presented by the K component will increase linearly with the increase of the frequency f of the input digital signal;

[0107] S42: According to the result of step S42, calculate the total impedance Z generated by the two coils of the single-phase common mode choke as the K element in the nth transmission signal network transformer K，n :

[0108]

[0109] S43: Calculate the common mode voltage of the single-phase common mode choke as the K component in the nth transmission signal network transformer:

[0110] Wherein, C3 is the capacitance value of the third capacitor C3 commonly connected before the N signal transmission network transformers and the RJ45 connector are grounded; N is the total number of signal transmission network transformers included in the system, N = 1 or 2, n = 1, 2, ..., N; R1, R2, R3 and R4 are the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4; j is an imaginary number; ω is the angular frequency of the input digital signal, ω = 2πf, and f is the frequency of the input digital signal. The data transmission frequency of 100M Ethernet and Gigabit Ethernet is 125MHz, f = 125MHz.

[0111] Figure 4 In the figure, the orange arrow represents the common mode data voltage signal V com，n (t) is divided into two common-mode current signals I CM，A ,I CM，B is the common mode data voltage signal V com，n (t) is half of the current generated in the total resistance of K. Therefore, I CM，A =I CM，B =0.5V com，n (t) / Z K，n ;

[0112] Furthermore, step S5 includes:

[0113] S51: Calculate the stray capacitance C of each coil in the nth signal transmission network transformer tt，n , the stray capacitance C between the qth coil and the magnetic core tc，q，n :

[0114]

[0115] Among them, δ r is the dielectric constant of the coil insulation layer, is δ r The reciprocal of Figure 6 , Figure 7 As shown, r win is the circular cross-sectional radius of the coil wire, δ0 is the vacuum dielectric constant of the coil, δ0=8.854×10 -12 F / m; r wo The outer diameter of the coil wire after it is surrounded by a circle of insulating medium; d coil A is the horizontal winding distance between the inside and outside of the magnetic core of each coil of a K-piece (i.e. the distance between conductors), coil is the effective capacitance area between the two coils of a K-piece; Figure 8 As shown, A tc，q is the effective capacitance area between the qth coil and the magnetic core in a K-piece, such as Figure 7 As shown, h tcA is the height difference between the center point of the cross section of a coil wire in a K part and the surface of the magnetic core; tc，q =D c，q ×(h c (r cin -r co )),like Figure 8 As shown, h c is the vertical height of the coil when it is wrapped around the core, r cin is the inner diameter of the core, r co is the outer diameter of the core; D c，q is the average path length of the qth coil wound around the toroidal core in a K-piece, 2D c，q +2d gap =2πr co ;like Figure 8 As shown in (a), h c (r cin -r co ) is the magnetic induction area between the coil and the core when the coil is wound around the core once, D c，q is the arc length of a coil surrounding the magnetic core. Therefore, the volume area of ​​the magnetic core surrounded by a coil can be regarded as h c (r cin -r co ) as the base, D c，q For high solid volume calculation, the calculated solid volume is the magnetic induction area of ​​a coil and the magnetic core, that is, the effective capacitance area; Figure 8 (b) is a schematic diagram of K coils wrapped around a circular magnetic core once, i.e., when N=1;

[0116] In the present invention, it is assumed that the insulation layer materials used for the two coils in the K part of all network transformers are consistent, and the thickness of the insulation material coated on the coil metal wire is consistent;

[0117] S52: Calculate the self-inductance L of the qth coil in the nth signal transmission network transformer self，q，n , the leakage inductance L of the qth coil leak，q，n :

[0118]

[0119] Among them, M q is the number of times the qth coil is wound around the magnetic core;

[0120] Among them, Figure 7 As shown, θ q is the angle that the qth coil passes through when it is wound around the toroidal core;

[0121] S53: Calculate the resistance R of the i-th coil wire，q，n、The resistance R of the magnetic core in the single-phase common mode choke as the K element in the nth transmission signal network transformer core，n Its impedance Z core，n :

[0122] Among them, ρ w is the density of the coil. Generally, the coil of K piece is enameled copper wire. w =8.9g / cm 3 ; γ is the skin depth of the coil material, ξ w is the resistivity of the coil, ξ w =1.68×10-8Ω·m; μ Copper is the relative magnetic permeability of the enameled copper wire coil, μ Copper =1; μ0 is the vacuum magnetic permeability, μ0=4π×10 -1 H / m;

[0123] Among them, A e is the cross-sectional area of ​​the core, Among them, η core , a and b are the first, second and third Steinmetz coefficients of the magnetic core respectively, η core It is related to the material of the magnetic core. The magnetic core material of the K part is generally Mn-Zn ferrite (generally suitable for operating frequencies of tens of kHz to hundreds of kHz, such as for switching power supplies, signal transmission, etc.) or Ni-Zn ferrite (generally suitable for operating frequencies of hundreds of kHz to several MHz, suitable for high-frequency applications, such as radio frequency (RF) transformers and inductors). When the magnetic core of the K part is Mn-Zn ferrite, η core =1.5×10 -3 ~3.0×10 -3 , when the core of K is Ni-Zn ferrite, η core =5.0×10 -6 ~5.0×10 -4 ; a=1.5~2, b=2~2.5; I rms，n is the equivalent RMS current in the magnetic core of the single-phase common-mode choke in the nth signal transmission network transformer, For I 1，n (t) and I 2，n (t) phase difference; f is the input digital signal frequency, that is, the voltage level V of the input analog voltage signal in，n The frequency of I 1，n (t), I 2，n(t) frequency;

[0124] During the operation of the transformer, the current in the coil generates an alternating magnetic field by winding, and the change of this magnetic field will pass through the magnetic core. The magnetic material of the magnetic core responds to this changing magnetic field, generating a certain amount of eddy current (related to the material's electrical conductivity and magnetic permeability), and at the same time generating hysteresis loss (related to the rate of change of the magnetic field, the material's magnetic permeability, etc.). The effective value of these losses per unit time can be calculated by the equivalent root mean square current I rms，n to describe.

[0125]

[0126] in, is the total inductance of the core, which is the result of the coupling of the self-inductance of the two coils. And the mutual inductance of the two coils composition is the total capacitance of the core, which is composed of the capacitance C between the two coils wound around the core tt And the capacitance C formed by the two coils and the magnetic core tc，i The sum of μ0 is the vacuum permeability, μ0=4π×10 -1 H / m,μ r is the relative magnetic permeability of the core material; the network transformer is based on its operating frequency, and the core of the K part uses the relative magnetic permeability μ of the Mn-Zn ferrite material r The relative magnetic permeability μ of Ni-Zn ferrite material is between 2000 and 5000. r Between 50 and 1000;

[0127] S54: Calculate the differential signal voltage V outputted from the first port corresponding to the single-phase common-mode choke in the nth signal transmission network transformer 1，n (t), differential signal voltage V output from the second port 2，n (t):

[0128]

[0129] Among them, I DM，1，n (t), I DM，2，n (t) are the differential signal currents flowing through the first and second coils of the single-phase common-mode choke in the nth transmitting signal network transformer, I DM，1，n (t) = I 1，n (t)-I CM，1，n (t), I DM，2，n (t) = I 2，n (t)-I CM，2，n (t), I CM，1，n (t) = I CM，2，n (t)=0.5V com，n (t) / Z K，n ;ICM，1，n (t), I CM，2，n (t) are the common-mode signal currents flowing through the first coil and the second coil of the single-phase common-mode choke in the nth transmitting signal network transformer; I CM，1，n (t), I CM，2，n (t) are respectively Figure 4 , Figure 5 I CM，A ,I CM，B , I DM，1，n (t), I DM，2，n (t) are Figure 4 , Figure 5 I DM，A ,I DM，B

[0130] S55: Further calculate the differential mode voltage V diff，n (t):

[0131] V diff，n (t) = V 1，n (t)-V 2，n (t).

[0132] When Ethernet is Gigabit Ethernet (1000BASE-T), the differential voltage V of the analog signal converted by the PHY chip is diff (t) is in the range of 0.4V to 2V; when Ethernet is 100M Ethernet (100BASE-TX), the differential voltage V of the analog signal converted by the PHY chip diff，n (t) is in the range of 0.2V to 2.5V.

[0133] In step S6, the power spectrum density S of the total electromagnetic interference of the differential signal generated by the single-phase common mode choke in the nth signal transmission network transformer is calculated. total，n The formula is as follows:

[0134]

[0135] in, is the differential mode voltage V diff，n (t) the power spectral density of the electromagnetic interference generated; is the common mode voltage V com，n (t) the power spectral density of the electromagnetic interference generated;

[0136]

[0137] Differential signal output PSD threshold S thr，n Adopt CISPR32 international standard, S thr，n =43.5dBμV / m.

[0138] Traditional methods for controlling EMI during Ethernet transmission, such as fixed resistor and capacitor filtering solutions, are only effective within a specific frequency range and cannot adapt to changes in different network cable lengths and electromagnetic environments. Although the digital signal processing (DSP) method of existing PHY chips can compensate for signal distortion to a certain extent, it is still difficult to ensure signal quality when high-frequency EMI interference is serious. Therefore, as another preferred embodiment of the present invention, the gradient descent optimization method is used in step S6 to optimize V 1，n (t) and V 2，n The steps of (t) are as follows:

[0139] S61: Construct optimization objective function:

[0140] S62: Constructing the gradient function of the objective function

[0141]

[0142] is the expected electromagnetic interference (EMI) value of the differential mode voltage signal, is the expected common mode voltage signal electromagnetic interference (EMI) value;

[0143]

[0144] Among them, V diff，n，ex (t) is the real-time expected differential voltage of the nth signal transmission network transformer, which meets the above requirements of 0.4V~2V or 0.2V~2.5V for different transmission speeds, V com，n，ex (t) is the real-time expected common-mode voltage of the single-phase common-mode choke of the nth signal transmission network transformer:

[0145]

[0146] V in，n，ex (t) the desired input digital signal level of 3.3V or 5V;

[0147] S63: The p-th generation optimization value of the differential signal voltage outputted from the first port corresponding to the single-phase common mode choke in the n-th transmission signal network transformer at the learning rate α The pth generation optimized value of the differential signal voltage output from the second port corresponding to the single-phase common-mode choke in the nth transmission signal network transformer Perform target gradient update:

[0148]

[0149] in, The differential signal voltages outputted from the first and second ports of the single-phase common-mode choke coil in the nth transmission signal network transformer obtained by the pth generation optimization are The objective function J is optimized based on the calculation, and the gradient function of the objective function is obtained by further taking the two as independent variables; are the p+1th generation optimized values ​​of the differential signal voltage outputted from the first port and the second port corresponding to the single-phase common mode choke in the nth transmitting signal network transformer; α=0.215;

[0150] S64: Determine the modulus of the gradient function of the p+1th generation objective function Is it less than the gradient optimization stop threshold 0.005? If so, stop the iteration; otherwise, repeat S61-S63.

[0151] In order to verify the effect of the method provided by the present invention on eliminating the electromagnetic interference generated by the common mode signal and the differential signal, Fig. 9 The comparison chart shown, Fig. 9 (a) is the change of the total EMI electromagnetic interference level using the method of the present invention with the monitoring time and the number of iterations, Fig. 9 (b) Only the S4 and S5 steps of the method of the present invention are used to calculate the impedance of the K component, but in the S6 step, when the differential mode signal output condition is not met, the ANN (artificial neural network) algorithm is used to calculate the impedance of the V 1，n (t) and V 2，n (t) The change of the total EMI electromagnetic interference level after optimization with the monitoring time and number of iterations; Fig. 9 (c) is the impedance of the K component, and the impedance of the K component is not accurately calculated using the S4 and S5 steps of the present invention, that is, the stray capacitance C of each coil in the two coils of K is not considered. tt，n , the stray capacitance C between the qth coil and the magnetic core tc，q，n , their own self-sensitivity self，q，n , leakage inductance L leak，q，n , resistor R wire，q，n And the core resistance R core，n and the impedance Z of the core core，n The impact on the accuracy of the impedance calculation of the K component is that only the impedance of the K component marked in the network transformer of the conventional prior art T component + K component (such as the publication number CN208045213U) is used to calculate V 1，n (t) and V 2，n (t), and in step S6, the total EMI electromagnetic interference noise level is iteratively optimized using the gradient optimization method of the present invention.

[0152] Depend on Fig. 9 (a) Fig. 9 (b) and Fig. 9 From the comparison of (c), we can see that in the initial stage of iteration (i.e., the stage of iterations 0-5), as the monitoring time increases, we can find that Fig. 9 The EMI noise fluctuation frequency of the method represented by (c) is the largest. Fig. 9 (b) Secondly, the method of the present invention Fig. 9 (a) The frequency is the lowest. It can be seen that the accurate calculation of the impedance parameters of the K element in the present invention can effectively improve the output differential signal V of the network transformer. 1，n (t) and V 2，n The control accuracy of (t) increases with the number of iterations. At the 30th iteration, it can be seen that Fig. 9 (b) The total EMI electromagnetic interference noise level still has certain fluctuations, and the gradient iteration method of step S6 of the present invention is Fig. 9 (a) and Fig. 9 (c) V obtained by optimization iteration 1，n (t) and V 2，n (t) The optimization result will no longer cause the total EMI electromagnetic interference noise level to fluctuate. It can be seen that the accurate calculation of the impedance parameters of the K component in steps S4-S5 of the method of the present invention, supplemented by the gradient optimization method in step S6, outputs the optimal differential mode signal.

[0153] The present invention also provides an Ethernet data transmission system using the above network transformer, the system includes a MAC layer main control module, a PHY chip, a plurality of feedback signal network transformers, a plurality of transmission signal network transformers and an RJ45 connector, and also includes a device for real-time monitoring of the real-time current I of the two coils of each network transformer. 1，n (t) and I 2，n (t) coil current monitoring module; such as Fig.10 , Fig.11 As shown in the figures, respectively, a 100M Ethernet data transmission system and a 100M Ethernet data transmission system using a network transformer having a single-phase common mode choke as a K element of the present invention are used; Figure 4 As shown on the left, the feedback signal transformer and the transmission signal network transformer are both network transformers with a single-phase common mode choke (CMC), including a transformer as a T-piece and a single-phase common mode choke as a K-piece. The coil ratio of the transformer as a T-piece is 1:1, and the center taps of the left coil and the right coil of the transformer as a T-piece are both grounded, and the two ends of the right coil are respectively connected in series with the first coil and the second coil of the single-phase common mode choke as the K-piece.

[0154] Because non-ideal transformers have parasitic capacitance, part of the EMI signal will be coupled to the primary end of the transformer through the parasitic capacitance. Therefore, in order to further block the mutual propagation of EMI between the primary and secondary coils, a K-piece (Common mode Choke) can be connected in series on the primary or secondary end of the transformer based on a single T-piece network transformer. This is a T-piece + K-piece network transformer.

[0155] The K component (common mode choke) is used to suppress coupled EMI. Its inductive reactance to balanced signals (differential mode) is almost zero, and its inductive reactance to unbalanced signals (common mode) is proportional to the frequency and inductance value.

[0156] Although placing the K component on the line side can better suppress EMI interference, the increased impedance of the common-mode inductor will affect the 75R termination effect of the transformer center tap (affecting impedance matching). Therefore, for voltage-type PHY, a network transformer with the common-mode inductor on the PHY side is generally selected; in addition, if POE is used, the common-mode inductor on the line side will cause magnetic saturation due to the POE power supply current, which greatly reduces the common-mode suppression effect. Therefore, the transformer with the common-mode inductor on the line side cannot be used in the POE scenario.

[0157] The MAC layer main control module is used to receive feedback differential signal pairs from external network devices such as RJ45 connectors through Ethernet cables (such as Cat5e, Cat6), and the feedback differential signal pairs are processed by the corresponding network transformer and transmitted to the feedback differential signal pair receiving first pin (positive end) and feedback differential signal pair receiving second pin (negative end) of the PHY chip; and the feedback differential signal pair restored to the digital signal is verified, and the processed data is transmitted to a higher layer (such as the IP layer and the transport layer) for further data analysis and processing; when 100M Ethernet is transmitted, as shown in Table 1, RX+ and RX- are a pair of differential signals, and TX+ and TX- are the second pair of differential signals. When Gigabit Ethernet is transmitted, as shown in Table 2, MX0+ and MX0- are the first pair of differential signals, MX1+ and MX1- are the second pair of differential signals, MX2+ and MX2- are the third pair of differential signals, and MX3+ and MX3- are the fourth pair of differential signals;

[0158] Table 1 Pin numbers and signal names of RJ45 connectors in 100M Ethernet data transmission system

[0159] Pin Number Signal name 1 TX+ 2 TX- 3 RX+ 4 5 6 RX- 7 8

[0160] Combining Table 1 and Fig.10As shown in the figure, when the system is a 100M Ethernet data transmission system, the system includes two network transformers, where the second transformer circuit composed of T and K from top to bottom is the signal transmission network transformer, and the RJ45 connector only uses four pins, namely 1, 2, 3, and 6. At this time, the feedback differential signal in step S1 is RX+ and RX-. After the external network device transmits the initial feedback differential signal to the RJ45 connector, the feedback differential signal pair RX+ and RX- is obtained. RX+ and RX- are then transmitted through pins 3 and 6 in the RJ45 connector and the feedback signal network transformer (i.e. Fig.10 The second voltage conversion circuit composed of T and K from top to bottom in the figure) is respectively transmitted to the feedback differential signal of the PHY chip to receive the first pin (i.e. Fig.10 RXIP pin in the PHY chip), and the feedback differential signal of the PHY chip receives the second pin (i.e. Fig.10 The PHY chip performs analog-to-digital conversion and transmits the analog-to-digital conversion to the MAC layer main control module connected to the PHY chip.

[0161] After the MAC layer main control module sends the data to be sent to the PHY chip, the digital signal pair to be sent is processed through steps S3-S6. The differential signal pair that meets the output standard in step S6 is TX+ and TX-, which are respectively sent through the differential signal pair of the PHY chip to the first pin (i.e. Fig.10 The TXOP pin in the PHY chip sends a differential signal to the second pin (i.e. Fig.10 Finally, the RJ45 connector receives the differential signal through the first pin (i.e., pin 1) and the second pin (i.e., pin 2) of the differential signal pair, which meets the differential signal output PSD threshold S. thr，n And the differential signal pair optimized by gradient descent optimization method: V 1，1 (t) and V 2，1 (t), and further adopted Fig.10 The right end of the RJ45 connector in the transmission is transmitted to the external network device connected to it. In this case, N = 1, n = 1.

[0162] Table 2 Gigabit Ethernet data transmission system RJ45 connector pin numbers and signal names

[0163] Pin Number Signal name 1 MX0+ 2 MX0- 3 MX1+ 4 MX1- 5 MX2+ 6 MX2- 7 MX3+ 8 MX3-

[0164] Combining Table 2 and Fig.11 As shown, when the system is a 100M Ethernet data transmission system, in this case, N=2, n=1 or 2. Fig.11Counting from top to bottom, the first and third transformer circuits composed of T and K components are the signal transmission network transformers, namely the first signal transmission network transformer and the second signal transmission network transformer; Fig.11 Counting from top to bottom, the second and fourth transformer circuits composed of T and K are feedback signal network transformers, namely the first feedback signal network transformer and the second feedback signal network transformer; all 8 pins of the RJ45 connector are used. At this time, there are two pairs of feedback differential signal pairs in S1, namely the first feedback differential signal pair: MX1+ and MX- and the second feedback differential signal pair: MX3+ and MX3-. In step S6, the differential signal pair received by the RJ45 connector is lower than the differential signal output PSD threshold S thr，n And the differential signal pairs optimized by the gradient descent optimization method also have two pairs: the first optimized output differential signal pair MX0+ and MX0-, that is, V 1，1 (t) and V 2，1 (t); The second optimization has an output differential signal pair MX2+ and MX2-, that is, V 1，2 (t) and V 2，2. (t).

[0165] After the external network device transmits two pairs of preliminary feedback differential signals to the RJ45 connector, the first feedback differential signal pair MX1+ and MX1-, and the second feedback differential signal pair MX3+ and MX3- are obtained. MX1+ and MX1- are processed by the first feedback signal network transformer, and MX3+ and MX3- are processed by the second feedback signal network transformer; MX1+ and MX1- are transmitted to the first feedback signal network transformer through pins 3 and 6 in the RJ45 connector respectively, and MX3+ and MX3- are transmitted to the second feedback signal network transformer through pins 7 and 8 of the RJ45 connector respectively. After the first feedback signal network transformer and the second feedback signal network transformer process the two pairs of feedback differential signals respectively, the processed differential signals corresponding to MX1+ and MX- are further received through the first feedback differential signal pair receiving first pin MDIP1 and the first feedback differential signal pair receiving second pin MDIN1 of the PHY chip, and are further transmitted to the MAC layer main control module; the processed differential signals corresponding to MX3+ and MX3- are further received through the second feedback differential signal pair receiving first pin MDIP3 and the second feedback differential signal pair receiving second pin MDIN3 of the PHY chip, and are further transmitted to the MAC layer main control module.

[0166] In this case, the data that the MAC layer main control module needs to send is also two digital signals. After the two are sent to the PHY chip, the PHY chip, the first sending signal network transformer and the second sending signal network transformer are controlled to process the digital signal pair to be sent through steps S3-S6. The differential signals that meet the output standard in step S6 include the first pair of differential signals: MX0+ and MX0- (corresponding to MX1+ and MX1-, that is, MX1+ and MX1- are feedback data information that the external network device needs to transmit to the MAC layer main control module. After analysis and processing, the MAC layer main control module needs to send digital signals MX0+ and MX0- corresponding to the feedback data information MX1+ and MX1- to the external network device.), and the differential signals that meet the output standard in step S6 also include the second pair of differential signals: MX2+ and MX2- (corresponding to MX3+ and MX3-).

[0167] The first pair of differential signals: MX0+ and MX0-, are sent to the first pin (i.e. Fig.11 MDIP1 pin in the PHY chip), and the first differential signal pair of the PHY chip sends the second pin (i.e. Fig.11 Finally, the RJ45 connector receives the first differential signal pair through the first pin (i.e., pin 1) and the second differential signal pair (i.e., pin 2) respectively, which meets the differential signal output PSD threshold S thr，n And the differential signal pair optimized by gradient descent optimization method: V 1，1 (t) and V 2，1 (t).

[0168] The second pair of differential signals: MX2+ and MX2-, are sent to the first pin (i.e. Fig.11 MDIP2 pin in the PHY chip), and the second differential signal pair of the PHY chip sends the second pin (i.e. Fig.11 Finally, the RJ45 connector receives the first pin (i.e., pin 4) through the second differential signal pair and the second pin (i.e., pin 5) through the second differential signal pair, and receives the signal that meets the differential signal output PSD threshold S lower than the PSD threshold S. thr，n And the differential signal pair optimized by gradient descent optimization method: V 1，2 (t) and V 2，2 (t).

[0169] The PHY chip in the Ethernet data transmission system provided in the present invention is preferably a voltage-driven chip. The PHY (physical layer) chip is located at the physical layer of Ethernet communication. The PHY chip converts digital data from the MAC layer into a signal suitable for transmission through a physical medium (such as a twisted pair), and performs signal reception and transmission operations, and is used to process the conversion between the input digital signal and the analog signal transmitted from the physical network line fed back through the RJ45 connector; the PHY chip decodes the feedback differential signal pair (analog signal) and restores it to a digital signal and transmits it to the MAC layer main control module, and is used to receive the digital signal input from the MAC main control module, and then convert the received parallel data into serial stream data, and encode the serial stream data according to the encoding rules of the physical layer; and real-time monitoring of the real-time current I in the first coil of the single-phase common mode choke coil as the K component in the nth signal transmission network transformer. 1，n (t), real-time current I in the second coil 2，n (t);

[0170] The MAC layer main control module is also used to calculate the impedance Z of the single-phase common mode choke coil as the K component in the corresponding nth transmission signal network transformer. K，n , according to the voltage level of the input analog voltage signal V in，n (t), calculate the common mode voltage V of the single-phase common mode choke com，n (t);

[0171] And calculate the differential signal voltage V output from the first port corresponding to the single-phase common mode choke of the nth signal transmission network transformer 1，n (t), differential signal voltage V output from the second port 2，n (t) and the differential mode voltage V diff，n (t); and calculate the power spectrum density S of the total electromagnetic interference of the differential signal generated by the single-phase common-mode choke of the nth signal transmission network transformer total，n , determine whether it is lower than the differential signal output PSD threshold S thr，n If so, the differential signal pair of the PHY chip is controlled to transmit the first pin and the differential signal pair to transmit the second pin to transmit V 1，n (t) and V 2，n (t) to the RJ45 connector and further output to the external network device; otherwise, the MAC layer main control module continues to use the gradient descent optimization method to optimize V 1，n (t) and V 2，n (t).

[0172] The communication connection between the MAC layer main control module and the PHY chip in the present invention can adopt MII interface (100M Ethernet data transmission), RMII interface (100M Ethernet data transmission), GMII interface (100M or 1000M), and RGMII interface (100M or 1000M) according to the requirements of Ethernet transmission rate of 100M or 1000M.

[0173] Although the present invention has been described with reference to preferred embodiments, various modifications may be made thereto and corresponding technical features or branch technical solutions therein may be replaced with equivalents without departing from the scope of the present invention. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there is no conflict between technical steps and branch technical solutions. The present invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. An Ethernet data transmission method based on a single-phase CMC network transformer, wherein the method dynamically optimizes electromagnetic interference during Ethernet data transmission based on a network transformer with a single-phase common mode choke, and is characterized in that: The method comprises the following steps: S1: The MAC layer main control module receives a feedback differential signal pair from an external network device such as an RJ45 connector through an Ethernet cable, and the feedback differential signal pair is processed by a corresponding feedback signal network transformer and transmitted to a feedback differential signal pair receiving first pin and a feedback differential signal pair receiving second pin of the PHY chip; S2: The PHY chip decodes the feedback differential signal pair and restores the digital signal to the MAC layer main control module; the MAC layer main control module verifies the feedback differential signal pair restored to the digital signal, and transmits the processed data to a higher layer for further data analysis and processing; S3: The MAC layer main control module sends the data to be sent to the PHY chip according to the situation. After receiving the digital signal input from the MAC main control module, the PHY chip converts the received parallel data into serial stream data, encodes the serial stream data according to the encoding rules of the physical layer, and controls the differential signal pair of the PHY chip to send the first pin and the differential signal pair to send the second pin to the network transformer; at the same time, real-time monitoring of the real-time current I in the first coil of the single-phase common mode choke coil as the K component in the nth signal sending network transformer 1,n (t), real-time current I in the second coil 2,n (t); S4: Calculate the impedance Z of the single-phase common mode choke as K component in the corresponding nth transmission signal network transformer K,n , according to the voltage level of the input analog voltage signal V in,n (t), calculate the common mode voltage V of the single-phase common mode choke com,n (t); S5: Calculate the differential signal voltage V output from the first port corresponding to the single-phase common-mode choke in the nth signal transmission network transformer 1,n (t), differential signal voltage V output from the second port 2,n (t) and the differential mode voltage V diff,n (t); S6: Calculate the power spectrum density S of the total electromagnetic interference of the differential signal generated by the single-phase common mode choke in the nth transmitting signal network transformer total,n , determine whether it is lower than the differential signal output PSD threshold S thr,n If so, the differential signal pair of the PHY chip is controlled to transmit the first pin and the differential signal pair to transmit the second pin to transmit V 1,n (t) and V 2,n (t) to the RJ45 connector, and further output to the external network device; otherwise, the MAC layer main control module continues to use the gradient descent optimization method to optimize V 1,n (t) and V 2,n (t).

2. The Ethernet data transmission method based on the single-phase CMC network transformer according to claim 1 is characterized in that: The S3 step includes: S31: Collect the received parallel data to obtain a parallel data set D: D = {D I-1 ,D I-2 ,…,D i ,…,D2,D1,D0}, where D i is the i+1th binary parallel data, D i =0 or 1; I is the total number of binary parallel data in the parallel data set D; I=4 or 8; S32: The PHY chip stores the data in the parallel data set D in step S11 according to the most significant bit D I-1 Arrange the bits from front to back to the least significant bit D0 and then output them bit by bit in the order of arrangement; S33: According to the NRZ encoding rule, the binary parallel data D outputted bit by bit in step S12 is i Convert to analog voltage signal according to the following mapping rules: Among them, U0 and U1 are respectively the high voltage level and the low voltage level after the digital signal is converted, U1 = 3.3V or 5V, and U0 = 0V.

3. The Ethernet data transmission method based on the single-phase CMC network transformer according to claim 1 is characterized in that: The S4 step includes: S41: Calculate the total impedance Z of the first coil of the K component in the nth signal transmission network transformer k1,n The total impedance Z of the second coil k2,n ; Z kq,n =R wire,q,n +jωL self,q,n +jωL leak,q,n +Z core,n ; q = 1 or 2; R wire,q,n , L self,q,n , L leak,q,n and Z core,n are the resistance, self-inductance, leakage inductance of the qth coil of the K-component in the nth signal transmission network transformer and the impedance of the nth magnetic core, q=1 or 2; S42: According to the result of step S42, calculate the total impedance Z generated by the two coils in the single-phase common mode choke coil as the K element in the nth signal transmission network transformer. K,n : S43: Calculate the common mode voltage of the single-phase common mode choke as the K component in the nth transmission signal network transformer: Among them, C3 is the capacitance value of the third capacitor C3 commonly connected before N signal transmission network transformers and the RJ45 connector are grounded; N is the total number of signal transmission network transformers included in the system, N=1 or 2, n=1,2,…,N; R1, R2, R3 and R4 are the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4; j is an imaginary number; ω is the angular frequency of the input digital signal, ω=2πf, f is the frequency of the input digital signal, f=125MHz.

4. The Ethernet data transmission method based on the single-phase CMC network transformer according to claim 3 is characterized in that: The S5 step includes: S51: Calculate the stray capacitance C of each coil in the nth signal transmission network transformer tt,n , the stray capacitance C between the qth coil and the magnetic core tc,q,n : Among them, δ r is the dielectric constant of the coil insulation layer; r win is the circular cross-sectional radius of the coil wire, δ0 is the vacuum dielectric constant of the coil, δ0=8.854×10 -12 F / m; r wo The outer diameter of the coil wire after it is surrounded by a circle of insulating medium; d coil A is the horizontal winding distance between the inner and outer cores of each coil of a K-piece, coil A is the effective capacitance area between the two coils of a K-piece; tc,q is the effective capacitance area between the qth coil and the magnetic core in a K-piece, h tc A is the height difference between the center point of the cross section of a coil wire in a K part and the surface of the magnetic core; tc,q =D c,q ×(h c (r cin -r co )),h c is the vertical height of the coil when it is wrapped around the core, r cin is the inner diameter of the core, r co is the outer diameter of the core; D c,q is the average path length of the qth coil wound around the toroidal core in a K-piece; S52: Calculate the self-inductance L of the qth coil in the nth signal transmission network transformer self,q,n , the leakage inductance L of the qth coil leak,q,n : Among them, M q is the number of times the qth coil is wound around the magnetic core; Among them, θ q is the angle that the qth coil passes through when it is wound around the toroidal core; S53: Calculate the resistance R of the i-th coil wire,q,n , the resistance R of the core in the single-phase common mode choke coil as the K element in the nth transmission signal network transformer core,n Its impedance Z core,n : Among them, ρ w is the density of the coil, ρ w =8.9g / cm 3 ; γ is the skin depth of the coil material, ξ w is the resistivity of the coil, ξ w =1.68×10-8Ω·m; μ Copper is the relative magnetic permeability of the enameled copper wire coil, μ Copper =1; μ0 is the vacuum magnetic permeability, μ0=4π×10 -1 H / m; Among them, A e is the cross-sectional area of ​​the core, η core , a and b are the first, second and third Steinmetz coefficients of the magnetic core respectively, η core It is related to the material of the magnetic core, a=1.5~2, b=2~2.5; I rms,n is the equivalent RMS current in the core of the single-phase common-mode choke in the nth transmitting signal network transformer, For I 1,n (t) and I 2,n (t) phase difference; Among them, μ r is the relative magnetic permeability of the core material; S54: Calculate the differential signal voltage V outputted from the first port corresponding to the single-phase common-mode choke in the nth signal transmission network transformer 1,n (t), differential signal voltage V output from the second port 2,n (t): Among them, I DM,1,n (t), I DM,2,n (t) are the differential signal currents flowing through the first and second coils of the single-phase common-mode choke in the nth transmitting signal network transformer, I DM,1,n (t) = I 1,n (t)-I CM,1,n (t), I DM,2,n (t) = I 2,n (t)-I CM,2,n (t), I CM,1,n (t) = I CM,2,n (t)=0.5V com,n (t) / Z K,n ;I CM,1,n (t), I CM,2,n (t) are the common mode signal currents flowing through the first coil and the second coil of the single-phase common mode choke in the nth transmitting signal network transformer; S55: Further calculate the differential mode voltage V diff,n (t): V diff,n (t)=V 1,n (t)-V 2,n (t)。 5. The Ethernet data transmission method based on the single-phase CMC network transformer according to claim 3 is characterized in that: When the Ethernet is Gigabit Ethernet (1000BASE-T), the differential voltage V of the analog signal converted by the PHY chip is diff (t) is in the range of 0.4V to 2V; when the Ethernet is 100M Ethernet (100BASE-TX), the differential voltage V of the analog signal converted by the PHY chip diff,n (t) is in the range of 0.2V to 2.5V.

6. The Ethernet data transmission method based on the single-phase CMC network transformer according to claim 4 is characterized in that: In the step S6, the power spectrum density S of the total electromagnetic interference of the differential signal generated by the single-phase common mode choke in the nth signal transmission network transformer is calculated. total,n The formula is as follows: in, is the differential mode voltage V diff,n (t) the power spectral density of the electromagnetic interference generated; is the common mode voltage V com,n (t) the power spectral density of the electromagnetic interference generated; The differential signal output PSD threshold S thr,n Adopt CISPR32 international standard, S thr,n =43.5dBμV / m.

7. The Ethernet data transmission method based on the single-phase CMC network transformer according to claim 6 is characterized in that: In the step S6, the gradient descent optimization method is used to optimize V 1,n (t) and V 2,n The steps of (t) are as follows: S61: Construct optimization objective function: S62: Constructing the gradient function of the objective function is the expected electromagnetic interference value of the differential mode voltage signal, is the expected common mode voltage signal electromagnetic interference value; S63: The p-th generation optimization value of the differential signal voltage outputted from the first port corresponding to the single-phase common mode choke in the n-th transmission signal network transformer at the learning rate α The pth generation optimized value of the differential signal voltage output from the second port corresponding to the single-phase common mode choke in the nth transmission signal network transformer Perform target gradient update: in, are the p+1th generation optimized values ​​of the differential signal voltage outputted from the first port and the second port corresponding to the single-phase common mode choke in the nth transmitting signal network transformer; α=0.215; S64: Determine the modulus of the gradient function of the p+1th generation objective function Is it less than the gradient optimization stop threshold 0.005? If so, stop the iteration; otherwise, repeat S61-S63.

8. An Ethernet data transmission system based on a single-phase CMC network transformer using the method as described in any one of claims 1 to 7, characterized in that: The system includes a MAC layer main control module, a PHY chip, multiple feedback signal transformers, multiple transmission signal network transformers and an RJ45 connector, and also includes a device for real-time monitoring of the real-time current I of two coils of each network transformer. 1,n (t) and I 2,n (t) coil current monitoring module; The MAC layer main control module is used to receive a feedback differential signal pair from an external network device such as an RJ45 connector through an Ethernet cable, and the feedback differential signal pair is processed by a corresponding feedback signal network transformer and transmitted to a feedback differential signal pair receiving first pin and a feedback differential signal pair receiving second pin of the PHY chip; and to verify the feedback differential signal pair restored to a digital signal, and transmit the processed data to a higher layer for further data analysis and processing; The PHY chip is used to process the conversion between the input digital signal and the analog signal transmitted from the physical network line fed back by the RJ45 connector; the PHY chip decodes the feedback differential signal pair and restores it to the digital signal for transmission to the MAC layer main control module, and is used to receive the digital signal input from the MAC main control module, convert the received parallel data into serial stream data, and encode the serial stream data according to the encoding rules of the physical layer; And real-time monitoring of the real-time current I in the first coil of the single-phase common mode choke coil as the K component in the nth signal transmission network transformer 1,n (t), real-time current I in the second coil 2,n (t); The MAC layer main control module is also used to calculate the impedance Z of the single-phase common mode choke coil as the K component in the corresponding nth signal transmission network transformer K,n , according to the voltage level of the input analog voltage signal V in,n (t), calculate the common mode voltage V of the single-phase common mode choke com,n (t); And calculate the differential signal voltage V output from the first port corresponding to the single-phase common mode choke in the nth signal transmission network transformer 1,n (t), differential signal voltage V output from the second port 2,n (t) and the differential mode voltage V diff,n (t); and calculate the power spectrum density S of the total electromagnetic interference of the differential signal generated by the single-phase common mode choke in the nth transmission signal network transformer total,n , determine whether it is lower than the differential signal output PSD threshold S thr,n If so, the differential signal pair of the PHY chip is controlled to transmit the first pin and the differential signal pair to transmit the second pin to transmit V 1,n (t) and V 2,n (t) to the RJ45 connector, and further output to the external network device; otherwise, the MAC layer main control module continues to use the gradient descent optimization method to optimize V 1,n (t) and V 2,n (t).

9. The Ethernet data transmission system based on the single-phase CMC network transformer according to claim 8, characterized in that: The network transformer includes a transformer as a T-piece and a single-phase common-mode choke as a K-piece. The coil ratio of the transformer as the T-piece is 1:

1. The center tap of the left coil and the center tap of the right coil of the transformer as the T-piece are both grounded, and the two ends of the right coil are respectively connected in series with the first coil and the second coil of the single-phase common-mode choke as the K-piece.

10. The Ethernet data transmission system based on the single-phase CMC network transformer according to claim 8, characterized in that: The PHY chip is a voltage driven chip.

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