Charging protocol compatibility test equipment

Abstract

The embodiment of the invention provides charging protocol compatibility testing equipment, and relates to the technical field of electronic appliances. According to the charging protocol compatibility test equipment, a test environment does not need to be built manually, and instrument operation and waveform observation do not need to be performed manually. And the testing precision is improved while the manpower is saved. The charging protocol compatibility test equipment comprises an upper computer connection port, a signal processing module, a first port, a first signal acquisition module, a first signal output module, a first constant current source and a first connection module. The first signal acquisition module is used for acquiring an analog quantity first voltage signal of the first port through the first connection module, and converting the analog quantity first voltage signal into a digital quantity first voltage signal. The first signal output module is used for acquiring a digital quantity second voltage signal of the signal processing module and converting the digital quantity second voltage signal into an analog quantity second voltage signal. The first constant current source is used for outputting current with a preset current value.

Description

Technical Field

[0001] The present application relates to the field of electronic and electrical technology, and in particular to a charging protocol compatibility testing device. Background Art

[0002] With the development of technology, the charging protocols used in portable mobile terminals and their chargers are changing with each passing day, and various charging protocols are emerging one after another. In order to confirm the charging protocol compatibility between the mobile terminal and the charger, it is often necessary to manually build the test environment required for testing the charging protocol compatibility, and then test the charging protocol compatibility of the mobile terminal or charger.

[0003] The above test method not only requires manual construction of the test environment, but also requires manual operation of the instrument and observation of the waveform, which has the problems of cumbersome operation, poor accuracy and very time-consuming. In addition, since the handshake time required for the charging protocol is short and the time required for the test is highly synchronized, manual testing cannot accurately capture the measurement value, which ultimately leads to increased error in the measurement result. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a charging protocol compatibility test device, which does not require manual construction of the test environment, manual operation of the instrument and observation of the waveform, thereby saving manpower and improving the test accuracy.

[0005] The embodiment of the present application provides a charging protocol compatibility test device, including: a host computer connection port, a signal processing module, a first port, a first signal acquisition module, a first signal output module, a first constant current source, and a first connection module; the host computer connection port is connected to the signal processing module for establishing a communication connection between the host computer and the signal processing module; the first connection module is connected to the positive data terminal and the negative data terminal of the first port for connecting the first signal acquisition module, the first signal output module, and the first constant current source to the positive data terminal and / or the negative data terminal of the first port under the control of the signal processing module; the first signal acquisition module is used to obtain an analog first voltage signal of the positive data terminal and / or the negative data terminal of the first port through the first connection module, and convert the analog first voltage signal into an analog first voltage signal. The first signal output module is used to obtain the digital second voltage signal output by the signal processing module, convert the digital second voltage signal into an analog second voltage signal that conforms to the voltage value range in the charging protocol, and output the analog second voltage signal to the positive data terminal and / or the negative data terminal of the first port through the first connection module; the first constant current source is used to output a current of a preset current value, and output it to the positive data terminal and / or the negative data terminal of the first port through the first connection module; the signal processing module is used to output the digital second voltage signal, obtain the digital first voltage signal, and determine whether the digital first voltage signal is consistent with the preset first voltage signal; or, obtain the digital first voltage signal.

[0006] The host computer can send control instructions to the signal processing module, and the signal processing module automatically executes the test task according to the control instructions, thus saving manpower and improving the test accuracy.

[0007] In some possible implementations, it also includes a second port, a second signal acquisition module, a second signal output module, a second constant current source, and a second connection module; the second connection module is connected to the positive data terminal and the negative data terminal of the second port, and is used to connect the second signal acquisition module, the second signal output module, and the second constant current source to the positive data terminal and / or the negative data terminal of the second port under the control of the signal processing module; the second signal acquisition module is used to obtain the analog third voltage signal of the positive data terminal and / or the negative data terminal of the second port through the second connection module, and convert the analog third voltage signal into a digital third voltage signal and input it into the signal processing module; the second signal output module The block is used to obtain the digital fourth voltage signal output by the signal processing module, convert the digital fourth voltage signal into an analog fourth voltage signal that complies with the voltage value range in the charging protocol, and output the analog fourth voltage signal to the positive data terminal and / or negative data terminal of the second port through the second connection module; the second constant current source is used to output a current of a preset current value, and output it to the positive data terminal and / or negative data terminal of the second port through the second connection module; the signal processing module is also used to output the digital fourth voltage signal, obtain the digital third voltage signal, and determine whether the digital third voltage signal is consistent with the preset third voltage signal; or, obtain the digital third voltage signal. Through the additional modules above, the simultaneous access of the mobile terminal and the charger can be realized, further expanding the scope of the testable items of the device.

[0008] In some possible implementations, a first device connection port and a first charging parameter acquisition circuit are also included; the first device connection port is used to connect a DC power supply or an electronic load, the positive end of the first device connection port is connected to the positive data terminal of the first port through the first charging parameter acquisition circuit, and the first charging parameter acquisition circuit is used to collect the positive terminal voltage and current of the first device connection port and input them into the signal processing module. An external DC power supply or electronic load can be connected through the first device connection port to realize power input or output of the first port. Further improve the simulation capability of the test equipment and expand the test items.

[0009] In some possible implementations, it also includes a first device connection port, a first charging parameter acquisition circuit, a second device connection port, and a second charging parameter acquisition circuit; the first device connection port is used to connect a DC power supply, the positive end of the first device connection port is connected to the positive data terminal of the first port through the first charging parameter acquisition circuit, and the first charging parameter acquisition circuit is used to collect the positive terminal voltage and current of the first device connection port, and input them into the signal processing module; the second device connection port is used to connect an electronic load, the positive end of the second device connection port is connected to the positive data terminal of the second port through the second charging parameter acquisition circuit, and the second charging parameter acquisition circuit is used to collect the positive terminal voltage and current of the second device connection port, and input them into the signal processing module. An external DC power supply and an electronic load can be connected through the first device connection port and the second device connection port to realize power input or output of the first port and the second port. Further improve the simulation capability of the test equipment and expand the test items.

[0010] In some possible implementations, the host computer connection port includes a local area network interface, the signal processing module includes a single-chip microcomputer and / or a field programmable gate array, and the first port includes a Type-C or USB-A interface. The port has a simple structure and high reliability.

[0011] In some possible implementations, the host computer connection port includes a local area network interface, the signal processing module includes a single-chip microcomputer and / or a field programmable gate array, and the first port and the second port both include a Type-C or USB-A interface. The port has a simple structure and high reliability.

[0012] In some possible implementations, the first connection module includes a first bus connected to the positive data terminal of the first port, a second bus connected to the negative data terminal of the first port, and a first switch, a second switch and a third switch connected to the first bus, and a fourth switch, a fifth switch and a sixth switch connected to the second bus; the first end of the first switch is connected to the first bus, the second end of the first switch is connected to the first constant current source, the first end of the fourth switch is connected to the second bus, the second end of the fourth switch is connected to the first constant current source, the first end of the second switch is connected to the first bus, the second end of the second switch is connected to the first signal output module, the first end of the fifth switch is connected to the first bus, the second end of the fifth switch is connected to the first signal output module, the first end of the third switch is connected to the first bus, the second end of the third switch is connected to the first signal acquisition module, the first end of the sixth switch is connected to the first bus, the second end of the sixth switch is connected to the first signal acquisition module, and the first switch, the second switch, the third switch, the fourth switch, the fifth switch and the sixth switch are all controlled by the signal processing module. The above structure is simple in structure and has high reliability, and can be connected to the corresponding module according to actual needs.

[0013] In some possible implementations, the first connection module and the second connection module each include a first bus connected to the positive data terminal of the first port / the second port, and a second bus connected to the negative data terminal of the first port / the second port, and a first switch, a second switch and a third switch connected to the first bus, and a fourth switch, a fifth switch and a sixth switch connected to the second bus; a first end of the first switch is connected to the first bus, a second end of the first switch is connected to the first constant current source / the second constant current source, a first end of the fourth switch is connected to the second bus, a second end of the fourth switch is connected to the first constant current source / the second constant current source, a first end of the second switch is connected to the first bus, a second end of the second switch is connected to the first signal output module / the second signal output module, a first end of the fifth switch is connected to the first bus, a second end of the fifth switch is connected to the first signal output module / the second signal output module, a first end of the third switch is connected to the first bus, a second end of the third switch is connected to the first signal acquisition module / the second signal acquisition module, a first end of the sixth switch is connected to the first bus, a second end of the sixth switch is connected to the first signal acquisition module / the second signal acquisition module, and the first switch, the second switch, the third switch, the fourth switch, the fifth switch and the sixth switch are all controlled by the signal processing module. The above structure is simple in construction and highly reliable, and can be connected to corresponding modules according to actual needs.

[0014] In some possible implementations, the first signal acquisition module includes a positive data terminal acquisition submodule and a negative data terminal acquisition submodule, and the positive data terminal acquisition submodule and the negative data terminal acquisition submodule each include a voltage follower, a first reverse amplifier, and an analog-to-digital conversion chip connected in series in sequence. The structure is simple in design, highly flexible, and has strong anti-interference capabilities.

[0015] In some possible implementations, the first signal acquisition module and the second signal acquisition module both include a positive data terminal acquisition submodule and a negative data terminal acquisition submodule, and the positive data terminal acquisition submodule and the negative data terminal acquisition submodule both include a voltage follower, a first reverse amplifier, and an analog-to-digital conversion chip connected in series in sequence. The structure is simple in design, highly flexible, and has strong anti-interference capabilities.

[0016] In some possible implementations, the voltage follower includes a first operational amplifier, the positive feedback input terminal of the first operational amplifier is used as the input terminal of the first operational amplifier, and the negative feedback input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier; the first reverse amplifier includes a first resistor, a second resistor, a third resistor and a second operational amplifier, the first end of the first resistor is connected to the output terminal of the first operational amplifier, the second end of the first resistor is connected to the negative feedback input terminal of the second operational amplifier, the first end of the second resistor is connected to the negative feedback input terminal of the second operational amplifier, the second end of the second resistor is connected to the output terminal of the second operational amplifier, the first end of the third resistor is connected to the positive feedback input terminal of the second operational amplifier, the second end of the third resistor is grounded, the output terminal of the second operational amplifier is connected to the input terminal of the analog-to-digital conversion chip, and the output terminal of the analog-to-digital conversion chip is connected to the input terminal of the signal processing module. The structure is simple in design and has high reliability.

[0017] In some possible implementations, the first signal output module includes a positive data terminal output submodule and a negative data terminal output submodule, and the positive data terminal output submodule and the negative data terminal output submodule each include a digital-to-analog conversion chip, a subtractor, and a second reverse amplifier connected in series. The structure is flexible in design and is suitable for adjusting the output voltage range according to actual needs.

[0018] In some possible implementations, the first signal output module and the second signal output module both include a positive data terminal output submodule and a negative data terminal output submodule, and the positive data terminal output submodule and the negative data terminal output submodule both include a digital-to-analog conversion chip, a subtractor, and a second reverse amplifier connected in series. This structure is flexible in design and is suitable for adjusting the output voltage range according to actual needs.

[0019] In some possible implementations, the output end of the signal processing module is connected to the input end of the digital-to-analog conversion chip; the subtractor includes a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor and a third operational amplifier, the first end of the fourth resistor is connected to the first current output end of the digital-to-analog conversion chip, the second end of the fourth resistor is grounded, the first end of the fifth resistor is connected to the second current output end of the digital-to-analog conversion chip, the second end of the fifth resistor is grounded, the first end of the sixth resistor is connected to the first current output end of the digital-to-analog conversion chip, the second end of the sixth resistor is connected to the negative feedback input end of the third operational amplifier, the first end of the seventh resistor is connected to the second current output end of the digital-to-analog conversion chip, and the second end of the seventh resistor is connected to the third The first end of the eighth resistor is connected to the negative feedback input end of the third operational amplifier, the second end of the eighth resistor is connected to the output end of the third operational amplifier, the first end of the ninth resistor is connected to the positive feedback input end of the third operational amplifier, and the second end of the ninth resistor is connected to the ground; the second reverse amplifier includes a tenth resistor, an eleventh resistor and a fourth operational amplifier, the first end of the tenth resistor is connected to the output end of the third operational amplifier, the second end of the tenth resistor is connected to the negative feedback input end of the fourth operational amplifier, the first end of the eleventh resistor is connected to the negative feedback input end of the fourth operational amplifier, the second end of the eleventh resistor is connected to the output end of the fourth operational amplifier, and the positive feedback input end of the fourth operational amplifier is connected to the ground. The structure is simple in design, high in reliability, and low in cost.

[0020] In some possible implementations, the first constant current source includes a twelfth resistor, a thirteenth resistor, a fifth operational amplifier, and a constant current source chip; the first end of the thirteenth resistor is connected to the output end of the fifth operational amplifier, the second end of the thirteenth resistor is used as the output end of the first constant current source, the first end of the twelfth resistor is connected to the positive feedback input end of the fifth operational amplifier, the second end of the twelfth resistor is connected to the second end of the thirteenth resistor, the output end of the constant current source chip is connected to the positive feedback input end of the fifth operational amplifier, and the negative feedback input end of the fifth operational amplifier is connected to the output end of the fifth operational amplifier. The structure is simple and flexible, which is conducive to adjusting the output current value according to actual needs.

[0021] In some possible implementations, the first constant current source and the second constant current source both include a twelfth resistor, a thirteenth resistor, a fifth operational amplifier, and a constant current source chip; the first end of the thirteenth resistor is connected to the output end of the fifth operational amplifier, the second end of the thirteenth resistor is used as the output end of the first constant current source / second constant current source, the first end of the twelfth resistor is connected to the positive feedback input end of the fifth operational amplifier, the second end of the twelfth resistor is connected to the second end of the thirteenth resistor, the output end of the constant current source chip is connected to the positive feedback input end of the fifth operational amplifier, and the negative feedback input end of the fifth operational amplifier is connected to the output end of the fifth operational amplifier. The structure is simple and flexible, which is conducive to adjusting the output current value according to actual needs.

[0022] In some possible implementations, the first charging parameter acquisition circuit includes a sampling resistor, a sampling chip, and a seventh switch, the first end of the sampling resistor is connected to the charging current terminal of the first port, the second end of the sampling resistor is connected to the first end of the seventh switch, the second end of the seventh switch is connected to the positive end of the first device connection port, the first sampling terminal and the second sampling terminal of the sampling chip are respectively connected to the first end and the second end of the sampling resistor, the output end of the sampling chip is connected to the sampling input end of the signal processing module, and the seventh switch is controlled by the signal processing module. The structure is simple and reliable.

[0023] In some possible implementations, the first charging parameter acquisition circuit and the second charging parameter acquisition circuit both include a sampling resistor, a sampling chip, and a seventh switch, the first end of the sampling resistor is connected to the charging current terminal of the first port / the second port, the second end of the sampling resistor is connected to the first end of the seventh switch, the second end of the seventh switch is connected to the positive end of the first device connection port / the second device connection port, the first sampling terminal and the second sampling terminal of the sampling chip are respectively connected to the first end and the second end of the sampling resistor, the output end of the sampling chip is connected to the sampling input end of the signal processing module, and the seventh switch is controlled by the signal processing module. The structure is simple and reliable.

[0024] In some possible implementations, a port connection circuit is further included, the port connection circuit includes an eighth switch, a ninth switch, and a tenth switch, the first end of the eighth switch is connected to the positive data terminal of the first port, the second end of the eighth switch is connected to the positive data terminal of the second port, the first end of the ninth switch is connected to the negative data terminal of the first port, the second end of the ninth switch is connected to the negative data terminal of the second port, the first end of the tenth switch is connected to the second end of the sampling resistor of the first charging parameter acquisition circuit, the second end of the tenth switch is connected to the second end of the sampling resistor of the second charging parameter acquisition circuit, and the eighth switch, the ninth switch, and the tenth switch are all controlled by the signal processing module. The structure is simple in design, the control logic is clear, and the reliability is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A structural diagram of a fast charging protocol test circuit provided for related technologies;

[0026] Figure 2 A structural diagram of another fast charging protocol test circuit provided for related technologies;

[0027] Figure 3 A schematic diagram of the structure of a charging protocol compatibility test device provided in an embodiment of the present application;

[0028] Figure 4 A diagram showing the connection relationship of external devices of a charging protocol compatibility test device provided in an embodiment of the present application;

[0029] Figure 5 A schematic diagram of the structure of a first connection module provided in an embodiment of the present application;

[0030] Figure 6 A schematic diagram of the structure of a first signal acquisition module provided in an embodiment of the present application;

[0031] Figure 7 A schematic diagram of the structure of a first signal output module provided in an embodiment of the present application;

[0032] Figure 8 A schematic diagram of the structure of a first constant current source provided in an embodiment of the present application;

[0033] Fig. 9 A schematic diagram of the structure of a first charging parameter acquisition circuit provided in an embodiment of the present application;

[0034] Fig.10 A schematic diagram of the structure of a port connection circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0036] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0037] The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects rather than to describe a specific order of objects. For example, a first target object and a second target object are used to distinguish different target objects rather than to describe a specific order of target objects.

[0038] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0039] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to two or more than two. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

[0040] The embodiment of the present application provides a charging protocol compatibility testing device, which is used to test the charging protocol compatibility of a mobile terminal and a charger, and can also test the charging cable connecting the mobile terminal and the charger. Thereby determining whether the mobile terminal, the charger and the charging cable are compatible with certain charging protocols. The mobile terminal mentioned in this article can be any electronic device that needs to be charged, such as a mobile phone, a laptop computer, a tablet computer, a personal digital assistant (PDA for short), a car computer, a smart wearable device, a smart home device, etc. Taking the electronic device as an example, the following introduces the scenario in which the charger charges the mobile phone under the fast charging protocol.

[0041] Generally speaking, mobile phone charging interfaces and charger interfaces that support the fast charging protocol have a charging current terminal Vbus, a positive data terminal D+, a negative data terminal D-, and a ground terminal GND. The terminals of the mobile phone charging interface are connected to the corresponding terminals of the charger charging interface through a charging cable. Taking the fast charging QC (Quick Charge) 2.0 fast charging protocol as an example, its handshake process is as follows:

[0042] First, connect the charger to the mobile phone through the charging cable. The charger short-circuits the positive data terminal D+ and the negative data terminal D﹣ by default. In this way, the mobile phone detects that the charger type is DCP (dedicated charging port mode). At this time, the default output voltage is 5V, and the mobile phone is charged normally. If the mobile phone supports the QC2.0 fast charging protocol, the high voltage dedicated charger port hvdcp (high voltage deticated charger port) process of the mobile phone is started, and 0.325V voltage is loaded on the positive data terminal D+ of the mobile phone, and maintained for more than 1.25S. When the charger detects that the voltage on the positive data terminal D+ of the charger is 0.325V and maintains for more than 1.25S, the charger disconnects the short circuit between the positive data terminal D+ and the negative data terminal D﹣ of the charger. Since the positive data terminal D+ and the negative data terminal D﹣ are disconnected, the voltage on the negative data terminal D﹣ no longer follows the change of the positive data terminal D+, and the voltage of the negative data terminal D﹣ begins to drop. When the mobile phone detects that the voltage on the negative data terminal D- starts to drop from 0.325V and maintains for more than 1ms, hvdcp reads the required charging voltage value determined by the mobile phone. If it is 9V, the voltage on the positive data terminal D+ of the mobile phone is set to 3.3V, and the voltage on the negative data terminal D- is set to 0.6V; if it is 5V, the voltage on the positive data terminal D+ of the mobile phone is set to 0.6V, and the voltage on the negative data terminal D- is set to 0V. After the charger detects the voltage on the positive data terminal D+ and the negative data terminal D-, it adjusts the voltage of the charger's charging current terminal Vbus to the corresponding voltage.

[0043] It can be seen from the above examples that during the fast charging protocol handshake process between the mobile terminal and the charger, the mobile terminal and the charger must follow the same communication protocol. That is, the mobile terminal and the charger need to use the same data communication exchange rules to confirm communication before the mobile terminal can be quickly charged, otherwise it cannot enter the fast charging mode. Therefore, it is necessary to perform a fast charging protocol compatibility test on the mobile terminal or charger before the mobile terminal or charger is mass-produced. This ensures that the mobile terminal or charger complies with the corresponding fast charging protocol standards, and can complete the fast charging handshake process with the corresponding charging or power supply equipment to enter the fast charging mode.

[0044] To address this issue, related technologies often use a manually constructed test environment to perform fast charging protocol compatibility tests on mobile terminals or chargers. Figure 1 A schematic diagram of a fast charging protocol test circuit provided for related technologies. Figure 1When performing a charging protocol compatibility test on a mobile terminal, it is necessary to prepare an oscilloscope 001, a charging protocol simulation test board 002, a DC power supply 003 and a charging plug 004. The charging plug 004 is used to be inserted into the charging interface of the mobile terminal 005, and the two terminals of the charging protocol simulation test board 002 are respectively connected to the positive data terminal D+ and the negative data terminal D﹣ of the mobile terminal 005 through a connecting wire and the charging plug 004. The output end of the DC power supply 003 is connected to the charging current terminal Vbus of the mobile terminal 005 through a connecting wire and the charging plug 004. The ground end of the DC power supply 003 is connected to the ground terminal GND of the mobile terminal 005 through a connecting wire and the charging plug 004. The current probe of the oscilloscope 001 is used to detect the current flowing through the connecting wire between the charging current terminal Vbus of the mobile terminal 005 and the output end of the DC power supply 003. The two voltage detection terminals of the oscilloscope 001 are respectively connected to the positive data terminal D+ and the negative data terminal D﹣ of the mobile terminal 005, and are used to obtain the voltage between the two terminals in the charging protocol simulation test board 002 and the positive data terminal D+ and the negative data terminal D﹣ of the charging interface of the mobile terminal 005 during the data exchange process. When using the above test environment to perform the fast charging protocol compatibility test of the mobile terminal 005, it is necessary to insert the charging plug 004 into the charging interface of the mobile terminal 005, adjust the output voltage of the DC power supply 003 to the voltage value required for the test, and adjust the charging protocol simulated by the charging protocol simulation test board 002 to the charging protocol required for the test. Then the tester controls and adjusts the oscilloscope 001 to collect the charging current of the mobile terminal 005, as well as the charging protocol handshake data received and sent by the mobile terminal 005 through the positive data terminal D+ and the negative data terminal D﹣. Based on these data, it is judged whether the mobile terminal 005 has completed the data interaction in accordance with the charging protocol and entered the fast charging mode.

[0045] Figure 2 A schematic diagram of another fast charging protocol test circuit provided for related technologies. Figure 2When performing the charging protocol compatibility test of the charger, it is necessary to prepare an oscilloscope 001, a charging protocol simulation test board 002, an electronic load 006 and a charging plug 004. The charging plug 004 is used to be inserted into the charging interface of the charger 007, and the two terminals of the charging protocol simulation test board 002 are respectively connected to the positive data terminal D+ and the negative data terminal D﹣ of the charger 007 through the connecting wire and the charging plug 004. The current input terminal of the electronic load 006 is connected to the charging current terminal Vbus of the charger 007 through the connecting wire and the charging plug 004. The ground terminal of the electronic load 006 is connected to the ground terminal GND of the charger 007 through the connecting wire and the charging plug 004. The current probe of the oscilloscope 001 is used to detect the current flowing through the connecting wire between the charging current terminal Vbus of the charger 007 and the input terminal of the electronic load 006. The two voltage detection terminals of the oscilloscope 001 are respectively connected to the positive data terminal D+ and the negative data terminal D﹣ of the charger 007, and are used to obtain the output voltage of the two terminals in the charging protocol simulation test board 002 during the data exchange process with the positive data terminal D+ and the negative data terminal D﹣ of the charger 007. When using the above test environment to perform the fast charging protocol compatibility test of the charger 007, it is necessary to insert the charging plug 004 into the charging interface of the charger 007, adjust the input power of the electronic load 006 to the power value required for the test, and adjust the charging protocol simulated by the charging protocol simulation test board 002 to the charging protocol required for the test. Then the tester controls and adjusts the oscilloscope 001 to collect the charging current of the charger 007, as well as the charging protocol handshake data received and sent by the charger 007 through the positive data terminal D+ and the negative data terminal D﹣. Based on these data, it is judged whether the charger 007 has completed the data interaction in accordance with the charging protocol and entered the fast charging mode.

[0046] From the above content, it can be known that in the related art, it is often cumbersome to perform fast charging protocol compatibility testing on mobile terminals 005 or chargers 007. Not only do various devices need to be connected, but also various devices need to be operated by testers during the test to complete the test. After obtaining the experimental data, it is also necessary to manually observe the waveform of the oscilloscope 001 to judge the experimental results. It has the problems of cumbersome operation, poor accuracy and very time-consuming. And because the time required for the charging protocol handshake is short and the time required for the test is highly synchronized, manual testing cannot accurately capture the measurement value, which ultimately leads to an increase in the error of the measurement result.

[0047] In order to overcome the problems existing in the related art, an embodiment of the present invention provides a charging protocol compatibility testing device. Figure 3 A schematic diagram of the structure of a charging protocol compatibility test device provided in an embodiment of the present application. Figure 3, the charging protocol compatibility test equipment includes a host computer connection port J0, a port connection circuit 10, a mobile terminal detection circuit and a charging head detection circuit. The mobile terminal detection circuit includes a first port J1, a first device connection port J2, a first signal acquisition module 11, a signal processing module 12, a first signal output module 13, a first constant current source 14, a first connection module 15 and a first charging parameter acquisition circuit 16. The charger detection circuit includes a second port J3, a second device connection port J4, a second signal acquisition module 21, a signal processing module 12, a second signal output module 22, a second constant current source 23, a second connection module 24 and a second charging parameter acquisition circuit 25, that is, the mobile terminal detection circuit and the charging head detection circuit share the same signal processing module 12. A port connection circuit 10 is also provided between the mobile terminal detection circuit and the charging head detection circuit, which can connect the corresponding terminals of the first port J1 and the second port J3 as needed. The host computer connection port J0 is used to connect the host computer 01, so that data can be exchanged between the host computer 01 and the signal processing module 12. This enables the signal processing module 12 to upload the current status and execute the instructions issued by the host computer 01.

[0048] The first port J1 is used to connect the charging interface of the mobile terminal to be tested through a charging cable. The first port J1 includes a charging current terminal Vbus, a positive data terminal D+, a negative data terminal D- and a ground terminal GND corresponding to the charging interface. The second port J3 is used to connect the charging interface of the charger to be tested through a charging cable. The second port J3 includes a charging current terminal Vbus, a positive data terminal D+, a negative data terminal D- and a ground terminal GND corresponding to the charging interface. The first device connection port J2 is used to connect a DC power supply 003, and power the mobile terminal to be tested through the charging current terminal Vbus of the charging interface of the mobile terminal to be tested. The second device connection port J4 is used to connect an electronic load 006, and consume the current of the charger to be tested through the charging current terminal Vbus of the charging interface of the charger to be tested. The first signal acquisition module 11 is used to convert the analog signals on the positive data terminal D+ and the negative data terminal D- of the first port J1 into digital signals that can be interpreted by the signal processing module 12, and transmit them to the signal processing module 12. The second signal acquisition module 21 is used to convert the analog signals on the positive data terminal D+ and the negative data terminal D- of the second port J3 into digital signals that can be interpreted by the signal processing module 12, and transmit them to the signal processing module 12. The signal processing module 12 determines the content to be output according to the preset fast charging protocol based on the data collected by the first signal acquisition module 11 or the second signal acquisition module 21 and outputs it to the first signal output module 13 or the second signal output module 22. The first signal output module 13 is used to convert the digital signal content output by the signal processing module 12 into an analog signal that complies with the fast charging protocol standard and outputs it to the positive data terminal D+ and the negative data terminal D- of the first port J1. The second signal output module 22 is used to convert the digital signal content output by the signal processing module 12 into an analog signal that complies with the fast charging protocol standard and outputs it to the positive data terminal D+ and the negative data terminal D- of the second port J3. The first connection module 15 includes a signal line and a switch connecting the first port J1, the first signal acquisition module 11, the first signal output module 13 and the first constant current source 14, which is used to turn on or off the corresponding switch in the first connection module 15 under the control of the signal processing module 12, so that the first signal acquisition module 11, the first signal output module 13 and the first constant current source 14 can be optionally connected to the positive data terminal D+ and the negative data terminal D- of the first port J1 according to actual needs. The second connection module 24 includes a signal line and a switch connecting the second port J3, the second signal acquisition module 21, the second signal output module 22 and the second constant current source 23, which is used to turn on or off the corresponding switch in the second connection module 24 under the control of the signal processing module 12, so that the second signal acquisition module 21, the second signal output module 22 and the second constant current source 23 can be optionally connected to the positive data terminal D+ and the negative data terminal D- of the second port J3 according to actual needs. The first constant current source 14 is used to output a current of a preset current value, wherein the preset current value can be determined according to actual needs.The second constant current source 23 is used to output a current of a preset current value, wherein the preset current value can be determined according to actual needs. The first charging parameter acquisition circuit 16 is used to collect the current between the charging current terminal Vbus flowing through the first port J1 and the positive terminal of the first device connection port J2, and the voltage of the charging current terminal Vbus of the first port J1. The second charging parameter acquisition circuit 25 is used to collect the current between the charging current terminal Vbus flowing through the second port J3 and the positive terminal of the second device connection port J4, and the voltage of the charging current terminal Vbus of the second port J3.

[0049] Figure 4 This is a diagram showing the connection relationship of external devices of a charging protocol compatibility test device provided in an embodiment of the present application. Figure 4 The host computer connection port J0 can be any interface that can connect a signal line and establish a communication connection between the host computer 01 and the signal processing module 12, for example, it can be a local area network (LAN) interface. The host computer 01 can be a computer device such as an industrial computer or a personal computer (PC). The signal processing module 12 can be a single-chip microcomputer and / or a field programmable gate array (FPGA).

[0050] Continue to see Figure 3 and Figure 4 , the first port J1 and the second port J3 can be any interface that complies with the fast charging protocol standard, for example, it can be an interface such as Type-C or USB-A. The first device connection port J2 and the second device connection port J4 can be any interface for connecting a DC power supply 003 or an electronic load 006, and the first device connection port J2 and the second device connection port J4 can both include a positive terminal V+ and a negative terminal V-. The charging current terminal Vbus of the first port J1 can be connected to the positive terminal V+ of the first device connection port J2 through the first charging parameter acquisition circuit 16, the ground terminal GND of the first port J1 and the negative terminal V- of the first device connection port J2 are grounded, and the first device connection port J2 is used to connect the DC power supply 003. The charging current terminal Vbus of the second port J3 can be connected to the positive terminal V+ of the second device connection port J4 through the second charging parameter acquisition circuit 25, the ground terminal GND of the second port J3 and the negative terminal V- of the second device connection port J4 are grounded, and the second device connection port J4 is used to connect the electronic load 006. The DC power supply 003 and the electronic load 006 can communicate with the host computer 01 and be controlled by the host computer 01. The voltage and current of the DC power supply 003 and the load size of the electronic load 006 are changed according to the instructions of the host computer 01. In fact, the devices that can be tested by this device are not limited to mobile terminals and chargers. Any charging equipment and power supply equipment can be tested using this device.

[0051] Figure 5This is a schematic diagram of the structure of a first connection module provided in an embodiment of the present application. Figure 5 , the first connection module 15 can be any circuit that can connect the first signal acquisition module 11, the first signal output module 13 and the first constant current source 14 to the positive data terminal D+ and the negative data terminal D- of the first port J1 as needed. Exemplarily, the first connection module 15 may include a first bus connected to the positive data terminal D+ of the first port J1, and a second bus connected to the negative data terminal D- of the first port J1, and a first switch S1, a second switch S2 and a third switch S3 connected to the first bus, and a fourth switch S4, a fifth switch S5 and a sixth switch S6 connected to the second bus. The first end of the first switch S1 is connected to the first bus, and the second end of the first switch S1 is connected to the first constant current source 14. The first end of the fourth switch S4 is connected to the second bus, and the second end of the fourth switch S4 is connected to the first constant current source 14. The first end of the second switch S2 is connected to the first bus, and the second end of the second switch S2 is connected to the first signal output module 13. The first end of the fifth switch S5 is connected to the first bus, and the second end of the fifth switch S5 is connected to the first signal output module 13. A first end of the third switch S3 is connected to the first bus, and a second end of the third switch S3 is connected to the first signal acquisition module 11. A first end of the sixth switch S6 is connected to the first bus, and a second end of the sixth switch S6 is connected to the first signal acquisition module 11. The first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5 and the sixth switch S6 are all controlled by the signal processing module 12, and can be turned on and off according to actual needs under the control of the signal processing module 12, so as to connect the required module to the positive data terminal D+ and the negative data terminal D- of the first port J1.

[0052] The second connection module 24 can be any circuit that can connect the second signal acquisition module 21, the second signal output module 22 and the second constant current source 23 to the positive data terminal D+ and the negative data terminal D- of the second port J3 as needed. Its specific structure can be the same as the first connection module 15 example mentioned above, and will not be repeated herein.

[0053] Figure 6 This is a schematic diagram of the structure of a first signal acquisition module provided in an embodiment of the present application. Figure 6, the first signal acquisition module 11 is used to convert the analog signals on the positive data terminal D+ and the negative data terminal D- of the first port J1 into digital signals that can be interpreted by the signal processing module 12. Any analog-to-digital conversion module that can meet the above functions can be used as the first signal acquisition module 11, which is not limited in this article. Exemplarily, the first signal acquisition module 11 may include a positive data terminal D+ acquisition submodule and a negative data terminal D- acquisition submodule. Taking the positive data terminal D+ acquisition submodule as an example, the positive data terminal D+ acquisition submodule may include a voltage follower, a first reverse amplifier, and an analog-to-digital conversion submodule connected in series.

[0054] The voltage follower may include a first operational amplifier U1, the positive feedback input terminal of the first operational amplifier U1 is connected to the second terminal of the third switch S3, and is used to obtain the signal on the positive data terminal D+ of the first port J1 when the third switch S3 is turned on. The negative feedback input terminal of the first operational amplifier U1 is connected to the output terminal of the first operational amplifier U1. Thus, a voltage follower is formed, and the output terminal OUT1 of the voltage follower (i.e., the output terminal of the first operational amplifier U1) has a voltage V OUT1 =V in1 ① The voltage follower has a large input impedance and a small output impedance, which can prevent the circuit in front of the voltage follower from affecting the circuit behind the voltage follower.

[0055] The first reverse amplifier may include a first resistor R1, a second resistor R2, a third resistor R3, and a second operational amplifier U2. The first end of the first resistor R1 is connected to the output end of the first operational amplifier U1, and the second end of the first resistor R1 is connected to the negative feedback input end of the second operational amplifier U2. The first end of the second resistor R2 is connected to the negative feedback input end of the second operational amplifier U2, the second end of the second resistor R2 is connected to the output end OUT2 of the second operational amplifier U2, the first end of the third resistor R3 is connected to the positive feedback input end of the second operational amplifier U2, and the second end of the third resistor R3 is grounded. The voltage at the output end OUT2 of the second operational amplifier U2 is According to formula ① and ②, we can get It can be seen that the first reverse amplifier can amplify or reduce the signal to a preset multiple according to actual needs, thereby achieving the purpose of adapting the measurement range of the analog-to-digital conversion submodule. The adjustment of the preset multiple can be achieved by adjusting the size of the first resistor R1 and the second resistor R2 according to actual needs.

[0056] The analog-to-digital conversion submodule includes an analog-to-digital conversion chip U3. The output terminal OUT2 of the second operational amplifier U2 is connected to the input terminal of the analog-to-digital conversion chip U3, and a clock signal is input to the clock signal input terminal of the analog-to-digital conversion chip U3 through any clock signal source. The analog-to-digital conversion chip U3 converts the input analog voltage into a binary digital value ADC. DATA and output to the signal processing module 12 through the output pins of the analog-to-digital conversion chip U3, namely, the output pins D0 to D9. Where 1.024 is an exemplary setting value of the analog-to-digital conversion chip U3, which can be modified by configuring the analog-to-digital conversion chip U3 according to actual needs. The structure and configuration of the negative data terminal D- acquisition submodule can be consistent with the positive data terminal D+ acquisition submodule, and the components, structure and configuration included in the second signal acquisition module 21 can be consistent with the first signal acquisition module 11, which will not be repeated herein. In other embodiments, the voltage follower, the first reverse amplifier and the analog-to-digital conversion submodule of the first signal acquisition module 11 can all be of different models or structures, and the circuits or devices included in the first signal acquisition module 11 can even be adjusted as needed, for example, the voltage follower can be omitted according to actual needs.

[0057] Figure 7 This is a schematic diagram of the structure of a first signal output module provided in an embodiment of the present application. Figure 7 , the first signal output module 13 is a module for converting the digital signal content output by the signal processing module 12 into an analog signal that complies with the fast charging protocol standard and outputs it to the positive data terminal D+ and the negative data terminal D- of the first port J1. Any digital-to-analog conversion module that can meet the above functions can be used as the first signal output module 13, which is not limited in this article. Exemplarily, the first signal output module 13 may include a positive data terminal D+ output submodule and a negative data terminal D- output submodule. Taking the positive data terminal D+ output submodule as an example, it includes a digital-to-analog conversion chip U4, a subtractor, and a second reverse amplifier.

[0058] The signal processing module 12 can send data to the digital-to-analog conversion chip U4 through its output port. For example, the signal processing module 12 can use the D10-D23 bus as an output port to output binary numbers 000000000000000-11111111111111 to the input port of the digital-to-analog conversion chip U4. The output digital data is converted to DAC CODE Indicates that the output current of the first current output terminal OUT3 of the digital-to-analog conversion chip U4 is The output current of the second current output terminal OUT4 Among them, 20mA in formula ⑥ and formula ⑦ is an exemplary setting value of the digital-to-analog conversion chip U4, which can be modified by configuring the digital-to-analog conversion chip U4 according to actual needs. 16383 and 16384 are exemplary specification parameters of the digital-to-analog conversion chip U4, which can be changed according to actual conditions.

[0059] The subtractor may include a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9 and a third operational amplifier U5. The first end of the fourth resistor R4 is connected to the first current output terminal OUT3 of the digital-to-analog conversion chip U4, and the second end of the fourth resistor R4 is grounded. The first end of the fifth resistor R5 is connected to the second current output terminal OUT4 of the digital-to-analog conversion chip U4, and the second end of the fifth resistor R5 is grounded. The first end of the sixth resistor R6 is connected to the first current output terminal OUT3 of the digital-to-analog conversion chip U4, and the second end of the sixth resistor R6 is connected to the negative feedback input terminal of the third operational amplifier U5. The first end of the seventh resistor R7 is connected to the second current output terminal OUT4 of the digital-to-analog conversion chip U4, and the second end of the seventh resistor R7 is connected to the positive feedback input terminal of the third operational amplifier U5. The first end of the eighth resistor R8 is connected to the negative feedback input terminal of the third operational amplifier U5, and the second end of the eighth resistor R8 is connected to the output terminal OUT5 of the third operational amplifier U5. The first end of the ninth resistor R9 is connected to the positive feedback input terminal of the third operational amplifier U5, and the second end of the ninth resistor R9 is grounded. The output voltage V of the first current output terminal OUT3 of the digital-to-analog conversion chip U4 is out3 =I out3 ×R4⑧, the output voltage V of the second current output terminal OUT4 of the digital-to-analog conversion chip U4 out4 =I out4 ×R5⑨, the output voltage of the output terminal OUT5 of the third operational amplifier U5 The current signal output by the digital-to-analog conversion chip U4 is converted into a voltage signal through a subtractor.

[0060] The second reverse amplifier may include a tenth resistor R10, an eleventh resistor R11 and a fourth operational amplifier U6. A first end of the tenth resistor R10 is connected to the output terminal OUT5 of the third operational amplifier U5, and a second end of the tenth resistor R10 is connected to the negative feedback input terminal of the fourth operational amplifier U6. A first end of the eleventh resistor R11 is connected to the negative feedback input terminal of the fourth operational amplifier U6, and a second end of the eleventh resistor R11 is connected to the output terminal OUT6 of the fourth operational amplifier U6. The positive feedback input terminal of the fourth operational amplifier U6 is grounded. The output terminal OUT6 voltage of the fourth operational amplifier U6 is Let R9 = R8, R7 = R6, according to formula ⑥, ⑦, ⑧, ⑨, ⑩ Available The output terminal OUT6 of the fourth operational amplifier U6 can be connected to the second end of the second switch S2, and is used to send data using the positive data terminal D+ of the first port J1 when the second switch S2 is turned on. The voltage signal output by the subtractor can be proportionally scaled by the second reverse amplifier to meet the voltage value range requirements in the charging protocol standard. The structure and configuration of the negative data terminal D- output submodule can be consistent with the positive data terminal D+ output submodule, and the structure and configuration of the second signal output module 22 can be consistent with the first signal output module 13, which will not be repeated herein. In other embodiments, the digital-to-analog conversion chip U4, the subtractor, and the second reverse amplifier of the first signal output module 13 can all be different models or structures, and the circuits or devices included in the first signal output module 13 can even be adjusted as needed. For example, the second reverse amplifier can be replaced with a forward amplifier according to actual needs.

[0061] When the signal processing module 12 needs to send the level duration data, it can query the preset level duration-level value comparison table and determine the level value according to the required level duration. Calculate the corresponding digital DAC CODE , the digital DAC CODE The signal is sent to the first signal output module 13 or the second signal output module 22 in binary form, thereby completing the conversion from the level duration coding mode to the level value coding mode. The signal is further processed and sent by the first signal output module 13 or the second signal output module 22. The level duration-level value comparison table can be determined according to actual needs.

[0062] Figure 8 This is a schematic diagram of the structure of a first constant current source provided in an embodiment of the present application. Figure 8 The first constant current source 14 may include a twelfth resistor R12, a thirteenth resistor R13, a fifth operational amplifier U7 and a constant current source chip U8. The output terminal OUT7 of the constant current source chip U8 may output a current I with a fixed current value. OUT7 . Exemplarily, the fixed current value can be 100μA. The first end of the thirteenth resistor R13 is connected to the output end of the fifth operational amplifier U7, and the second end of the thirteenth resistor R13 serves as the output end OUT8 of the first constant current source 14. The first end of the twelfth resistor R12 is connected to the positive feedback input end of the fifth operational amplifier U7, and the second end of the twelfth resistor R12 is connected to the second end of the thirteenth resistor R13. The output end OUT7 of the constant current source chip U8 is connected to the positive feedback input end of the fifth operational amplifier U7, and the negative feedback input end of the fifth operational amplifier U7 is connected to the output end of the fifth operational amplifier U7. The output current of the first constant current source 14 Exemplarily, the output current of the first constant current source 14 can be 500μA. According to actual needs, the current amplification factor of the fifth operational amplifier U7 can be changed by changing the resistance of the twelfth resistor R12 and the thirteenth resistor R13. The structure of the above-mentioned first constant current source 14 is only used as an example. The embodiment of the present invention is not limited to the structure of the first constant current source 14, and the structure of the above-mentioned first constant current source 14 is only used as an example. The structure of the second constant current source 23 can be the same as that of the first constant current source 14, which will not be repeated herein. In other embodiments, the first constant current source 14 can also be other circuit structures capable of providing a constant current, such as a solution that only includes a constant current source chip, or a solution such as a pull-up resistor and a pull-down resistor are set at the output end of the constant current source chip.

[0063] Fig. 9 This is a schematic diagram of the structure of a first charging parameter acquisition circuit provided in an embodiment of the present application. Fig. 9 , the first charging parameter acquisition circuit 16 may include a sampling resistor R14, a sampling chip U9 and a seventh switch S7. The first end of the sampling resistor R14 is connected to the charging current terminal Vbus of the first port J1, the second end of the sampling resistor R14 is connected to the first end of the seventh switch S7, and the second end of the seventh switch S7 is connected to the positive terminal V+ of the first device connection port J2. The two sampling terminals of the sampling chip U9 are respectively connected to the first end and the second end of the sampling resistor R14. The seventh switch S7 is controlled by the signal processing module 12 and can be turned on and off under the control of the signal processing module 12. After the sampling chip U9 collects the current flowing through the two ends of the sampling resistor R14 and the voltage of the charging current terminal Vbus of the first port J1, the current and voltage are transmitted to the signal processing module 12, thereby realizing the monitoring and collection of the voltage and current of the charging current terminal Vbus of the first port J1. The embodiment of the present invention does not limit the structure of the first charging parameter acquisition circuit 16, and the structure of the above-mentioned first charging parameter acquisition circuit 16 is only used as an example. The structure of the second charging parameter acquisition circuit 25 can be the same as that of the first charging parameter acquisition circuit 16, which will not be repeated herein.

[0064] Fig.10 This is a schematic diagram of a port connection circuit provided in an embodiment of the present application. Fig.10, the port connection circuit 10 may include an eighth switch S8, a ninth switch S9 and a tenth switch S10. The first end of the eighth switch S8 is connected to the positive data terminal D+ of the first port J1, and the second end of the eighth switch S8 is connected to the positive data terminal D+ of the second port J3. The first end of the ninth switch S9 is connected to the negative data terminal D- of the first port J1, and the second end of the ninth switch S9 is connected to the negative data terminal D- of the second port J3. The first end of the tenth switch S10 is connected to the second end of the sampling resistor R14 of the first charging parameter acquisition circuit 16, and the second end of the tenth switch S10 is connected to the second charging parameter acquisition circuit 25 and the position corresponding to the second end of the sampling resistor R14 of the first charging parameter acquisition circuit 16. The eighth switch S8, the ninth switch S9 and the tenth switch S10 are all controlled by the signal processing module 12, and can connect the first port J1 and the second port J3 according to actual needs.

[0065] Of course, the above embodiments are part of several embodiments of the present invention. In specific implementation, the port connection circuit 10 and the charging head detection circuit can also be omitted, and only the mobile terminal detection circuit can be retained. Such an implementation can detect the mobile terminal to be tested or the charger to be tested separately, that is, when the first port J1 is connected to the mobile terminal to be tested, the first device connection port J2 is connected to the DC power supply 003; when the first port J1 is connected to the charger to be tested, the first device connection port J2 is connected to the electronic load 006. Alternatively, the first device connection port J2 and the second device connection port J4, as well as the first charging parameter acquisition circuit 16 and the second charging parameter acquisition circuit 25 are omitted. During the test, no substantial charging and discharging test is performed, only the fast charging protocol data interaction process is tested. The above implementation modes that do not deviate from the main purpose of the present invention can be used as embodiments of the present invention.

[0066] The above charging protocol compatibility test equipment can be applied to the following scenarios.

[0067] Scene 1

[0068] When testing the fast charging protocol handshake detection of the charger, the signal processing module 12 can be configured through the host computer 01, so as to use the charging protocol compatibility test equipment to simulate the mobile terminal. The charger to be tested is inserted into the second port J3. When the charger to be tested is in operation and the output is unloaded, the signal processing module 12 outputs the handshake signal to be sent by the second signal output module 22, which specifically includes:

[0069] 1a) The negative data terminal D﹣ of the second port J3 sends the first high-level signal of handshake detection, which lasts for T1. At the same time, the second signal acquisition module 21 collects the data on the negative data terminal D﹣ of the second port J3 during the handshake duration, and compares the obtained data with the return data specified in the protocol. If the data are the same, it is determined that the positive data terminal D+ and the negative data terminal D﹣ of the charger to be tested are short-circuited, and the charger communication and operation status are normal.

[0070] 1b) The negative data terminal D of the second port J3 sends a second low level signal for handshake detection, which lasts for T2;

[0071] 1c) The negative data terminal D of the second port J3 sends a third high level signal for handshake detection, which lasts for T3;

[0072] 1d) The negative data terminal D- of the second port J3 sends the fourth low-level signal of handshake detection, which lasts for T4; the second signal acquisition module 21 collects the level signals of the positive data terminal D+ and the negative data terminal D- of the second port J3 within T time, obtains the data within T time, and compares the obtained data with the corresponding standard data of the communication protocol to obtain the test result of the charger in the no-load state. If the two data are consistent after comparison, it means that the fast charging protocol handshake test of the charger in the no-load state has passed.

[0073] After determining that the charger under test is compatible with the charging protocol in the no-load state, the test result of the charger under test can also be tested in the full-load state. That is, the charger under test is plugged into the second port J3, and steps 1a) to 1d) are repeated when the charger under test is in operation and the output is fully loaded.

[0074] Scene 2

[0075] When testing the recognition of the low level output of the charger, the signal processing module 12 can be configured by the host computer 01, so as to simulate the mobile terminal using the charging protocol compatibility test equipment. Insert the charger to be tested into the second port J3. After the charger to be tested completes the fast charging protocol handshake with the mobile terminal simulated by the charging protocol compatibility test equipment, the signal processing module 12 outputs the required Internet packet explorer (ping) signal from the second signal output module 22. The signal processing module 12 controls the switch connected to the constant current source to turn on, so that the device outputs 500μA of the constant current source through the positive data terminal D+ of the second port J3. After receiving the above current, the charger should reply to the low level signal. Therefore, the positive data terminal D+ level value of the second port J3 can be collected by the second signal acquisition module 21, and the signal processing module 12 compares the collected level value with the standard value. If the collected level value falls into the standard value, it means that the recognition test of the low level output of the charger passes. Exemplarily, the standard value can be less than or equal to 0.5V.

[0076] Scene 3

[0077] When testing the recognition of the low level output of the mobile terminal, the signal processing module 12 can be configured by the host computer 01, so as to simulate the charger using the charging protocol compatibility test equipment. The mobile terminal to be tested is inserted into the first port J1. After the mobile terminal to be tested completes the fast charging protocol handshake with the charger simulated by the charging protocol compatibility test equipment, the signal processing module 12 outputs the required Internet packet explorer (ping) signal from the second signal output module 22. The signal processing module 12 controls the switch connected to the constant current source to turn on, so that the device outputs 500μA of the constant current source through the negative data terminal D- of the second port J3. After receiving the above current, the charger should reply to the low level signal. Therefore, the negative data terminal D-level value of the second port J3 can be collected by the second signal acquisition module 21, and the signal processing module 12 compares the collected level value with the standard value. If the collected level value falls into the standard value, it means that the recognition test of the mobile terminal outputting a low level is passed. Exemplarily, the standard value can be less than or equal to 0.5V.

[0078] Scene 4

[0079] When testing the physical channel role switching of the charging cable, you can use two charging protocol compatibility test devices, configured as a simulated mobile terminal and a simulated charger respectively. Insert both ends of the charging cable into the two charging protocol compatibility test devices to verify whether the simulated mobile terminal and the simulated charger can complete the fast charging protocol recognition. Specifically, it includes:

[0080] 2a) The host computer 01 configures the device. Two charging protocol compatibility test devices simulate the mobile terminal and the charger respectively. One end of the charging cable is connected to the second port J3 of the simulated mobile terminal device, and the other end of the charging cable is connected to the first port J1 of the simulated charger device;

[0081] 2b) The device simulating a charger is connected to a power source;

[0082] 2c) The device simulating the mobile terminal sends a Universal Fast Charging Specification (UFCS) handshake signal to the device simulating the charger. After the handshake between the two parties succeeds;

[0083] 2d) The device simulating the mobile terminal sends a Ping message to the device simulating the charger to confirm whether both parties have completed the UFCS fast charging protocol identification.

[0084] If the UFCS fast charging protocol is identified, it means that the physical channel role switching test of the charging cable has passed. It should be noted that in addition to using two charging protocol compatibility test devices for simulation testing as mentioned above, you can also use one charging protocol compatibility test device and insert the charging cable into the first port and the second port of the charging protocol compatibility test device to complete the above test.

[0085] Scene 5

[0086] When monitoring the handshake process and charging status information between the mobile terminal and the charger, the mobile terminal can be connected to the second port J3, and the charger can enter the first port J1. The signal processing module 12 controls the third switch S3, the sixth switch S6, the eighth switch S8, the ninth switch S9 and the tenth switch S10 to close, so that the mobile terminal and the charger are connected through the port connection circuit 10. At the same time, the first signal acquisition module 11 is connected to the first port J1 and the second port J3 of the corresponding device, so as to collect the voltage waveforms on the positive data terminal D+ and the negative data terminal D﹣. In this way, the signal processing module 12 can monitor the protocol handshake process and charging status information between the mobile terminal and the charger in real time.

[0087] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A charging protocol compatibility test device, It is characterized in that include: Host computer connection port, signal processing module, first port, first signal acquisition module, first signal output module, first constant current source, first connection module; The host computer connection port is connected to the signal processing module, and is used to establish a communication connection between the host computer and the signal processing module; The first connection module is connected to the positive data terminal and the negative data terminal of the first port, and is used to connect the first signal acquisition module, the first signal output module, and the first constant current source to the positive data terminal and / or the negative data terminal of the first port under the control of the signal processing module; The first signal acquisition module is used to obtain an analog first voltage signal of the positive data terminal and / or the negative data terminal of the first port through the first connection module, and convert the analog first voltage signal into a digital first voltage signal and input it into the signal processing module; The first signal output module is used to obtain the digital second voltage signal output by the signal processing module, convert the digital second voltage signal into an analog second voltage signal that complies with the voltage value range in the charging protocol, and output the analog second voltage signal to the positive data terminal and / or the negative data terminal of the first port through the first connection module; The first constant current source is used to output a current of a preset current value, and output the current to the positive data terminal and / or the negative data terminal of the first port through the first connection module; The signal processing module is used to output the digital second voltage signal, obtain the digital first voltage signal, and determine whether the digital first voltage signal is consistent with a preset first voltage signal; or, obtain the digital first voltage signal.

2. The charging protocol compatibility test device according to claim 1, It is characterized in that It also includes a second port, a second signal acquisition module, a second signal output module, a second constant current source and a second connection module; The second connection module is connected to the positive data terminal and the negative data terminal of the second port, and is used to connect the second signal acquisition module, the second signal output module, and the second constant current source to the positive data terminal and / or the negative data terminal of the second port under the control of the signal processing module; The second signal acquisition module is used to obtain the analog third voltage signal of the positive data terminal and / or the negative data terminal of the second port through the second connection module, and convert the analog third voltage signal into a digital third voltage signal and input it into the signal processing module; The second signal output module is used to obtain the digital fourth voltage signal output by the signal processing module, convert the digital fourth voltage signal into an analog fourth voltage signal that complies with the voltage value range in the charging protocol, and output the analog fourth voltage signal to the positive data terminal and / or the negative data terminal of the second port through the second connection module; The second constant current source is used to output a current of a preset current value, and output the current to the positive data terminal and / or the negative data terminal of the second port through the second connection module; The signal processing module is also used to output the digital fourth voltage signal, obtain the digital third voltage signal, and determine whether the digital third voltage signal is consistent with a preset third voltage signal; or, obtain the digital third voltage signal.

3. The charging protocol compatibility test device according to claim 1, It is characterized in that It also includes a first device connection port and a first charging parameter acquisition circuit; The first device connection port is used to connect a DC power supply or an electronic load, and the positive end of the first device connection port is connected to the positive data terminal of the first port through the first charging parameter acquisition circuit. The first charging parameter acquisition circuit is used to collect the positive terminal voltage and current of the first device connection port and input them into the signal processing module.

4. The charging protocol compatibility test device according to claim 2, It is characterized in that It also includes a first device connection port, a first charging parameter collection circuit, a second device connection port, and a second charging parameter collection circuit; The first device connection port is used to connect a DC power supply, the positive end of the first device connection port is connected to the positive data terminal of the first port through the first charging parameter acquisition circuit, and the first charging parameter acquisition circuit is used to collect the positive terminal voltage and current of the first device connection port and input them into the signal processing module; The second device connection port is used to connect an electronic load, and the positive end of the second device connection port is connected to the positive data terminal of the second port through the second charging parameter acquisition circuit. The second charging parameter acquisition circuit is used to collect the positive terminal voltage and current of the second device connection port and input them into the signal processing module.

5. The charging protocol compatibility test device according to claim 1, It is characterized in that The host computer connection port includes a local area network interface, the signal processing module includes a single-chip microcomputer and / or a field programmable gate array, and the first port includes a Type-C or USB-A interface.

6. The charging protocol compatibility test device according to claim 2, It is characterized in that The host computer connection port includes a local area network interface, the signal processing module includes a single-chip microcomputer and / or a field programmable gate array, and the first port and the second port both include a Type-C or USB-A interface.

7. The charging protocol compatibility test device according to claim 1, It is characterized in that The first connection module includes a first bus connected to the positive data terminal of the first port, a second bus connected to the negative data terminal of the first port, a first switch, a second switch and a third switch connected to the first bus, and a fourth switch, a fifth switch and a sixth switch connected to the second bus; A first end of the first switch is connected to the first bus, a second end of the first switch is connected to the first constant current source, a first end of the fourth switch is connected to the second bus, a second end of the fourth switch is connected to the first constant current source, a first end of the second switch is connected to the first bus, a second end of the second switch is connected to the first signal output module, a first end of the fifth switch is connected to the first bus, a second end of the fifth switch is connected to the first signal output module, a first end of the third switch is connected to the first bus, a second end of the third switch is connected to the first signal acquisition module, a first end of the sixth switch is connected to the first bus, a second end of the sixth switch is connected to the first signal acquisition module, and the first switch, the second switch, the third switch, the fourth switch, the fifth switch and the sixth switch are all controlled by the signal processing module.

8. The charging protocol compatibility test device according to claim 2, It is characterized in that The first connection module and the second connection module each include a first bus connected to the positive data terminal of the first port / the second port, and a second bus connected to the negative data terminal of the first port / the second port, and a first switch, a second switch and a third switch connected to the first bus, and a fourth switch, a fifth switch and a sixth switch connected to the second bus; A first end of the first switch is connected to the first bus, and a second end of the first switch is connected to the first constant current source / the second constant current source. A first end of the fourth switch is connected to the second bus, and a second end of the fourth switch is connected to the first constant current source / the second constant current source. A first end of the second switch is connected to the first bus, and a second end of the second switch is connected to the first signal output module / the second signal output module. A first end of the fifth switch is connected to the first bus, and a second end of the fifth switch is connected to the first signal output module / the second signal output module. A first end of the third switch is connected to the first bus, and a second end of the third switch is connected to the first signal acquisition module / the second signal acquisition module. A first end of the sixth switch is connected to the first bus, and a second end of the sixth switch is connected to the first signal acquisition module / the second signal acquisition module. The first switch, the second switch, the third switch, the fourth switch, the fifth switch and the sixth switch are all controlled by the signal processing module.

9. The charging protocol compatibility test device according to claim 1, It is characterized in that The first signal acquisition module includes a positive data terminal acquisition submodule and a negative data terminal acquisition submodule, and the positive data terminal acquisition submodule and the negative data terminal acquisition submodule each include a voltage follower, a first reverse amplifier and an analog-to-digital conversion chip connected in series in sequence.

10. The charging protocol compatibility test device according to claim 2, It is characterized in that The first signal acquisition module and the second signal acquisition module both include a positive data terminal acquisition submodule and a negative data terminal acquisition submodule, and the positive data terminal acquisition submodule and the negative data terminal acquisition submodule both include a voltage follower, a first reverse amplifier and an analog-to-digital conversion chip connected in series in sequence.

11. The charging protocol compatibility test device according to claim 9 or 10, It is characterized in that The voltage follower comprises a first operational amplifier, a positive feedback input terminal of the first operational amplifier serves as an input terminal of the first operational amplifier, and a negative feedback input terminal of the first operational amplifier is connected to an output terminal of the first operational amplifier; The first reverse amplifier includes a first resistor, a second resistor, a third resistor and a second operational amplifier, the first end of the first resistor is connected to the output end of the first operational amplifier, the second end of the first resistor is connected to the negative feedback input end of the second operational amplifier, the first end of the second resistor is connected to the negative feedback input end of the second operational amplifier, the second end of the second resistor is connected to the output end of the second operational amplifier, the first end of the third resistor is connected to the positive feedback input end of the second operational amplifier, the second end of the third resistor is grounded, the output end of the second operational amplifier is connected to the input end of the analog-to-digital conversion chip, and the output end of the analog-to-digital conversion chip is connected to the input end of the signal processing module.

12. The charging protocol compatibility test device according to claim 1, It is characterized in that The first signal output module includes a positive data terminal output submodule and a negative data terminal output submodule, and the positive data terminal output submodule and the negative data terminal output submodule each include a digital-to-analog conversion chip, a subtractor, and a second reverse amplifier connected in series.

13. The charging protocol compatibility test device according to claim 2, It is characterized in that The first signal output module and the second signal output module both include a positive data terminal output submodule and a negative data terminal output submodule, and the positive data terminal output submodule and the negative data terminal output submodule both include a digital-to-analog conversion chip, a subtractor, and a second reverse amplifier connected in series.

14. The charging protocol compatibility test device according to claim 12 or 13, It is characterized in that The output end of the signal processing module is connected to the input end of the digital-to-analog conversion chip; The subtractor includes a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor and a third operational amplifier, wherein a first end of the fourth resistor is connected to a first current output end of the digital-to-analog conversion chip, a second end of the fourth resistor is grounded, a first end of the fifth resistor is connected to a second current output end of the digital-to-analog conversion chip, a second end of the fifth resistor is grounded, a first end of the sixth resistor is connected to the first current output end of the digital-to-analog conversion chip, a second end of the sixth resistor is connected to a negative feedback input end of the third operational amplifier, a first end of the seventh resistor is connected to the second current output end of the digital-to-analog conversion chip, a second end of the seventh resistor is connected to a positive feedback input end of the third operational amplifier, a first end of the eighth resistor is connected to a negative feedback input end of the third operational amplifier, a second end of the eighth resistor is connected to an output end of the third operational amplifier, a first end of the ninth resistor is connected to a positive feedback input end of the third operational amplifier, and a second end of the ninth resistor is grounded; The second reverse amplifier includes a tenth resistor, an eleventh resistor and a fourth operational amplifier, the first end of the tenth resistor is connected to the output end of the third operational amplifier, the second end of the tenth resistor is connected to the negative feedback input end of the fourth operational amplifier, the first end of the eleventh resistor is connected to the negative feedback input end of the fourth operational amplifier, the second end of the eleventh resistor is connected to the output end of the fourth operational amplifier, and the positive feedback input end of the fourth operational amplifier is grounded.

15. The charging protocol compatibility testing device according to claim 1, It is characterized in that The first constant current source includes a twelfth resistor, a thirteenth resistor, a fifth operational amplifier and a constant current source chip; the first end of the thirteenth resistor is connected to the output end of the fifth operational amplifier, the second end of the thirteenth resistor serves as the output end of the first constant current source, the first end of the twelfth resistor is connected to the positive feedback input end of the fifth operational amplifier, the second end of the twelfth resistor is connected to the second end of the thirteenth resistor, the output end of the constant current source chip is connected to the positive feedback input end of the fifth operational amplifier, and the negative feedback input end of the fifth operational amplifier is connected to the output end of the fifth operational amplifier.

16. The charging protocol compatibility test device according to claim 2, It is characterized in that The first constant current source and the second constant current source both include a twelfth resistor, a thirteenth resistor, a fifth operational amplifier and a constant current source chip; the first end of the thirteenth resistor is connected to the output end of the fifth operational amplifier, the second end of the thirteenth resistor serves as the output end of the first constant current source / the second constant current source, the first end of the twelfth resistor is connected to the positive feedback input end of the fifth operational amplifier, the second end of the twelfth resistor is connected to the second end of the thirteenth resistor, the output end of the constant current source chip is connected to the positive feedback input end of the fifth operational amplifier, and the negative feedback input end of the fifth operational amplifier is connected to the output end of the fifth operational amplifier.

17. The charging protocol compatibility test device according to claim 3, It is characterized in that The first charging parameter acquisition circuit includes a sampling resistor, a sampling chip and a seventh switch, wherein a first end of the sampling resistor is connected to a charging current terminal of the first port, a second end of the sampling resistor is connected to a first end of the seventh switch, a second end of the seventh switch is connected to a positive end of the first device connection port, a first sampling terminal and a second sampling terminal of the sampling chip are respectively connected to a first end and a second end of the sampling resistor, an output end of the sampling chip is connected to a sampling input end of the signal processing module, and the seventh switch is controlled by the signal processing module.

18. The charging protocol compatibility testing device according to claim 4, It is characterized in that The first charging parameter acquisition circuit and the second charging parameter acquisition circuit both include a sampling resistor, a sampling chip and a seventh switch, wherein a first end of the sampling resistor is connected to a charging current terminal of the first port / the second port, a second end of the sampling resistor is connected to a first end of the seventh switch, a second end of the seventh switch is connected to a positive end of the first device connection port / the second device connection port, a first sampling terminal and a second sampling terminal of the sampling chip are respectively connected to a first end and a second end of the sampling resistor, an output end of the sampling chip is connected to a sampling input end of the signal processing module, and the seventh switch is controlled by the signal processing module.

19. The charging protocol compatibility testing device according to claim 18, It is characterized in that It also includes a port connection circuit, which includes an eighth switch, a ninth switch and a tenth switch, wherein a first end of the eighth switch is connected to a positive data terminal of the first port, a second end of the eighth switch is connected to a positive data terminal of the second port, a first end of the ninth switch is connected to a negative data terminal of the first port, a second end of the ninth switch is connected to a negative data terminal of the second port, a first end of the tenth switch is connected to a second end of the sampling resistor of the first charging parameter acquisition circuit, a second end of the tenth switch is connected to a second end of the sampling resistor of the second charging parameter acquisition circuit, and the eighth switch, the ninth switch and the tenth switch are all controlled by the signal processing module.

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