Data processing method and device, equipment and storage medium

Abstract

The invention discloses a data processing method and device, equipment and a storage medium. Receiving an original data frame sent by a data generation device through a first processing chip, and determining the original data frame meeting a verification condition as a target data frame; according to the frame data information of the target data frame, determining file header information of the target data frame, the file header information including the determined frame control information and valid data cache information, and the valid data cache information being cache information corresponding to valid data in the target data frame; when it is detected that the data acquisition condition of the second processing chip is met, the file header information is transmitted to the second processing chip, so that the second processing chip obtains target effective data meeting the use requirement from the cached effective data according to the file header information. According to the method, the data processing efficiency is improved, the requirement for large-data-volume storage is met, and the second processing chip can select and efficiently obtain target effective data meeting the use requirement.

Description

Technical Field

[0001] The present invention relates to the field of data processing, and in particular to a data processing method, device, equipment and storage medium. Background Art

[0002] With the continuous development and advancement of radar technology, the amount of data generated by radar arrays has increased significantly, placing higher demands on the required data processing capabilities.

[0003] The traditional data processing solution is to use the digital receiving components on the radar array to transmit the received high-speed echo data through optical fiber to the CPU in the radar system for real-time data processing and then save to disk or playback.

[0004] However, due to the dramatic increase in data volume, traditional data processing solutions require the CPU to process too much data, resulting in data processing delays and slow response speeds, which affects the real-time nature of the data and cannot meet the processing capabilities required for radar data. Summary of the invention

[0005] The present invention provides a data processing method, device, equipment and storage medium to solve the problem that when the amount of data to be processed is too large, the traditional data processing solution has insufficient data processing capacity, resulting in data processing delays and slow response speed, and cannot meet the processing capacity required for radar data.

[0006] In a first aspect, an embodiment of the present invention provides a data processing method, which is applied to a signal receiving device, wherein the signal receiving device includes: a first processing chip and a second processing chip, and the method includes:

[0007] Receiving the original data frame sent by the data generating device through the first processing chip, and determining the original data frame that meets the verification condition as the target data frame;

[0008] Determine, according to the frame data information of the target data frame, the file header information of the target data frame, wherein the file header information includes the determined frame control information and valid data cache information, and the valid data cache information is the cache information corresponding to the valid data in the target data frame;

[0009] When it is detected that the data acquisition condition of the second processing chip is met, the file header information is transmitted to the second processing chip, so that the second processing chip acquires target valid data that meets the usage requirements from the cached valid data according to the file header information.

[0010] In a second aspect, an embodiment of the present invention provides a data processing device, which is applied to a signal receiving device, wherein the signal receiving device includes: a first processing chip and a second processing chip, and the device includes:

[0011] A target data frame determination module, configured to receive an original data frame sent by a data generation device through a first processing chip, and determine the original data frame that meets the verification condition as the target data frame;

[0012] A file header information determination module, configured to determine file header information of the target data frame according to the frame data information of the target data frame, where the file header information includes the determined frame control information and valid data cache information, and the valid data cache information is cache information corresponding to valid data in the target data frame;

[0013] A file header information transmission module, configured to transmit the file header information to the second processing chip when it is detected that the data acquisition condition of the second processing chip is met, so that the second processing chip can obtain target valid data that meets the usage requirements from the cached valid data according to the file header information.

[0014] In a third aspect, an embodiment of the present invention provides a signal receiving device, where the signal receiving device includes:

[0015] At least one processor;

[0016] And a memory communicatively connected to the at least one processor;

[0017] Wherein, the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor, so that the at least one processor can execute the data processing method described in any embodiment of the present invention.

[0018] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, characterized in that the computer-readable storage medium stores computer instructions, and the computer instructions are used to implement the data processing method described in any embodiment of the present invention when executed by a processor.

[0019] The technical solution of the embodiment of the present invention, by adding a first processing chip with high-speed processing capabilities to determine the file header information of the target data frame and cache the valid data of the target data frame to the cache device, improves the data processing efficiency of the signal receiving device, ensures the real-time nature of the data, and meets the requirements of large data volume storage, thus meeting the processing capabilities required for high-speed transmission data such as radar data; in addition, when the data acquisition condition of the second processing chip is met, the file header information is transmitted to the second processing chip, so that the second processing chip can select the target valid data that meets the usage requirements according to the file header information, rather than passively obtaining all processed target data frames or valid data, and the fast determination and acquisition of the target valid data are improved through the valid data cache information included in the file header information.

[0020] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 A flowchart of a data processing method provided by an embodiment of the present invention;

[0023] Figure 2 A logical schematic diagram of a data processing method provided by an embodiment of the present invention;

[0024] Figure 3 A schematic diagram of the structure of a data processing device provided by an embodiment of the present invention;

[0025] Figure 4 A schematic structural diagram of a signal receiving device that can be used to implement an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "first", "second", "original", "target", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] It should be noted that in traditional radar data processing solutions, the digital receiving components on the radar array often transmit the received high-speed echo data through optical fiber to the CPU in the radar system for real-time data processing and then storage or playback. This method may cause data processing delays, slow response speeds, and loss of some data when faced with the current radar data with a sharp increase in data volume. It cannot meet the processing capabilities required for radar data. At the same time, the CPU will occupy a lot of computing resources when processing large amounts of data, which may affect the execution efficiency of other tasks.

[0029] Based on this, an embodiment of the present invention provides a data processing method, which is applied to a signal receiving device. The signal receiving device includes: a first processing chip and a second processing chip.

[0030] It should be noted that the first processing chip needs to receive a large amount of high-speed data and process the received data efficiently. Therefore, the first processing chip can be understood as a chip with high configurability, parallel processing capabilities and low latency advantages. Exemplarily, the first processing chip can be a chip built on a field programmable gate array FPGA. The second processing chip can be understood as a chip that is responsible for sending operation control information, data, etc. to various components in the signal receiving device or other data application devices that establish communication to coordinate the collaborative work of various components. Since it involves the stable operation of the program in the entire signal receiving device, the computing power, logic execution and information processing capabilities of the second processing chip have higher requirements. Exemplarily, the second processing chip can be a chip built on the basis of a CPU.

[0031] Figure 1 A flow chart of a data processing method provided in an embodiment of the present invention. The embodiment of the present invention can be applied to scenarios where radar data is received and processed to achieve disk storage or playback. The method can be executed by a data processing device, which can be implemented in the form of software and / or hardware. Optionally, it can be implemented by a signal receiving device, which is preferably a desktop computer, a laptop computer, a server, etc.

[0032] like Figure 1 As shown, the data processing method provided by the embodiment of the present invention may specifically include:

[0033] S101. Receive, via a first processing chip, an original data frame sent by a data generating device, and determine an original data frame that meets a verification condition as a target data frame.

[0034] The original data frame can be understood as a data frame that has not been processed by the first processing chip. The data frame is a basic unit in data transmission and can be composed of a frame header, valid data, and a frame tail. The target data frame can be understood as an original data frame that meets the verification condition (i.e., expected to be received) for subsequent data processing.

[0035] In this embodiment, the first processing chip receives the original data frame sent to the first processing chip by the data generating device (such as a car sensor, a radar array, etc.) in real time after being turned on (powered on). After receiving the original data frame, the first processing chip can perform adaptive processing on the original data frame and verify whether the original data frame meets the preset verification condition, which is pre-configured by the second processing chip. Exemplarily, the verification condition can be that the frame header and / or frame tail in the original data frame are respectively the same as the preset frame header and / or frame tail. If the frame header and frame tail in the original data frame are confirmed to be the same as the preset frame header and frame tail through comparison, it is considered that the original data frame meets the verification condition and the original data frame is determined as the target data frame; the verification condition can also be that the frame header, frame tail and data length in the original data frame are respectively the same as the preset frame header, frame tail and data length.

[0036] Exemplarily, the data generating device is a radar array included in the signal receiving device, and the raw data frame is a fiber data frame formed after the radar array performs analog-to-digital conversion. The specific process of receiving the raw data frame sent by the data generating device through the first processing chip and determining the raw data frame that meets the verification condition as the target data frame can be that the digital receiving component on the radar array performs analog-to-digital conversion on the high-speed echo data received by the radar array to form a fiber data frame, that is, a raw data frame, and then transmits the raw data frame to the first processing chip through the optical fiber channel. The first processing chip can receive the raw data frame through a high-speed serial transceiver (such as GTX), and restore the raw data frame according to the protocol and rate requirements to meet the processing format of the first processing chip. Then, according to the verification condition pre-configured by the second processing chip, it is determined whether the raw data frame is a data frame expected to be acquired and processed. If the verification condition is met, the raw data frame is determined as the target data frame.

[0037] S102. Determine file header information of the target data frame according to the frame data information of the target data frame, wherein the file header information includes the determined frame control information and valid data cache information, and the valid data cache information is cache information corresponding to the valid data in the target data frame.

[0038] Among them, the frame data information can be understood as the information composed of the frame header information, frame tail information and valid data of the target data frame. The file header information can be understood as the information used to describe the characteristics of the target data frame, including the frame control information and valid data cache information of the target data frame; the frame control information can be understood as the information used to describe the data frame characteristics of the target data frame, which can include the frame header information, frame tail information, and the target data frame length and type information; the valid data cache information can be understood as the information generated after the valid data in the target data frame (that is, the data in the target data frame except the frame header and frame tail) is cached, which can include the cache address of the valid data, that is, the specific location of the valid data in the cache, such as a valid data with a data length of 500, the storage revelation point in the cache is 500, then the cache address can be 500-1000; it can also include the cache data amount (that is, the total amount of valid data stored in the cache) and the cache number (that is, the number of valid data cached in the cache) and other information.

[0039] In this embodiment, the frame header information and frame tail information corresponding to the frame data information in the target data frame are parsed and obtained, and the data type, data length and frame receiving timestamp of the target data frame are determined according to the frame header information and frame tail information. The frame receiving timestamp can be determined according to the time pre-configured by the second processing chip for the first processing chip clock, and then the frame header information, frame tail information, data type data length and frame receiving timestamp are integrated to form frame control information. Then, the valid data in the target data frame is determined, and the valid data is processed according to the requirements, such as adjusting the data format and size, slicing the valid data, etc., and the processed valid data is cached in the cache device according to the interface size and rate of the cache device. After the valid data is cached, the valid data cache information fed back by the cache device is obtained, and the frame control information and the valid data cache information are integrated to form the file header information of the target data frame, so that the first processing chip can efficiently read the valid data.

[0040] Exemplarily, the specific process of caching valid data can be to write the valid data into a non-volatile external cache device based on frame control information through a tool with memory read and write functions, such as a MIG controller. The external cache device can use a double data rate DDR memory to improve the cache efficiency and be able to cope with the disturbance caused by the second processing chip under high load conditions, thereby ensuring the integrity and correctness of the valid data and solving the problem of data loss under high-speed transmission.

[0041] S103: When it is detected that the data acquisition condition of the second processing chip is met, the file header information is transmitted to the second processing chip, so that the second processing chip acquires target valid data that meets the usage requirement from the cached valid data according to the file header information.

[0042] The target valid data may be understood as valid data selected by the second processing chip, ie, expected to be obtained.

[0043] In this embodiment, the data acquisition condition can be that the first processing chip determines the file header information; it can also be that the current moment reaches a time period (such as one period of 10 seconds) pre-set in the first processing chip to transmit interrupt instructions and file header information to the second processing chip; it can also be that the first processing chip receives a data acquisition request sent by the second processing chip.

[0044] In this embodiment, when it is detected that the data acquisition condition of the second processing chip is met, an interrupt instruction is sent to the second processing chip and the file header information is passed to the second processing chip, so that the second processing chip can select the target valid data that meets the usage requirements according to the frame control information contained in the file header information, and send the file feature information corresponding to the target valid data (that is, one or more information in the frame control information) and the request information for the target valid data (such as a transfer request) to the first processing chip, so that the first processing chip determines the valid data cache information of the target valid data corresponding to the file feature information in the file header information after receiving the file feature information, and obtains the target valid data from the cache according to the valid data cache information and the request information, and passes the obtained target valid data to the second processing chip through the first processing chip, so that the second processing chip can obtain the target valid data that meets the usage requirements from the cached valid data according to the file header information.

[0045] Exemplarily, the first processing chip can adopt a function that allows peripherals to directly transfer data to the memory, such as a direct memory access DMA function, and can read the file header information cached in the first processing chip in real time through DMA and pass the file header information to the second processing chip. It can also receive file feature information and request information sent by the second processing chip, and obtain target valid data from the cache based on the file feature information and request information to send to the second processing chip. Since DMA can provide a higher data transmission rate, the data transmission efficiency between the first processing chip and the second processing chip is further improved. Since the second processing chip does not need to frequently participate in the control and handling of data transmission, the latency of data processing is reduced, and the resource occupation of the second processing chip is reduced, so that the second processing chip can focus on other important tasks, such as transmitting target valid data to other data application devices that establish communication connections.

[0046] Exemplarily, following the above description, the specific process of the second processing chip obtaining the target valid data that meets the usage requirements from the cached valid data according to the file header information may be that the first processing chip receives the file feature information sent by the second processing chip through DMA, determines the valid data cache information corresponding to the target valid data in the file header information read by DMA according to the received file feature information, uses the MIG controller to quickly and accurately determine the target valid data in the cache device according to the valid data cache information and the request information, and passes the target valid data to DMA, and the DMA driver port sends the target valid data to the second processing chip on the PCIE bus. The entire process of the first processing chip obtaining the target valid data does not require the second processing chip to continuously participate in the control, thereby reducing the occupation of the resources of the second processing chip.

[0047] It should be noted that the first processing chip and the second processing chip can communicate through the PCIE bus (such as sending terminal instructions and receiving data acquisition requests, etc.), transfer file header information and transfer target valid data. The on-chip bus in the first processing chip can adopt the AXI-LITE bus to reduce the wiring difficulty between the first processing chip and the second processing chip and reduce signal reflection and interference.

[0048] A data processing method provided by an embodiment of the present invention improves the data processing efficiency of a signal receiving device, ensures the real-time nature of data, and meets the needs of large data storage by adding a first processing chip with high-speed processing capability to determine the file header information of a target data frame and cache the valid data of the target data frame to a cache device, thereby meeting the processing capability required for high-speed transmission data such as radar data; in addition, when the data acquisition conditions of the second processing chip are met, the file header information is transmitted to the second processing chip, so that the second processing chip can select the target valid data that meets the usage requirements according to the file header information, rather than passively acquiring all processed target data frames or valid data, and the rapid determination and acquisition of the target valid data is improved through the valid data cache information contained in the file header information.

[0049] As a first optional embodiment of this embodiment, based on the above embodiment, the data generating device is a radar array included in the signal receiving device, and the original data frame is a fiber optic data frame formed after the radar array performs analog-to-digital conversion.

[0050] In this embodiment, the data generating device is a radar array included in the signal receiving device. The digital receiving component on the radar array performs analog-to-digital conversion on the high-speed echo data received by the radar array to form an optical fiber data frame, i.e., the original data frame, so as to transmit the high-speed echo data received by the radar array through the optical fiber channel at a higher transmission speed.

[0051] As a second optional embodiment of this embodiment, the original data frame that meets the verification condition may be determined as the target data frame, which is specifically implemented as the following steps:

[0052] a1) Obtaining preset verification and comparison information, wherein the verification and comparison information includes reference frame information.

[0053] In this embodiment, verification and comparison information pre-set by the second processing chip for the first processing chip is obtained to determine the target data frame expected to be obtained in the original data frame, and the verification and comparison information includes reference frame information, wherein the reference frame information can be understood as the frame information that the target data frame expected to be obtained should have, and the frame information may include frame header information, frame tail information and / or valid data length information.

[0054] b1) If the frame data information included in the original data frame matches the reference frame information, the original data frame is determined as a target data frame that meets the verification condition.

[0055] In this embodiment, the frame data information included in the original data frame can be obtained by parsing, byte-by-byte judgment, etc., and by judging whether the frame data information matches the reference frame information, the target data frame that meets the verification condition is determined.

[0056] Exemplarily, the specific method of judging whether the frame data information matches the reference frame information may be to judge byte by byte, that is, first check whether the starting position of the original data frame is the frame header information preset in the reference frame information, and then check whether the ending position of the original data frame is the frame tail information preset in the reference frame information. If so, it is considered that the frame data information included in the original data frame matches the reference frame information, that is, the original data frame is determined to be a target data frame that meets the verification conditions.

[0057] Exemplarily, following the above example description, on the basis of verifying the frame header information and the frame tail information, the length of the valid data can also be verified at the same time. If they are the same as the corresponding information in the reference frame information, the original data frame is considered to be the target data frame that meets the verification conditions.

[0058] The above technical scheme of the present embodiment obtains verification and comparison information including reference frame information, and when verifying that the frame data information included in the original data frame matches the reference frame information, determines the original data frame as a target data frame that meets the verification conditions, thereby improving the accuracy of obtaining the target data frame, avoiding the first processing chip from processing unnecessary data frames, saving computing resources of the first processing chip, improving the data processing efficiency of the first processing chip, and saving cache resources and the transmission of unnecessary file header information, thereby reducing interference with valid file header information in the second processing chip and occupation of resources of the second processing chip.

[0059] As a third optional embodiment of this embodiment, the step of determining the file header information of the target data frame according to the frame data information of the target data frame may be specifically optimized into the following steps:

[0060] a2) determining frame control information of the target data frame according to the frame header information and frame tail information in the frame data information corresponding to the target data frame, wherein the frame control information includes data length, data type and frame receiving timestamp.

[0061] In this embodiment, the frame header information and frame tail information in the frame data information corresponding to the target data frame are obtained by parsing, and the data length (i.e., the amount of valid data) and data type (i.e., the format or type of valid data, such as video stream, audio data, control command, etc.) of the target data frame are determined according to the frame header information and the frame tail information. The frame reception timestamp (i.e., the specific time when the frame is received) of the target data frame is recorded in real time according to the clock in the first processing chip, and the frame header information, frame tail information, data length, data type and frame reception timestamp are integrated to form frame control information.

[0062] b2) determining the data in the target data frame except the frame control information as valid data, and buffering the valid data in a set buffer.

[0063] In this embodiment, the data in the target data frame except the frame control information is determined as valid data, and the valid data is cached in the setting buffer. Exemplarily, the data after the frame control information is deleted in the target data frame can be determined as valid data, and the valid data can be sorted and packaged according to the interface size and rate of the buffer, and the sorted and packaged valid data can be transmitted to the setting buffer through the MIG controller according to the frame control information. The setting buffer can use a double data rate memory, and use its advantages of high-speed data transmission, low power consumption, high stability and reliability to meet the storage and transmission requirements of large amounts of data, and at the same time cope with the disturbance caused by the high load of the second processing chip, ensure the integrity and correctness of the cached valid data, and solve the problem of data loss under high-speed transmission.

[0064] c2) obtaining a cache address and a cache data amount corresponding to the valid data in the set cache memory to form valid data cache information of the valid data.

[0065] In this embodiment, the cache address and cache data volume corresponding to the valid data in the set cache are obtained from the information returned by the set cache after caching the valid data, and the cache address and cache data volume are integrated to form the valid data cache information of the valid data.

[0066] d2) determining the frame control information and the valid data cache information as the file header information of the target data frame.

[0067] In this embodiment, the frame control information and the valid data buffer information are integrated and determined as the file header information of the target data frame.

[0068] The above technical scheme of this embodiment determines the file header information of the target data frame by acquiring the frame control information and the valid data cache information, realizes the extraction of the characteristic conditions and cache information that are most likely to be screened in the valid data, and provides strong support for the subsequent second processing chip to select the target valid data and efficiently acquire the target valid data.

[0069] As a fourth optional embodiment of this embodiment, based on the above embodiment, the data acquisition condition of the second processing chip can be concretized as follows:

[0070] The current moment reaches the set periodic data transmission moment; or, a data acquisition request sent by the second processing chip is received.

[0071] The above technical solution of this embodiment sends file header information to the second processing chip when a set period is reached or a data acquisition request sent by the second processing chip is received, so as to inform and update the file header information historically received in the second processing chip, so that the second processing chip can obtain the updated file header information in time, thereby ensuring the timeliness, reliability and effectiveness of obtaining valid data in the cache and improving the response speed.

[0072] As one implementation of any embodiment of the present invention, it also includes:

[0073] a3) determining, by the second processing chip, target valid data that meets the usage requirement from valid data cached relative to the target data frame according to the file header information.

[0074] In this embodiment, the second processing chip can select target valid data that meets the usage requirements based on the frame control information contained in the file header information (such as data type, frame reception timestamp, etc.), and the target valid data can be one or more, and send the file feature information corresponding to the target valid data (that is, one or more information in the frame control information that can characterize the target valid data, such as the frame reception timestamp of 20241223) to the first processing chip.

[0075] The first processing chip can use direct memory access technology to receive file feature information sent by the second processing chip, determine the valid data cache information corresponding to the target valid data in the file header information based on the received file feature information, and quickly and accurately determine the target valid data in the valid data cached relative to the target data frame based on the valid data cache information.

[0076] The above technical scheme of this embodiment provides an implementation method for the second processing chip to determine the target valid data that meets the usage requirements from the valid data cached relative to the target data frame. By determining the target valid data based on the file header information, the second processing chip actively selects the target valid data that is expected to be obtained, thereby improving the efficiency of obtaining the target valid data and reducing the occupation of the resources of the second processing chip. Moreover, since the file header information contains frame control information such as data length and data type, the screening items for the second processing chip to determine the target valid data are enriched, thereby improving the accuracy and effectiveness of determining the target valid data.

[0077] In an optional embodiment, it also includes:

[0078] a4) Determine, through the second processing chip, response data that satisfies the application request from the file header information and the target valid data, and transmit the response data to the data application device that establishes a communication connection with the signal receiving device. The application request is sent by the data application device.

[0079] In this embodiment, when the second processing chip receives an application request sent by a data application device that establishes a communication connection with the signal receiving device, the response data that satisfies the application request is determined from the file header information and the target valid data. Exemplarily, the method of determining the response data that satisfies the application request from the file header information and the target valid data may be to use the target valid data corresponding to the application request as the response data, or to integrate the corresponding target valid data and the corresponding file header information according to the application request, and use the integrated data as the response data of the application request. Then, the response data is transmitted to the data application device that establishes a communication connection with the signal receiving device, and the transmission method may be interrupt transmission, IO processor transmission, unconditional transmission, query transmission, etc.

[0080] The above technical solution of this embodiment processes and caches valid data through the first processing chip, and the second processing chip obtains and transmits the target valid data to other data application devices that establish a communication connection with the signal receiving device, thereby improving the transmission efficiency of the second processing chip and meeting the requirements for large data volume transmission.

[0081] In order to better understand the data processing method provided by the present invention, a specific example is provided here.

[0082] Figure 2 A logical schematic diagram of a data processing method provided by an embodiment of the present invention, such as Figure 2 As shown, the first processing chip may be an FPGA, and the first processing chip may include an optical fiber data transceiver module, a data processing module, a DMA transmission module, a control module, and a MIG controller. The first processing chip uses the MIG controller to communicate with the cache module through the AXI-LITE bus, and communicates and transmits data with the second processing chip through the PCIE bus. The second processing chip may be a CPU.

[0083] The first processing chip receives the radar optical fiber data sent by the data generating device through the GTX receiver on the optical fiber data transceiver module, and restores the differential radar optical fiber data into a data frame recognizable by the FPGA according to the protocol and rate of the data generating device, and transmits the data frame to the data processing module.

[0084] After receiving the data frame transmitted by the optical fiber data transceiver module, the data processing module parses the frame header and frame tail, and determines whether the data frame meets the verification condition according to the reference frame information pre-configured in the control module. If it meets the condition, the frame control information, i.e., the frame header information, frame tail information, data length, data type, and frame receiving timestamp, etc., is determined according to the frame header information, frame tail information, and clock information. After format adjustment, slicing, compression, and other processing are performed on the pure data information (i.e., valid data) that deletes the frame control information, it is sorted and packaged according to the interface size and rate of the cache module, and written into the cache module through the MIG controller according to the frame control information. The cache module can use a DDR memory. After all the valid data is written into the cache module, the MIG controller obtains the valid data cache information of the valid data, integrates the frame control information and the valid data cache information, and determines them as the file header information of the target data frame, and writes the file header information into the internal cache area of ​​the FPGA for storage. It can be understood that the cache address of the valid data in the file header information corresponds to the cache address of the DDR memory, which is convenient for the DMA transmission module to read.

[0085] The DMA transmission module reads the cache address, cache data volume and other information in the file header, and informs the CPU through the register in the control module that it has received the file header information corresponding to the fiber data and the valid data. After receiving the interrupt instruction sent by the register, the CPU can initiate a data transfer request to the DMA transmission module based on the file header information, and at the same time send the file characteristics (i.e., one or more information in the frame control information) to the DMA transmission module. After receiving the data transfer request, the DMA transmission module determines the cache address information from the file header information based on the file characteristics, and sends the cache address information and transfer request to the MIG controller. After receiving the data transfer request, the MIG controller reads the corresponding valid data from the DDR memory based on the cache address information and transmits it to the DMA transmission module. The DMA transmission module sends the valid data to the driver port of the DMA transmission module, so that the CPU can receive the corresponding data on the PCIE bus.

[0086] It should be noted that the interaction between the modules in the first processing chip is carried out through the AXI-LITE bus, and the communication between the control module and the CPU (such as the control module sending an interrupt instruction to the CPU and the CPU reading the status register in the control module) can be carried out through the AXI-LITE bus established between the control module and the DMA transmission module and the PCIE bus established between the DMA transmission module and the CPU. At the same time, the DMA transmission module can also upload file header information to the CPU through the PCIE bus. By establishing only one PCIE bus between the FPGA and the CPU, the wiring difficulty between the FPGA and the CPU is reduced, and two-way control is achieved.

[0087] If the CPU sends a playback data request to the DMA transmission module according to the file header information after receiving the interrupt instruction sent by the register, the file characteristics and playback address will be sent together with the playback data request, the cache address information will be determined from the file header information according to the file characteristics, and the cache address information, playback address and playback request will be sent to the MIG controller. After receiving the playback request, the MIG controller reads the corresponding valid data from the DDR memory according to the cache address information, and transmits the playback address and valid data to the optical fiber data transceiver module, so that the optical fiber data transceiver module performs digital-to-analog conversion, restores the valid data into a differential signal, and sends it to the playback address through the optical fiber channel.

[0088] Figure 3 The present invention provides a schematic diagram of a data processing device according to an embodiment of the present invention. The data processing device is applied to a signal receiving device. The signal receiving device includes: a first processing chip and a second processing chip. Figure 3 As shown, the device includes: a target data frame determination module 31, a file header information determination module 32 and a file header information transmission module 33, wherein:

[0089] The target data frame determination module 31 is used to receive the original data frame sent by the data generation device through the first processing chip, and determine the original data frame that meets the verification condition as the target data frame, wherein the data generation device is the radar array included in the signal receiving device, and the original data frame is the optical fiber data frame formed after the radar array performs analog-to-digital conversion;

[0090] A file header information determination module 32, configured to determine the file header information of the target data frame according to the frame data information of the target data frame, wherein the file header information includes the determined frame control information and valid data cache information, and the valid data cache information is the cache information corresponding to the valid data in the target data frame;

[0091] The file header information transmission module 33 is used to transmit the file header information to the second processing chip when it is detected that the data acquisition condition of the second processing chip is met, so that the second processing chip obtains the target valid data that meets the usage requirements from the cached valid data according to the file header information. The data acquisition condition of the second processing chip includes: the current moment reaches the set periodic data transmission moment; or, a data acquisition request sent by the second processing chip is received.

[0092] A data processing device provided by an embodiment of the present invention improves the data processing efficiency of a signal receiving device, ensures the real-time nature of data, and meets the needs of large data storage by adding a first processing chip with high-speed processing capability to determine the file header information of a target data frame and cache the valid data of the target data frame to a cache device, thereby meeting the processing capability required for high-speed transmission of data such as radar data; in addition, when the data acquisition conditions of the second processing chip are met, the file header information is transmitted to the second processing chip, so that the second processing chip can select the target valid data that meets the usage requirements according to the file header information, rather than passively acquiring all processed target data frames or valid data, and the rapid determination and acquisition of the target valid data is improved through the valid data cache information contained in the file header information.

[0093] Furthermore, the target data frame determination module 31 may be specifically used for:

[0094] Obtaining preset verification and comparison information, wherein the verification and comparison information includes reference frame information;

[0095] If the frame data information included in the original data frame matches the reference frame information, the original data frame is determined as a target data frame that meets the verification condition.

[0096] Furthermore, the file header information determination module 32 can be specifically used for:

[0097] Determine frame control information of the target data frame according to frame header information and frame tail information in the frame data information corresponding to the target data frame, wherein the frame control information includes data length, data type and frame receiving timestamp;

[0098] Determine the data in the target data frame except the frame control information as valid data, and cache the valid data in a set buffer;

[0099] Acquire the cache address and cache data amount corresponding to the valid data in the set cache to form the valid data cache information of the valid data;

[0100] The frame control information and the valid data cache information are determined as file header information of the target data frame.

[0101] Furthermore, the data processing device also includes a data transmission module, which may specifically include:

[0102] a target valid data determination unit, configured to determine, through the second processing chip, target valid data that meets the usage requirements from valid data cached relative to the target data frame according to the file header information;

[0103] A target valid data transmission unit is used to determine, through the second processing chip, response data that meets the application request from the file header information and the target valid data, and transmit the response data to a data application device that establishes a communication connection with the signal receiving device. The application request is sent by the data application device.

[0104] The data processing device provided in the embodiment of the present invention can execute the data processing method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0105] Figure 4 A schematic diagram of a signal receiving device 40 that can be used to implement an embodiment of the present invention is shown. The signal receiving device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0106] like Figure 4As shown, the signal receiving device 40 includes at least one processor 41, and a memory connected to the at least one processor 41, such as a read-only memory (ROM) 42, a random access memory (RAM) 43, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 41 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 42 or the computer program loaded from the storage unit 48 to the random access memory (RAM) 43. In the RAM 43, various programs and data required for the operation of the signal receiving device 40 can also be stored. The processor 41, the ROM 42, and the RAM 43 are connected to each other through a bus 44. An input / output (I / O) interface 45 is also connected to the bus 44.

[0107] A number of components in the signal receiving device 40 are connected to the I / O interface 45, including: an input unit 46, such as a keyboard, a mouse, etc.; an output unit 47, such as various types of displays, speakers, etc.; a storage unit 48, such as a disk, an optical disk, etc.; and a communication unit 49, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 49 allows the signal receiving device 40 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0108] The processor 41 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 41 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 41 performs the various methods and processes described above, such as a data processing method.

[0109] In some embodiments, the data processing method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 48. In some embodiments, part or all of the computer program may be loaded and / or installed on the signal receiving device 40 via the ROM 42 and / or the communication unit 49. When the computer program is loaded into the RAM 43 and executed by the processor 41, one or more steps of the data processing method described above may be performed. Alternatively, in other embodiments, the processor 41 may be configured to perform the data processing method in any other suitable manner (e.g., by means of firmware).

[0110] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0111] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0112] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0113] To provide interaction with a user, the systems and techniques described herein may be implemented on a signal receiving device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the signal receiving device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0114] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0115] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0116] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0117] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A data processing method, characterized in that: Applied to a signal receiving device, the signal receiving device comprises: a first processing chip and a second processing chip, and the method comprises: Receiving the original data frame sent by the data generating device through the first processing chip, and determining the original data frame that meets the verification condition as the target data frame; Determine, according to the frame data information of the target data frame, the file header information of the target data frame, wherein the file header information includes the determined frame control information and valid data cache information, and the valid data cache information is the cache information corresponding to the valid data in the target data frame; When it is detected that the data acquisition condition of the second processing chip is met, the file header information is transmitted to the second processing chip, so that the second processing chip acquires target valid data that meets the usage requirements from the cached valid data according to the file header information.

2. The method according to claim 1, characterized in that The data generating device is a radar array included in the signal receiving device, and the original data frame is an optical fiber data frame formed after the radar array performs analog-to-digital conversion.

3. The method according to claim 1, characterized in that The step of determining the original data frame satisfying the verification condition as the target data frame comprises: Obtaining preset verification and comparison information, wherein the verification and comparison information includes reference frame information; If the frame data information included in the original data frame matches the reference frame information, the original data frame is determined as a target data frame that meets the verification condition.

4. The method according to claim 1, characterized in that: The step of determining the file header information of the target data frame according to the frame data information of the target data frame comprises: Determine frame control information of the target data frame according to frame header information and frame tail information in the frame data information corresponding to the target data frame, wherein the frame control information includes data length, data type and frame receiving timestamp; Determine the data in the target data frame except the frame control information as valid data, and cache the valid data in a set buffer; Acquire the cache address and cache data amount corresponding to the valid data in the set cache to form the valid data cache information of the valid data; The frame control information and the valid data cache information are determined as file header information of the target data frame.

5. The method according to claim 1, characterized in that The data acquisition condition of the second processing chip includes: the current time reaches the set periodic data transmission time; or, a data acquisition request sent by the second processing chip is received.

6. The method according to any one of claims 1 to 5, characterized in that: Also includes: The target valid data that meets the usage requirement is determined from the valid data cached relative to the target data frame by the second processing chip according to the file header information.

7. The method according to claims 1-5, characterized in that: Also includes: The second processing chip determines response data that meets the application request from the file header information and the target valid data, and transmits the response data to a data application device that establishes a communication connection with the signal receiving device. The application request is sent by the data application device.

8. A data processing device, characterized in that: Applied to a signal receiving device, the signal receiving device comprises: a first processing chip and a second processing chip, and the apparatus comprises: A target data frame determination module, configured to receive, through the first processing chip, an original data frame sent by the data generation device, and determine an original data frame that meets a verification condition as a target data frame; A file header information determination module, used to determine the file header information of the target data frame according to the frame data information of the target data frame, wherein the file header information includes the determined frame control information and valid data cache information, and the valid data cache information is the cache information corresponding to the valid data in the target data frame; The file header information transmission module is used to transmit the file header information to the second processing chip when it is detected that the data acquisition condition of the second processing chip is met, so that the second processing chip can obtain the target valid data that meets the usage requirements from the cached valid data according to the file header information.

9. A signal receiving device, characterized in that: The signal receiving device comprises: at least one processor; and a memory communicatively coupled to the at least one processor; The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the data processing method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the data processing method according to any one of claims 1 to 7 when executed.

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