Data writing method, flash memory device, and computer readable storage medium

Abstract

The embodiment of the application relates to the application field of storage devices, and discloses a data writing method, a flash memory device and a computer readable storage medium. The data writing method caches user data written into a flash memory space by setting a second cache space in a cache space, and determines a release bandwidth of the second cache space by using an average write bandwidth of the flash memory space, so that the second cache space releases the user data at the average write bandwidth of the flash memory space, thereby being capable of smoothing bandwidth fluctuation of a host. The application can improve the write performance consistency of the host, and further improves the service quality of the flash memory device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of storage devices, in particular to a data writing method, a flash memory device and a computer readable storage medium. BACKGROUND

[0002] A flash memory device refers to a storage device manufactured based on flash memory technology. Flash memory is an electronic storage medium that uses electric current to store and read data in semiconductor transistors. For example, NAND flash memory is a type of flash memory composed of multiple memory cells, each of which can store a data bit (0 or 1). A flash memory device can be a standalone memory unit, such as a USB flash drive, a solid state drive (SSD), etc., or a storage module embedded in other devices, such as eMMC or UFS storage in a smartphone.

[0003] When a host writes user data to a flash memory device, the user data is usually cached in a cache space. Since the write speed and read speed of the cache space are both greater than the write speed of the flash memory space, when the host continuously writes user data, the cache space will be filled with user data written by the host. At this time, since the cache space is limited in size, the cache space needs to be obtained by releasing user data in the cache space to enable the host to continuously write user data. Therefore, the write speed of the host is essentially equal to the release speed of the cache space.

[0004] Currently, the release of the cache space is usually performed after the programming of the flash memory space is completed. However, the programming time of each word line within a physical block is fluctuating, which causes the release speed of the cache space to fluctuate, resulting in a large fluctuation in the bandwidth of the host write. In addition, due to garbage collection and other data writing within the SSD, the bandwidth fluctuation is further aggravated, which leads to insufficient consistency of the write performance of the host, and further leads to low quality of service (QoS) of the flash memory device. SUMMARY

[0005] The embodiments of the present application provide a data writing method to improve the consistency of the write performance of the host, and further improve the quality of service of the flash memory device.

[0006] The embodiments of the present application provide the following technical solutions:

[0007] In a first aspect, the embodiments of the present application provide a data writing method applied to a flash memory device, the flash memory device comprising a cache space and a flash memory space, the cache space comprising a first cache space and a second cache space, wherein the first cache space is used to cache user data issued by a host, and the second cache space is used to cache user data that has been written into the flash memory space;

[0008] The method comprises:

[0009] obtaining user data issued by the host, and storing the user data in the first cache space;

[0010] writing the user data in the first cache space into the flash memory space;

[0011] after the user data is written into the flash memory space, caching the user data that has been written into the flash memory space in the second cache space;

[0012] smoothing the write bandwidth of the flash memory space to obtain an average write bandwidth of the flash memory space;

[0013] determining a first release bandwidth according to the average write bandwidth of the flash memory space, wherein the first release bandwidth is equal to the average write bandwidth;

[0014] releasing the user data in the second cache space according to the first release bandwidth.

[0015] In some embodiments,

[0016] The smoothing the write bandwidth of the flash memory space to obtain an average write bandwidth of the flash memory space comprises:

[0017] real-time counting the amount of write data successfully written into the flash memory space;

[0018] after each sampling time, counting the data increment of the amount of write data to calculate a first write bandwidth corresponding to each sampling time, wherein the first write bandwidth = data increment / sampling time;

[0019] smoothing the plurality of first write bandwidths by a smoothing algorithm to obtain the average write bandwidth.

[0020] In some embodiments,

[0021] The method further comprises:

[0022] obtaining a current bandwidth of the flash memory space;

[0023] determining whether the average write bandwidth is less than the current bandwidth of the flash memory space;

[0024] if the average write bandwidth is less than the current bandwidth, taking the average write bandwidth as the first release bandwidth;

[0025] If the average write bandwidth is greater than or equal to the current bandwidth, a first release bandwidth is set as a sum of the current bandwidth and a feedback bandwidth, wherein the feedback bandwidth = a first coefficient * a user data space, and the user data space is a size of user data in the second cache space.

[0026] In some embodiments,

[0027] The method further comprises:

[0028] According to the user data space, the feedback bandwidth is determined, comprising:

[0029] A waterline threshold is set, wherein the waterline threshold is less than the second cache space;

[0030] It is judged whether the user data space is less than or equal to the waterline threshold;

[0031] If yes, the feedback bandwidth is set as zero;

[0032] If no, the feedback bandwidth is set as a second coefficient * (the user data space - the waterline threshold).

[0033] In some embodiments,

[0034] The user data issued by the host is acquired and stored in the first cache space, comprising:

[0035] A cache application command corresponding to a write request of the host is acquired, wherein the cache application command corresponds to a current application space;

[0036] According to the cache application command, the current application space is applied to the cache space to store the user data in the first cache space, wherein the first cache space = the first cache space already applied + the current application space.

[0037] In some embodiments,

[0038] After the user data in the second cache space is released, the method further comprises:

[0039] A current release space is determined, wherein the current release space is used to compensate the first cache space;

[0040] If the release space is less than the current application space, it is determined that the cache application command is failed to apply;

[0041] If the release space is greater than or equal to the current application space, it is determined that the cache application command is successfully applied.

[0042] In some embodiments,

[0043] The method further comprises:

[0044] determining a smoothing state of the flash memory device according to current conditions of the flash memory device and the host, comprising:

[0045] if the current conditions satisfy a first condition, determining the smoothing state of the flash memory device as a closed state, wherein the first condition comprises: the write bandwidth of the host is zero, or, when the host applies for cache space to the cache space, the number of successes is greater than the number of failures, or, the write bandwidth of the host is less than a target bandwidth of the flash memory device;

[0046] if the current conditions satisfy a second condition, determining the smoothing state of the flash memory device as a sampling state, wherein the second condition comprises: the write bandwidth of the host is not zero, and, when the host applies for cache space to the cache space, the number of successes is less than the number of failures, or, the write bandwidth of the host is greater than the target bandwidth of the flash memory device;

[0047] if the current conditions satisfy a third condition, determining the smoothing state of the flash memory device as a working state, wherein the third condition comprises: a sampling time of the sampling state is greater than a preset time threshold.

[0048] In some embodiments,

[0049] The method further comprises:

[0050] switching the smoothing state of the flash memory device, comprising:

[0051] if the current conditions satisfy the second condition when the smoothing state of the flash memory device is in the closed state, switching the smoothing state of the flash memory device to the sampling state;

[0052] if the current conditions satisfy the first condition when the smoothing state of the flash memory device is in the sampling state, switching the smoothing state of the flash memory device to the closed state; or, if the current conditions satisfy the third condition, switching the smoothing state of the flash memory device to the working state;

[0053] if the current conditions satisfy the first condition when the smoothing state of the flash memory device is in the working state, switching the system state of the flash memory device to the closed state.

[0054] In some embodiments,

[0055] switching the smoothing state of the flash memory device, further comprising:

[0056] when the smoothing state of the flash memory device is in the working state,

[0057] calculating a first average write bandwidth of the flash memory space in a first sampling period;

[0058] calculating a second average write bandwidth of the flash memory space in a second sampling period, wherein the second sampling period is greater than the first sampling period;

[0059] If the difference between the first average write bandwidth and the second average write bandwidth is greater than the difference threshold, the working state is switched to the closed state.

[0060] In a second aspect, an embodiment of the present application provides a flash memory device, comprising:

[0061] a processor and a memory, the processor being configured to execute executable program code in the memory, and when the executable program code is executed, the processor executes instructions of the data writing method of the first aspect.

[0062] In a third aspect, an embodiment of the present application provides a computer readable storage medium, which stores a computer program, and when the computer program is executed, the data writing method of the first aspect is implemented.

[0063] The embodiment of the present application has the following beneficial effects: Different from the prior art, the data writing method provided by the embodiment of the present application is applied to a flash memory device, the flash memory device comprises a cache space and a flash memory space, the cache space comprises a first cache space and a second cache space, the first cache space is used to cache user data issued by a host, and the second cache space is used to cache user data that has been written into the flash memory space; the method comprises the following steps: obtaining user data issued by the host and storing the user data in the first cache space; writing the user data in the first cache space into the flash memory space; after the user data is written into the flash memory space, caching the user data that has been written into the flash memory space in the second cache space; smoothing a write bandwidth of the flash memory space to obtain an average write bandwidth of the flash memory space; determining a first release bandwidth according to the average write bandwidth of the flash memory space, wherein the first release bandwidth is equal to the average write bandwidth; and releasing the user data in the second cache space according to the first release bandwidth.

[0064] The user data that has been written into the flash memory space is cached in the second cache space in the cache space, and the average write bandwidth of the flash memory space is used to determine the release bandwidth of the second cache space, so that the second cache space releases the user data at the average write bandwidth of the flash memory space, thereby smoothing the bandwidth fluctuation of the host, the write performance consistency of the host can be improved, and the service quality of the flash memory device is further improved. BRIEF DESCRIPTION OF DRAWINGS

[0065] One or more embodiments are illustrated by way of example in the figures that are part of this document and which illustrate key / representative principles of the one or more embodiments. Such embodiments do not constitute an exhaustive list of embodiments that can be made therewithin. Like reference numerals have been used in the drawings to indicate like elements and no particularized description of a figure will be rendered, except for purposes of clarity and a better understanding of the embodiments disclosed herein. The drawings are not necessarily to scale and are provided merely for purposes of illustration of the embodiments.

[0066] Figure 1 is a structural schematic diagram of a flash memory device provided by an embodiment of the present application;

[0067] Figure 2 is a schematic diagram of a programming time provided by an embodiment of the present application;

[0068] Figure 3 is a schematic diagram of host data writing provided by an embodiment of the present application;

[0069] Figure 4 is a schematic diagram of a data writing method provided by an embodiment of the present application;

[0070] Figure 5 is a schematic diagram of step S401 in Figure 4 ;

[0071] Figure 6 is a schematic diagram of another host data writing provided by an embodiment of the present application;

[0072] Figure 7 is a schematic diagram of a flow of determining whether a cache application command corresponding to a write request of a host is successfully applied provided by an embodiment of the present application;

[0073] Figure 8 is a schematic diagram of step S404 in Figure 4 ;

[0074] Figure 9 is a schematic diagram of cache space release provided by an embodiment of the present application;

[0075] Figure 10 is a schematic diagram of a feedback mechanism of bandwidth provided by an embodiment of the present application;

[0076] Figure 11 is a schematic diagram of a flow of determining a first release bandwidth provided by an embodiment of the present application;

[0077] Figure 12 is a schematic diagram of a waterline threshold provided by an embodiment of the present application;

[0078] Figure 13 is a schematic diagram of a flow of determining a feedback bandwidth provided by an embodiment of the present application;

[0079] Figure 14 is a schematic diagram of a flow of determining a smoothing state of a flash device provided by an embodiment of the present application;

[0080] Figure 15 is a schematic diagram of switching a smoothing state provided by an embodiment of the present application;

[0081] Figure 16 is another schematic diagram of a flash device provided by an embodiment of the present application.

[0082] BRIEF DESCRIPTION OF THE DRAWINGS

[0083] Reference Name Reference Name 100 Flash memory device 200 Host 110 Flash memory media 120 Controller 121 Processor 122 Memory 123 Flash memory controller 124 Interface DETAILED DESCRIPTION

[0084] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not used to limit the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0085] It should be noted that the various features in the embodiments of the present application can be combined with each other without conflict, and all within the scope of protection of the present application. In addition, although the functional modules are divided in the device schematic diagram, and the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order from the module division in the device or the order in the flowchart. Furthermore, the "first", "second", "third" and the like used in the present application do not limit the data and execution order, but only distinguish the same items or similar items with basically the same function and effect.

[0086] The technical solutions of the present application are described in detail below in combination with the drawings of the specification:

[0087] The data writing method in the embodiments of the present application is applied to a flash memory device, such as a U disk, an SD card, a microSD card, a CF card, a solid state disk (SSD) and the like. The flash memory device is a storage device using a semiconductor flash memory (NAND Flash) as a medium, and its main components include a flash memory medium, a flash memory controller, a dynamic random access memory (DRAM) and the like. Among them, an important function of the flash memory controller is to act as a driver of the flash memory chip to perform storage operations, and its main operations include erasing, writing and reading.

[0088] Please refer to Figure 1 , Figure 1 is a structural schematic diagram of a flash memory device provided by the embodiments of the present application.

[0089] As shown in Figure 1 , the flash memory device 100 includes a flash memory medium 110 and a controller 120 connected with the flash memory medium 110. Among them, the flash memory device 100 is connected with a host 200 in a wired or wireless manner to realize data interaction.

[0090] The flash media 110, as the storage medium of the flash device 100, is also called flash, NAND Flash, Flash memory or Flash particle, belongs to a kind of memory device, is a kind of nonvolatile memory, and can save data for a long time under the condition of no current supply, and its storage characteristics are equivalent to hard disk, so that the flash media 110 can become the basis of the storage medium of various portable digital devices.

[0091] The controller 120 includes a processor 121, a memory 122, a flash controller 123 and an interface 124.

[0092] The processor 121 is connected with the memory 122, the flash controller 123 and the interface 124 respectively, wherein the processor 121 can be connected with the memory 122, the flash controller 123 and the interface 124 through a bus or other ways, and the processor is used to run the nonvolatile software program, instruction and module stored in the memory 122, so as to realize any one method embodiment of the present application. On this basis, through firmware development, the processor is also used to be responsible for the core processing of the flash translation layer (FTL).

[0093] The memory 122 is mainly used to cache the read / write instruction sent by the host 200, and cache the read data or write data obtained from the flash media 110 according to the read / write instruction sent by the host 200.

[0094] The flash controller 123 is connected with the flash media 110, the processor 121 and the memory 122, and is used to access the back-end flash media 110 and manage various parameters and data I / O of the flash media 110.

[0095] The interface 124 is connected with the host 200, the processor 121 and the memory 122, is used to receive the data sent by the host 200 or the data sent by the processor 121, realizes the data transmission between the host 200 and the processor 121, and the interface 124 can be a SATA-2 interface, a SATA-3 interface, a SAS interface, a MSATA interface, a PCI-E interface, a NGFF interface, a CFast interface, a SFF-8639 interface and an M.2 NVME / SATA protocol.

[0096] At present, with the development of NAND Flash manufacturing process, the number of stacked layers of Flash is more and more, and the number of physical pages in the physical block (Block) is more and more, for example: a physical block of mainstream Flash includes more than 4000 pages.

[0097] It can be understood that, since the program of the Flash is performed according to the word line, one word line contains multiple pages, for example, SLC contains one page, MLC contains two pages, TLC contains three pages, and QLC contains four pages. Therefore, for a Block including more than 4000 pages, more than 1000 programs are required to complete one Block. Moreover, for some NAND, for example, QLC Nand, two programs are required for one word line to complete the program of data, so that the number of programs to complete one Block is more.

[0098] It is assumed that the program time of one word line is tProgram, tProgram is in the order of milliseconds, for example, the tProgram of TLC Nand is between 1 and 2 ms, and the tProgram of QLC Nand is between 6 and 9 ms. At this time, it takes seconds to write one Block, and the TLC Nand requires 1000 programs, tProgram is 1.5 ms, and it takes 1.5 s to write one Block. The QLC Nand requires 2000 programs, tProgram is 7 ms, and it takes 10.5 s to write one Block.

[0099] When the host writes user data to the flash device, the user data is usually cached in the cache space. Since the write speed and read speed of the cache space are greater than the write speed of the flash space, when the host continuously writes user data, the cache space will be full of user data written by the host. At this time, since the size of the cache space is limited, the cache space needs to be released to obtain the cache space to enable the host to continuously write user data. Therefore, the write speed of the host is essentially equal to the release speed of the cache space.

[0100] At present, the release of the cache space is usually performed after the program of the flash space is completed. However, the program time of each word line in the physical Block is fluctuant, that is, the tProgram of each word line is fluctuant. Taking QLC Nand as an example, it is assumed that one Block includes 5544 pages, and each word line needs to be programmed twice.

[0101] Please refer to Figure 2 , Figure 2 is a schematic diagram of a program time provided by an embodiment of the present application.

[0102] As Figure 2 shown, the abscissa is the number of Page, and the ordinate is the programming time (tProgram), wherein, Figure 2 The tProgram statistics of the second program are between 4.6 ms and 6 ms, resulting in periodic fluctuations in the performance bandwidth of the host, even with a fluctuation amplitude of more than 20%.

[0103] That is, within the physical block (Block), the program time of each word line is fluctuant, resulting in fluctuation in the release speed of the cache space, causing a large amplitude fluctuation in the bandwidth of the host write, and due to other data writes such as garbage collection inside the SSD, further exacerbating the bandwidth fluctuation, resulting in insufficient consistency of the write performance of the host, and further resulting in low service quality of the flash device.

[0104] Please refer to Figure 3 , Figure 3 is a schematic diagram of host data writing provided by an embodiment of the present application.

[0105] As Figure 3 shown, the host data (Host data) is written to the cache space (Cache), for example, the host writes data A to the cache space (Cache), and the cache space (Cache) writes data A to the flash memory space, i.e., the flash array (Flash Array), and after data A is successfully written to the flash array, data A' in the cache space corresponding to data A is released.

[0106] Specifically, the host data writing includes the following steps (1) to (3):

[0107] Step (1): The host data is written to the cache space.

[0108] The cache space (Cache) includes storage media such as synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRAM), single-level cell NAND flash (SLC NAND Flash), etc.

[0109] Step (2): Write the host data to the flash space.

[0110] Specifically, the data in the cache space is written to the flash space through firmware processing. The flash space includes a flash array, and the flash array includes MLC NAND Flash, TLC NAND Flash, QLC NAND Flash, and the like.

[0111] Step (3): After the flash space successfully writes the data, the cache space is released.

[0112] Specifically, after the data A is successfully written to the flash array, the data A' in the cache space corresponding to the data A is released.

[0113] It can be understood that when the host writes user data to the flash device, the user data is usually cached through the cache space. Since the write speed and the read speed of the cache space are both greater than the write speed of the flash space, when the host continuously writes user data, the cache space will be filled with the user data written by the host. At this time, since the size of the cache space is limited, the cache space needs to be released to obtain the cache space in order to continuously write user data by the host. Therefore, the write speed of the host is essentially equal to the release speed of the cache space.

[0114] The above-mentioned manner releases the cache space after the data is successfully written to the flash space and the program is completed. However, the program time of each word line in the physical block is fluctuant, thereby causing the release speed of the cache space to fluctuate, causing the bandwidth written by the host to fluctuate greatly. In addition, due to the garbage collection and other data writing in the SSD, the bandwidth fluctuation is further aggravated, causing the write performance consistency of the host to be insufficient, and further causing the quality of service (QoS) of the flash device to be not high.

[0115] Based on this, the embodiment of the present application provides a data writing method. The second cache space is set in the cache space to cache the user data that has been written to the flash space, and the release bandwidth of the second cache space is determined by using the average write bandwidth of the flash space, so that the second cache space releases the user data at the average write bandwidth of the flash space, thereby being able to smooth the bandwidth fluctuation of the host. The present application can improve the write performance consistency of the host, and further improve the quality of service of the flash device.

[0116] Specifically, please refer to Figure 4 , Figure 4is a flowchart of a data writing method provided by an embodiment of the present application.

[0117] The data writing method is applied to a flash device, and in particular, to at least one processor of the flash device. The execution subject of the data writing method is at least one processor of the flash device.

[0118] As shown in Figure 4 The data writing method includes the following steps S401-S406.

[0119] Step S401: Obtain user data issued by a host, and store the user data in a first cache space.

[0120] Specifically, the flash device obtains user data issued by a host. The flash device includes a cache space, and the cache space includes a first cache space. After receiving the user data sent by the host, the flash device caches the user data in the cache space, and in particular, caches the user data in the first cache space of the cache space. The first cache space is used to cache user data issued by the host.

[0121] Please refer to Figure 5 , Figure 5 is Figure 4 a detailed flowchart of step S401 in

[0122] As shown in Figure 5 The step S401 includes the following steps S4011-S4012.

[0123] Step S4011: Obtain a cache application command corresponding to a write request of a host.

[0124] Specifically, the host issues a write request, and the write request corresponds to a cache application command. The flash device receives the cache application command, and the cache application command is used to apply for a cache space to cache user data corresponding to the write request. The cache application command corresponds to a current application space.

[0125] Step S4012: Apply for a current application space of the cache space according to the cache application command, to store the user data in the first cache space.

[0126] Specifically, after receiving the cache application command, the flash device applies for a current application space corresponding to the cache application command in the cache space. The first cache space = the first cache space that has been applied + the current application space.

[0127] Step S402: Write the user data in the first cache space to a flash space.

[0128] Specifically, after the flash device caches the user data issued by the host in the first cache space, the user data in the first cache space is written to the flash space, i.e., the user data in the first cache space is sent to the flash space, so that the flash space stores the user data.

[0129] Step S403: After the user data is written to the flash space, the user data written to the flash space is cached in the second cache space.

[0130] Specifically, the cache space further includes a first cache space. After the user data is flushed from the first cache space to the flash space, the flash space needs to program the data to write to the flash array of the flash space. After the user data is successfully written to the flash array of the flash space, the user data written to the flash space is cached in the second cache space of the cache space, where the second cache space is used to cache the user data written to the flash space.

[0131] In the embodiment of the present application, the completion state of the flash program can be checked through the Ready / busy pin of the Nand flash, or the state of the Nand flash is checked through a register to determine whether the user data is successfully written to the flash array of the flash space.

[0132] Please refer to Figure 6 , Figure 6 is another schematic diagram of host data writing provided by the embodiment of the present application.

[0133] As Figure 6 shown, the cache space includes a first cache space and a second cache space, where the first cache space is used to cache the user data written by the host, and the second cache space is used to cache the user data written to the flash space. For example, the user data A written by the host is stored in the first cache space, then the user data A in the first cache space is programmed and written to the flash array of the flash space, and after the user data A is successfully written to the flash array, the user data A' in the second cache space is released from the second cache space to supplement the released cache space to the first cache space.

[0134] Specifically, it is assumed that the first cache space is denoted as Cache total , the space applied by the cache application command corresponding to the write request of the host is denoted as Cache alloc , i.e., the space applied by the host is denoted as Cache alloc , and the space not applied by the host is denoted as Cache free, the cache that stores the program in the second cache space (Rsv cache) is recorded as Cache rsv .

[0135] The following describes the change process of the cache space, including the following steps (1) - step (3):

[0136] (1) When the host write request (Host Write) occurs, the host applies for a cache to store user data, assuming that the size of the user data is Size data At this time, Cache alloc increases by Size data , Cache free decreases by Size data , Cache alloc + Cache free = Cache total .

[0137] (2) As the user data continues to be written, Cache free decreases to 0, causing the new write request (Host Write) to fail to apply for Cache. Moreover, since the writing speed of the flash is less than the writing speed of the cache, that is, the writing speed of the flash space is less than the writing speed of the cache space. At this time, Cache free increases at a speed equal to the writing speed of the host.

[0138] (3) After the Size data corresponding data is successfully written to the flash space, that is, the program is completed, Cache rsv increases by Size data , Cache free remains unchanged, still satisfying Cache alloc + Cache free = Cache total .

[0139] (4) According to the smoothed average bandwidth, the user data in the second cache space is released to compensate for the first cache space, that is, Cache rsv is released to supplement Cache free , so that Cache rsv decreases, Cache free increases, and the release of buffer A" from cache A' is achieved.

[0140] Further, in Cache freeWhen the first cache space is reduced to 0, the first cache space can continue to be used to satisfy the cache application of the host, because the user data needs to be released from the second cache space to compensate for the first cache space.

[0141] Specifically, please refer to Figure 7 , Figure 7 is a flowchart of a process for judging whether a cache application command corresponding to a write request of a host is successful or not, provided by an embodiment of the present application.

[0142] As shown in Figure 7 , the process for judging whether the cache application command corresponding to the write request of the host is successful or not includes the following steps S701-S703:

[0143] Step S701: determining the current release space.

[0144] Specifically, after the user data in the second cache space is released, the current release space is determined, wherein the current release space is used to compensate for the first cache space, so that the first cache space can continue to be used to satisfy the cache application of the host.

[0145] Step S702: judging whether the release space is less than the current application space.

[0146] If the release space is less than the current application space, step S703 is entered.

[0147] If the release space is greater than or equal to the current application space, step S704 is entered.

[0148] Step S703: determining that the cache application command is failed;

[0149] It can be understood that if the current application space corresponding to the cache application command is greater than the release space of the second cache space, at this time, the idle space in the first cache space is insufficient to satisfy the cache application command, and it is determined that the cache application command is failed.

[0150] Step S704: determining that the cache application command is successful.

[0151] If the release space is greater than or equal to the current application space, it is determined that the cache application command is successful.

[0152] Step S404: smoothing the write bandwidth of the flash memory space to obtain the average write bandwidth of the flash memory space.

[0153] It can be understood that the write bandwidth of the flash memory space is real-time, and the write bandwidths corresponding to different moments are different, therefore, the average write bandwidth of the flash memory space is obtained by smoothing the write bandwidth of the flash memory space, so as to represent the write bandwidth of the flash memory space by the average write bandwidth of the flash memory space.

[0154] Please refer to Figure 8 , Figure 8 is Figure 4 a refinement flowchart of step S404 in FIG. 4.

[0155] As shown in FIG. 4, the step S404 of smoothing the write bandwidth of the flash memory space to obtain the average write bandwidth of the flash memory space comprises the following steps S4041-S4043: Figure 8

[0156] The step S4041 is to count the amount of write data successfully written into the flash memory space in real time.

[0157] Specifically, the amount of write data successfully written into the flash memory space is sampled, i.e., the amount of data of Program completion is sampled. It can be understood that the amount of write data increases with time as data is continuously written.

[0158] The step S4042 is to count the data increment of the amount of write data after each sampling time to calculate the first write bandwidth corresponding to each sampling time.

[0159] Specifically, the first write bandwidth = data increment / sampling time, for example: at the first time, the amount of write data counted is X1, and after 100 ms, the amount of write data counted is X2, then the data increment of the amount of write data within 100 ms is X2-X1, at this time, the first write bandwidth is (X2-X1) / 100 ms.

[0160] For example: in the recent time T1, T1 includes multiple sampling times, i.e., sampling periods, such as the sampling time is 100 ms, then the first write bandwidth is calculated every 100 ms, and through multiple sampling times, the first write bandwidth corresponding to multiple sampling times is continuously calculated, thereby obtaining multiple write bandwidths.

[0161] The step S4043 is to smooth the multiple first write bandwidths by a smoothing algorithm to obtain the average write bandwidth.

[0162] Specifically, the multiple first write bandwidths are smoothed by a smoothing algorithm, and the smoothing algorithm includes Moving Average, Median Filtering, Local Weighted Regression Smoothing, Gaussian Smoothing, Weighted Regression, Box Smoothing, Exponential Smoothing, etc., for example: the smoothing algorithm is a first-order lag filter algorithm in the Exponential Smoothing, and the calculation method of the first-order lag filter algorithm is as follows:

[0163] BW​avg = BW avg *(1-a)+BW*a

[0164] wherein, BW avg is the average write bandwidth, a is a coefficient, and BW is the first write bandwidth.

[0165] Alternatively, a ring queue is used to record the bandwidth data of the last period of time, i.e., a plurality of first write bandwidths of the last period of time, and the plurality of first write bandwidths are averaged to obtain the average write bandwidth.

[0166] It can be understood that the smaller the value of a is, the better the smoothing effect is, and the longer the sampling period is, but at this time, the average value of the first write bandwidth BW changes more slowly in response to the fluctuation of BW, for example: a Block needs 10s to be filled, the sampling period is 100ms, and a can be taken as 1 / 64.

[0167] In the embodiments of the present application, the plurality of historical bandwidths are smoothed by sampling the historical bandwidths and using a smoothing algorithm, so that the release bandwidth of the cache space can be better determined.

[0168] Step S405: determining a first release bandwidth according to the average write bandwidth of the flash memory space.

[0169] Specifically, the first release bandwidth is equal to the average write bandwidth BW avg , i.e., the average write bandwidth of the flash memory space is taken as the first release bandwidth, wherein the first release bandwidth is used to represent the release speed of the user data in the second cache space.

[0170] Step S406: releasing the user data in the second cache space according to the first release bandwidth.

[0171] Specifically, the user data in the second cache space is released at the first release bandwidth.

[0172] In the embodiments of the present application, the user data written into the flash memory space is cached in the second cache space set in the cache space, and the release bandwidth of the second cache space is determined by using the average write bandwidth of the flash memory space, so that the second cache space releases the user data at the average write bandwidth of the flash memory space, thereby smoothing the bandwidth fluctuation of the host. The present application can improve the consistency of the write performance of the host, and further improve the service quality of the flash memory device.

[0173] It can be understood that the bandwidth BW Flash of the Flash is sampled by using a smoothing algorithm, and the average write bandwidth BW avg is calculated, and the second cache space is released by taking the average write bandwidth BW avg as the release bandwidth, so that the write bandwidth BW host= BW avg .

[0174] Please refer to Figure 9 , Figure 9 is a schematic diagram of the cache space release provided by the embodiment of the present application.

[0175] As Figure 9 indicated, the host writes user data to the first cache space (Cache), writes the user data in the first cache space (Cache) to the Flash Array, samples the bandwidth BW Flash of the flash space (Flash Array) in real time, and calculates the average write bandwidth BW avg . avg The second cache space (Rsv Cache) is released with the average write bandwidth BW avg , and the released space is compensated to the first cache space (Cache).

[0176] However, when sampling the bandwidth BW Flash of the flash, sampling errors may occur, so that the performance of the entire disk is lower than the real performance of the flash space. Based on this, the present application further proposes a feedback mechanism to adjust the released bandwidth to obtain the adjusted released bandwidth.

[0177] Specifically, please refer to Figure 10 , Figure 10 is a schematic diagram of the bandwidth feedback mechanism provided by the embodiment of the present application.

[0178] As Figure 10 indicated, after sampling the bandwidth BW Flash of the flash space (Flash Array) in real time and calculating the average write bandwidth BW avg , the average write bandwidth is compensated by using the feedback bandwidth (BW fd ) to obtain the first released bandwidth after adjustment, so that the write bandwidth (BW host ) of the host is equal to the first released bandwidth after adjustment.

[0179] Specifically, please refer to Figure 11 , Figure 11 is a flowchart of determining the first released bandwidth provided by the embodiment of the present application.

[0180] As Figure 11 indicated, the flow of determining the first released bandwidth includes the following steps S1101-S1104:

[0181] Step S1101: obtaining the current bandwidth of the flash space;

[0182] Specifically, the current bandwidth of the flash memory is the current write bandwidth of the flash memory. It is calculated by statistically analyzing the incremental data volume written within the sampling time and then calculating the current bandwidth BW of the flash memory within the sampling time. Flash Where, current bandwidth = BW Flash = The data increment of the amount of data written within the sampling time / sampling time.

[0183] Step S1102: Determine whether the average write bandwidth is less than the current bandwidth of the flash memory space.

[0184] Specifically, determine the average write bandwidth BW. avg Is it less than the current bandwidth BW of the flash memory space? Flash If yes, proceed to step S1103; otherwise, proceed to step S1104.

[0185] Understandably, if the average write bandwidth BW avg The current bandwidth BW of the flash memory space is greater than or equal to that of the flash memory space. Flash Then the average write bandwidth BW avg It will converge to BW through a smoothing algorithm. Flash .

[0186] If the average write bandwidth is BW avg Less than the current bandwidth BW Flash Since the second cache space uses the average write bandwidth as the release bandwidth, the amount of data written will be greater than the amount of data released. Therefore, the user data space in the second cache space will be greater than the release space compensated to the first cache space. This results in a portion of the user data space (program-done cache) still existing in the second cache space, i.e., BW. flash -BW avg The program done cache will first accumulate in the second cache space (RSV cache), and the amount of data accumulated will increase over time.

[0187] In view of this, in the average write bandwidth BW avg Greater than the current bandwidth BW Flash Under the conditions, this application further improves upon the current bandwidth BW Flash Based on this, add a feedback bandwidth (FeedBack BW, BW) fd ), to the current bandwidth BW Flash Compensation is performed, and the compensated bandwidth is used as the first released bandwidth.

[0188] Step S1103: Use the average write bandwidth as the first release bandwidth.

[0189] Understandably, this is true for the average write bandwidth BW. avg Less than the current bandwidth BWFlash In this case, the average write bandwidth is directly taken as the first release bandwidth to release the user data in the second cache space through the first release bandwidth.

[0190] Step S1104: Taking the sum of the current bandwidth and the feedback bandwidth as the first release bandwidth.

[0191] Specifically, if the average write bandwidth BW avg is greater than or equal to the current bandwidth BW Flash , the sum of the current bandwidth and the feedback bandwidth is taken as the first release bandwidth, that is, the first release bandwidth = current bandwidth BW Flash + feedback bandwidth BW fd , to release the user data in the second cache space through the updated first release bandwidth.

[0192] In the embodiments of the present application, the feedback bandwidth = first coefficient * user data space, wherein the user data space is the size of the user data in the second cache space.

[0193] Specifically, the user data space is the user data that has been successfully written into the flash memory space in the second cache space, that is, the user data that has completed program in the second cache space (Rsv cache). The first coefficient can be set according to actual needs, or calibrated according to experimental results.

[0194] In the embodiments of the present application, through the feedback mechanism, that is, under the condition that the average write bandwidth is greater than or equal to the current bandwidth of the flash memory space, the current bandwidth is compensated through the feedback bandwidth, which can better solve the performance problem caused by sampling error, correct the small performance evaluation error, and thus better improve the write performance consistency of the host, and further improve the service quality of the flash memory device.

[0195] Further, on the basis of the feedback mechanism, the embodiments of the present application provide a waterline mechanism.

[0196] It can be understood that the user data in the second cache space will be released, and therefore the size of the user data in the second cache space is dynamically changed, that is, the user data space is dynamically changed, which is the size of the data successfully written into the flash memory space, that is, the cache of the user data that has completed program in the second cache space (Rsv cache), denoted as Cache rsv .

[0197] In the embodiments of the present application, the feedback bandwidth is determined by the size relationship between the user data space Cache rsv and the waterline threshold.

[0198] Please refer back to Figure 12 , Figure 12is a schematic diagram of a water line threshold provided by an embodiment of the present application.

[0199] As shown in Figure 12 , the water line threshold is less than the size of the second cache space (Rsv cache).

[0200] Specifically, please refer to Figure 13 , Figure 13 is a flowchart of a process for determining a feedback bandwidth provided by an embodiment of the present application.

[0201] As shown in Figure 13 , the process for determining a feedback bandwidth includes the following steps S1301-S1304:

[0202] Step S1301: setting a water line threshold.

[0203] Among them, Cache waterLine The water line threshold is less than the size of the second cache space.

[0204] Step S1302: judging whether the user data space is less than or equal to the water line threshold.

[0205] Specifically, if the user data space is less than or equal to the water line threshold, go to step S1303; otherwise, go to step S1304.

[0206] Step S1303: setting the feedback bandwidth to zero.

[0207] Specifically, if the user data space is less than or equal to the water line threshold, set the feedback bandwidth to zero.

[0208] Step S1304: setting the feedback bandwidth to a second coefficient*(user data space-water line threshold).

[0209] Specifically, if the user data space is greater than the water line threshold, set the feedback bandwidth to a second coefficient*(user data space-water line threshold).

[0210] In the embodiment of the present application, the feedback bandwidth BW fd = b*MAX(0, Cache rsv -Cache waterLine ), where b is a second coefficient, and MAX(0, Cache rsv -Cache waterLine ) refers to the larger value of 0 and (Cache rsv -Cache waterLine ), for example:

[0211] If the difference between the user data space and the water line threshold is greater than 0, that is, Cachersv -Cache waterLine If the value is greater than 0, then the feedback bandwidth = b * (Cache) rsv -Cache waterLine ).

[0212] If the difference between the user data space and the waterline threshold is less than or equal to 0, that is, the cache... rsv -Cache waterLine If ≤0, then the feedback bandwidth = b * 0 = 0.

[0213] In this embodiment, the second coefficient may be equal to or different from the first coefficient. The second coefficient can be set according to actual needs or calibrated based on experimental results.

[0214] Understandably, this is in the absence of a waterline threshold cache. waterLine At that time, Cache rsv It is based on 0, that is, BW fd =a*Cache rsv In the Cache rsv When the value is 0, no feedback compensation is needed, and the compensation cache is limited when performance degrades. However, this application's embodiment sets a waterline threshold cache. waterLine This makes BW fd =b*MAX(0, Cache) rsv -Cache waterLine When the current bandwidth is less than the average bandwidth, the cache... rsv There will be more cache to compensate.

[0215] For example: Figure 12 As shown, Cache waterLine If the current bandwidth is greater than the average bandwidth, and the cache is set to 10MB, then... rsv If the data size is less than 10MB, meaning the user data space does not exceed the dotted line, no feedback compensation is needed; the data will be stored in the cache. rsv Inside; and in the cache rsv When the user data space exceeds 10MB (i.e., the dotted line), feedback compensation is performed to improve cache performance. rsv The rate of release.

[0216] Understandably, the waterline threshold cache waterLine The larger the better, as it can compensate for more performance drops. However, cache is also subject to cost constraints. The waterline threshold needs to be weighed against cost and smoothing effect in actual use.

[0217] In this embodiment, a waterline mechanism is used to implement the cache.rsv Less than Cache waterLine Without feedback compensation, more cache is accumulated in the second cache space (RSV cache), which can better compensate for performance lower than BW. avg Compensation will be provided in a timely manner.

[0218] Understandably, before sampling the current bandwidth of the flash memory, smoothing the write bandwidth of the flash memory cannot be performed due to the lack of an assessment of the write bandwidth. However, in flash memory application scenarios, there are situations where the host's write bandwidth is lower than the flash memory device's bandwidth capability. For example, the SSD's write bandwidth capability is 2GB / s, but the host's write bandwidth is only 300MB / s. In this case, smoothing is not necessary.

[0219] Therefore, embodiments of this application further determine the smoothing state of the flash memory device based on the current conditions of the flash memory device and the host to adapt to different application scenarios, thereby enabling fast response for different IO models to complete the ramp-up.

[0220] For details, please refer to Figure 14 , Figure 14 This is a schematic diagram of a process for determining the smooth state of a flash memory device according to an embodiment of this application.

[0221] like Figure 14 As shown, determining the smooth state of the flash memory device includes the following steps S1401-S1404:

[0222] Step S1401: Obtain the current conditions of the flash memory device and the host.

[0223] Specifically, the smooth states of a flash memory device include the off state, the sampling state, and the operating state.

[0224] Step S1402: If the current condition meets the first condition, then determine that the smoothing state of the flash memory device is off.

[0225] It is understandable that if the smooth state of the flash memory device is the off state (State) off If the value is 0, then smoothing is not required.

[0226] Specifically, the first condition includes the host's write bandwidth being zero, or the number of successful requests for cache space from the host being greater than the number of failed requests, or the host's write bandwidth being less than the target bandwidth of the flash memory device.

[0227] The first condition includes the following three cases, and it is only necessary to satisfy at least one of the following three cases:

[0228] (1) the write bandwidth of the host is zero.

[0229] Specifically, the write bandwidth of the host is zero, which means that the host does not send a write request to the flash device, so that the host does not need to write user data to the flash device, and at this time, the write bandwidth of the host is zero, that is, Host write is 0.

[0230] (2) when the host applies for a cache space to the cache space, the number of successful applications is greater than the number of failed applications.

[0231] Specifically, when the host sends a cache application command to the flash device, the number of successful applications and the number of failed applications are counted, and if the number of successful applications is greater than the number of failed applications, the first condition is met.

[0232] Further, if the number of successful applications is much greater than the number of failed applications, the first condition is met, for example: a first ratio of the number of successful applications to the number of failed applications is calculated, the first ratio = the number of successful applications / the number of failed applications, and if the first ratio is greater than a preset coefficient, it is determined that the first condition is met. In the embodiments of the present application, the preset coefficient can be set according to actual needs, or calibrated according to experimental results, for example: the preset coefficient is set to 100.

[0233] (3) the write bandwidth of the host is less than the target bandwidth of the flash device.

[0234] Specifically, the target bandwidth of the flash device refers to the maximum bandwidth of the flash device, and if the write bandwidth of the host is less than the target bandwidth of the flash device, it means that the writing speed of the host cannot keep up with the writing speed of the flash space, and at this time, the write bandwidth of the flash device does not need to be smoothed.

[0235] Step S1403: if the current condition meets the second condition, it is determined that the smoothing state of the flash device is a sampling state.

[0236] It can be understood that if the smoothing state of the flash device is a sampling state (State ramp ), the bandwidth is not limited, and at this time, the write bandwidth of the flash space needs to be sampled.

[0237] Specifically, the second condition includes that the write bandwidth of the host is not zero, and when the host applies for a cache space to the cache space, the number of successful applications is less than the number of failed applications, or the write bandwidth of the host is greater than the target bandwidth of the flash device.

[0238] The first condition includes the following three cases, and the following three cases need to be met at the same time:

[0239] (1) the write bandwidth of the host is not zero.

[0240] Specifically, the write bandwidth of the host is not zero, which means that the host sends a write request to the flash device, so that the host needs to write user data to the flash device, and at this time, the write bandwidth of the host is not zero, that is, Host write is not 0.

[0241] (2) When the host applies for a cache space to the cache space, the number of successful applications is less than the number of failed applications.

[0242] Specifically, when the host sends a cache application command to the flash device, the number of successful applications and the number of failed applications are counted, and if the number of successful applications is less than the number of failed applications, the (2) point is met.

[0243] Further, if the first ratio of the number of successful applications to the number of failed applications is less than a preset coefficient, the (2) point is met. The first ratio = the number of successful applications / the number of failed applications. In the embodiments of the present application, the preset coefficient can be set according to actual needs, or calibrated according to experimental results, for example: the preset coefficient is set to 100.

[0244] (3) The write bandwidth of the host is greater than the target bandwidth of the flash device.

[0245] Specifically, the target bandwidth of the flash device refers to the maximum bandwidth of the flash device, and if the write bandwidth of the host is greater than the target bandwidth of the flash device, it means that the write speed of the host is greater than the write speed of the flash space, and at this time, the write bandwidth of the flash device needs to be smoothed.

[0246] Step S1404: If the current condition meets the third condition, it is determined that the smoothing state of the flash device is the working state.

[0247] It can be understood that if the smoothing state of the flash device is the working state (State on ), the write bandwidth of the flash device needs to be smoothed.

[0248] Specifically, the third condition includes that the sampling time of the sampling state is greater than a preset time threshold. The preset time threshold can be set according to specific needs, for example, set to 10s, and after the sampling time is greater than 10s, the write bandwidth of the flash space is smoothed to obtain the average write bandwidth of the flash space.

[0249] It can be understood that when the current condition of the flash device and the host changes, the smoothing state of the flash device needs to be switched.

[0250] Specifically, please refer to Figure 15 , Figure 15 is a schematic diagram provided by the embodiments of the present application for switching the smoothing state.

[0251] As Figure 15The smooth state of the flash memory device is switched, including:

[0252] When the smooth state of the flash memory device is in the closed state, if the current condition meets the second condition, the smooth state of the flash memory device is switched to the sampling state;

[0253] When the smooth state of the flash memory device is in the sampling state, if the current condition meets the first condition, the smooth state of the flash memory device is switched to the closed state; or, if the current condition meets the third condition, the smooth state of the flash memory device is switched to the working state;

[0254] When the smooth state of the flash memory device is in the working state, if the current condition meets the first condition, the system state of the flash memory device is switched to the closed state.

[0255] It should be noted that the first condition, the second condition, and the third condition can refer to the content described above, which will not be repeated here.

[0256] In the embodiments of the present application, the smooth state of the flash memory device is switched, further including:

[0257] When the smooth state of the flash memory device is in the working state,

[0258] In the first sampling period, the first average write bandwidth of the flash memory space is calculated;

[0259] In the second sampling period, the second average write bandwidth of the flash memory space is calculated, wherein the second sampling period is greater than the first sampling period;

[0260] If the difference between the first average write bandwidth and the second average write bandwidth is greater than a difference threshold, the working state is switched to the closed state.

[0261] It can be understood that the first sampling period is a short period, and the second sampling period is a long period. Long period sampling represents long-term average bandwidth, and short period represents short-term average bandwidth. When the long period and the short period are not equal, it indicates that the flash memory device is not in a stable bandwidth state, and the working state needs to be switched to the closed state to re-adjust the flash memory device to a stable bandwidth state, so as to balance the bandwidth.

[0262] Specifically, assuming that the first sampling period is T1, and the second sampling period is T2, wherein T2>T1, each sampling time in the first sampling period T1 is sampled to obtain a plurality of first write bandwidths, and the plurality of first write bandwidths are smoothed by a smoothing algorithm to obtain the first average write bandwidth corresponding to the first sampling period; similarly, each sampling time in the second sampling period T2 is sampled to obtain a plurality of first write bandwidths, and the plurality of first write bandwidths are smoothed by a smoothing algorithm to obtain the second average write bandwidth corresponding to the second sampling period.

[0263] If the difference between the first average write bandwidth and the second average write bandwidth is greater than the difference threshold value, the working state is switched to the closed state (State off ).

[0264] In the embodiments of the present application, the first sampling period T1 and the second sampling period T2 can be set according to specific needs, for example, the first sampling period T1 is set to 5s and the second sampling period T2 is set to 8s.

[0265] In the embodiments of the present application, the difference threshold value can be set according to specific needs, for example, the difference threshold value is set to the larger value of the preset bandwidth threshold value and (the average write bandwidth * the third coefficient), that is, the difference threshold value = Max (the preset bandwidth threshold value, the average write bandwidth * the third coefficient), for example, the preset bandwidth threshold value is 50MB / s and the third coefficient is 0.1, then the difference threshold value = Max (50MB / s, BW avg * 0.1).

[0266] In the embodiments of the present application, by determining the smoothing state of the flash memory device and switching the smoothing state of the flash memory device in real time according to the current conditions, the state management can be better implemented, so as to quickly respond to the changes of the IO model and improve the stability of the flash memory device.

[0267] In the embodiments of the present application, by providing a data writing method applied to a flash memory device, the flash memory device includes a cache space and a flash memory space, the cache space includes a first cache space and a second cache space, wherein the first cache space is used to cache user data issued by a host, and the second cache space is used to cache user data that has been written into the flash memory space; the method includes: obtaining user data issued by the host and storing the user data in the first cache space; writing the user data in the first cache space into the flash memory space; after the user data is written into the flash memory space, caching the user data that has been written into the flash memory space in the second cache space; smoothing the write bandwidth of the flash memory space to obtain an average write bandwidth of the flash memory space; determining a first release bandwidth according to the average write bandwidth of the flash memory space, wherein the first release bandwidth is equal to the average write bandwidth; and releasing the user data in the second cache space according to the first release bandwidth.

[0268] By setting the second cache space in the cache space to cache the user data that has been written into the flash memory space, and using the average write bandwidth of the flash memory space to determine the release bandwidth of the second cache space, the second cache space releases the user data at the average write bandwidth of the flash memory space, so that the bandwidth fluctuation of the host can be smoothed, the write performance consistency of the host can be improved, and the service quality of the flash memory device can be improved.

[0269] Please refer to Figure 16 ,Figure 16 is a structural schematic diagram of another flash memory device provided by an embodiment of the present application.

[0270] As shown in Figure 16 The flash memory device 100 includes one or more processors 121 and a memory 122. Among them, Figure 16 Take the processor 121 as an example.

[0271] The processor 121 and the memory 122 can be connected by a bus or other means, Figure 16 Take the connection by the bus as an example.

[0272] The processor 121 is configured to provide computing and control capabilities to control the flash memory device 100 to perform corresponding tasks, for example, to control the flash memory device 100 to perform the data writing method in any one of the above method embodiments. The data writing method is applied to a flash memory device, and the flash memory device includes a cache space and a flash memory space. The cache space includes a first cache space and a second cache space. The first cache space is used to cache user data issued by a host, and the second cache space is used to cache user data that has been written to the flash memory space. The method includes: obtaining user data issued by the host, and storing the user data in the first cache space; writing the user data in the first cache space to the flash memory space; after the user data is written to the flash memory space, caching the user data that has been written to the flash memory space in the second cache space; smoothing the write bandwidth of the flash memory space to obtain an average write bandwidth of the flash memory space; determining a first release bandwidth according to the average write bandwidth of the flash memory space, wherein the first release bandwidth is equal to the average write bandwidth; and releasing the user data in the second cache space according to the first release bandwidth.

[0273] By setting the second cache space in the cache space to cache the user data that has been written to the flash memory space, and using the average write bandwidth of the flash memory space to determine the release bandwidth of the second cache space, the second cache space releases the user data at the average write bandwidth of the flash memory space, so that the bandwidth fluctuation of the host can be smoothed. The present application can improve the consistency of the write performance of the host, and further improve the service quality of the flash memory device.

[0274] The processor 121 can be a general processor, including a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof; and can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0275] The memory 122, as a non-transitory computer readable storage medium, can be used to store non-transitory software programs, non-transitory computer executable programs and modules, such as program instructions / modules corresponding to the data writing method in the embodiments of the present application. The processor 121 can implement the data writing method in any one of the method embodiments by running the non-transitory software programs, instructions and modules stored in the memory 122. Specifically, the memory 122 can include a volatile memory (VM), such as a random access memory (RAM); the memory 122 can also include a non-volatile memory (NVM), such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD), or other non-transitory solid-state storage devices; and the memory 122 can further include a combination of the above types of memories.

[0276] The memory 122 can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 122 can optionally include a memory disposed remotely relative to the processor 121, and these remote memories can be connected to the processor 121 through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0277] One or more modules are stored in the memory 122, and when executed by the one or more processors 121, perform the data writing method in any of the above method embodiments, for example, perform the data writing method described above. Figure 3 The various steps are shown.

[0278] In the embodiments of the present application, the flash memory device 100 can also have a wired or wireless network interface, a keyboard, and an input and output interface, and the like, so as to perform input and output, and the flash memory device 100 can also include other components for implementing device functions, which are not described herein.

[0279] The embodiments of the present application also provide a computer readable storage medium, for example, a memory including program codes, which can be executed by a processor to complete the data writing method in the above embodiments. For example, the computer readable storage medium can be a Read-Only Memory (ROM), a Random Access Memory (RAM), a Compact Disc Read-Only Memory (CDROM), a magnetic tape, a floppy disk, and an optical data storage device, and the like.

[0280] The embodiments of the present application also provide a computer program product, which includes one or more program codes stored in a computer readable storage medium. The processor of the flash memory device reads the program codes from the computer readable storage medium, and the processor executes the program codes to complete the method steps of the data writing method provided in the above embodiments.

[0281] Those skilled in the art can understand that all or part of the steps of the above embodiments can be completed by hardware, or by program codes related hardware, and the program can be stored in a computer readable storage medium, and the above mentioned storage medium can be a Read-Only Memory, a magnetic disk or an optical disk, and the like.

[0282] Those skilled in the art can clearly understand from the above description of the embodiments that the embodiments can be implemented by means of software and a general hardware platform, and of course, can also be implemented by hardware. Those skilled in the art can understand that all or part of the processes in the above embodiments can be completed by a computer program to instruct related hardware, and the program can be stored in a computer readable storage medium, and when the program is executed, can include the processes of the above embodiments. The storage medium can be a magnetic disk, an optical disk, a Read-Only Memory (ROM) or a Random Access Memory (RAM), and the like.

[0283] It should be noted that the above examples are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; under the idea of the present application, the technical features in the above examples or different examples can also be combined, the steps can be implemented in any order, and there are many other changes of different aspects of the present application as described above, which are not provided in details for the sake of simplicity; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data writing method, characterized in that, The invention is applied to a flash memory device, which includes a cache space and a flash memory space. The cache space includes a first cache space and a second cache space. The first cache space is used to cache user data sent by the host, and the second cache space is used to cache user data that has been written to the flash memory space. The method includes: Obtain user data sent by the host and store the user data in the first cache space; Write the user data in the first cache space to the flash memory space; After the user data is written to the flash memory space, the user data already written to the flash memory space is cached in the second cache space; The write bandwidth of the flash memory space is smoothed to obtain the average write bandwidth of the flash memory space; A first release bandwidth is determined based on the average write bandwidth of the flash memory space, wherein the first release bandwidth is equal to the average write bandwidth; Based on the first released bandwidth, release the user data in the second cache space; The method further includes: Obtain the current bandwidth of the flash memory space; Determine whether the average write bandwidth is less than the current bandwidth of the flash memory space; If the average write bandwidth is less than the current bandwidth, then the average write bandwidth is used as the first release bandwidth; If the average write bandwidth is greater than or equal to the current bandwidth, then the sum of the current bandwidth and the feedback bandwidth is taken as the first release bandwidth; The method further includes: Determining the feedback bandwidth based on the user data space includes: Set a waterline threshold, wherein the user data space is the size of the user data in the second cache space, and the waterline threshold is smaller than the second cache space; Determine whether the user data space is less than or equal to the waterline threshold; If so, then set the feedback bandwidth to zero; If not, then set the feedback bandwidth to the second coefficient * (user data space - waterline threshold).

2. The method according to claim 1, characterized in that, The smoothing of the write bandwidth of the flash memory space to obtain the average write bandwidth of the flash memory space includes: The amount of data successfully written to the flash memory space is counted in real time. After each sampling time, the data increment of the written data is counted to calculate the first write bandwidth corresponding to each sampling time, wherein the first write bandwidth = data increment / sampling time; The average write bandwidth is obtained by smoothing multiple first write bandwidths using a smoothing algorithm.

3. The method according to claim 1, characterized in that, The step of obtaining user data sent by the host and storing the user data in the first cache space includes: Obtain the cache request command corresponding to the write request of the host, wherein the cache request command corresponds to the currently requested space; According to the cache request command, the currently requested space is requested from the cache space to store the user data in the first cache space, wherein the first cache space = the already requested first cache space + the currently requested space.

4. The method according to claim 3, characterized in that, After releasing the user data in the second cache space, the method further includes: Determine the current freed space, where the current freed space is used to compensate the first cache space; If the space to be released is less than the space currently requested, then the cache request command is determined to have failed. If the released space is greater than or equal to the currently requested space, then the cache request command is determined to be successful.

5. The method according to claim 1, characterized in that, The method further includes: Determining the smoothing state of the flash memory device based on the current conditions of the flash memory device and the host includes: If the current conditions meet the first condition, then the smoothing state of the flash memory device is determined to be off. The first condition includes: the host's write bandwidth is zero, or, when the host requests cache space from the cache space, the number of successful requests is greater than the number of failures, or, the host's write bandwidth is less than the target bandwidth of the flash memory device. If the current condition meets the second condition, then the smooth state of the flash memory device is determined to be the sampling state. The second condition includes: the host's write bandwidth is not zero, and when the host requests cache space from the cache space, the number of successful requests is less than the number of failures, or the host's write bandwidth is greater than the target bandwidth of the flash memory device. If the current conditions meet the third condition, then the smooth state of the flash memory device is determined to be the working state, wherein the third condition includes: the sampling time of the sampling state is greater than a preset time threshold.

6. The method according to claim 5, characterized in that, The method further includes: Switching the smooth state of the flash memory device includes: When the smoothing state of the flash memory device is off, if the current condition meets the second condition, the smoothing state of the flash memory device is switched to the sampling state. When the smoothing state of the flash memory device is in the sampling state, if the current condition meets the first condition, the smoothing state of the flash memory device is switched to the off state; or, if the current condition meets the third condition, the smoothing state of the flash memory device is switched to the working state. When the smooth state of the flash memory device is in the working state, if the current condition meets the first condition, the system state of the flash memory device is switched to the off state.

7. The method according to claim 6, characterized in that, The smooth switching of the flash memory device also includes: When the smoothing state of the flash memory device is in operation. During the first sampling period, the first average write bandwidth of the flash memory space is calculated; During the second sampling period, the second average write bandwidth of the flash memory space is calculated, wherein the second sampling period is greater than the first sampling period; If the difference between the first average write bandwidth and the second average write bandwidth is greater than the difference threshold, then the working state is switched to the off state.

8. A flash memory device, characterized in that, include: A processor and a memory, the processor being configured to execute executable program code in the memory, wherein when the executable program code is executed, the processor executes instructions of the data writing method as described in any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed, implements the data writing method as described in any one of claims 1 to 7.

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