Direct memory access controller task management method and device, equipment and medium
By storing tasks according to priority in a multi-core system and dynamically allocating them to the appropriate DMA, the problems of DMA load imbalance and cache access conflicts are solved, and system performance and DMA resource utilization are improved.
Patent Information
- Application Number
- CN202510237522.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-28
- Publication Date
- 2025-05-23
AI Technical Summary
In multi-core systems, some DMAs are overloaded due to overloading tasks, and the task waiting queue is long, while the other DMAs are too light and even idle, resulting in waste of DMA array resources and extended task waiting time. At the same time, cache access conflicts cause other tasks to wait for transmission when tasks with high priority, reducing the operating efficiency of the DMA array.
By storing the tasks sent by the processor core to the first cache according to priority and determining whether the target task in the second cache meets the processing conditions, dynamically allocating the tasks to the appropriate direct memory access controller to avoid memory access conflicts, and filtering the appropriate DMA based on the load factor constituent factors and load weights.
It effectively avoids task waiting caused by cache access conflicts, improves the efficiency of the direct memory access controller array during cache access, improves system performance, and reduces resource waste and waiting cycles.
Smart Images
Figure CN120029949A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of computer technology, and in particular to a direct memory access controller task management method, device, equipment and medium. Background Art
[0002] In the development of digital systems, DMA (Direct Memory Access) technology has become a key force in improving data transmission efficiency due to its unique advantages. DMA can bypass the CPU (Central Processing Unit) and use DMAC (Direct Memory Access Controller) to achieve batch transfer of data between different address spaces, building a high-speed data transmission channel between peripherals and memory, and between memory and memory, see Figure 1 As shown, Figure 1 A schematic diagram of a DMA sequence in a multi-core system.
[0003] In a multi-core system, a pre-set mapping relationship is established between each processor or processing core and the DMA controller and its internal DMA channels. When the processing core generates data transmission requirements and issues tasks, the system will deploy the corresponding DMA module based on this mapping relationship to ensure orderly data transmission.
[0004] However, some DMAs are overloaded due to taking on too many tasks, and the task waiting queue is long, while other DMAs are underloaded or even idle, which not only causes a serious waste of DMA array resources, but also causes the waiting DMA tasks to be unable to be processed in time, greatly extending the waiting time. In addition, when multiple DMA tasks need to access the same cache space, once the high-priority task starts transmitting, other DMA tasks can only be forced to wait until the high-priority task is completed, which not only reduces the operating efficiency of the DMA array, but also adds additional waiting cycles, restricting the improvement of system performance. Summary of the invention
[0005] In view of this, the purpose of the present invention is to provide a direct memory access controller task management method, device, equipment and medium, which effectively avoids task waiting caused by cache access conflicts, improves the efficiency of the direct memory access controller array during cache access, and improves the performance of the system. The specific scheme is as follows:
[0006] In a first aspect, the present application discloses a direct memory access controller task management method, comprising:
[0007] The tasks issued by different processor cores are stored in the first cache according to the priority, and it is determined whether the first target task in the second cache meets the processing condition; wherein the first cache stores the tasks issued by the processor core, and the second cache stores the tasks issued, which have a memory access conflict with the task currently being processed, and meeting the processing condition indicates that the memory access conflict is ended;
[0008] If the first target task in the second cache meets the processing condition, the first target task is allocated to a corresponding direct memory access controller based on a preset rule, and the first target task is processed by the corresponding direct memory access controller;
[0009] If the first target task in the second cache does not meet the processing conditions, the second target task is obtained from the first cache according to the priority. If there is no memory access conflict between the second target task and the task currently being processed, the second target task is processed by an adapted direct memory access controller, and then jumps to the step of determining whether the first target task in the second cache meets the processing conditions.
[0010] Optionally, allocating the first target task to a corresponding direct memory access controller based on a preset rule includes:
[0011] Determine the load factor components corresponding to the current task management scenario, and obtain the load factor according to the load factor components;
[0012] The load factor components include one or two of a task-related factor and a processing capacity-related factor, the task-related factor is obtained based on the number and length of tasks being processed or to be processed by each direct memory access controller, and the processing capacity-related factor is obtained based on the number of transmission channels of each direct memory access controller, the transmission rate of each transmission channel, and the maximum number of outstanding requests of each transmission channel;
[0013] According to the transmission requirements of the current task management scenario for each direct memory access controller, configure the load weight of each load factor component in the load factor;
[0014] According to the load factor components and the corresponding load weights, a direct memory access controller that matches the first target task is selected from each direct memory access controller, and the first target task is allocated to the matched direct memory access controller.
[0015] Optionally, determine the load factor components corresponding to the current task management scenario, including:
[0016] If the current task management scenario is a real-time task processing scenario, the load factor components are task-related factors; wherein the task response time of the real-time task processing scenario is less than a first threshold, and the task processing time is less than a second threshold.
[0017] Optionally, determine the load factor components corresponding to the current task management scenario, including:
[0018] If the current task management scenario is a data transmission intensive scenario, the load factor components are determined as task-related factors and processing capacity-related factors; the data transmission rate of the data transmission intensive scenario is greater than the third threshold, and the total data transmission amount is greater than the fourth threshold.
[0019] Optionally, selecting a direct memory access controller that is compatible with the first target task from each direct memory access controller according to the load factor components and the corresponding load weights includes:
[0020] For any of the direct memory access controllers, determining a product value of the load factor component and the corresponding load weight, and using the product value as a load evaluation value of the direct memory access controller;
[0021] The direct memory access controller having the lowest load evaluation value is used as the direct memory access controller adapted to the first target task.
[0022] Optionally, direct memory access controller task management, also includes:
[0023] For any direct memory access controller, transmission information of each transmission channel is obtained, and the state of the direct memory access controller is monitored according to the transmission information; wherein the transmission information includes task description information and task state information.
[0024] Optionally, after obtaining the second target task from the first cache according to the priority, the method further includes:
[0025] If there is a memory access conflict between the second target task and the task currently being processed, the second target task is transferred from the first cache to the second cache, and then the process jumps to the step of determining whether the first target task in the second cache meets the processing condition.
[0026] In a second aspect, the present application discloses a direct memory access controller task management device, comprising:
[0027] The task storage module is used to store the tasks issued by different processor cores into the first cache according to the priority, and judge whether the first target task in the second cache meets the processing condition; wherein the first cache stores the tasks issued by the processor core, and the second cache stores the tasks issued, which have a memory access conflict with the task currently being processed, and the memory access conflict is ended when the processing condition is met;
[0028] a conflicting task processing module, configured to allocate the first target task to a corresponding direct memory access controller based on a preset rule if the first target task in the second cache meets the processing condition, and process the first target task through the corresponding direct memory access controller;
[0029] The task hierarchical processing module is used to obtain the second target task from the first cache according to the priority if the first target task in the second cache does not meet the processing conditions; if there is no memory access conflict between the second target task and the task currently being processed, the second target task is processed by a corresponding direct memory access controller, and then jumps to the step of determining whether the first target task in the second cache meets the processing conditions.
[0030] In a third aspect, the present application discloses an electronic device, including:
[0031] Memory, used to store computer programs;
[0032] The processor is used to execute a computer program to implement the direct memory access controller task management method disclosed above.
[0033] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the direct memory access controller task management method disclosed above is implemented.
[0034] It can be seen that the present application proposes a direct memory access controller task management method, including: storing tasks issued by different processor cores in a first cache according to priority, and judging whether a first target task in a second cache meets processing conditions; storing tasks issued by the processor core in the first cache, and storing tasks in the second cache that have memory access conflicts with tasks currently being processed, and satisfying the processing conditions indicates that the memory access conflict is ended; if the first target task in the second cache meets the processing conditions, the first target task is allocated to an adapted direct memory access controller based on preset rules, and the first target task is processed by the adapted direct memory access controller; if the first target task in the second cache does not meet the processing conditions, the second target task is obtained from the first cache according to priority, and if the second target task does not have a memory access conflict with the task currently being processed, the second target task is processed by the adapted direct memory access controller, and then the step of jumping to judging whether the first target task in the second cache meets the processing conditions. It can be seen that the present application stores the tasks issued by different processor cores in the first cache first, and then distributes the tasks to the corresponding direct memory access controller based on preset rules, so that the tasks can be more reasonably distributed to each DMA, avoiding the situation where some DMAs are overloaded and some are idle, improving the utilization rate of DMA array resources and reducing resource waste. Furthermore, the present application judges the memory access conflict of tasks, and processes tasks according to the priority and preset rules. When there is no first target task that meets the processing conditions in the second cache, the second target task without memory access conflict is obtained from the first cache according to the first priority, avoiding the invalid waiting of other tasks when the high-priority task is transmitted, improving the efficiency of the DMA array in cache access, and then improving the overall performance of the system, and reducing the negative impact of additional waiting cycles on system performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.
[0036] Figure 1 A schematic diagram of a DMA sequence in a traditional multi-core system;
[0037] Figure 2 A flow chart of a direct memory access controller task management method disclosed in this application;
[0038] Figure 3 A schematic diagram of a DMA sequence in a multi-core system disclosed in this application;
[0039] Figure 4 A schematic diagram of the structure of a task management system disclosed in this application;
[0040] Figure 5 A schematic diagram of an information matrix disclosed in this application;
[0041] Figure 6 A flow chart of a specific direct memory access controller task management method disclosed in this application;
[0042] Figure 7 A comparison diagram before and after the method is adopted is disclosed;
[0043] Figure 8 A schematic diagram of a direct memory access controller task management device disclosed in this application;
[0044] Fig. 9 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION
[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0046] When the processor core issues a task, the system will deploy the corresponding DMA module to ensure orderly data transmission. However, some DMAs are overloaded due to taking on too many tasks, and the task waiting queue is long, while other DMAs are underloaded or even idle, which not only causes a serious waste of DMA array resources, but also causes the waiting DMA tasks to be unable to be processed in time, greatly extending the waiting time. In addition, when multiple DMA tasks need to access the same cache space, once the high-priority task starts transmitting, other DMA tasks can only be forced to wait until the high-priority task is completed, which not only reduces the operating efficiency of the DMA array, but also adds additional waiting cycles, restricting the improvement of system performance.
[0047] To this end, an embodiment of the present application proposes a direct memory access controller task management solution, which can effectively avoid task waiting caused by cache access conflicts, improve the efficiency of the direct memory access controller array during cache access, avoid additional waiting cycles, and improve system performance.
[0048] The present application embodiment discloses a direct memory access controller task management method, see Figure 2 As shown, the method includes:
[0049] Step S11: Store the tasks issued by different processor cores into the first cache according to priority, and determine whether the first target task in the second cache meets the processing conditions; wherein the first cache stores the tasks issued by the processor core, and the second cache stores the issued tasks, and the tasks that have a memory access conflict with the task currently being processed, and meeting the processing conditions indicates that the memory access conflict is ended.
[0050] This application adds a task management control system between different processor cores and DMA arrays. Figure 3 It can be seen that the control state machine in the system can monitor in real time and make intelligent adjustments to the task distribution strategy of the DMA array. By allocating tasks in this way, the load of the DMA array can be balanced, thereby improving its utilization. In this way, it is effectively avoided that the DMA array will waste extra waiting time due to conflicts when accessing the memory, and the cache access efficiency will be greatly improved. Figure 4 The structure diagram of the task management system is shown in Figure 1. The system mainly includes a task priority arbitration module, a task list buffer (including a first buffer and a second buffer), a control state machine, a DMA arbitration module, a state monitoring module, and an interrupt control module.
[0051] Specifically, the task priority arbitration module stores the tasks issued by different processor cores into the first cache according to the priority ( Figure 4 The cache where Task 1, Task 2, Task 3, etc. are located) controls the state machine to determine the second cache ( Figure 4 whether the first target task in the conflicting task queue) meets the processing condition; the first cache stores the tasks issued by the processor core, and the second cache stores the tasks issued, which have a memory access conflict with the task currently being processed. Meeting the processing condition indicates that the memory access conflict is ended. It can be understood that the memory access conflict means that the storage area pointed to by the two tasks is the same storage area.
[0052] Step S12: if the first target task in the second cache meets the processing condition, the first target task is allocated to a corresponding direct memory access controller based on a preset rule, and the first target task is processed by the corresponding direct memory access controller.
[0053] In this embodiment, if the first target task in the second cache meets the processing conditions, the DMA arbitration module allocates the first target task to a corresponding direct memory access controller based on a preset rule, and processes the first target task through the corresponding direct memory access controller.
[0054] The following is a detailed description of allocating the first target task to the corresponding direct memory access controller based on the preset rules: determine the load factor components corresponding to the current task management scenario, and obtain the load factor according to the load factor components; the load factor components include one or two of the task-related factors and the processing capacity-related factors, the task-related factors are obtained based on the number of tasks being processed or to be processed by each direct memory access controller and the task length, and the processing capacity-related factors are obtained based on the number of transmission channels of each direct memory access controller, the transmission rate of each transmission channel, and the maximum number of uncompleted requests of each transmission channel. According to the transmission requirements of the current task management scenario for each direct memory access controller, the load weights of each load factor component in the load factor are configured. Further, according to the load factor components and the corresponding load weights, a direct memory access controller that is compatible with the first target task is selected from each direct memory access controller, and the first target task is allocated to the compatible direct memory access controller. Specifically, for any of the direct memory access controllers, determine the product value of the load factor components and the corresponding load weight, and use the product value as the load assessment value of the direct memory access controller; use the direct memory access controller with the lowest load assessment value as the direct memory access controller that is compatible with the first target task.
[0055] In the first aspect, if the current task management scenario is a real-time task processing scenario, the load factor components are task-related factors; wherein the task response time of the real-time task processing scenario is less than the first threshold, and the task processing time is less than the second threshold. For example, assuming that there are three direct memory access controllers (DMAs), namely DMA1, DMA2, and DMA3, and the current task management scenario is a real-time task processing scenario, the first threshold of the task response time is set to 50ms, and the second threshold of the task processing time is set to 100ms. Then the task-related factors of each DMA are: the number of tasks being processed and to be processed by DMA1 is 3, and the total task length is 30 data units; the number of tasks being processed and to be processed by DMA2 is 2, and the total task length is 15 data units; the number of tasks being processed and to be processed by DMA3 is 4, and the total task length is 40 data units. According to the calculation method of task-related factors (assuming that it is the weighted sum of the number of tasks and the task length, where the weights are all set to 1), the value of the task-related factor of DMA1 is 3+30=33; DMA2 is 2+15=17; DMA3 is 4+40=44. In the real-time task processing scenario, the load factor consists only of task-related factors, and the load weight is 1. Therefore, the load evaluation value of DMA1 is 33×1=33; DMA2 is 17×1=17; and DMA3 is 44×1=44. Therefore, DMA2, which has the lowest load evaluation value, is used as the direct memory access controller adapted to the first target task, and the first target task is assigned to DMA2.
[0056] On the second aspect, if the current task management scenario is a data transmission intensive scenario, the load factor components are determined as task-related factors and processing capacity-related factors; the data transmission rate of the data transmission intensive scenario is greater than the third threshold, and the total data transmission amount is greater than the fourth threshold. For example, assuming that there are three direct memory access controllers DMA4, DMA5, and DMA6, the current task management scenario is a data transmission intensive scenario, the third threshold of the data transmission rate is set to 100MB / s, and the fourth threshold of the total data transmission amount is set to 500MB. Calculate the relevant factors of each DMA task: the number of tasks being processed and to be processed by DMA4 is 2, the total task length is 25 data units, and its task-related factor value is 2+25=27; the number of tasks being processed and to be processed by DMA5 is 3, the total task length is 35 data units, and its task-related factor value is 3+35=38; the number of tasks being processed and to be processed by DMA6 is 1, the total task length is 10 data units, and its task-related factor value is 1+10=11. Calculate the processing capacity-related factors of each DMA: DMA4 has 2 transmission channels, each channel has a transmission rate of 20MB / s, and the maximum number of outstanding requests is 5. Its processing capacity-related factor value = 2×20+5=45; DMA5 has 3 transmission channels, each channel has a transmission rate of 15MB / s, and the maximum number of outstanding requests is 4. Its processing capacity-related factor value = 3×15+4=49; DMA6 has 1 transmission channel, each channel has a transmission rate of 30MB / s, and the maximum number of outstanding requests is 3. Its processing capacity-related factor value = 1×30+3=33. Configure the load weight and calculate the load evaluation value: Assume that the load weights of the task-related factors and the processing capacity-related factors are both set to 0.5. Then the DMA4 load evaluation value = 27×0.5+45×0.5=36; the DMA5 load evaluation value = 38×0.5+49×0.5=43.5; the DMA6 load evaluation value = 11×0.5+33×0.5=22. Therefore, DMA6 having the lowest load evaluation value is used as the direct memory access controller adapted to the first target task, and the first target task is allocated to DMA6.
[0057] Step S13: If the first target task in the second cache does not meet the processing conditions, the second target task is obtained from the first cache according to the priority. If there is no memory access conflict between the second target task and the task currently being processed, the second target task is processed by a corresponding direct memory access controller, and the process jumps to the step of determining whether the first target task in the second cache meets the processing conditions.
[0058] In this embodiment, if the first target task in the second cache does not meet the processing conditions, the second target task is obtained from the first cache according to the priority. If there is no memory access conflict between the second target task and the task currently being processed, the second target task is processed by the corresponding direct memory access controller, and the process jumps to the step of determining whether the first target task in the second cache meets the processing conditions. If there is a memory access conflict between the second target task and the task currently being processed, the second target task is transferred from the first cache to the second cache, and then the process jumps to the step of determining whether the first target task in the second cache meets the processing conditions. In other words, if there is a memory access conflict between the second target task and the task currently being processed, the second target task is first transferred to the second cache, and the state of the direct memory access controller is monitored in real time through the state monitoring module to obtain the task execution progress, and the task is issued after the corresponding memory access conflict is released. It should be pointed out that in this embodiment, the state of the direct memory access controller can be monitored based on the transmission information of each transmission channel of the direct memory access controller, and this information provides a basis for the control unit to determine whether there is a list of conflicting tasks that can be released. The transmission information includes task description information and task status information, which are presented in the form of an information matrix (see Figure 5 ). Among them, the task description information covers the source address, target address, transfer length and corresponding core corresponding to the DMA transfer, and the task status information mainly refers to the transfer status. When the first cache or the second cache cannot accommodate more transfer tasks, the interrupt control module will send a corresponding interrupt to the processor core to inform that no more DMA transfer tasks can be performed. In addition, when the DMA array transfer is completed normally, or the transfer is terminated due to a certain type of error, the corresponding interrupt needs to be processed and the corresponding processor needs to be found for reporting. When the task is completed normally, the corresponding monitoring matrix information needs to be updated and cleared to release the storage space in time. In response to the needs of different scenarios of the multi-core architecture, the interrupt control and processing module can also perform a limited number of retransmissions on the DMA tasks that have errors according to the relevant information and requirements of different transmissions. This information is also recorded in the transmission status of the information matrix. In this way, the interrupt control and processing module completes part of the functions instead of the processor, which not only improves the information processing efficiency of the DMA array, but also enhances the control ability of complex data streams.
[0059] Figure 6 A flow chart of a direct memory access controller task management method is disclosed. Specifically,
[0060] 1. The processor core sends multiple DMA tasks to the DMA array task management system based on actual scenarios and requirements, and configures the source address, target address, and transfer length of DMA transfers;
[0061] 2. Arbitrate according to the task priority, so that the tasks are temporarily stored in the first cache in sequence;
[0062] 3. Monitor the DMA array status in real time to determine whether there are completed and releasable conflicting tasks in the second cache (i.e., the conflicting task queue). If so, select the task from the second cache and proceed to step 5; if not, obtain the DMA task from the first cache according to the priority and proceed to step 4;
[0063] 4. Monitor the tasks being executed in the DMA array to determine whether there is a memory access conflict with the current pending task. If so, put the pending task into the second cache to wait; if not, proceed to the next step;
[0064] 5. Preliminary screening of available DMAs based on the remaining available space of the DMA controller in the DMA array;
[0065] 6. For the available DMAs, sort them according to their load capacity to select the DMAC or corresponding DMA channel with the lowest load.
[0066] 7. According to the DMA arbitration result, after address conversion, the current pending task is issued.
[0067] Figure 7 The comparison between the traditional task dispatching method and the DMA array transfer process after adopting the task management of this application is demonstrated. Assume that processor cores 0, 1, and 2 correspond to DMA0, 1, and 2 respectively, where processor core 0 has 4 tasks to be transferred, processor core 1 has 3 tasks to be transferred, and processor core 2 has 1 task to be transferred. The lower the task number, the higher its priority; the line segment length is used to indicate the transfer length of the DMA task; the same letters in the task name mean that they have the same access space, which will cause memory access conflicts. Moreover, DMA0, 1, and 2 can all access the space involved in tasks A, B, C, and D.
[0068] When the method of this application is not adopted, the multi-core system issues DMA tasks as follows: Figure 7 As shown in (a). Due to the memory access conflict between task A1 and tasks A0, C0 and C1, A1 must wait for task A0 to complete the transmission before it can start the transmission. Similarly, task C1 also needs to wait for the higher priority task C0 to complete the transmission before it can be executed. This situation leads to additional waiting cycles, so that the waste caused by memory access conflicts is continuously transmitted throughout the task sequence. In addition, DMA2 has been in an idle state after executing task D2, which makes the load between DMA arrays unbalanced, resulting in a waste of DMA array resources, and ultimately leads to overall low efficiency of the system.
[0069] When this application method is adopted, in an ideal situation, the distribution and allocation of tasks are as follows: Figure 7 (b) When memory access conflicts occur between DMA tasks, the conflicting tasks can be placed in a specially set waiting sequence with conflicts, and then other tasks can be sent and processed. In addition, sending and allocating tasks based on the load capacity of available DMAs can more effectively utilize the currently available DMA controllers or corresponding channels. As shown in Figure 7 As shown in the figure on the right, this method can complete more transmission tasks in a shorter time, so that the load between DMAs is basically balanced. This not only improves the overall transmission efficiency and utilization of the DMA array, enhances the application capability of the DMA array in complex multi-core architecture scenarios, but also improves the overall processing efficiency of the system in large data transmission scenarios.
[0070] The beneficial effects of the present application are as follows: First, the task management method proposed in the present application dynamically adjusts the priority of tasks issued by the processor when multiple DMA tasks access the same cache, suspends tasks with lower priority in conflicting tasks, and gives priority to executing other tasks, thereby avoiding DMA from wasting resources due to extra waiting cycles, thereby improving the efficiency of the DMA array. Second, the task management method proposed in the present application collects and organizes DMA tasks issued by the processor, and manages and allocates tasks according to the load capacity of different DMAs, which can effectively achieve load balancing of the DMA array, thereby improving the data transmission efficiency of the DMA array. Third, the task management scheme proposed in the present application can monitor the transmission status of the DMA array in real time, adjust the corresponding relationship between the DMAC or DMA corresponding channel and the processor through address conversion, realize dynamic scheduling of the DMA array by the multi-core system, and improve the utilization rate of the DMA array. This scheme can avoid the generation of extra waiting cycles when the DMA array accesses the same cache, thereby preventing the waste of DMA resources and improving the efficiency of DMA data transmission. Through the task management system of the DMA array in the multi-core system proposed in the present application, it is possible to effectively schedule the DMA array in a complex data transfer scenario with large amounts of data, keep the load of the DMA array as balanced as possible, and improve the resource utilization of the DMA array; at the same time, it is possible to avoid request conflicts for the same DMA controller or the same channel during data transfer operations of the multi-core system, improve the efficiency of processor data transfer, and thus improve the overall performance of the system.
[0071] In addition, the task management system in this embodiment will analyze in real time the trend of tasks issued by each processor core, the task type, and the current resource usage of the system. Based on this information, the upcoming tasks are pre-scheduled in advance. For example, when the system predicts that a large number of real-time tasks will be incoming, the load factor composition factors and load weights will be adjusted in advance to prioritize the allocation of resources for real-time tasks. At the same time, for tasks that may cause memory access conflicts, the processing order is planned in advance to reduce the waiting time when conflicts occur, thereby improving the system's adaptability to different task types and load changes, and ensuring the stable and efficient operation of the system in complex scenarios.
[0072] It can be seen that the present application proposes a direct memory access controller task management method, including: storing tasks issued by different processor cores in a first cache according to priority, and judging whether a first target task in a second cache meets processing conditions; storing tasks issued by the processor core in the first cache, and storing tasks in the second cache that have memory access conflicts with tasks currently being processed, and satisfying the processing conditions indicates that the memory access conflict is ended; if the first target task in the second cache meets the processing conditions, the first target task is allocated to an adapted direct memory access controller based on preset rules, and the first target task is processed by the adapted direct memory access controller; if the first target task in the second cache does not meet the processing conditions, the second target task is obtained from the first cache according to priority, and if the second target task does not have a memory access conflict with the task currently being processed, the second target task is processed by the adapted direct memory access controller, and then the step of jumping to judging whether the first target task in the second cache meets the processing conditions. It can be seen that the present application stores the tasks issued by different processor cores in the first cache first, and then distributes the tasks to the corresponding direct memory access controller based on preset rules, so that the tasks can be more reasonably distributed to each DMA, avoiding the situation where some DMAs are overloaded and some are idle, improving the utilization rate of DMA array resources and reducing resource waste. Furthermore, the present application judges the memory access conflict of tasks, and processes tasks according to the priority and preset rules. When there is no first target task that meets the processing conditions in the second cache, the second target task without memory access conflict is obtained from the first cache according to the first priority, avoiding the invalid waiting of other tasks when the high-priority task is transmitted, improving the efficiency of the DMA array in cache access, and then improving the overall performance of the system, and reducing the negative impact of additional waiting cycles on system performance.
[0073] Correspondingly, the embodiment of the present application also discloses a direct memory access controller task management device, see Figure 8 As shown, the device comprises:
[0074] The task storage module 11 is used to store the tasks issued by different processor cores into the first cache according to the priority, and judge whether the first target task in the second cache meets the processing condition; wherein the first cache stores the tasks issued by the processor core, and the second cache stores the tasks issued, which have a memory access conflict with the task currently being processed, and the memory access conflict is ended when the processing condition is met;
[0075] The conflicting task processing module 12 is used to allocate the first target task to a corresponding direct memory access controller based on a preset rule if the first target task in the second cache meets the processing condition, and process the first target task through the corresponding direct memory access controller;
[0076] The task hierarchical processing module 13 is used to obtain the second target task from the first cache according to the priority if the first target task in the second cache does not meet the processing conditions; if there is no memory access conflict between the second target task and the task currently being processed, the second target task is processed by a corresponding direct memory access controller, and then jumps to the step of determining whether the first target task in the second cache meets the processing conditions.
[0077] Among them, for more specific working processes of the above-mentioned modules, please refer to the corresponding contents disclosed in the aforementioned embodiments, which will not be repeated here.
[0078] It can be seen that the present application proposes a direct memory access controller task management method, including: storing tasks issued by different processor cores in a first cache according to priority, and judging whether a first target task in a second cache meets processing conditions; storing tasks issued by the processor core in the first cache, and storing tasks in the second cache that have memory access conflicts with tasks currently being processed, and satisfying the processing conditions indicates that the memory access conflict is ended; if the first target task in the second cache meets the processing conditions, the first target task is allocated to an adapted direct memory access controller based on preset rules, and the first target task is processed by the adapted direct memory access controller; if the first target task in the second cache does not meet the processing conditions, the second target task is obtained from the first cache according to priority, and if the second target task does not have a memory access conflict with the task currently being processed, the second target task is processed by the adapted direct memory access controller, and then the step of jumping to judging whether the first target task in the second cache meets the processing conditions. It can be seen that the present application stores the tasks issued by different processor cores in the first cache first, and then distributes the tasks to the corresponding direct memory access controller based on preset rules, so that the tasks can be more reasonably distributed to each DMA, avoiding the situation where some DMAs are overloaded and some are idle, improving the utilization rate of DMA array resources and reducing resource waste. Furthermore, the present application judges the memory access conflict of tasks, and processes tasks according to the priority and preset rules. When there is no first target task that meets the processing conditions in the second cache, the second target task without memory access conflict is obtained from the first cache according to the first priority, avoiding the invalid waiting of other tasks when the high-priority task is transmitted, improving the efficiency of the DMA array in cache access, and then improving the overall performance of the system, and reducing the negative impact of additional waiting cycles on system performance.
[0079] Furthermore, an embodiment of the present application also provides an electronic device. Fig. 9 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram cannot be regarded as any limitation on the scope of use of the present application.
[0080] Fig. 9 The present invention provides a schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a display screen 23, an input / output interface 24, a communication interface 25, a power supply 26, and a communication bus 27. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the direct memory access controller task management method disclosed in any of the aforementioned embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.
[0081] In this embodiment, the power supply 26 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 25 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 24 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.
[0082] In addition, the memory 22, as a carrier for storing resources, may be a read-only memory, a random access memory, a disk or an optical disk, etc., and the resources stored thereon may include a computer program 221, and the storage method may be a temporary storage or a permanent storage. In addition to including a computer program that can be used to complete the direct memory access controller task management method executed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 221 may further include a computer program that can be used to complete other specific tasks.
[0083] Furthermore, an embodiment of the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the above-disclosed direct memory access controller task management method is implemented.
[0084] For the specific steps of the method, reference may be made to the corresponding contents disclosed in the aforementioned embodiments, which will not be described in detail here.
[0085] The various embodiments in this application are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.
[0086] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.
[0087] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
[0088] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.
[0089] The above is a detailed introduction to a direct memory access controller task management method, device, equipment, and storage medium provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, according to the ideas of the present application, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present application.
Claims
1. A direct memory access controller task management method, characterized in that: include: The tasks issued by different processor cores are stored in the first cache according to the priority, and it is determined whether the first target task in the second cache meets the processing condition; wherein the first cache stores the tasks issued by the processor core, and the second cache stores the tasks in the issued tasks that have a memory access conflict with the task currently being processed, and meeting the processing condition indicates that the memory access conflict is ended; If the first target task in the second cache meets the processing condition, the first target task is allocated to a corresponding direct memory access controller based on a preset rule, and the first target task is processed by the corresponding direct memory access controller; If the first target task in the second cache does not meet the processing conditions, the second target task is obtained from the first cache according to the priority. If there is no memory access conflict between the second target task and the task currently being processed, the second target task is processed by an adapted direct memory access controller, and then the process jumps to the step of determining whether the first target task in the second cache meets the processing conditions.
2. The direct memory access controller task management method according to claim 1, characterized in that: The allocating the first target task to a corresponding direct memory access controller based on a preset rule includes: Determining load factor components corresponding to the current task management scenario, and obtaining a load factor according to the load factor components; The load factor components include one or two of a task-related factor and a processing capacity-related factor, wherein the task-related factor is obtained based on the number and length of tasks being processed or to be processed by each of the direct memory access controllers, and the processing capacity-related factor is obtained based on the number of transmission channels of each of the direct memory access controllers, the transmission rate of each transmission channel, and the maximum number of outstanding requests of each of the transmission channels; According to the transmission requirements of the current task management scenario for each direct memory access controller, configuring the load weight of each load factor component in the load factor; According to the load factor components and the corresponding load weights, a direct memory access controller that is compatible with the first target task is selected from each of the direct memory access controllers, and the first target task is allocated to the compatible direct memory access controller.
3. The direct memory access controller task management method according to claim 2, characterized in that: The determining of the load factor components corresponding to the current task management scenario includes: If the current task management scenario is a real-time task processing scenario, the load factor components are the task-related factors; wherein the task response time of the real-time task processing scenario is less than a first threshold, and the task processing time is less than a second threshold.
4. The direct memory access controller task management method according to claim 2, characterized in that: The determining of the load factor components corresponding to the current task management scenario includes: If the current task management scenario is a data transmission intensive scenario, the load factor components are determined as the task-related factors and the processing capacity-related factors; the data transmission rate of the data transmission intensive scenario is greater than the third threshold, and the total data transmission amount is greater than the fourth threshold.
5. The direct memory access controller task management method according to claim 2, characterized in that: The step of selecting a direct memory access controller that matches the first target task from each of the direct memory access controllers according to the load factor components and the corresponding load weights includes: For any of the direct memory access controllers, determining a product value of the load factor component and the corresponding load weight, and using the product value as a load evaluation value of the direct memory access controller; The direct memory access controller having the lowest load evaluation value is used as the direct memory access controller adapted to the first target task.
6. The direct memory access controller task management method according to claim 1, characterized in that: Also includes: For any of the direct memory access controllers, transmission information of each of the transmission channels is obtained, and the state of the direct memory access controller is monitored according to the transmission information; wherein the transmission information includes task description information and task state information.
7. The direct memory access controller task management method according to any one of claims 1 to 6, characterized in that: After acquiring the second target task from the first cache according to the priority, the method further includes: If there is a memory access conflict between the second target task and the task currently being processed, the second target task is transferred from the first cache to the second cache, and then the process jumps to the step of determining whether the first target task in the second cache meets the processing condition.
8. A direct memory access controller task management device, characterized in that: include: The task storage module is used to store the tasks issued by different processor cores into the first cache according to the priority, and judge whether the first target task in the second cache meets the processing condition; wherein the first cache stores the tasks issued by the processor core, and the second cache stores the tasks in the issued tasks that have a memory access conflict with the task currently being processed, and meeting the processing condition indicates that the memory access conflict is ended; a conflicting task processing module, configured to allocate the first target task to a corresponding direct memory access controller based on a preset rule if the first target task in the second cache meets a processing condition, and process the first target task through the corresponding direct memory access controller; A task hierarchical processing module is used to obtain the second target task from the first cache according to the priority if the first target task in the second cache does not meet the processing conditions, and if there is no memory access conflict between the second target task and the task currently being processed, process the second target task through an adapted direct memory access controller, and then jump to the step of determining whether the first target task in the second cache meets the processing conditions.
9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the direct memory access controller task management method according to any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that: Used to store a computer program; wherein, when the computer program is executed by a processor, the direct memory access controller task management method according to any one of claims 1 to 7 is implemented.