XDMA-based random trigger type data stream transmission method and device

Abstract

The invention provides a random trigger type data stream transmission method and device based on XDMA, and the method comprises the steps: distributing a DDR SDRAM space of a board card, and obtaining a data record storage region for storing data records generated by the board card in each triggering event and a shared control word storage region for storing control word information, after an upper computer controls to start data acquisition, an XDMA of a board card writes control word information into a shared control word storage area based on a preset interruption period to generate periodic PCIe interruption, and after the board card generates the PCIe interruption, the upper computer receives the PCIe interruption in time and responds to the PCIe interruption in time to read the control word information of the shared control word storage area, so that the control word information of the shared control word storage area is read. And on the basis of the control word information of the shared control word storage area, corresponding data records are read in the DDR SDRAM space.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a random triggered data stream transmission method and device based on XDMA. Background Art

[0002] XDMA (Xilinx's DMA / Bridge Subsystem for PCI Express) is a data transfer engine designed specifically for the PCIe bus launched by Xilinx. It encapsulates the PCIe protocol and provides a simplified API interface, making data transfer between FPGA and host more intuitive and efficient.

[0003] At present, for boards based on PCIe interface, the XDMA solution is basically adopted in FPGA logic software. This is mainly because XDMA provides an efficient and flexible data transmission method that can meet the needs of complex application scenarios such as large data volume and low latency.

[0004] However, the previous XDMA generates PCIe interrupts based on the amount of data. The FPGA will trigger the PCIe interrupt only when the amount of sampled data reaches a certain value. Once the amount of data does not meet the conditions for triggering the interrupt, even if there are only a few bytes of sampled data missing, the stored valid records cannot be uploaded to the host computer. In random trigger applications, in a certain period of time, a large amount of sampled data records may be generated suddenly, or only one sampled data record may be generated. The previous XDMA is difficult to cope with data transmission in similar scenarios, and it is difficult for the host computer to clearly understand the status information of the valid data records currently stored in the board, so that the host computer cannot read the data record information currently stored in the board in time. Summary of the invention

[0005] In view of this, the purpose of this application is to provide a random triggered data stream transmission method and device based on XDMA, which stores the data records generated by the board for each trigger event through the data record storage area in the DDR SDRAM space of the board, and stores the control word information in the shared control word storage area, so as to generate and respond to interrupts, and read the corresponding data records based on the control word information, so that the collection records of small data volumes can be uploaded to the host computer more flexibly, and there is no need to generate a PCIe interrupt only when the collected data volume reaches a certain value, thereby improving the real-time and integrity of the data, and can be applied to random trigger collection scenarios. At the same time, the host computer can clearly obtain more detailed board storage data record status information through the control word information.

[0006] In a first aspect, an embodiment of the present application provides a random triggered data stream transmission method based on XDMA, which is applied to a random triggered data stream transmission device, wherein the random triggered data stream transmission device includes a host computer and a board; the board has XDMA and DDR SDRAM space, and the DDR SDRAM space represents a DDR address space; the method includes: Allocate the DDR SDRAM space of the board to obtain a data record storage area for storing the data record generated by the board for each trigger event and a shared control word storage area for storing control word information; wherein the data record storage area is used to store the data record generated by the board for each trigger event, and is stored in sequence according to the DDR storage address of the board until the data record fills the area, and then stops storing; the shared control word storage area is used to store the control word information of the data record written by the current board; After the host computer controls to start data collection, the XDMA of the board writes the control word information into the shared control word storage area based on a preset interrupt cycle to generate a periodic PCIe interrupt; After the board generates a PCIe interrupt, the host computer promptly receives the PCIe interrupt and promptly responds to the PCIe interrupt to read the control word information in the shared control word storage area, and promptly clears the interrupt, and reads the corresponding data record in the DDR SDRAM space based on the control word information in the shared control word storage area.

[0007] In a possible implementation manner, storing the data records generated by the board for each triggering event includes: For a data record generated by the board in response to a trigger event, the XDMA of the board stores the data record into the DDR SDRAM space; For the data records generated by the board for the next trigger event, the XDMA of the board writes the data records incrementally into the DDR SDRAM space in sequence, so as to sequentially store the data records generated by each trigger event into the DDR SDRAM space.

[0008] In a possible implementation, the method further includes: After the host computer controls and starts data collection, the board monitors the trigger events that meet the preset trigger conditions; When the trigger event meets the trigger condition, the host computer collects data records of corresponding length based on the pre-configured data collection length, and writes the data records into the DDR SDRAM space of the board.

[0009] In a possible implementation, the method further includes: Write a first data record to a first starting address of the DDR SDRAM space of the board, and write a second data record to a second starting address of the DDR SDRAM space; wherein the difference between the first starting address and the second starting address is the data length of each data record; and the interval between the first starting address and the second starting address is the shortest time interval between two random trigger events configured by the host computer; In response to writing the target data record to the target start address of the DDR SDRAM space, the control word information is written to the shared control word storage area, and a corresponding PCIe interrupt signal is generated to generate a PCIe interrupt.

[0010] In a possible implementation manner, the host computer receives the PCIe interrupt in a timely manner, and responds to the PCIe interrupt in a timely manner to read the control word information of the shared control word storage area, and clears the interrupt in a timely manner, and reads the corresponding data record in the DDR SDRAM space based on the control word information of the shared control word storage area, including: After receiving the PCIe interrupt, the host computer immediately clears the PCIe interrupt and generates a corresponding semaphore to notify the interrupt response thread of the host computer; In the interrupt response thread, the host computer reads the control word information from the shared control word storage area in the DDR SDRAM space, and parses the control word information to obtain the data record currently stored in the DDR SDRAM space of the board.

[0011] In a possible implementation, the method further includes: The host computer obtains necessary data record information stored in the current board based on the control word information; wherein the necessary data record information at least includes data record, total length of all data records and the starting address of the last data record stored in the DDR SDRAM space; The host computer calculates the starting address of each data record in the DDRSDRAM space of the board and the total length of all data records based on the necessary information of the data record, and moves all data records through one or more DMAs.

[0012] In a possible implementation manner, the control word information is stored in a shared control word storage area in the DDR SDRAM space of the board; The starting address and size of the DDR SDRAM space are configured by the host computer; the shared control word storage area is the last continuous area of ​​the DDR SDRAM space; The board has read and write permissions to the shared control word storage area, and the host computer has read permissions to the shared control word storage area.

[0013] In a possible implementation manner, the board corresponds to a control program; and the method further includes: When the host computer controls and starts data collection, the shared control word storage area is cleared through the control program of the board; Before the board generates a PCIe interrupt, the board updates the control word information; When the host computer responds to the PCIe interrupt, the control word information of the shared control word storage area is read by the host computer.

[0014] In a possible implementation, the method further includes: In response to the fact that the DDR SDRAM space of the board contains data records that have not been read by the host computer, the host computer continuously reads the unread data records through DMA.

[0015] In a second aspect, an embodiment of the present application further provides a random triggered data stream transmission device based on XDMA, wherein the random triggered data stream transmission device based on XDMA includes a host computer and a board; the board has XDMA and DDR SDRAM space, and the DDR SDRAM space represents a DDR address space; The XDMA-based random triggered data stream transmission device is used to execute the XDMA-based random triggered data stream transmission method provided by the first aspect embodiment.

[0016] The embodiment of the present application provides a random triggered data stream transmission method and device based on XDMA, which allocates the DDR SDRAM space of the board to obtain a data record storage area for storing the data records generated by the board for each trigger event and a shared control word storage area for storing control word information. After the host computer controls to start data acquisition, the XDMA of the board writes the control word information to the shared control word storage area based on a preset interrupt cycle to generate a periodic PCIe interrupt. After the board generates a PCIe interrupt, the host computer receives the PCIe interrupt in time and responds to the PCIe interrupt in time to read the control word information in the shared control word storage area, clear the interrupt in time, and read the corresponding data record in the DDR SDRAM space based on the control word information in the shared control word storage area. This application uses the data record storage area in the DDR SDRAM space of the board to store the data records generated by each trigger event board, and the shared control word storage area stores the control word information, so as to generate and respond to interrupts, and read the corresponding data records based on the control word information, which can more flexibly upload the small amount of data collection records to the host computer, and does not need to generate PCIe interrupts when the amount of collected data reaches a certain value, thereby improving the real-time and integrity of the data, and can be applied to random trigger collection scenarios. At the same time, the host computer can clearly obtain more detailed board storage data record status information through the control word information.

[0017] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 is a flow chart of a random triggered data stream transmission method based on XDMA provided in an embodiment of the present application; Figure 2 This is a schematic diagram of DDR SDRAM space allocation; Figure 3 It is a schematic diagram of the interaction between trigger records and control word messages between Card / DDR / Host; Figure 4 is a schematic diagram of the shared control word description. DETAILED DESCRIPTION

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of this application. It should be understood that the accompanying drawings in this application are only for the purpose of illustration and description, and are not used to limit the protection scope of this application. In addition, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate the operations implemented according to some embodiments of this application. It should be understood that the operations in the flowchart may not be implemented in sequence, and steps without a logical context relationship may be reversed or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart or remove one or more operations from the flowchart under the guidance of the content of this application.

[0021] In addition, the described embodiments are only a part of the embodiments of this application, rather than all of the embodiments. The components of the embodiments of this application usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but only represents the selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative efforts belong to the scope of protection of this application.

[0022] It should be noted that the term "including" will be used in the embodiments of this application to indicate the existence of the features stated thereafter, but does not exclude adding other features.

[0023] Considering that XDMA (Xilinx’s DMA / Bridge Subsystem for PCI Express) is a data transfer engine specifically designed for the PCIe bus launched by Xilinx. It encapsulates the PCIe protocol and provides a simplified API interface, making the data transfer between the FPGA and the host more intuitive and efficient. Currently, for boards based on the PCIe interface, the XDMA solution is basically adopted in the FPGA logic software, mainly because XDMA provides an efficient and flexible data transfer method, which can meet the requirements of complex application scenarios such as large data volume and low latency.

[0024] However, the previous XDMA generates PCIe interrupts based on the amount of data. The FPGA will trigger the PCIe interrupt only when the amount of sampled data reaches a certain value. Once the amount of data does not meet the conditions for triggering the interrupt, even if there are only a few bytes of sampled data missing, the stored valid records cannot be uploaded to the host computer. In random trigger applications, in a certain period of time, a large amount of sampled data records may be generated suddenly, or only one sampled data record may be generated. The previous XDMA is difficult to cope with data transmission in similar scenarios, and it is difficult for the host computer to clearly understand the status information of the valid data records currently stored in the board, so that the host computer cannot read the data record information currently stored in the board in time.

[0025] In response to this problem, the present application provides a random triggered data stream transmission method and device based on XDMA, which stores the data records generated by the board for each trigger event through the data record storage area in the DDR SDRAM space of the board, and stores the control word information in the shared control word storage area, so as to generate and respond to interrupts, and read the corresponding data records based on the control word information, so that the collection records of small data volumes can be uploaded to the host computer more flexibly, and there is no need to generate a PCIe interrupt only when the collected data volume reaches a certain value, thereby improving the real-time and integrity of the data, and can be applied to random trigger collection scenarios. At the same time, the host computer can clearly obtain more detailed board storage data record status information through the control word information.

[0026] Figure 1 It is a flow chart of a random triggered data stream transmission method based on XDMA provided in an embodiment of the present application. The random triggered data stream transmission method based on XDMA in an embodiment of the present application is applied to a random triggered data stream transmission device. The random triggered data stream transmission device includes a host computer and a board; the board has XDMA and DDR SDRAM space, and the DDR SDRAM space represents the DDR address space; the host computer and the board are connected, for example, by communication connection, physical connection, etc.

[0027] like Figure 1 As shown, the random triggered data stream transmission method based on XDMA in the embodiment of the present application may specifically include: S101, allocating the DDR SDRAM space of the board to obtain a data record storage area for storing data records generated by the board for each trigger event and a shared control word storage area for storing control word information.

[0028] S102: After the host computer starts to collect data, the XDMA of the board writes the control word information into the shared control word storage area based on a preset interruption period to generate a periodic PCIe interruption.

[0029] S103. After the board generates a PCIe interrupt, the host computer promptly receives the PCIe interrupt and promptly responds to the PCIe interrupt to read the control word information in the shared control word storage area, and promptly clear the interrupt, and read the corresponding data record in the DDR SDRAM space based on the control word information in the shared control word storage area.

[0030] In the above-mentioned random triggered data stream transmission method based on XDMA, the data record storage area in the DDR SDRAM space of the board stores the data record generated by the board for each trigger event, and the shared control word storage area stores the control word information, so as to generate and respond to interrupts, and read the corresponding data record based on the control word information, which can more flexibly upload the small amount of data collection records to the host computer, and does not need to generate a PCIe interrupt when the amount of collected data reaches a certain value, thereby improving the real-time and integrity of the data, and can be applied to random trigger collection scenarios. At the same time, the host computer can clearly obtain more detailed board storage data record status information through the control word information.

[0031] The above exemplary steps of the embodiment of the present application are described below with reference to specific examples: S101, allocating the DDR SDRAM space of the board to obtain a data record storage area for storing data records generated by the board for each trigger event and a shared control word storage area for storing control word information.

[0032] In the embodiment of the present application, the data record storage area is used to store the data records generated by the board for each trigger event, and is stored in sequence according to the DDR storage address of the board until the data record fills the area, then stops storing (stops recording), or records in a loop from the DDR start address; the shared control word storage area is used to store the control word information of the data record written by the current board, and only stores the control word information, but does not store the data record; the DDR SDRAM space of the board is allocated to obtain a data record storage area for storing the data records generated by the board for each trigger event and a shared control word storage area for storing the control word information. Among them, the data record storage area and the shared control word storage area each occupy an independent DDR address space and do not overlap; the control word information includes at least the data length of a single data record, the pre-trigger length, the number of trigger events, the total length of the trigger event data record, and the DDR start address (Start_addr) of the data record most recently written to the DDR SDRAM space (DDR for short). For example, Figure 2 As shown, the DDR SDRAM space is allocated as a data record storage area and a shared control word (Ctrl word) storage area, that is, Figure 2The sampled data area and control word area shown in the figure, the left side 1 to N represent the N data records in the data record (represented by Rec) storage area, namely the sampled data, the right side represents the shared control word storage area, Rec length represents the total length of the data record, CW (Ctrl word, control word) length represents the control word length, and Start_addr represents the DDR starting address.

[0033] It should be noted that the control word information is stored in the shared control word storage area in the DDR SDRAM space of the board; the starting address and size of the DDR SDRAM space are configured by the host computer; the shared control word storage area is the last continuous area of ​​the DDR SDRAM space; the board has read and write permissions to the shared control word storage area, and the host computer has read permissions to the shared control word storage area. That is, for the shared control word storage area, the host computer only has read permissions, not write permissions; the board XDMA has write and read permissions to this area.

[0034] Optionally, when storing the data records generated by the board for each trigger event, for the data records generated by the board for a trigger event, the XDMA of the board stores the data records in the DDR SDRAM space of the board; for the data records generated by the board for the next trigger event, the XDMA of the board writes the data records in sequence according to the DDR SDRAM space (DDR address space) of the board, so as to sequentially store the data records generated by each trigger event in the DDR SDRAM space of the board. It can be understood that after the trigger processing starts, the trigger event will form a data record, and the XDMA will store the acquisition record in the DDR SDRAM space of the board. The data record formed by the next trigger event will be written in sequence according to the DDR address space, and so on, and the data record formed by each trigger event will be sequentially stored in the DDR SDRAM space of the board.

[0035] S102, after the host computer controls to start data collection, the XDMA of the board writes the control word information into the shared control word storage area based on a preset interrupt period to generate a periodic PCIe interrupt.

[0036] In the embodiment of the present application, the interruption period is configured by the host computer, for example, 100ms. After the host computer controls and starts data acquisition, the board XDMA writes the control word information to the shared control word storage area based on the interruption period to generate a periodic PCIe interrupt for subsequent processing. For example, the board XDMA periodically writes the control word information to the shared control word storage area and then generates a PCIe interrupt. For example, Figure 3As shown, for example, when the PCIe interrupt cycle is set to 100ms, within 100ms, the Card side (representing the board) and the Host side (representing the host computer) can normally process the interrupt handshake operation process, where Rd represents Read, Wr represents Write, Wr Rec represents read trigger record, i.e. data record, Wr CW represents write control word, Rd Rec represents write trigger record, i.e. data record, Read CW represents read control word, PCIe INT (Interrupt) represents PCIe interrupt generation, and INT clear represents interrupt clearing. In addition, within 100ms, the maximum amount of stored data will not cause the data in the DDR to be overwritten. If the trigger acquisition of data record is completed within 1 second, the example of the data record storage area and the address space for storing control word information is shown in Table 1 below. At this time, since there are 9 PCIe interrupts in 1 second, the shared control word address space of the Card side will be updated 9 times, and the Host side will obtain the control word information from the shared control word address space after receiving each PCIe interrupt.

[0037] Table 1

[0038] It should be noted that before an interrupt is generated, the total amount of data recorded, the number of trigger events, the address of the most recent trigger event written into the DDR and other information will be written into the shared control word storage area of ​​the DDR.

[0039] It should also be noted that after the trigger event is processed, XDMA will periodically generate interrupts, and the interrupt period needs to be determined by calculation. Specifically, the interrupt period of the XDMA interrupt (PCIe interrupt) generated by the Card is configured by the host computer and is not related to whether a trigger event occurs during the interrupt period. An extreme example is that there is no trigger time that meets the trigger condition between two PCIe interrupts. Assuming that the host computer sets the PCIe interrupt period to 100ms, after the acquisition starts, the Card will periodically generate PCIe interrupts at a time of 100ms.

[0040] S103, after the board generates a PCIe interrupt, the host computer promptly receives the PCIe interrupt and promptly responds to the PCIe interrupt to read the control word information in the shared control word storage area, and promptly clears the interrupt, and reads the corresponding data record in the DDR SDRAM space based on the control word information in the shared control word storage area.

[0041] In the embodiment of the present application, after the board card generates a PCIe interrupt in step S102, the host computer promptly receives the PCIe interrupt and promptly responds to the PCIe interrupt to read the control word information in the shared control word storage area, promptly clears the interrupt, and based on the control word information in the shared control word storage area, reads the corresponding data record in the DDR SDRAM space. That is, after the host computer obtains the control word information, it initiates an operation to read the data record from the board card DDR. For example, as Figure 3 shown. Specifically, the host computer promptly receives the PCIe interrupt through the XDMA driver.

[0042] It should be noted that when the host computer promptly receives the PCIe interrupt, promptly responds to the PCIe interrupt to read the control word information in the shared control word storage area, promptly clears the interrupt, and based on the control word information in the shared control word storage area, reads the corresponding data record in the DDR SDRAM space, after the host computer receives the PCIe interrupt, it immediately clears the PCIe interrupt and generates a corresponding semaphore to notify the interrupt response thread of the host computer; in the interrupt response thread, the host computer reads the control word information from the shared control word storage area in the DDR SDRAM space and parses the control word information to obtain the data record that has been stored in the DDR SDRAM space of the current board card.

[0043] Specifically, after the Card generates a PCIe interrupt, the Host XDMA driver will promptly receive the interrupt event and promptly respond to the interrupt (host int response). Generally speaking, after the Host receives the interrupt, it immediately performs an interrupt clearing operation on the interrupt and generates a semaphore to notify the) interrupt response thread. In the Host interrupt response thread, the Host first initiates an operation to read the control word information from the shared control word space in the Card DDR. The Host parses the control word information to obtain the acquisition record information that has been stored in the current Card-side DDR. When there are unread data records stored in the Card DDR that the Host side has not read, the Host continuously reads the valid unread data records to the Host side through DMA.

[0044] The random trigger-based data stream transmission method based on XDMA provided by the embodiments of the present application allocates the DDR SDRAM space of the board card to obtain a data record storage area for storing the data records generated by the board card for each trigger event and a shared control word storage area for storing control word information. After the host computer controls the start of data acquisition, the XDMA of the board card writes the control word information into the shared control word storage area based on a preset interrupt period to generate periodic PCIe interrupts. After the board card generates a PCIe interrupt, the host computer promptly receives the PCIe interrupt and promptly responds to the PCIe interrupt to read the control word information in the shared control word storage area, promptly clear the interrupt, and based on the control word information in the shared control word storage area, read the corresponding data records in the DDR SDRAM space. In the random trigger-based data stream transmission method based on XDMA of the present application, the data record storage area in the DDR SDRAM space of the board card stores the data records generated by the board card for each trigger event, and the shared control word storage area stores the control word information, thereby generating and responding to interrupts, and reading the corresponding data records based on the control word information, which can more flexibly upload the acquisition records of small data volumes to the host computer without generating PCIe interrupts only when the acquired data volume reaches a certain value, improving the timeliness and integrity of the data, and being applicable to random trigger acquisition scenarios. At the same time, through the control word information, the host computer can clearly obtain more detailed status information of the data records stored on the board card.

[0045] Further, after the host computer controls the start of data acquisition, the board card monitors trigger events that meet the preset trigger conditions; when a trigger event meets the trigger conditions, the host computer acquires a data record of a corresponding length based on the pre-configured data acquisition length and writes the data record into the DDR SDRAM space of the board card. It should be noted that for each trigger event, the data length of the data record can be set by the host computer. For example, if the ADC sampling rate of the board card is 1 GS / s and the data bit width of each sampling point is 16 bit, the data duration of the trigger record can be set to 1 μs to 4 μs, and this time range can be accurate to 0.5 μs. Since the number of sampling points corresponding to a single channel for 1 μs is 1 μs / 0.5 ns = 2000, 2000 sample points, and each sample point is 16 bit, the data volume is 4000 Bytes, that is, 4000 Bytes, which is the data acquisition length.

[0046] It should be noted that after the host computer controls the start of data acquisition, the Card monitors trigger events that meet the trigger conditions. Once the trigger conditions are met, a certain length of data record is acquired and written into the Card DDR. The length of the data acquired for each trigger is configured by the host computer.

[0047] Furthermore, the first data record is written to the first starting address of the DDR SDRAM space of the board, and the second data record is written to the second starting address of the DDR SDRAM space; in response to writing the target data record to the target starting address of the DDR SDRAM space, the control word information is written to the shared control word storage area, and a corresponding PCIe interrupt signal is generated to generate a PCIe interrupt. Among them, the difference between the first starting address and the second starting address is the data length of each data record; the interval time between the first starting address and the second starting address is the shortest time interval between two random trigger events configured by the host computer; the target data record represents the Nth data record, that is, the last data record written before the interrupt is generated, and the target starting address represents the Nth starting address, that is, the last starting address written before the interrupt is generated. For example, Figure 3 shown.

[0048] For example, Figure 2 As shown, the Rec1 data record is written to the starting address addr1 of the DDR address space, and the Rec2 data record is written to the starting address addr2 of the DDR address space. The difference between addr1 and addr2 is generally set to the data length of each data record. The interval between Rec1 and Rec2, that is, the shortest time interval between two random triggers, is configured by the host computer. When RecN is written to the starting address addrN of the DDR, the time condition for the generation of the PCIe interrupt, that is, the interrupt cycle, is just reached in the time dimension (whether RecN is generated does not affect the generation of the PCIe interrupt). The control word information needs to be written into the DDR SDRAM space, specifically the shared control word storage area, and then the PCIe interrupt signal is generated to the host computer.

[0049] Furthermore, the host computer obtains the necessary data record information stored in the current board based on the control word information; the host computer calculates the starting address of each data record in the DDR SDRAM space of the board and the total length of all data records based on the necessary data record information, and moves all data records through one or more DMAs. The necessary data record information at least includes the data record, the total length of all data records, and the starting address of the last data record stored in the DDR SDRAM space.

[0050] It should be noted that since the content in the control word information can indicate necessary information such as the data records stored in the current Card DDR, the total length of the data records, the DDR address of the most recent data record, etc., this application can clearly obtain more detailed board storage data record status information.

[0051] Specifically, for example, at the first PCIe interrupt response, the Host can obtain N data records stored in the current Card through the control word information. The total length of these N data records and the starting address of the last RecN stored in the DDR can all be obtained from the control word information. The Host can calculate the starting address of the N data records in the Card DDR and the total length of the N data records, and then initiate DMA data movement to move the N records to the Host through one or more DMAs. The Host needs to cache and record the necessary information such as the number of data records in this interrupt response operation, the start and end positions of the read DDR address space, etc., for use in the next interrupt response. Continuing, for example, at the second PCIe interrupt response, another M data records are stored in the Card DDR. As described above, the Host can obtain the current total number of data records from the shared control word message as N+M, and the address of the last data record RecN+M stored in the DDR starts at addrN+M. The host side combines the operation record information of the first interrupt response, and it is clear that the host side needs to read a total of M data records from the DDR address addrN+1 to addrN+M address space, instead of reading all N+M data records. Because in the first interrupt response, the first N data records have been read. The reading process of subsequent data records is similar, and this application will not go into details.

[0052] It should be noted that the board corresponds to the control program; when the host computer controls to start data acquisition, the shared control word storage area is cleared through the control program of the board; before the board generates a PCIe interrupt, the board updates the control word information; when the host computer responds to the PCIe interrupt, the control word information in the shared control word storage area is read through the host computer.

[0053] Further, in response to the fact that the DDR SDRAM space of the board contains data records that are not read by the host computer, the host computer continuously reads the unread data records through DMA.

[0054] The control word information of the present application, i.e., the shared control word information, is described in detail below, and is stored in the fixed starting address area of ​​the Card-side DDR, i.e., the shared control word storage area. The starting address of the address space is configured by the host computer, and the size of the address space is configured by the host computer. Generally, the last continuous area of ​​the Card-side DDR SDRAM space can be configured as the shared control word storage area. Since the amount of data that the host computer moves from the Card-side DDR at a time has a minimum data amount limit, the shared control word space should at least meet 4096Bytes without wasting DDR storage space. (Address alignment operation needs to be considered). For the shared control word space (i.e., the shared control word storage area), the Card side has the authority to read and write the area; the Host side only has the read permission but not the write permission. The Card side needs to complete the clearing operation on the shared control word space when starting data acquisition. Before the Card side generates a PCIe interrupt, the Card side updates the control word information. When the Host side responds to the PCIe interrupt, the Host side reads out the control word information.

[0055] In this way, the write operation and the read operation of the shared control word address space are separated in time, avoiding the occurrence of simultaneous reading and writing, thereby ensuring the correctness of the control word information obtained by the Host.

[0056] To continue, since the effective information actually used by the shared control word occupies a small number of bytes, the present application exemplarily proposes the following shared control data structure, which occupies a total of 16 32-bit DDR storage spaces. The data structure of the shared control word is described as follows: typedef struct{ U32magicCode; / *Message code: defined as a constant, such as 0x5555AAAA* / U32intCnt; / *Interrupt counter: Each time XDMA generates an interrupt, the counter increases by 1* / U32trigCnt; / *Trigger count counter: Each time an external trigger or channel triggers, the counter increases by 1* / U32preTrigLen; / *Pre-trigger length: unit Byte * / U32singleRecLen; / *Single trigger sampling data record length: Unit: Byte* / U32totalRecLen_Hi; / *Total sampling data record length: unit Byte, high 32 bits* / U32totalRecLen_Lo; / *Total sampling data record length: unit Byte, lower 32 bits * / U32curRecDDRaddr_Hi; / *The address where the most recent data record is stored in DDR, high 32 bits, byte address* / U32curRecDDRaddr_Lo; / *The address where the most recent data record is stored in DDR, lower 32 bits, byte address* / U32resv[7]; / *Reserved field* / }PCIeIntCtrlWord_t; Further, the shared control word is described as Figure 4 shown.

[0057] It should be noted that in a short period of time, when there are dense random trigger events, the maximum amount of data that can be stored in the DDR SDRAM space can be used. Once the DDR SDRAM space is full, it will no longer respond to subsequent trigger event records. Once the trigger storage is met, the XDMA will periodically generate a hardware interrupt. The generation of the interrupt signal has nothing to do with the cumulative number of trigger events.

[0058] Therefore, this application is based on user scheduling (initiated by the host computer, the user develops the host computer software, and implements different implementation methods), through the interrupt handshake mechanism, using the shared control word between the FPGA and the host computer as a message communication channel, to achieve FPGA random trigger event data record upload to the host computer. Compared with the previous interrupt handshake mechanism based on data volume to transmit data, the host computer can clearly obtain more detailed board storage data record status information through control word information, and can more flexibly upload small data volume collection records to the host computer, and can be applied to random trigger collection scenarios. At the same time, the PCIe interrupt handshake mechanism continues to be used to ensure that the shared control word message can be correctly obtained by the host computer.

[0059] It should be noted that the random triggered data stream transmission method based on XDMA of the present application is a triggered stream data acquisition and transmission method based on XDMA, that is, a random triggered data stream processing method based on XDMA.

[0060] The embodiment of the present application also provides a random triggered data stream transmission device based on XDMA, the random triggered data stream transmission device includes a host computer and a board; the board has XDMA and DDR SDRAM space, and the DDR SDRAM space represents the DDR address space. The random triggered data stream transmission device based on XDMA is used to execute the random triggered data stream transmission method based on XDMA.

[0061] The XDMA-based random triggered data stream transmission device provided in the embodiment of the present application allocates the DDR SDRAM space of the board to obtain a data record storage area for storing the data records generated by the board for each trigger event and a shared control word storage area for storing control word information. After the host computer controls to start data acquisition, the XDMA of the board writes the control word information to the shared control word storage area based on a preset interrupt cycle to generate a periodic PCIe interrupt. After the board generates a PCIe interrupt, the host computer promptly receives the PCIe interrupt and promptly responds to the PCIe interrupt to read the control word information in the shared control word storage area, and promptly clears the interrupt, and reads the corresponding data record in the DDR SDRAM space based on the control word information in the shared control word storage area. The random triggered data stream transmission device based on XDMA of the present application stores the data records generated by the board for each trigger event through the data record storage area in the DDR SDRAM space of the board, and stores the control word information in the shared control word storage area, so as to generate and respond to interrupts, and read the corresponding data records based on the control word information, so as to upload the small amount of data collection records to the host computer more flexibly, and it is not necessary to generate a PCIe interrupt only when the amount of collected data reaches a certain value, thereby improving the real-time and integrity of the data, and can be applied to random trigger collection scenarios. At the same time, the host computer can clearly obtain more detailed board storage data record status information through the control word information.

[0062] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application. In the several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0063] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0064] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0065] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the deployment method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks, or optical disks.

[0066] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A random triggered data stream transmission method based on XDMA, characterized in that: The invention is applied to a random triggered data stream transmission device, the random triggered data stream transmission device comprises a host computer and a board; the board has XDMA and DDR SDRAM space, the DDR SDRAM space represents the DDR address space; the method comprises: Allocate the DDR SDRAM space of the board to obtain a data record storage area for storing the data record generated by the board for each trigger event and a shared control word storage area for storing control word information; wherein the data record storage area is used to store the data record generated by the board for each trigger event, and is stored in sequence according to the DDR storage address of the board until the data record fills the area, and then stops storing; the shared control word storage area is used to store the control word information of the data record written by the current board; After the host computer controls to start data collection, the XDMA of the board writes the control word information into the shared control word storage area based on a preset interrupt cycle to generate a periodic PCIe interrupt; After the board generates a PCIe interrupt, the host computer promptly receives the PCIe interrupt and promptly responds to the PCIe interrupt to read the control word information in the shared control word storage area, and promptly clears the interrupt, and reads the corresponding data record in the DDR SDRAM space based on the control word information in the shared control word storage area.

2. The random triggered data stream transmission method based on XDMA according to claim 1, characterized in that: The storing of data records generated by the board each time a triggering event occurs includes: For a data record generated by the board in response to a trigger event, the XDMA of the board stores the data record into the DDR SDRAM space of the board; For the data records generated by the board for the next trigger event, the XDMA of the board writes the data records incrementally into the DDR SDRAM space of the board in sequence, so as to sequentially store the data records generated by each trigger event into the DDR SDRAM space of the board.

3. The random triggered data stream transmission method based on XDMA according to claim 2, characterized in that: The method further comprises: After the host computer controls and starts data collection, the board monitors the trigger events that meet the preset trigger conditions; When the trigger event meets the trigger condition, the host computer collects data records of corresponding length based on the pre-configured data collection length, and writes the data records into the DDR SDRAM space of the board.

4. The random triggered data stream transmission method based on XDMA according to claim 3, characterized in that: The method further comprises: Write a first data record to a first starting address of the DDR SDRAM space of the board, and write a second data record to a second starting address of the DDR SDRAM space; wherein the difference between the first starting address and the second starting address is the data length of each data record; and the interval between the first starting address and the second starting address is the shortest time interval between two random trigger events configured by the host computer; In response to writing the target data record to the target start address of the DDR SDRAM space, the control word information is written to the shared control word storage area, and a corresponding PCIe interrupt signal is generated to generate a PCIe interrupt.

5. The random triggered data stream transmission method based on XDMA according to claim 4, characterized in that: The host computer receives the PCIe interrupt in time, and responds to the PCIe interrupt in time, so as to read the control word information of the shared control word storage area, clear the interrupt in time, and read the corresponding data record in the DDR SDRAM space based on the control word information of the shared control word storage area, including: After receiving the PCIe interrupt, the host computer immediately clears the PCIe interrupt and generates a corresponding semaphore to notify the interrupt response thread of the host computer; In the interrupt response thread, the host computer reads the control word information from the shared control word storage area in the DDR SDRAM space, and parses the control word information to obtain the data record currently stored in the DDR SDRAM space of the board.

6. The random triggered data stream transmission method based on XDMA according to claim 5, characterized in that: The method further comprises: The host computer obtains necessary data record information stored in the current board based on the control word information; wherein the necessary data record information at least includes data record, total length of all data records and the starting address of the last data record stored in the DDR SDRAM space; The host computer calculates the starting address of each data record in the DDR SDRAM space of the board and the total length of all data records based on the necessary information of the data record, and moves all data records through one or more DMAs.

7. The random triggered data stream transmission method based on XDMA according to claim 6, characterized in that: The control word information is stored in a shared control word storage area in the DDR SDRAM space of the board; The starting address and size of the DDR SDRAM space are configured by the host computer; the shared control word storage area is the last continuous area of ​​the DDR SDRAM space; The board has read and write permissions to the shared control word storage area, and the host computer has read permissions to the shared control word storage area.

8. The random triggered data stream transmission method based on XDMA according to claim 7, characterized in that: The board corresponds to a control program; the method further comprises: When the host computer controls and starts data collection, the shared control word storage area is cleared through the control program of the board; Before the board generates a PCIe interrupt, the board updates the control word information; When the host computer responds to the PCIe interrupt, the control word information of the shared control word storage area is read by the host computer.

9. The random triggered data stream transmission method based on XDMA according to claim 8, characterized in that: The method further comprises: In response to the fact that the DDR SDRAM space of the board contains data records that have not been read by the host computer, the host computer continuously reads the unread data records through DMA.

10. A random triggered data stream transmission device based on XDMA, characterized in that: The random triggered data stream transmission device based on XDMA includes a host computer and a board; the board has XDMA and DDR SDRAM space, and the DDR SDRAM space represents the DDR address space; The XDMA-based random triggered data stream transmission device is used to execute the XDMA-based random triggered data stream transmission method as described in any one of claims 1-9.

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