Communication method, device and equipment of consumable chip, and storage medium
By changing the analog method of the clock line and data line in the communication of the consumable chip and conducting multiple verifications, the problem of the consumable chip being easily cracked in the existing technology has been solved, and the security of the image forming equipment has been improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHUHAI PANTUM ELECTRONICS CO LTD
- Filing Date
- 2025-01-02
- Publication Date
- 2026-05-29
AI Technical Summary
Existing consumable chip communication verification is easily cracked, resulting in insufficient security for image forming equipment.
After the first communication verification is successful, the analog mode of the clock line and data line is changed to generate a second analog I2C interface, and a second communication verification is performed, increasing the difficulty of cracking.
This improves the security of consumable chips, prevents the use of counterfeit chips, and ensures data security.
Smart Images
Figure CN120029958B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of image forming technology, and more specifically to a communication method, apparatus, device, and storage medium for a consumable chip. Background Technology
[0002] Image forming equipment is equipped with a removable consumable unit to supply printing consumables, such as ink for inkjet printers or toner for laser printers. A consumable chip is typically installed on the housing of the consumable unit, storing consumable information such as consumable model, capacity, and remaining quantity. After the consumable unit is installed in the image forming equipment, the main control chip of the image forming equipment can communicate with the consumable chip to verify its security.
[0003] Existing main control chips and consumable chips typically communicate and verify each other using a fixed hardware internal integrated circuit (I2C) protocol. This method is easily cracked, which allows counterfeit consumable chips to pass verification, thus reducing the security of image forming equipment. Summary of the Invention
[0004] In view of this, this application provides a communication method, apparatus, device and storage medium for consumable chips, in order to solve the problem that the communication verification of consumable chips in the prior art is easily cracked, resulting in insufficient security.
[0005] In a first aspect, embodiments of this application provide a communication method for a consumable chip, applied to a main control chip, the method comprising:
[0006] The first communication verification process is performed on the consumable chip based on the first clock line and the first data line of the first analog I2C interface.
[0007] When the first communication verification is detected to be successful, the first clock line is converted to the second data line, and the first data line is converted to the second clock line to generate a second analog I2C interface;
[0008] The consumable chip performs a second communication verification process based on the second clock line and the second data line of the second analog I2C interface.
[0009] In an optional embodiment, the main control chip includes a first pin and a second pin, and the consumable chip includes a third pin and a fourth pin. Before the step of performing the first communication verification process on the consumable chip based on the first clock line and the first data line of the first analog I2C interface, the method further includes:
[0010] Based on the first simulation method, the first pin and the third pin are controlled to simulate the generation of the first clock line.
[0011] And control the second pin and the fourth pin to simulate the generation of the first data line;
[0012] The first simulated I2C interface is generated based on the first data line and the first clock line.
[0013] In an optional embodiment, before the step of controlling the first pin and the third pin to simulate generating the first clock line based on the first simulation method, and controlling the second pin and the fourth pin to simulate generating the first data line, the method further includes:
[0014] Retrieve the pre-stored first simulation method;
[0015] The first simulation method is sent to the consumable chip.
[0016] In an optional embodiment, the step of converting the first clock line to a second data line and the first data line to a second clock line to generate a second analog I2C interface when the first communication verification is detected as successful includes:
[0017] When the first communication verification is detected as successful, a second simulation method is determined based on the first simulation method;
[0018] Based on the second simulation method, the first pin and the third pin are controlled to simulate the generation of the second data line, and
[0019] The second pin and the fourth pin are controlled to simulate the generation of the second clock line;
[0020] The second simulated I2C interface is generated based on the second data line and the second clock line.
[0021] In an optional embodiment, the method further includes:
[0022] If the first communication verification fails, the consumable chip is determined to be a counterfeit chip; or,
[0023] If the first communication verification passes and the second communication verification fails, the consumable chip is determined to be a counterfeit chip; or,
[0024] When both the first and second communication verifications are passed, the consumable chip is determined to be a genuine chip.
[0025] In an optional embodiment, after the step of performing a second communication verification process on the consumable chip based on the second clock line and the second data line of the second analog I2C interface, the method further includes:
[0026] If it is determined that the consumable chip is a non-genuine chip, an error message will be displayed, indicating that the current consumable chip cannot communicate normally with the main control chip.
[0027] Secondly, embodiments of this application provide a communication method for a consumable chip, applied to a consumable chip, the method comprising:
[0028] When the main control chip triggers the first communication verification process, it performs the first communication verification with the main control chip based on the first clock line and the first data line of the first analog I2C interface.
[0029] When the main control chip triggers the second communication verification process, it converts the first clock line into a second data line, and the first data line into a second clock line to generate a second analog I2C interface.
[0030] The main control chip is subjected to a second communication verification based on the second clock line and the second data line of the second simulated I2C interface.
[0031] In an optional embodiment, the main control chip includes a first pin and a second pin, and the consumable chip includes a third pin and a fourth pin. Before performing the first communication verification with the main control chip based on the first clock line and the first data line of the first analog I2C interface when the main control chip triggers the first communication verification process, the method further includes:
[0032] Receive first agreed-upon data sent by the main control chip, wherein the first agreed-upon data includes a first simulation mode;
[0033] Based on the first simulation method, the third pin and the first pin are controlled to simulate the generation of the first clock line, and the fourth pin and the second pin are controlled to simulate the generation of the first data line;
[0034] The system receives first verification data sent by the main control chip, which is used to confirm that the first clock line and the second clock line can communicate normally.
[0035] In one optional embodiment, when the main control chip triggers the second communication verification process, converting the first clock line to a second data line and the first data line to a second clock line to generate a second analog I2C interface includes:
[0036] Receive second agreed-upon data sent by the main control chip, wherein the second agreed-upon data includes a second simulation mode;
[0037] Based on the second simulation method, the third pin and the first pin are controlled to simulate the generation of the second data line, and the fourth pin and the second pin are controlled to simulate the generation of the second clock line.
[0038] In one optional embodiment, the second communication verification of the main control chip based on the second clock line and the second data line of the second analog I2C interface includes:
[0039] After receiving the second verification data sent by the main control chip, the main control chip is subjected to a second communication verification based on the second clock line and the second data line.
[0040] Thirdly, embodiments of this application provide a communication device for a consumable chip, deployed on a main control chip, the communication device for the consumable chip comprising:
[0041] The first verification module is used to perform a first communication verification process on the consumable chip based on the first clock line and the first data line of the first analog I2C interface.
[0042] The control module is used to convert the first clock line to a second data line and the first data line to a second clock line when the first communication verification is successful, thereby generating a second analog I2C interface.
[0043] The second verification module is used to perform a second communication verification process on the consumable chip based on the second clock line and the second data line of the second simulated I2C interface.
[0044] Fourthly, embodiments of this application provide a communication device for a consumable chip, deployed on the consumable chip, the communication device for the consumable chip comprising:
[0045] The first communication verification module is used to perform first communication verification with the main control chip based on the first clock line and the first data line of the first analog I2C interface when the main control chip triggers the first communication verification process.
[0046] The simulation module is used to convert the first clock line into a second data line and the first data line into a second clock line to generate a second simulated I2C interface when the main control chip triggers the second communication verification process.
[0047] The second communication verification module is used to perform a second communication verification on the main control chip based on the second clock line and the second data line of the second simulated I2C interface.
[0048] Fifthly, embodiments of this application provide an electronic device, including a memory for storing computer program instructions and a processor for executing the program instructions, wherein when the computer program instructions are executed by the processor, the electronic device is triggered to execute the method described in any of the first aspects above.
[0049] In a sixth aspect, embodiments of this application provide a computer-readable storage medium including a stored program, wherein, when the program is executed, it controls the device where the computer-readable storage medium is located to perform the method described in any of the first aspects.
[0050] The solution provided in this application involves performing a first communication verification process on the consumable chip based on the first clock line and first data line of a first simulated I2C interface. When the first communication verification passes, the first clock line is converted to a second data line, and the first data line is converted to a second clock line, generating a second simulated I2C interface. A second communication verification process is then performed on the consumable chip based on the second clock line and second data line of the second simulated I2C interface. After the first communication verification passes, the clock line and data line are regenerated in a different simulation mode for a second communication verification, increasing the difficulty of cracking the communication verification and improving the security of the consumable chip. Attached Figure Description
[0051] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0052] Figure 1 A schematic diagram illustrating an example of a communication method for a consumable chip provided in an embodiment of this application;
[0053] Figure 2 A schematic diagram illustrating an example of a communication method for another consumable chip provided in an embodiment of this application;
[0054] Figure 3 A flowchart illustrating a communication method for a consumable chip provided in an embodiment of this application;
[0055] Figure 4a A schematic diagram illustrating an example of a communication method for another consumable chip provided in an embodiment of this application;
[0056] Figure 4b A schematic diagram illustrating an example of a communication method for another consumable chip provided in an embodiment of this application;
[0057] Figure 5A flowchart illustrating a communication method for a consumable chip provided in an embodiment of this application;
[0058] Figure 6 A flowchart illustrating another communication method for a consumable chip provided in an embodiment of this application;
[0059] Figure 7 A flowchart illustrating another communication method for a consumable chip provided in an embodiment of this application;
[0060] Figure 8 A schematic diagram of the structure of a communication device for a consumable chip provided in an embodiment of this application;
[0061] Figure 9 A schematic diagram of the structure of a communication device for a consumable chip provided in an embodiment of this application;
[0062] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0063] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.
[0064] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.
[0065] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.
[0066] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.
[0067] Common image forming equipment typically includes a removable consumable unit. This unit contains consumables (such as ink or toner), and a consumable chip on its casing records the consumable data. (See reference...) Figure 1An image forming apparatus may include an image forming device and a consumable device. The image forming device performs image forming-related operations to output a printed image. The consumable device consists of replaceable parts within the image forming apparatus. For example, when the image forming apparatus is an inkjet printer, laser printer, 3D printer, label printer, or dot matrix printer, the corresponding consumable device includes ink cartridges, toner cartridges, drum units, toner cartridges, ribbon cartridges, etc.
[0068] The consumable chip is an electronic device with storage function. When the consumable device is installed on the image forming device, the consumable chip is communicatively connected to the main control chip of the image forming device. This communication connection can be through contacts, antennas, or coils, and this application embodiment does not limit this. It should be noted that the consumable chip stores information including raw data, which is information related to the image forming device. For example, the raw data can include at least one of the following categories: (1) imaging control related parameters, such as printing engine control parameter information, specifically high voltage control parameters, fixing temperature parameters, paper feed speed control parameters, etc. When the image forming device is a color printer, it also includes color calibration parameter information or calibration patterns; (2) consumable related parameters, such as various proportional factors for calculating toner consumption; or basic attribute information of the consumable, wherein the basic attribute information of the consumable can specifically be consumable model, consumable serial number, consumable capacity life, etc. It should be noted that those skilled in the art can also design the consumable chip to store other types of raw data according to actual needs, and this application embodiment does not limit this.
[0069] When consumables are depleted, the user needs to disassemble the consumable device for an update, including replenishing consumables and replacing the consumable chip (or updating the data in the original consumable chip). After the consumable device is updated, the user can reinstall it into the image forming equipment. After the main control chip and the consumable chip re-establish their connection, the main control chip needs to perform communication verification on the consumable chip to confirm that the current consumable chip is a genuine chip and to ensure communication security.
[0070] The main control chip and consumable chips simulate the Inter-Integrated Circuit (I2C) bus based on General Purpose Input Output (GPIO) pins. Communication verification and subsequent normal communication are then performed based on the simulated I2C bus. The I2C bus includes clock and data lines; the data lines are used for data transmission, and the clock lines are used for clock synchronization between the two devices. The I2C bus structure is simple, reducing system cost and improving system reliability.
[0071] Reference Figure 2The main control chip and the consumable chip communicate and verify each other through fixed hardware IIC interfaces. Interface A of the main control chip and interface C of the consumable chip constitute the clock line, and interface B of the main control chip and interface D of the consumable chip constitute the data line. The clock line is connected to power supply VCC through resistor R1, and the data line is connected to power supply VCC through resistor R2. In existing communication verification methods, the main control chip performs communication verification with the consumable chip only through fixed clock and / or data lines. This method is easily cracked, potentially leading to chip counterfeiting and information leakage.
[0072] To address the above issues, this application provides a communication method for consumable chips. By modifying the simulation method of the clock line and data line and performing multiple communication verifications, the difficulty of cracking the consumable chip can be effectively increased, thus improving its security.
[0073] Figure 3 This is a flowchart illustrating a communication method for a consumable chip provided in an embodiment of this application. This method can be applied to the main control chip of an image forming device. Figure 3 As shown, the method may include:
[0074] Step 301: Simulate and generate a first clock line based on the first pin and the third pin, simulate and generate a first data line based on the second pin and the fourth pin, and generate a first simulated I2C interface based on the first data line and the first clock line.
[0075] Step 302: Perform the first communication verification through the first clock line and the first data line of the first analog I2C interface.
[0076] Step 303: Determine whether the first communication verification is successful. If it is successful, proceed to step 304; otherwise, proceed to step 308.
[0077] Step 304: Simulate and generate a second data line based on the first and third pins, simulate and generate a second clock line based on the second and fourth pins, and generate a second simulated I2C interface based on the second clock line and the second data line.
[0078] Step 305: Perform the second communication verification through the second clock line and the second data line of the second analog I2C interface.
[0079] Step 306: Determine whether the second communication verification is successful. If it is successful, proceed to step 307; otherwise, proceed to step 308.
[0080] Step 307: Determine the compatibility of the current consumable chip.
[0081] Step 308: Determine that the current consumable chip is incompatible.
[0082] Combination Figure 4a , Figure 4b right Figure 3 The process will be explained. Figure 4a Pins A, B, C, and D in the circuit can be considered as the first pin, second pin, third pin, and fourth pin, respectively. After the main control chip connects to the consumable chip, the main control chip simulates and generates the first clock line of the first analog I2C interface based on its own pin A and the consumable chip's pin C. Simultaneously, it simulates and generates the first data line of the first analog I2C interface based on its own pin B and the consumable chip's pin D. The main control chip can perform a first communication verification process on the consumable chip through the first clock line and the first data line of the first analog I2C interface. This first communication verification process can generate a level signal by manually controlling the high and low levels of the main control chip's GPIO pins, and transmit this level signal to the consumable chip. This checks whether the simulated clock line and data line can generate start, stop, and acknowledge signals according to the I2C protocol, and whether the data transmission is correct.
[0083] If the first communication verification fails, the current consumable chip is directly determined to be incompatible. If the first communication verification passes, the second communication verification process is executed. For details, refer to... Figure 4b The main control chip simulates the switching of clock and data lines, using its own pin A and the consumable chip's pin C to generate the second data line of the second simulated I2C interface, and simultaneously using its own pin B and the consumable chip's pin D to generate the second clock line of the second simulated I2C interface. The main control chip can perform a second communication verification through the second clock and data lines of the second simulated I2C interface. If the second communication fails, the current consumable chip is deemed incompatible; if the second communication verification passes, the current consumable chip is confirmed to be compatible. Consumable chips deemed compatible are considered genuine and secure and can be used normally, while consumable chips deemed incompatible are considered counterfeit and cannot be used. This second communication verification process can be achieved by manually controlling the high and low levels of the main control chip's GPIO pins to generate level signals, which are then transmitted to the consumable chip to check whether the simulated clock and data lines can generate start, stop, and acknowledge signals according to the I2C protocol, and whether the data transmission is correct.
[0084] Compared to existing verification methods that perform a single communication verification process through a fixed hardware IIC interface, this application embodiment uses a simulation method that swaps clock and data lines after performing one communication verification, and then performs a second communication verification based on the newly simulated clock and data lines. This makes the overall verification process more difficult to crack, effectively preventing the counterfeiting of consumable chips and ensuring data security.
[0085] In both communication verifications, the analog mode of the clock line and data line can be preset to... Figure 3Taking the verification process as an example, after the main control chip and the consumable chip are connected, the clock line is simulated using pins A and C by default, and the data line is simulated using pins B and D. During the second communication verification, the simulation mode is directly switched, with the data line simulated using pins A and C, and the clock line simulated using pins B and D.
[0086] In one optional embodiment, the analog configuration of the clock and data lines can be determined through negotiation between the parties. The overall communication verification process can be referred to... Figure 5 Specifically, it may include:
[0087] Step 501: Send first agreed data to the consumable chip to determine the first simulation mode.
[0088] Step 502: Generate a first clock line and a first data line based on the first analog method, and generate a first analog I2C interface based on the first clock line and the first data line.
[0089] Step 503: Send the first verification data to the consumable chip.
[0090] Step 504: Perform the first communication verification through the first clock line and the first data line of the first analog I2C interface.
[0091] Step 505: Determine whether the first communication verification is successful. If it is successful, proceed to step 506; otherwise, proceed to step 512.
[0092] Step 506: Send the second agreed data to the consumable chip to determine the second simulation mode.
[0093] Step 507: Generate a second clock line and a second data line based on the second analog method, and generate a second analog I2C interface based on the second clock line and the second data line.
[0094] Step 508: Send the second verification data to the consumable chip.
[0095] Step 509: Perform the second communication verification through the second clock line and the second data line of the second analog I2C interface.
[0096] Step 510: Determine whether the second communication verification is successful. If it is successful, proceed to step 511; otherwise, proceed to step 512.
[0097] Step 511: Determine if the current consumable chip is usable.
[0098] Step 512: Determine that the current consumable chip is unavailable.
[0099] Taking Figure 4 as an example, Figure 5The process is explained below. After the main control chip and the consumable chip are connected, the main control chip can send first agreed-upon data to the consumable chip through pin A and / or pin C. The first agreed-upon data includes a first simulation mode. The first simulation mode is used to determine the simulation mode of the clock line and data line in the first communication verification. For example, the first simulation mode can instruct pins A and C to simulate the generation of a clock line, and pins B and D to simulate the generation of a data line. Optionally, the first simulation mode can also instruct pins A and C to simulate the generation of a data line, and pins B and D to simulate the generation of a clock line; the specific method is not limited.
[0100] The main control chip uses control pins A, B, C, and D to simulate and generate the first data line and the first clock line according to the rules of the first simulation method, and generates the first simulated I2C interface based on the first clock line and the first data line. After the simulation of the first data line and the first clock line is completed, the main control chip can send the first verification data to the consumable chip. The first verification data can be used to determine that the first data line and the first clock line can communicate normally or to notify the consumable chip that the first communication verification is about to begin.
[0101] The main control chip performs a first communication verification through the first data line and the first clock line of the first simulated I2C interface. If the first communication verification fails, the current consumable chip is determined to be unusable. If the first communication verification passes, the main control chip sends second agreed-upon data to the consumable chip to determine the second simulation mode. The main control chip controls pins A, B, C, and D to simulate and generate a second data line and a second clock line according to the rules of the second simulation mode, and generates a second simulated I2C interface based on the second clock line and the second data line. After the second data line and the second clock line simulation is completed, the main control chip can send second verification data to the consumable chip, and then perform a second communication verification through the second data line and the second clock line of the second simulated I2C interface. If the second verification fails, the current consumable chip is determined to be unusable; if the second communication verification passes, the current consumable chip is determined to be usable.
[0102] In one optional embodiment, the aforementioned first agreed-upon data, second agreed-upon data, first verification data, and second verification data can be implemented using data levels of a specific length. For example, the main control chip can send a set of 8-bit data levels (first agreed-upon data) to the consumable chip to notify the consumable chip of relevant information regarding the first analog mode. Then, the main control chip can first send two sets of 8-bit invalid data (first verification data) to the consumable chip, and then perform the first communication verification. After the first communication verification is successful, the main control chip can send another set of 8-bit data levels (second agreed-upon data) to the consumable chip to notify the consumable chip of relevant information regarding the second analog mode. Before the second communication verification begins, the main control chip sends two sets of 8-bit invalid data (second verification data) to the consumable chip, and then performs the second communication verification; successful verification allows normal use.
[0103] In this embodiment, the specific rules for the first and second simulation methods can be flexibly set. For example, the first simulation method uses pins A and C to simulate a clock line and pins B and D to simulate a data line, while the second simulation method uses pins A and C to simulate a data line and pins B and D to simulate a clock line. Alternatively, the first simulation method uses pins A and C to simulate a data line and pins B and D to simulate a clock line, while the second simulation method uses pins A and C to simulate a clock line and pins B and D to simulate a data line. The above two communication verifications are merely illustrative examples. In other embodiments, the main control chip may perform three or more communication verifications, and the simulation methods used for different communication verifications may be negotiated and determined. By flexibly setting the simulation methods for clock and data lines, the difficulty of cracking communication verification can be further increased, ensuring the security of the consumable chip.
[0104] Figure 6 This is a flowchart illustrating another communication method for a consumable chip provided in an embodiment of this application. This method can be applied to the main control chip of an image forming device. Figure 6 As shown, the method may include:
[0105] Step 601: Perform a first communication verification process on the consumable chip based on the first clock line and the first data line of the first analog I2C interface.
[0106] Step 602: When the first communication verification is detected as successful, the first clock line is converted to the second data line, and the first data line is converted to the second clock line to generate the second analog I2C interface.
[0107] Step 603: Perform a second communication verification process on the consumable chip based on the second clock line and the second data line of the second analog I2C interface.
[0108] In one optional embodiment, before performing the first communication verification, the main control chip simulates and generates a first data line and a first clock line based on a first simulation mode, a first pin, and a second pin. Specifically, based on the first simulation mode, the first pin and the third pin are controlled to simulate and generate a first clock line, and the second pin and the fourth pin are controlled to simulate and generate a first data line; a first simulated I2C interface is simulated and generated based on the first data line and the first clock line. The first simulation mode can be a default mode or can be determined by the main control device through negotiation by sending first agreed-upon data to the consumable chip.
[0109] After the first communication verification is passed, the main control chip controls the first and third pins to simulate the generation of the second data line based on the second simulation method, and controls the second and fourth pins to simulate the generation of the second clock line; and simulates the generation of the second analog I2C interface based on the second data line and the second clock line.
[0110] Through the two communication verifications described above, the main control chip can accurately determine whether the current consumable chip is genuine. If it is confirmed to be genuine, it can be used normally; if it is confirmed to be counterfeit, the consumable chip cannot be used. Simultaneously, the main control chip can also generate an error message to inform the user that the current consumable chip has a problem and cannot be used normally. Optionally, this error message can be displayed through the control panel of the image forming device.
[0111] Figure 7 This is a flowchart illustrating another communication method for a consumable chip provided in an embodiment of this application. This method can be applied to consumable chips in image forming equipment. Figure 7 As shown, the method may include:
[0112] Step 701: When the main control chip triggers the first communication verification process, it performs the first communication verification with the main control chip based on the first clock line and the first data line of the first analog I2C interface.
[0113] Step 702: When the main control chip triggers the second communication verification process, the first clock line is converted into the second data line, and the first data line is converted into the second clock line to generate the second analog I2C interface.
[0114] Step 703: Perform a second communication verification on the main control chip based on the second clock line and the second data line of the second analog I2C interface.
[0115] Before the first communication verification, the consumable chip can receive first agreed-upon data sent by the main control chip. This first agreed-upon data includes a first analog mode. Based on the first analog mode, the consumable chip can control the third pin to simulate the generation of a first clock line and control the fourth pin to simulate the generation of a first data line. After receiving the first verification data sent by the main control chip, the consumable chip can perform the first communication verification.
[0116] After the first verification is successful, the consumable chip receives the second agreed-upon data sent by the main control chip to determine the second simulation mode. Based on the second simulation mode, the consumable chip controls the third pin to simulate the generation of the second data line and the fourth pin to simulate the generation of the second clock line. After receiving the second verification data sent by the main control chip, the consumable chip performs the second communication verification.
[0117] The communication method for consumable chips provided in the embodiments of this application can effectively improve the security of consumable chips and protect the rights and interests of genuine chips.
[0118] Figure 8 This is a schematic diagram of a communication device for a consumable chip provided in an embodiment of this application. The device can be deployed on a main control chip, such as... Figure 8As shown, the device may include: a first verification module 810, a control module 820, and a second verification module 830.
[0119] The first verification module 810 is used to perform a first communication verification process on the consumable chip based on the first clock line and the first data line of the first analog I2C interface.
[0120] The control module 820 is used to convert the first clock line to the second data line and the first data line to the second clock line when the first communication verification is successful, thereby generating a second analog I2C interface.
[0121] The second verification module 830 is used to perform a second communication verification process on the consumable chip based on the second clock line and the second data line of the second analog I2C interface.
[0122] Figure 9 This is a schematic diagram of a communication device for a consumable chip provided in an embodiment of this application. The device can be deployed on a consumable chip, such as... Figure 9 As shown, the device may include: a first communication verification module 910, an analog module 920, and a second communication verification module 930.
[0123] The first communication verification module 910 is used to perform first communication verification with the main control chip based on the first clock line and the first data line of the first analog I2C interface when the main control chip triggers the first communication verification process.
[0124] The analog module 920 is used to convert the first clock line into the second data line and the first data line into the second clock line to generate a second analog I2C interface when the main control chip triggers the second communication verification process.
[0125] The second communication verification module 930 is used to perform second communication verification on the main control chip based on the second clock line and the second data line of the second analog I2C interface.
[0126] For the specific process, please refer to the description in the flowchart above.
[0127] Corresponding to the above embodiments, this application also provides an electronic device. Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device 1000 may include a processor 1001, a memory 1002, and a communication unit 1003. These components communicate through one or more buses. Those skilled in the art will understand that the structure of the electronic device shown in the figure does not constitute a limitation on the embodiment of this application. It may be a bus topology or a star topology, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.
[0128] The communication unit 1003 is used to establish a communication channel, enabling the electronic device to communicate with other devices. It receives user data from other devices or sends user data to other devices.
[0129] The processor 1001 serves as the control center of the electronic device, connecting various parts of the device via various interfaces and lines. It executes software programs, instructions, and / or modules stored in the memory 1002, and calls data stored in the memory to perform various functions and / or process data. The processor may be composed of integrated circuits (ICs), such as a single packaged IC or multiple packaged ICs with the same or different functions connected together. For example, the processor 1001 may consist only of a central processing unit (CPU). In this embodiment, the CPU may have a single processing core or include multiple processing cores.
[0130] The memory 1002 is used to store the execution instructions of the processor 1001. The memory 1002 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.
[0131] When the execution instructions in memory 1002 are executed by processor 1001, the electronic device 1000 is able to perform operations. Figures 5 to 7 Some or all of the steps in the illustrated embodiments.
[0132] In a specific implementation, this application also provides a computer storage medium, wherein the computer storage medium may store a program, which, when executed, may include some or all of the steps of the communication method of the consumable chip provided in this application. The storage medium may be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.
[0133] In a specific implementation, this application also provides a computer program product, wherein the computer program product includes executable instructions, which, when executed on a computer, cause the computer to perform some or all of the steps in various embodiments of the communication method for the consumable chip provided in this application.
[0134] This application also provides a non-transitory computer-readable storage medium that stores computer instructions, which cause the computer to execute the communication method of the consumable chip provided in this application.
[0135] The aforementioned non-transitory computer-readable storage medium may be any combination of one or more computer-readable media. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or flash memory, optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in connection with an instruction execution system, apparatus, or device.
[0136] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including—but not limited to—electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of transmitting, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.
[0137] The program code contained on a computer-readable medium may be transmitted using any suitable medium, including—but not limited to—wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.
[0138] Those skilled in the art will clearly understand that the techniques in the embodiments of this application can be implemented using software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of this application, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application or some parts of the embodiments.
[0139] The same or similar parts between the various embodiments in this specification can be referred to mutually. In particular, the device embodiments and terminal embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.
Claims
1. A communication method for a consumable chip, characterized in that, A main control chip for use in an image forming apparatus, the main control chip including a first pin and a second pin, and a consumable chip including a third pin and a fourth pin, the method comprising: Based on the first simulation method, the first pin and the third pin are controlled to simulate the generation of the first clock line, and the second pin and the fourth pin are controlled to simulate the generation of the first data line; A first analog I2C interface is generated based on the first data line and the first clock line; The first communication verification process is performed on the consumable chip based on the first clock line and the first data line of the first analog I2C interface. When the first communication verification is detected to be successful, the first clock line is converted to the second data line, and the first data line is converted to the second clock line to generate a second analog I2C interface; The second communication verification process is performed on the consumable chip based on the second clock line and the second data line of the second analog I2C interface; The step of converting the first clock line to a second data line and the first data line to a second clock line to generate a second analog I2C interface when the first communication verification is successful includes: When the first communication verification is detected as successful, a second simulation method is determined based on the first simulation method; Based on the second simulation method, the first pin and the third pin are controlled to simulate the generation of the second data line, and The second pin and the fourth pin are controlled to simulate the generation of the second clock line; The second simulated I2C interface is generated based on the second data line and the second clock line; The method further includes: If the first communication verification fails, the consumable chip is determined to be a counterfeit chip; or, If the first communication verification passes and the second communication verification fails, the consumable chip is determined to be a counterfeit chip; or, When both the first and second communication verifications are passed, the consumable chip is determined to be a genuine chip.
2. The method according to claim 1, characterized in that, Before the step of controlling the first pin and the third pin to simulate generating the first clock line based on the first simulation method, and controlling the second pin and the fourth pin to simulate generating the first data line, the method further includes: Retrieve the pre-stored first simulation method; The first simulation method is sent to the consumable chip.
3. The method according to claim 1, characterized in that, After the step of performing the second communication verification process on the consumable chip based on the second clock line and the second data line of the second analog I2C interface, the method further includes: If it is determined that the consumable chip is a non-genuine chip, an error message will be displayed, indicating that the current consumable chip cannot communicate normally with the main control chip.
4. A communication method for a consumable chip, characterized in that, The method includes: (The text abruptly ends here, likely due to an incomplete sentence or missing information.) The system receives first agreed-upon data sent by the main control chip, the first agreed-upon data including a first analog mode, the main control chip including a first pin and a second pin, and the consumable chip including a third pin and a fourth pin. Based on the first simulation method, the third pin and the first pin are controlled to simulate the generation of the first clock line, and the fourth pin and the second pin are controlled to simulate the generation of the first data line; The system receives first verification data sent by the main control chip, which is used to confirm that the first clock line and the first data line can communicate normally. When the main control chip triggers the first communication verification process, it performs the first communication verification with the main control chip based on the first clock line and the first data line of the first analog I2C interface. When the main control chip triggers the second communication verification process, it converts the first clock line into a second data line, and the first data line into a second clock line to generate a second analog I2C interface. The main control chip is subjected to a second communication verification based on the second clock line and the second data line of the second simulated I2C interface. If the first communication verification fails, the consumable chip is unusable; If the first communication verification passes and the second communication verification fails, the consumable chip is unusable; If both the first and second communication verifications pass, the consumable chip can be used. When the main control chip triggers the second communication verification process, it converts the first clock line to a second data line, and the first data line to a second clock line, generating a second analog I2C interface, including: Receive second agreed-upon data sent by the main control chip, wherein the second agreed-upon data includes a second simulation mode; Based on the second simulation method, the third pin and the first pin are controlled to simulate the generation of the second data line, and the fourth pin and the second pin are controlled to simulate the generation of the second clock line; After the first communication verification is successful, the system receives the second agreed-upon data sent by the main control chip to determine the second simulation mode.
5. The method according to claim 4, characterized in that, The second communication verification of the main control chip based on the second clock line and the second data line of the second analog I2C interface includes: After receiving the second verification data sent by the main control chip, the second communication verification is performed on the main control chip based on the second clock line and the second data line.
6. An electronic device, characterized in that, It includes a memory for storing computer program instructions and a processor for executing the program instructions, wherein when the computer program instructions are executed by the processor, the electronic device performs the method according to any one of claims 1 to 3 or any one of claims 4 to 5.
7. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored program, wherein, when the program is executed, it controls the device on which the computer-readable storage medium is located to perform the method according to any one of claims 1 to 3 or any one of claims 4 to 5.