Data transmission method and device based on FFT (Fast Fourier Transform)

Abstract

The invention provides a data transmission method and device based on FFT (Fast Fourier Transform). The method comprises the following steps: constructing an FFT butterfly operation network; calculating a read address, and reading the input data from the memory according to the read address; configuring a butterfly operator in the FFT butterfly operation network, and performing data processing on the input data by using the butterfly operator; calculating a write address, and writing data processed by the FFT butterfly operation network into a memory according to the write address; and calculating an address sequence, and reading the data from the memory. A butterfly operation network is constructed and configured according to calculation requirements of FFT butterfly operation and array characteristics of a memory, and an in-situ operation result is accessed to the memory for cross processing through a read address and a write address, so that full-load work of all butterfly operators in each period can be realized in the FFT operation; therefore, the FFT butterfly operation in each period can perform data transmission with the maximum parallel number, the data processing efficiency of the butterfly operation network is effectively improved, and the problem that the data processing efficiency of the existing butterfly operation network is low is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a data transmission method and device based on FFT. Background Art

[0002] In the field of data processing, Fourier transform is an important computing tool. To facilitate large-scale digital processing, fast Fourier transform (FFT) has become the standard process for implementing Fourier transform. Fourier transform is often used for noise filtering, digital compression and pattern detection in signal processing, often used for noise reduction, feature extraction and edge detection in image processing, and used for modulation, transmission and demodulation of signals in communication systems. Fourier transform has a large amount of calculation for longer signals, and the improved fast Fourier transform method effectively reduces the number of operations, greatly improving the practicality of the transform.

[0003] In the existing fast Fourier transform, the most commonly used sub-operation is the complex multiplication and addition operation. The general process is that the data is input in the order of the address, and the order of the input data is changed according to different butterfly operation networks and read out. After reading, the data enters the complex butterfly operation network and passes through N×log 2 N times of complex sub-operation (N is the data length), and finally output the result. Therefore, adding operation channels to perform butterfly operation becomes a basic method to effectively improve the FFT operation speed.

[0004] The input data of the butterfly operation network usually uses reverse data as the address; starting from the input data of the first layer, the input data and output data of each butterfly operator are in-situ operations (that is, the output data generated after the input data is operated by the butterfly is stored in the storage location of the input data). The butterfly operator is generally designed as a pipeline. When a set of inputs is given to the butterfly operator in each cycle, the operation load of the butterfly operator can reach the maximum. Therefore, taking out a set of operation data from the data storage at one time each cycle becomes the key to the rate. However, according to the principle of in-situ operation and the characteristics of the butterfly network, after the number of layers increases, the step size of the butterfly operator increases, and the theoretical distance is an integer power of 2. Since a large number of data groups are read or written in the same memory, it takes x cycles to take out x data in the same memory, and it also takes y cycles to write y data in the same memory, which seriously reduces the parallelism of the butterfly operator and becomes a bottleneck for parallel operation. Summary of the invention

[0005] The object of the present invention is to provide a data transmission method and device based on FFT to solve the problem of low data processing efficiency of existing butterfly computing networks.

[0006] In order to solve the above technical problems, the present invention provides a data transmission method based on FFT, comprising: Construct FFT butterfly operation network; Calculate the read address and read the input data from the memory according to the read address; Configure the butterfly operator in the FFT butterfly operation network, and use the configured FFT butterfly operation network to process the input data; Calculate the write address and write the data in the FFT butterfly operation network processing into the memory according to the write address; The address sequence is calculated according to the preset output formula, and the data is read from the memory to obtain the final output data.

[0007] Optionally, in the FFT-based data transmission method, the method for constructing the FFT butterfly operation network includes: Building an FFT butterfly operation network, wherein the FFT butterfly operation network includes multiple layers of butterfly operators; Define the parameters in the FFT butterfly operation network, including the length N of the input data, the number M of butterfly operators participating in the operation per cycle, the number D of butterfly operator cycles, the number L of butterfly operator layers, the number C of storage units in the memory, and the number G of times each layer of butterfly operators needs to read data; Initialize the FFT butterfly network.

[0008] Optionally, in the FFT-based data transmission method, the method for defining parameters in the FFT butterfly operation network includes: Define the length N of the input data to be an integer power of 2; Define the number M of butterfly operators participating in the operation in each cycle as an integer power of 2; Define N / 2M to be greater than or equal to D; Define the number of layers of the butterfly operator L=log 2 N; Define the number of storage units C in the memory as the amount of data that can be read in a single cycle, and C=2M; Define the number of times each layer of butterfly operator needs to read data G=N / C.

[0009] Optionally, in the FFT-based data transmission method, the method for initializing the FFT butterfly operation network includes: Let the number sequence stored in the memory be the address reverse sequence of the input data; Let the current layer be the first layer, and record layer=0; Let the address difference between the two input data of the butterfly operator in the layer and the memory be Xstep=2 i , where i represents the number of layers; Let the number of reads in the layer g=0; Let the starting address addr_start read in each cycle = 0, and the width of addr_start and log 2 N+1 consistent; Let the low Log of each read address addr_r 2 The C bit corresponds to the number of the storage unit in the memory, and the other high bits correspond to the read physical address of the storage unit; Let the number of reads of each operation group in the current layer be o=0, wherein the operation group includes at least one butterfly operator.

[0010] Optionally, in the FFT-based data transmission method, the method of calculating the read address and reading the input data from the memory according to the read address includes: Calculate the position of the data in the current layer input sequence; Calculate the value of the starting address addr_start to be read in the next cycle; Calculate the number of times the current layer is read in the next cycle g; Calculate the number of times o the data is read in the current operation group in the next cycle; Perform odd-even cross processing on the original address to obtain the hardware read address; Read input data from memory according to the hardware address.

[0011] Optionally, in the FFT-based data transmission method, the method for calculating the position of data in the current layer input sequence includes: Calculate the position of the odd data in the current layer input sequence, expressed as: addr_o[i]=addr_start+(i / Xstep)×Xstep+i Calculate the position of the even data in the current layer input sequence, expressed as: addr_e[i]=addr_start+(i / Xstep)×Xstep+Xstep+i Among them, i represents the i-th odd data or even data, i=0,1,…,M-1.

[0012] Optionally, in the FFT-based data transmission method, the method for calculating the value of the starting address addr_start read in the next cycle includes: Calculate the increment value cycle_step of the start address addr_start read in the next cycle compared to the start address addr_start read in the current cycle in the auto-increment state; According to the number of reads g in the layer and the number of times G that data needs to be read, the value of the start address addr_start read in the next cycle is calculated using the value of the start address addr_start read in the current cycle and the increment value cycle_step.

[0013] Optionally, in the FFT-based data transmission method, the method for calculating the number of times g that the current layer is read in the next cycle includes: Determine whether the number of reads g of the current layer in the current cycle reaches the number of data reads G required by the current layer; If it is not reached, the number of readings in the current cycle is increased by 1, which is used as the number of readings in the next cycle g; If it is reached, the calculation is judged to enter a new layer, and the number of reads g of the current layer is set to 0.

[0014] Optionally, in the FFT-based data transmission method, the method for calculating the number of read times o of the data to be read in the next cycle in the current operation group includes: Determine whether the address difference Xstep in the current layer is greater than the number M of butterfly operators; If yes, then further determine whether the number of reads o in the current cycle is less than Xstep / M-1; If yes, add 1 to the number of reads in the current cycle as the number of reads in the next cycle o; Otherwise, the calculation is judged to enter a new layer and the number of reads o of the current layer is set to 0.

[0015] Optionally, in the FFT-based data transmission method, the method of performing parity crossover processing on the original address to obtain the hardware read address includes: For odd data, let its position in the current layer input sequence be its hardware read address; For even data, determine whether the address difference Xstep in the current layer is greater than the number of butterfly operators M. If so, invert the low bit of the position of the even data in the current layer input sequence to obtain its hardware read address, otherwise use its position in the current layer input sequence as its hardware read address.

[0016] Optionally, in the FFT-based data transmission method, the method for configuring the butterfly operator in the FFT butterfly operation network includes: The address and ID of each storage unit in the configuration memory; Configure the twiddle factor W of the butterfly operator.

[0017] Optionally, in the FFT-based data transmission method, the method for configuring the address and ID of each storage unit in the memory includes: Let the address of the storage unit be the high bit of the position of the data in the current layer input sequence; Let the ID of the storage unit be the low bit of the position of the data in the current layer input sequence.

[0018] Optionally, in the FFT-based data transmission method, the method for configuring the rotation factor W of the butterfly operator includes: If the number of layers in the current layer is less than or equal to log 2 C, the rotation factor is determined according to the current layer number and the position of the data in the current layer input sequence; If the number of layers in the current layer is greater than log 2 C, then let the high bit of the address of the storage unit be the ID of the operation group, and perform an XOR operation on all bits of the ID of the operation group to obtain the rotation factor.

[0019] Optionally, in the FFT-based data transmission method, the method of calculating a write address and writing data in the FFT butterfly operation network processing into a memory according to the write address includes: According to the number of the next layer, the odd data write address and the even data write address are calculated; According to the odd data write address, the odd data output after processing by the FFT butterfly operation network is sent to the corresponding storage unit of the memory; according to the even data write address, the even data output after processing by the FFT butterfly operation network is sent to the corresponding storage unit of the memory.

[0020] Optionally, in the FFT-based data transmission method, the method for calculating the odd data write address and the even data write address according to the number of layers of the next layer includes: Let the number of the next layer be the number of the current layer plus 1; Synchronize the hardware read address with the butterfly operator calculation process to obtain an odd data synchronization address and an even data synchronization address; If the number of layers in the next layer is less than or equal to log 2 C-1, the odd data write address is the odd data synchronization address, and the even data write address is the even data synchronization address; If the number of layers in the next layer is greater than log 2 C-1, then determine whether the [layer_next] bit of the odd data synchronization address of the next layer is 1. If so, invert the low bit of the odd data synchronization address to obtain the odd data write address. If not, keep the odd data synchronization address unchanged; determine whether the [layer_next] bit of the even data synchronization address of the next layer is 1. If so, invert the low bit of the even data synchronization address to obtain the even data write address. If not, keep the even data synchronization address unchanged.

[0021] Optionally, in the FFT-based data transmission method, the method of calculating the address sequence according to a preset output formula and reading data from the memory to obtain the final output data includes: Set the output address to be initialized to 0 and increment every cycle; Perform XOR calculation on all bits of the output address; If the result of the XOR calculation is 1, the read output address is configured as addr_r_output[i]=addr_output×C+C-1-i; otherwise, the read output address is configured as addr_r_output[i]=addr_output×C+i, where i=1,2,…,C-1.

[0022] In order to solve the above technical problems, the present invention further provides an FFT-based data transmission device, which is used to implement the FFT-based data transmission method as described in any one of the above items, and the FFT-based data transmission device includes: A network construction module is used to construct an FFT butterfly operation network and configure a butterfly operator in the FFT butterfly operation network; the FFT butterfly operation network is used to input data for data processing; A data reading and writing module is used to calculate a read address and read input data from a memory according to the read address; it is also used to calculate a write address and write data in the FFT butterfly operation network processing into the memory according to the write address; The result output module is used to calculate the address sequence according to the preset output formula and read the data from the memory to obtain the final output data.

[0023] The FFT-based data transmission method and device provided by the present invention include: constructing an FFT butterfly operation network; calculating a read address, and reading input data from a memory according to the read address; configuring a butterfly operator in the FFT butterfly operation network, and using the configured FFT butterfly operation network to process the input data; calculating a write address, and writing the data processed by the FFT butterfly operation network into the memory according to the write address; performing address sequence calculation according to a preset output formula, and reading data from the memory to obtain the final output data. By constructing and configuring a butterfly operation network according to the calculation requirements of the FFT butterfly operation and the array characteristics of the memory, and connecting the original operation results to the memory for cross processing through the read address and the write address, it is possible to achieve full load operation of all butterfly operators in each cycle in the FFT operation, so that the FFT butterfly operation in each cycle can perform data transmission with the maximum parallel number, effectively improving the data processing efficiency of the butterfly operation network, and solving the problem of low data processing efficiency of the existing butterfly operation network. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1A flowchart of the FFT-based data transmission method provided in this embodiment; Figure 2 A schematic diagram of the principle of a 16-point FFT butterfly operation network provided in this embodiment; 3(A) to 3(F) are schematic diagrams of address and data calculation in each layer of the reading and writing process when the FFT-based data transmission method provided in this embodiment is specifically implemented with 64-length data; Figure 4 The FFT-based data transmission method provided in this embodiment specifically implements the address and data calculation diagram of the result data read when the length of data is 64.

[0025] Figure 5 A structural block diagram of the FFT-based data transmission device provided in this embodiment; Figure 6 A schematic diagram of the specific structure of the FFT butterfly operation network provided in this embodiment. DETAILED DESCRIPTION

[0026] The FFT-based data transmission method and device proposed in the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the accompanying drawings is often a part of the actual structure. In particular, the emphasis of each accompanying drawing is different, and sometimes different proportions are used.

[0027] It should be noted that the terms "first", "second", etc. in the specification, claims and drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, rather than to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] This embodiment provides a data transmission method based on FFT, such as Figure 1 As shown, including: S1, construct FFT butterfly operation network; S2, calculate the read address and read the input data from the memory according to the read address; S3, configuring a butterfly operator in the FFT butterfly operation network, and using the configured FFT butterfly operation network to perform data processing on the input data; S4, calculating a write address, and writing the data being processed by the FFT butterfly operation network into a memory according to the write address; S5, performing address sequence calculation according to a preset output formula, and reading data from the memory to obtain final output data.

[0029] The FFT-based data transmission method provided in this embodiment constructs and configures a butterfly operation network according to the calculation requirements of the FFT butterfly operation and the array characteristics of the memory, and connects the original operation results to the memory for cross-processing through read addresses and write addresses, so that all butterfly operators can work at full load in each cycle in the FFT operation, so that the FFT butterfly operation in each cycle can perform data transmission with the maximum parallel number, effectively improving the data processing efficiency of the butterfly operation network and solving the problem of low data processing efficiency of the existing butterfly operation network.

[0030] Specifically, in this embodiment, step S1, the method of constructing an FFT butterfly operation network includes: S11, building an FFT butterfly operation network, wherein the FFT butterfly operation network includes multiple layers of butterfly operators.

[0031] In practical applications, an FFT butterfly operation network can be built according to actual computing requirements. The structure of the FFT butterfly operation network is well known to those skilled in the art and will not be described in detail in this application.

[0032] The calculation process of the butterfly operation network is a multi-layer combination of complex multiplication and complex addition of the input sequence data and the rotation factors. Figure 2 Taking the 16-point FFT butterfly operation network shown as an example, the left side is the input data, two butterfly operators participate in the operation in each cycle, each layer requires four cycles for butterfly operation, and the right side is the output data.

[0033] Of course, in practical applications, a butterfly computing network with more points (such as 1024 points or 2048 points) can be used. The process principle of the FFT-based data transmission method provided in the present application is the same as that of the present embodiment. Those skilled in the art can, based on the present embodiment, know the specific implementation method of the FFT-based data transmission method of other butterfly computing networks.

[0034] S12, define the parameters in the FFT butterfly operation network, the parameters include the length N of the input data, the number M of butterfly operators, the number D of butterfly operator cycles, the number L of butterfly operator layers, the number C of storage units in the memory, and the number G of times each layer of butterfly operators needs to read data.

[0035] In practical applications, the specific values ​​of the above parameters can be obtained according to actual needs. Usually, the length N of the input data is an integer power of 2; the number of butterfly operators M is an integer power of 2; N / 2M is greater than or equal to D, where the parameter D represents the number of cycles that each butterfly operator completes when a set of data is read from the memory (RAM), calculated, and then written back to the memory in the pipeline state; the number of layers of the butterfly operator L = log 2 N; the number of storage units in the memory C is the amount of data that can be read in a single cycle, and C=2M; the number of times each layer of butterfly operator needs to read data G=N / C.

[0036] The parameters N, M and D are determined by the hardware resource constraints before designing the network. This embodiment increases the limit N / 2M≥D to ensure that the entire process of the butterfly operation network is seamlessly connected and all operators run at full capacity, thereby effectively improving the FFT operation efficiency and resource utilization efficiency.

[0037] Also, by configuring parameter C (the number of storage units in the designed memory) according to the amount of data that can be read in a single cycle, it is possible to ensure that the storage units in the memory can meet the data calculation requirements without wasting excess storage units, thereby improving the utilization of storage resources. In practical applications, before the butterfly network starts calculating, the content stored in the memory is sequence B, where sequence B is the reverse sequence of the addresses of sequence A (data to be processed).

[0038] S13, initialize the FFT butterfly operation network.

[0039] Specifically, in this embodiment, first, let the number sequence stored in the memory be the address reverse sequence of the input data, that is, the above-mentioned number sequence B. And let the current layer be the first layer, layer=0, that is, the second layer is represented by layer=1.

[0040] Then, let the address difference between the two input data of the butterfly operator in the layer and the memory be Xstep=2 i , where i represents the number of layers. Figure 2 As shown, Xstep=1 for layer 0, Xstep=2 for layer 1, Xstep=4 for layer 2, and Xstep=2 for layer n. n .

[0041] Next, let the number of reads in the layer g = 0. When the total amount of input data in each layer is N and C data are read out in each cycle, g means the number of times the data is read out in the current layer in the current cycle.

[0042] After that, set the starting address addr_start = 0 for each cycle, and the width of addr_start and log 2N+1 is consistent; let the low Log of each read address addr_r 2 The C bit corresponds to the number of the storage unit in the memory, and the other high bits correspond to the read physical address of the storage unit.

[0043] Finally, let the number of reads of each operation group in the current layer be o=0, wherein the operation group includes at least one butterfly operator.

[0044] Considering that in practical applications, Figure 2 As shown, M=2, in the 0th and 1st layers, the four data read out each time can form continuous data; in the 2nd and 3rd layers, because Xstep is greater than M, the 4 data read in at a time are scattered in the upper and lower parts, which are non-continuous data; and the two (four in each) non-continuous data read in through cycle 9 and cycle 10 form 8 continuous data and enter the next layer. Therefore, in this embodiment, the 8 data read in these two cycles are regarded as an operation group.

[0045] It can be further inferred that in the first few layers of FFT butterfly operation networks with other structures, since Xstep is not greater than M, there is no need to set operation groups; when the number of network layers increases and Xstep is greater than M, operation groups will appear in each layer, and the number of operation groups is N / (Xstep×2), the number of data in each operation group is Xstep×2, and the number of times each operation data group is read is Xstep / M.

[0046] Further, in this embodiment, step S2, the method of calculating the read address and reading the input data from the memory according to the read address includes: S21, calculate the position of the data in the input sequence of the current layer.

[0047] Specifically, in this embodiment, a method for calculating the position of data in the current layer input sequence is given: Calculate the position of the odd data in the current layer input sequence, expressed as: addr_o[i]=addr_start+(i / Xstep)×Xstep+i Calculate the position of the even data in the current layer input sequence, expressed as: addr_e[i]=addr_start+(i / Xstep)×Xstep+Xstep+i Among them, i represents the i-th odd data or even data, i=0,1,…,M-1.

[0048] S22, calculate the value of the starting address addr_start to be read in the next cycle.

[0049] Specifically, in this embodiment, first, the increment value cycle_step of the start address addr_start read in the next cycle compared to the start address addr_start read in the current cycle in the self-increment state is calculated. Considering that when Xstep is not greater than M, it means that the current layer is relatively early, and the continuous C data read in are exactly the data required by M operators, so the data address to be read in the next cycle increases by C, for example Figure 2 layer0 and layer1 in; when Xstep is greater than M, due to the operation group, if the current cycle does not read an operation group, the address step of the next cycle is M; if the current cycle reads an operation group, the address step of the next cycle is Xstep+M, refer to Figure 2 The cycle of layer2 in the example is 10. Therefore, the calculation method of setting the increase value cycle_step in this embodiment is: if Xstep≤M, then set cycle_step=C; otherwise, further determine 2 layer / Is M-1 greater than 0? If so, set cycle_step=M, otherwise set cycle_step=Xstep+M.

[0050] Then, according to the number of reads g in the layer and the number of times G that the data needs to be read, the value of the start address addr_start of the next cycle is calculated using the start address addr_start value of the current cycle and the increment value cycle_step. It is determined whether the current cycle is the last read of this layer, that is, whether g<G-1 is satisfied. If so, addr_start=addr_start+cycle_step is set, otherwise addr_start=0.

[0051] S23, calculating the number of times the current layer is read in the next cycle g.

[0052] Specifically, in this embodiment, it is determined whether the number of read times g of the current layer in the current cycle reaches the number of times G required to read data for the current layer, that is, it is determined whether g<G-1 is satisfied; if not, that is, g<G-1 is satisfied, then the number of read times in the current cycle is increased by 1, which is used as the number of read times g in the next cycle; if reached, that is, g<G-1 is not satisfied, then it is determined that the calculation enters a new layer, and the number of read times g of the current layer is set to 0.

[0053] S24, calculating the number of times o of reading the data in the current operation group in the next cycle.

[0054] Specifically, in this embodiment, it is determined whether the address difference Xstep in the current layer is greater than the number M of butterfly operators, that is, whether there is an operation group in the current layer; if so, it is further determined whether the number of reads o in the current cycle is less than the maximum number Xstep / M-1 in the operation group; if so, the number of reads in the current cycle is increased by 1, which is used as the number of reads o in the next cycle; otherwise, it is determined that the calculation enters a new layer, and the number of reads o in the current layer is set to 0. If there is no operation group in the current layer (Xstep≤M), the number of reads o is set to 0.

[0055] S25, performing parity cross processing on the original address to obtain a hardware read address.

[0056] When Xstep is greater than M, the difference between each pair of addr_o and addr_e in the operation group is an integer multiple of C, so the input of an operator needs to read the same storage unit (RAM) twice, which will generate data waiting cycles and reduce the efficiency of the operation. Figure 2 As shown, it can be seen that M=2, C=4, and N=8, so ram0 to ram3 are used to store the 8 data in one layer, so data0 and data4 are both stored in ram0; when reading in the 9th cycle, it is found that the odd input of the first operator is data0 and the even input is data4, and ram0 needs to be read twice.

[0057] To solve this problem, addr_o and addr_e are analyzed. These two sets of values ​​represent the position of the current read data in the current layer input sequence N or the previous layer output result sequence, and the sequence is stored in the memory. Therefore, the high bits [log2N-1:log2C] of addr_o and addr_e represent the read address of the corresponding storage unit, and the low bits [log2C-1:0] represent the storage unit number corresponding to the address. For example, Figure 2 The addr_o of the second operator in the 5th cycle is 001, and its high bit is [2:2] with a value of 0, which means that the read address of the storage unit it selects is 0, and its low bit is [1:0] with a value of 01, which means that the storage unit 01 among the 4 storage units in the memory is selected.

[0058] Therefore, this embodiment designs a parity interleaving access mode of a memory: For odd data, use it as a reference and let its position in the current layer input sequence be its hardware read address; For even data, determine whether the address difference Xstep in the current layer is greater than the number of butterfly operators M. If so, invert the low bit [log2C-1:0] of the position of the even data in the current layer input sequence to obtain its hardware read address, otherwise use its position in the current layer input sequence as its hardware read address.

[0059] For the negation operation, Figure 2 Take the 9th cycle as an example: addr_o[0]=0000, addr_o[1]=0001, addr_e[0]=0100, addr_e[1]=0101, and invert the lower 2 bits of addr_e to get addr_r_e[0]=0111, addr_r_e[1]=0110. In this way, the four data are scattered into 4 different storage units (RAM), so that they can be read out at the same time, which improves the data processing efficiency of the butterfly operation network.

[0060] S26, reading input data from the memory according to the hardware address.

[0061] Specifically, according to the generated hardware address, the data stored crosswise in the previous layer can be read out in a crosswise manner when needed according to the requirements of the butterfly operation.

[0062] At this point, the address calculation of the input data of all operators in each cycle has been completed. It can be seen that no matter how the value of M changes, the calculated set of addr_r_o[i] and addr_r_e[i] are stored in different C storage units in the memory. In this way, C data can be read out in parallel in one cycle, thus avoiding the reading waiting situation caused by multiple data in a set of data in the same storage unit, effectively improving the data processing efficiency of the butterfly operation network.

[0063] Furthermore, in this embodiment, in step S3, the method of configuring the butterfly operator in the FFT butterfly operation network and using the configured FFT butterfly operation network to process the input data includes: S31, configuring the address and ID of each storage unit in the memory.

[0064] Specifically, in this embodiment, the address of the storage unit is set to the high bit of the position of the data in the current layer input sequence, that is, ram_addr[i]=addr_o[i][log2N-1:log2C]; the ID of the storage unit is set to the low bit of the position of the data in the current layer input sequence, that is, ram_id[i]=addr_o[i][log2C-1:0].

[0065] S32, configure the rotation factor W of the butterfly operator.

[0066] Specifically, in this embodiment, if the number of layers of the current layer is less than or equal to log 2 C, the rotation factor is determined according to the current layer number and the position of the data in the current layer input sequence, that is, ; If the number of layers in the current layer is greater than log2 C, then let the high bit of the address of the storage unit be the ID of the operation group, that is, group_id[i]=ram_addr[i][layer-1:log2C], and perform an XOR operation on all bits of the ID of the operation group to obtain the rotation factor.

[0067] In practical applications, the rotation factor W array is generally stored in advance in a fixed complex form in a memory storing the rotation factors. The storage and reading methods of the rotation factors are well known to those skilled in the art and will not be described in detail in this application.

[0068] Furthermore, in this embodiment, the method of calculating the write address in step S4 and writing the data in the FFT butterfly operation network processing into the memory according to the write address includes: S41, calculating an odd data write address and an even data write address according to the layer number of the next layer.

[0069] Specifically, in this embodiment, first, because the writing process is to prepare for the reading process of the next layer, the layer number of the next layer is set to be the layer number of the current layer plus 1, that is, layer_next=layer+1. Then, the hardware read address is synchronized with the butterfly operator calculation process to obtain the odd data synchronization address addr_o_sync and the even data synchronization address addr_e_sync.

[0070] Then, if the number of layers in the next layer (layer_next) is less than or equal to log 2 C-1, the odd data write address is the odd data synchronization address, and the even data write address is the even data synchronization address, that is, addr_w_o[i]=addr_o_sync[i], addr_w_e[i]=addr_e_sync[i]; if the number of the next layer is greater than log 2 C-1, then determine whether the [layer_next]th bit of the odd data synchronization address of the next layer is 1. If so, the lower bit of the odd data synchronization address is inverted to obtain the odd data write address, that is, addr_w_o[i]=(addr_o_sync[i] / C)×C+(C-1-addr_o_sync[i]%C). If not, the address remains unchanged, that is, addr_w_o[i]=addr_o_sync[i]. Determine whether the [layer_next]th bit of the even data synchronization address of the next layer is 1. If so, the lower bit of the even data synchronization address is inverted to obtain the even data write address, that is, addr_w_e[i]=(addr_e_sync[i] / C)×C+(C-1-addr_e_sync[i]%C). If not, the address remains unchanged, that is, addr_w_e[i]=addr_e_sync[i].

[0071] by Figure 2 Taking cycle 5, cycle 6, cycle 9, and cycle 10 as examples, we calculate that addr_r_o[i]=000, 010, and addr_r_e[i]=001, 011 in cycle 5. Because the four data outputs of the two operators in cycle 5 are all odd inputs of the four operators in cycle 9 and cycle 10, and addr_r_o[i] and addr_o[i] are equal, the write addresses addr_w_o[i] and addr_w_e[i] of the four output data in cycle 5 are equal to addr_o_sync[i] and addr_e_sync[i] synchronized by the operators. The read addresses of the four data in cycle 6 are addr_r_o[i]=100, 110, and addr_r_e[i]=101, 111. The outputs are all even inputs of the four operators in cycle 9 and cycle 10. Their original write addresses are addr_w_o[i]. According to the calculation of the read address process, there are operation groups starting from the 9th cycle, so the even inputs and odd inputs of the two operators need to be allocated to different storage units. Therefore, this embodiment adopts an interleaving method to reverse the lower 2 bits of the 4 output data write addresses generated in the 6th cycle, so that the write address of the 6th cycle becomes addr_w_o[i]=111, 101, and addr_w_e[i]=110, 100. It can be seen from the lower 2 bits that the storage unit exchange of the output data is realized, so that it can be ensured that when reading out in the 9th cycle and the 10th cycle in layer=2, all even input values ​​are read out simultaneously from storage units different from odd values.

[0072] Also, when the output value of the current layer is used as an odd input in the next layer, the address does not need to be changed (no storage unit swapping), but when the output value of the current layer is used as an even input in the next layer, the address needs to be changed (storage units swapping). At the same time, when the [layer_next] bit of the current layer address addr_o_sync[i] and the address addr_e_sync[i] is 0, the output value is an odd input in the next layer, and when this bit is 1, the output value is an even input in the next layer. Therefore, this bit can be used as a flag to indicate whether to cross storage units.

[0073] In this way, cross-writing is completed when writing to the memory, so that when the next layer reads out the data of the butterfly operation, the data required for each cycle can be dispersed in C storage units.

[0074] S42, according to the odd data write address, the odd data output after the FFT butterfly operation network is processed is sent to the corresponding storage unit of the memory; according to the even data write address, the even data output after the FFT butterfly operation network is processed is sent to the corresponding storage unit of the memory.

[0075] Specifically, in this embodiment, the calculated Y_o[i] is sent to the addr_w_o[i] address of the memory, and the calculated Y_e[i] is sent to the addr_w_e[i] address of the memory, completing the entire process from input to output of a set of data of a set of operators. When the last data of the current layer is written back to the memory, and layer_next=L (the current layer is the last calculation layer), the butterfly network completes all data calculations.

[0076] At this point, the temporary data output by each layer of the FFT butterfly operation network is written into the memory.

[0077] S5, the method of calculating the address sequence according to the preset output formula and reading the data from the memory to obtain the final output data includes: First, the output address is initialized to 0, that is, addr_output = 0, and increments itself every cycle. Specifically, C is incremented every cycle.

[0078] Then, considering that data should be read out from C storage cells according to the address and arranged according to ram_id (ram_id is 0 to C-1) in each cycle, but because multiple RAM exchange accesses are designed between layers in this embodiment, all bits of the output address are XORed.

[0079] Finally, the data is read out according to the result of the XOR calculation. If the result of the XOR calculation is 1, the read output address is configured as addr_r_output[i]=addr_output×C+C-1-i; otherwise, the read output address is configured as addr_r_output[i]=addr_output×C+i, where i=1,2,...,C-1.

[0080] In this way, the data read out according to the address sequence is a natural sequence of the FFT results of the input N-length data.

[0081] It should be noted that the result of the division “ / ” operation used in this embodiment is the quotient of the integer division result according to the general meaning of digital circuits, that is, the result is the integer part, for example, the result of 1 / 2 is 0.

[0082] The FFT-based data transmission method provided in this embodiment is based on DMA (Direct Memory Access) design as the technical core, memory (cache RAM) as input, and the inter-layer data calculation order of the FFT butterfly operation network as the requirement. A storage cache array formed by multiple storage units is proposed as the butterfly operation inter-layer cache, and a read-write method of memory cross-use with parity group, layer number and data spacing as parameters is proposed. The design combination of address lines and chip select signals is used to cross-arrange the process and order of data storage and data reading, so that not only can the data used in a single cycle of the current calculation layer always be dispersed in different storage units, and can be read out in parallel according to the jump change requirements of the butterfly operation, but also The data output in a single cycle of the current computing layer is written into different storage units, and preparation is made for the parallel reading requirements of the next computing layer for data; moreover, after the final computing layer, the data stored in the cache array is in the natural order after FFT transformation, and can be directly provided for subsequent use by the computing demander; in addition, the FFT-based data transmission method provided in this embodiment is a flexible switching when switching between layers, that is, the reading and writing of data is a continuous process and will not be interrupted by the switching of the computing layer; the data input and output process is carried out as little as possible without a waiting period (window period), thereby maximizing the FFT operation efficiency and resource utilization efficiency.

[0083] Furthermore, the FFT-based data transmission method provided in this embodiment forms a control structure that is independent of the data type and length, does not add additional storage area, and only cross-uses RAM according to the reading requirements of the next layer when writing data, without adding additional storage resources. Moreover, the FFT-based data transmission method provided in this embodiment has strong compatibility, can flexibly match control modules according to base-2 operator resources, use the same formula group to generate the required control modules, and one control module can simultaneously control the entire butterfly operation network process, consuming less logical resources.

[0084] The following is a specific example to illustrate the implementation process of the FFT-based data transmission method provided by the present application. In this example, the length of the processing sequence N is 64, the number of radix-2 butterfly operators M used is 4, the delay period of the operator used is determined to be 3, and the read delay period of the memory RAM is 1, then the delay period number D of the overall operator is 4.

[0085] The first step is to define the parameters: the maximum level L calculated is log 2 N=6, the number of storage units in the used memory is C=2×M=8, and the number of times a layer of data needs to be read is G=N / C=8.

[0086] Step 2: Initialize variables: Set: current layer layer = 0, current layer read count g = 0, current layer operator input distance Xstep = 1, current group read count o = 0, current layer data start address addr_start = 0. Wait for input data and rotation factors to be ready in their respective memories.

[0087] The third step is to read data continuously: According to the above content, the hardware read addresses addr_r_o and addr_r_e of odd and even data are calculated each cycle, and layer, g, Xstep, o and addr_start are updated. Data is read from the memory and provided to the butterfly operator group for use. At the same time, the write addresses addr_w_o and addr_w_e of odd and even data are calculated each cycle, and the calculated data Y_o and Y_e are written to the memory in parallel.

[0088] In this embodiment, the read and write process is shown in Figures 3 (A) to 3 (F), where Figures 3 (A) to 3 (F) respectively reflect the address addr and data data calculated by the read cycle and the write cycle in each layer when layer=0 to layer=5. It can be seen from Figures 3 (A) to 3 (F) that the green-bottomed portion performs crossover when writing to the memory.

[0089] Step 4: Reading out the sequence: Figure 4 As shown in the figure, after 47 cycles, the FFT calculation process is completed, and the sequence is read out starting from the 48th cycle. Figure 4 It can be seen that when the data is finally read out, the data is read out in natural sequence order according to the read address addr_r_real.

[0090] This embodiment also provides a FFT-based data transmission device, which is used to implement the FFT-based data transmission method as described above. Figure 5 As shown, the FFT-based data transmission device includes: A network construction module is used to construct an FFT butterfly operation network and configure a butterfly operator in the FFT butterfly operation network; the FFT butterfly operation network is used to input data for data processing; A data reading and writing module is used to calculate a read address and read input data from a memory according to the read address; it is also used to calculate a write address and write data in the FFT butterfly operation network processing into the memory according to the write address; The result output module is used to calculate the address sequence according to the preset output formula and read the data from the memory to obtain the final output data.

[0091] In practical applications, the FFT input layer structure can be implemented based on FPGA, hardware programmable SoC or ASIC chip.

[0092] In a specific embodiment, if Figure 6 As shown, the constructed FFT butterfly operation network includes a memory and controller part and a butterfly operation operator group part. Among them, the memory and controller part includes a read address generation unit, an address synchronization unit, a write address generation unit and a memory. The read address generation unit is used to generate an odd data read address and an even data read address; the address synchronization unit is used to synchronize the odd data read address and the even data read address so that the write address generation unit obtains the odd data write address and the even data write address; the memory includes a plurality of (C) storage units RAM, thereby ensuring the reading and writing of multi-channel data. The butterfly operation operator group includes a plurality of (M) butterfly operators, and the butterfly operation operator group reads data from the memory and performs FFT butterfly operation, and returns the operation result to the memory for storage. When the operation result needs to be output, the operation result can be directly read out sequentially from the memory.

[0093] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.

[0094] The FFT-based data transmission method and device provided in this embodiment include: constructing an FFT butterfly operation network; calculating a read address, and reading input data from a memory according to the read address; configuring a butterfly operator in the FFT butterfly operation network, and using the configured FFT butterfly operation network to process the input data; calculating a write address, and writing the data processed by the FFT butterfly operation network into the memory according to the write address; performing address sequence calculation according to a preset output formula, and reading data from the memory to obtain the final output data. By constructing and configuring a butterfly operation network according to the calculation requirements of the FFT butterfly operation and the array characteristics of the memory, and connecting the original operation results to the memory for cross-processing through the read address and the write address, it is possible to achieve full load operation of all butterfly operators in each cycle in the FFT operation, so that the FFT butterfly operation in each cycle can transmit data with the maximum parallel number, effectively improving the data processing efficiency of the butterfly operation network, and solving the problem of low data processing efficiency of the existing butterfly operation network.

[0095] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A data transmission method based on FFT, characterized in that: include: Construct FFT butterfly operation network; Calculate the read address and read the input data from the memory according to the read address; Configure the butterfly operator in the FFT butterfly operation network, and use the configured FFT butterfly operation network to process the input data; Calculate the write address and write the data in the FFT butterfly operation network processing into the memory according to the write address; The address sequence is calculated according to the preset output formula, and the data is read from the memory to obtain the final output data.

2. The FFT-based data transmission method according to claim 1, characterized in that: The method for constructing the FFT butterfly operation network comprises: Building an FFT butterfly operation network, wherein the FFT butterfly operation network includes multiple layers of butterfly operators; Define the parameters in the FFT butterfly operation network, including the length N of the input data, the number M of butterfly operators participating in the operation per cycle, the number D of butterfly operator cycles, the number L of butterfly operator layers, the number C of storage units in the memory, and the number G of times each layer of butterfly operators needs to read data; Initialize the FFT butterfly network.

3. The FFT-based data transmission method according to claim 2, characterized in that: The method for defining parameters in the FFT butterfly operation network includes: Define the length N of the input data to be an integer power of 2; Define the number M of butterfly operators participating in the operation in each cycle as an integer power of 2; Define N / 2M to be greater than or equal to D; Define the number of layers of the butterfly operator L=log2N; Define the number of storage units C in the memory as the amount of data that can be read in a single cycle, and C=2M; Define the number of times each layer of butterfly operator needs to read data G=N / C.

4. The FFT-based data transmission method according to claim 3, characterized in that: The method for initializing the FFT butterfly operation network includes: Let the number sequence stored in the memory be the address reverse sequence of the input data; Let the current layer be the first layer, and record layer=0; Let the address difference between the two input data of the butterfly operator in the layer and the memory be Xstep=2 i , where i represents the number of layers; Let the number of reads in the layer g=0; Let the starting address addr_start read in each cycle = 0, and the width of addr_start is consistent with log2N+1; Let the lower Log2C bits of each read address addr_r correspond to the number of the storage unit in the memory, and the other higher bits correspond to the read physical address of the storage unit; Let the number of reads of each operation group in the current layer be o=0, wherein the operation group includes at least one butterfly operator.

5. The FFT-based data transmission method according to claim 4, characterized in that: The method of calculating a read address and reading input data from a memory according to the read address comprises: Calculate the position of the data in the current layer input sequence; Calculate the value of the starting address addr_start to be read in the next cycle; Calculate the number of times the current layer is read in the next cycle g; Calculate the number of times o the data is read in the current operation group in the next cycle; Perform odd-even cross processing on the original address to obtain the hardware read address; Read input data from memory according to the hardware address.

6. The FFT-based data transmission method according to claim 5, characterized in that: The method for calculating the position of data in the current layer input sequence includes: Calculate the position of the odd data in the current layer input sequence, expressed as: addr_o[i]=addr_start+(i / Xstep)×Xstep+i Calculate the position of the even data in the current layer input sequence, expressed as: addr_e[i]=addr_start+(i / Xstep)×Xstep+Xstep+i Among them, i represents the i-th odd data or even data, i=0,1,…,M-1.

7. The FFT-based data transmission method according to claim 5, characterized in that: The method for calculating the value of the starting address addr_start read in the next cycle includes: Calculate the increment value cycle_step of the start address addr_start read in the next cycle compared to the start address addr_start read in the current cycle in the auto-increment state; According to the number of reads g in the layer and the number of times G that data needs to be read, the value of the start address addr_start read in the next cycle is calculated using the value of the start address addr_start read in the current cycle and the increment value cycle_step.

8. The FFT-based data transmission method according to claim 5, characterized in that: The method for calculating the number of times the current layer is read in the next cycle g includes: Determine whether the number of reads g of the current layer in the current cycle reaches the number of data reads G required by the current layer; If it is not reached, the number of readings in the current cycle is increased by 1, which is used as the number of readings in the next cycle g; If it is reached, the calculation is judged to enter a new layer, and the number of reads g of the current layer is set to 0.

9. The FFT-based data transmission method according to claim 5, characterized in that: The method for calculating the number of times o of reading data in the current operation group in the next cycle comprises: Determine whether the address difference Xstep in the current layer is greater than the number M of butterfly operators; If yes, then further determine whether the number of reads o in the current cycle is less than Xstep / M-1; If yes, add 1 to the number of reads in the current cycle as the number of reads in the next cycle o; Otherwise, the calculation is judged to enter a new layer and the number of reads o of the current layer is set to 0.

10. The FFT-based data transmission method according to claim 5, characterized in that: The method of performing parity cross processing on the original address to obtain the hardware read address includes: For odd data, let its position in the current layer input sequence be its hardware read address; For even data, determine whether the address difference Xstep in the current layer is greater than the number of butterfly operators M. If so, invert the low bit of the position of the even data in the current layer input sequence to obtain its hardware read address, otherwise use its position in the current layer input sequence as its hardware read address.

11. The FFT-based data transmission method according to claim 4, characterized in that: The method for configuring a butterfly operator in an FFT butterfly operation network comprises: The address and ID of each storage unit in the configuration memory; Configure the twiddle factor W of the butterfly operator.

12. The FFT-based data transmission method according to claim 11, characterized in that: The method for configuring the address and ID of each storage unit in the memory includes: Let the address of the storage unit be the high bit of the position of the data in the current layer input sequence; Let the ID of the storage unit be the low bit of the position of the data in the current layer input sequence.

13. The FFT-based data transmission method according to claim 11, characterized in that: The method for configuring the rotation factor W of the butterfly operator includes: If the number of layers of the current layer is less than or equal to log2C, the rotation factor is determined according to the number of layers and the position of the data in the input sequence of the current layer; If the number of layers of the current layer is greater than log2C, the high bit of the address of the storage unit is set as the ID of the operation group, and an XOR operation is performed on all bits of the ID of the operation group to obtain the corresponding rotation factor.

14. The FFT-based data transmission method according to claim 5, characterized in that: The method of calculating a write address and writing data in the FFT butterfly operation network processing into a memory according to the write address comprises: According to the number of the next layer, the odd data write address and the even data write address are calculated; According to the odd data write address, the odd data output after processing by the FFT butterfly operation network is sent to the corresponding storage unit of the memory; according to the even data write address, the even data output after processing by the FFT butterfly operation network is sent to the corresponding storage unit of the memory.

15. The FFT-based data transmission method according to claim 14, characterized in that: The method for calculating the odd data write address and the even data write address according to the number of the next layer includes: Let the number of the next layer be the number of the current layer plus 1; Synchronize the hardware read address with the butterfly operator calculation process to obtain an odd data synchronization address and an even data synchronization address; If the number of layers of the next layer is less than or equal to log2C-1, the odd data write address is the odd data synchronization address, and the even data write address is the even data synchronization address; If the number of the next layer is greater than log2C-1, determine whether the [layer_next]th bit of the odd data synchronization address of the next layer is 1. If so, invert the low bit of the odd data synchronization address. If not, keep the odd data synchronization address unchanged to obtain the odd data write address; determine whether the [layer_next]th bit of the even data synchronization address of the next layer is 1. If so, invert the low bit of the even data synchronization address. If not, keep the even data synchronization address unchanged to obtain the even data write address.

16. The FFT-based data transmission method according to claim 1, characterized in that: The method of calculating the address sequence according to the preset output formula and reading data from the memory to obtain the final output data includes: Set the output address to be initialized to 0 and increment every cycle; Perform XOR calculation on all bits of the output address; If the result of the XOR calculation is 1, the read output address is configured as addr_r_output[i]=addr_output×C+C-1-i; otherwise, the read output address is configured as addr_r_output[i]=addr_output×C+i, where i=1,2,…,C-1.

17. A data transmission device based on FFT, used to implement the data transmission method based on FFT according to any one of claims 1 to 16, characterized in that: The FFT-based data transmission device comprises: A network construction module is used to construct an FFT butterfly operation network and configure a butterfly operator in the FFT butterfly operation network; the FFT butterfly operation network is used to input data for data processing; A data reading and writing module is used to calculate a read address and read input data from a memory according to the read address; it is also used to calculate a write address and write data in the FFT butterfly operation network processing into the memory according to the write address; The result output module is used to calculate the address sequence according to the preset output formula and read the data from the memory to obtain the final output data.

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