Decoder with redundant code words, electronic equipment and rapid decoding method

Abstract

The invention relates to the technical field of communication, in particular to a decoder with redundant code words, electronic equipment and a fast decoding method, and the decoder comprises a first input signal line and a first output signal line; the decoder module decodes the binary code word input by the first input signal line into a target code word; the shift number generator module is used for adjusting the number of output code word overlapping elements between two adjacent periods through an assembly line and a finite-state machine so as to control the bit number of output code word switching; and the shifter module is used for generating a full-unit weight code word according to the first bit target code word output by the decoder module, an output result of the shift number generator module and the second bit redundancy code word, and outputting the full-unit weight code word through a first output signal line. Therefore, the problems of mismatch and inter-symbol interference can be effectively solved, and an effective solution is provided for high-speed and high-linearity decoding.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a decoder with redundant code words, an electronic device and a fast decoding method. Background Art

[0002] In modern wireless communication systems, fast decoders play a vital role. In order to increase the speed, a variety of decoder work with different ideas has been proposed, including but not limited to the design of efficient decoders based on low-density parity-check codes. As the frequency increases, in broadband and high-linearity application scenarios, dynamic errors such as inter-symbol crosstalk caused by the number of codeword switching times output by the decoder will become more significant. Therefore, the design of decoders with redundant codewords has become a hot topic in the development of decoders in recent years.

[0003] The decoder design in the related art ensures that the number of output codeword switching times is independent of the signal input within the frequency band by adding redundant codewords. This has the following advantages: no oversampling is required, which is beneficial for high-speed applications; there is no limit on the upper and lower bounds of the input signal. However, when processing high-speed data streams, existing decoders cannot provide sufficient efficiency and have problems of mismatch and inter-code interference. Summary of the invention

[0004] The present application provides a decoder with redundant code words, an electronic device and a fast decoding method to solve the problem that the decoder design in the related art cannot solve the mismatch and inter-code crosstalk problems.

[0005] A first aspect of the present application provides a decoder with redundant codewords, including: a first input signal line and a first output signal line; a decoder module, decoding the binary codeword input by the first input signal line into a target codeword; a shift number generator module, adjusting the number of overlapping elements of the output codeword between two adjacent cycles through a pipeline and a finite state machine to control the number of bits switched by the output codeword; a shifter module, generating a full-unit weight codeword according to the first-bit target codeword output by the decoder module, the output result of the shift number generator module and the second-bit redundant codeword, and outputting the full-unit weight codeword through the first output signal line.

[0006] Optionally, the shift number generator module includes a second input signal line, a second output signal line, a first adder unit, a second adder unit, a third adder unit, a subtractor unit, a divider unit, a first delay unit, a second delay unit, a pseudo-random number generator module, a first register unit, a second register unit, a multiplexer module and a modulo P counter module.

[0007] Optionally, the second input signal line is connected to the input port of the first delay unit and the negative input port of the subtractor unit, the positive input port of the subtractor unit is connected to the output port of the first delay unit, the output port of the subtractor unit is connected to the first input port of the first adder unit, the first input port of the multiplexer module is connected to the output port of the pseudo-random number generator module, the second input port of the multiplexer module is connected to the 0 signal, the control port of the multiplexer module is connected to the output port of the first register unit, the output port of the multiplexer module is connected to the first input port of the second adder unit, and the The second input port of the second adder unit is connected to the output port of the second register, the output port of the second adder unit is connected to the second input port of the first adder unit, the output port of the first adder unit is connected to the input port of the divider unit, the output port of the divider unit is connected to the first input port of the third adder unit, the second input port of the third adder unit is connected to the output port of the second delay unit, the output port of the third adder unit is connected to the input port of the modulo-P counter module, and the output port of the modulo-P counter module is connected to the input port of the second delay unit and the second output signal line.

[0008] Optionally, the shift number generator module determines the mean value and probability distribution variance of the output codeword switching times according to the frequency range of the binary codeword input by the first input signal line, and stores the mean value and probability distribution variance of the output codeword switching times in the first register unit and the second register unit, respectively.

[0009] Optionally, the modulo-P counter module includes a third input signal line, a third output signal line, a fourth adder unit, a fifth adder unit, a third delay unit and a finite state machine.

[0010] Optionally, the third input signal line is connected to the first input port of the fourth adder unit, the output port of the third delay unit is connected to the second input port of the fourth adder unit, the output port of the fourth adder unit is connected to the input port of the finite state machine, the input port of the third delay unit and the second input port of the fifth adder unit, the output port of the finite state machine module is connected to the first input port of the fifth adder unit, and the output port of the fifth adder unit is connected to the third output signal line.

[0011] Optionally, the modulo P counter module is implemented using a pipeline technology based on a finite state machine. The modulo P counter module includes a three-stage pipeline, wherein the first stage of the pipeline is a fourth addition unit, which adds input data to the output of the previous cycle; the second stage of the pipeline is a finite state machine and a third delay unit, which inputs the addition result into the finite state machine for overflow compensation processing, and forwards the data back to the previous stage through the third delay unit; the third stage of the pipeline is a fifth addition unit, which adds the overflow compensation value to the addition result to obtain a final remainder result.

[0012] Optionally, a finite state machine is used to correct K-bit addition overflows. Each time a K-bit addition overflow occurs, the modulo 2 K The difference between the result of the operation and the correct output is a finite number of states. The final remainder result is corrected according to the number of overflows, and K is a positive integer.

[0013] Optionally, in the second bit redundant codeword of the shifter module input port, the codeword of a part of the bits is fixed to be all 1s, and the codeword of the remaining bits is fixed to be all 0s.

[0014] A second aspect of the present application provides an electronic device, comprising: a decoder with redundant codewords according to any one of the above embodiments.

[0015] A third aspect of the present application provides a fast decoding method, which uses a decoder with redundant codewords of any one of the above embodiments for decoding, and includes the following steps: obtaining a binary codeword to be decoded and inputting the binary codeword into the decoder; inputting the binary codeword into a decoder module through a first input signal line of the decoder, and the decoder module decodes the binary codeword input by the first input signal line into a target codeword; inputting the binary codeword into a shift number generator module through the first input signal line of the decoder, and the shift number generator module adjusts the number of overlapping elements of the output codeword between two adjacent cycles through a pipeline and a finite state machine to control the number of bits switched by the output codeword; inputting the first bit target codeword output by the decoder module, the output result of the shift number generator module and the second bit redundant codeword into the shifter module, the shifter module generates a full unit weight codeword, and outputs the full unit weight codeword through the first output signal line of the decoder.

[0016] Therefore, this application includes the following beneficial effects:

[0017] The embodiment of the present application can convert binary codewords into full unit weight codewords, and the shift number generator module ensures that the mean value of the number of output codeword switching times is constant and has nothing to do with the input signal by fine-tuning the number of overlapping elements of the output codewords between two adjacent cycles. This method effectively solves the mismatch and inter-code crosstalk problems, and the output codeword activity range of the decoder is adjustable, which allows a balance to be achieved between amplitude mismatch, timing mismatch and inter-code crosstalk suppression, making it a general technology suitable for a variety of design scenarios.

[0018] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0020] Figure 1 A block diagram of a decoder with redundant codewords provided according to an embodiment of the present application;

[0021] Figure 2 A block diagram of a shift number generator module provided according to an embodiment of the present application;

[0022] Figure 3 An example diagram of a pipelined modulo operator module provided according to an embodiment of the present application;

[0023] Figure 4 A timing diagram of a pipelined modulo operation at a normalized frequency of 0.0636 according to an embodiment of the present application;

[0024] Figure 5 A timing diagram of a temperature calculation method provided according to an embodiment of the present application at a normalized frequency of 0.0636;

[0025] Figure 6 This is a timing diagram of the dem algorithm provided according to one embodiment of the present application at a normalized frequency of 0.0636;

[0026] Figure 7 A timing diagram of a pipelined modulo operation at a normalized frequency of 0.4548 according to an embodiment of the present application;

[0027] Figure 8 A timing diagram of a temperature calculation method provided according to an embodiment of the present application at a normalized frequency of 0.4548;

[0028] Fig. 9 This is a timing diagram of the dem algorithm provided according to one embodiment of the present application at a normalized frequency of 0.4548;

[0029] Fig.10 It is a flowchart of a fast decoding method provided according to an embodiment of the present application. Detailed implementation manners

[0030] The embodiments of the present application will be described in detail below. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present application and should not be construed as a limitation to the present application.

[0031] The decoder with redundant codewords, electronic device, and fast decoding method according to the embodiments of the present application will be described below with reference to the accompanying drawings. In view of the problems mentioned in the above background art, the present application provides a decoder with redundant codewords, which can encode digital inputs to ensure that the number of corresponding bit changes between the decoding results of two temporally adjacent digital codewords is a random number with a constant mean. Using the redundant decoded output bit positions, the shift number generator module can quickly control the number of bit positions for output codeword switching by adjusting the number of overlapping elements of the output codewords between two adjacent cycles through a pipeline and a finite state machine, and can effectively solve the mismatch and inter-symbol interference problems.

[0032] Specifically, Figure 1 A block diagram of the decoder with redundant codewords according to the embodiment of the present application.

[0033] As Figure 1 shown, the decoder with redundant codewords includes: a first input signal line, a decoder module 100, a shift number generator module 200, a shifter module 300, and a first output signal line.

[0034] Among them, the decoder module 100 decodes the binary codeword input through the first input signal line into a target codeword; the shift number generator module 200 adjusts the number of overlapping elements of the output codewords between two adjacent cycles through a pipeline and a finite state machine to control the number of bit positions for output codeword switching; the shifter module 300 generates a full unit weight codeword according to the first-bit target codeword output by the decoder module 100, the output result of the shift number generator module 200, and the second-bit redundant codeword, and outputs the full unit weight codeword through the first output signal line.

[0035] In the embodiment of the present application, the decoder module 100 can be an n-bit thermometer decoder, where n is a positive integer. The shifter module 100 has an input port, an output port and a control port, and the control port is used to control the shift number of the shifter; among the M-bit redundant codewords at the input port of the shifter module, half of the codewords are fixed to all 1s, and the other half of the codewords are fixed to all 0s. The first input signal line is connected to the input port of the shift number generator module 200 and the input port of the n-bit thermometer decoder module 100; the output port of the shift number generator module is connected to the control port of the shifter; the N+M (N=2 n , M is a positive integer) bit input port, the N bit input port is connected to the output port of the n-bit thermometer decoder module 100, the M bit input port is connected to the redundant codeword, and the output port of the shifter module 300 is connected to the first output signal line.

[0036] It is understandable that the decoder with redundant codewords in the embodiment of the present application can convert binary codewords into full unit weight codewords, wherein the shift number generator module 200 ensures that the mean value of the number of output codeword switching times is constant and has nothing to do with the input signal by fine-tuning the number of overlapping elements of the output codewords between two adjacent cycles. This method effectively solves the problems of mismatch and inter-code crosstalk. Secondly, the output codeword activity range of the decoder is adjustable, which allows a balance to be achieved between amplitude mismatch, timing mismatch and inter-code crosstalk suppression, making it a general technology suitable for a variety of design scenarios.

[0037] In one embodiment of the present application, Figure 2 As shown, the shift number generator module 200 includes a second input signal line, a second output signal line, a first adder unit 201, a second adder unit 202, a third adder unit 203, a subtractor unit 204, a divider unit 205, a first delay unit 206, a second delay unit 207, a pseudo-random number generator module 208, a first register unit 209, a second register unit 210, a multiplexer module 211 and a modulo P counter module 212.

[0038] Among them, the second input signal line is connected to the input port of the first delay unit 206 and the negative input port of the subtractor unit 204, the positive input port of the subtractor unit 204 is connected to the output port of the first delay unit 206, the output port of the subtractor unit 204 is connected to the first input port of the first adder unit 201, the first input port of the multiplexer module 211 is connected to the output port of the pseudo-random number generator module 208, the second input port of the multiplexer module 211 is connected to the 0 signal, the control port of the multiplexer module 211 is connected to the output port of the first register unit 209, the output port of the multiplexer module 211 is connected to the first input port of the second adder unit 202, and the The second input port of the second adder unit 202 is connected to the output port of the second register, the output port of the second adder unit 202 is connected to the second input port of the first adder unit 201, the output port of the first adder unit 201 is connected to the input port of the divider unit 205, the output port of the divider unit 205 is connected to the first input port of the third adder unit 203, the second input port of the third adder unit 203 is connected to the output port of the second delay unit 207, the output port of the third adder unit 203 is connected to the input port of the modulo-P counter module 212, and the output port of the modulo-P counter module 212 is connected to the input port of the second delay unit 207 and the second output signal line.

[0039] In addition, the shift number generator module 300 of the embodiment of the present application determines the mean and probability distribution variance of the output codeword switching times according to the frequency range of the binary codeword input by the first input signal line, and stores the mean and probability distribution variance of the output codeword switching times in the first register unit 209 and the second register unit 210, respectively.

[0040] In one embodiment of the present application, Figure 3 As shown, the modulo-P counter module 212 includes a third input signal line, a third output signal line, a fourth adder unit 400 , a fifth adder unit 500 , a third delay unit 600 , and a finite state machine 700 .

[0041] Among them, the third input signal line is connected to the first input port of the fourth adder unit 400, the output port of the third delay unit 600 is connected to the second input port of the fourth adder unit 400, the output port of the fourth adder unit 400 is connected to the input port of the finite state machine 700, the input port of the third delay unit 600 is connected to the second input port of the fifth adder unit 500, the output port of the finite state machine 700 module is connected to the first input port of the fifth adder unit 500, and the output port of the fifth adder unit 500 is connected to the third output signal line.

[0042] In one embodiment of the present application, the modulo P counter module 212 is implemented using a pipeline technology based on a finite state machine 700. The modulo P counter module 212 includes a three-stage pipeline, wherein the first stage of the pipeline is the fourth addition unit 400, which adds the input data to the output of the previous cycle; the second stage of the pipeline is the finite state machine 700 and the third delay unit 600, and the result of the addition is input into the finite state machine 700 for overflow compensation processing, and the data is forwarded back to the previous stage through the third delay unit 600; the third stage of the pipeline is the fifth addition unit 500, which adds the overflow compensation value to the addition result to obtain the final remainder result.

[0043] The finite state machine 700 is used to correct the K-bit addition overflow. Each time a K-bit addition overflow occurs, the modulo 2 K The difference between the result of the operation and the correct output is a finite number of states. The final remainder result is corrected according to the number of overflows, and K is a positive integer. For example, taking a 4-bit binary input as an example, the traditional thermometer encoding requires 15 action units. The present invention adds an additional 10 action units on this basis, so that 24 elements out of a total of 25 elements are cyclically selected, while one element remains in a fixed state. Therefore, the original modulo 23 operation is replaced by modulo 24 operation. Since the carry chain in the modulo 24 operation is shorter, this significantly simplifies the hardware implementation. Furthermore, a key observation of the modulo 24 operation is that whenever a 5-bit addition overflow occurs, it is equivalent to a modulo 32 operation, and the difference between the result and the correct output is +8 / +16 / +0. Therefore, after the conventional adder, the present invention introduces a correction module based on a finite state machine, as shown in the schematic diagram Figure 3 As shown. The finite state machine module can adjust the result according to the number of overflows. In addition, the finite state machine module avoids the branch operation in the traditional modular operation, so that the processing speed of more than tens of gigahertz can be achieved through a simple pipeline structure.

[0044] In the actual execution process, the critical path modulo P counter module 212 in the embodiment of the present application is limited, and the embodiment of the present application uses a finite state machine to detect and process overflow, such as Figure 3 As shown, adding a suitable number of redundant units reduces the number of states, which greatly reduces the delay of the critical path and can be applied in higher-speed application scenarios. In addition, since the number of output codeword switching times is a random number with a constant mean, the correlation between mismatch and input codeword is eliminated, and the influence of inter-code crosstalk is reduced. Figures 4 to 9 shown.

[0045] According to the decoder with redundant codewords proposed in the embodiment of the present application, the digital input is encoded to ensure that the number of corresponding bit changes between the decoding results of two digital codewords adjacent in time is a random number with a constant mean. By using the redundant decoded output bits, the shift number generator module adjusts the number of overlapping elements of the output codewords between two adjacent cycles through the pipeline and the finite state machine to quickly control the number of bits of the output codeword switching, which can effectively solve the mismatch and inter-code crosstalk problems.

[0046] Next, the fast decoding method proposed according to the embodiment of the present application is described with reference to the accompanying drawings.

[0047] Fig.10 A flowchart of a fast decoding method provided in an embodiment of the present application.

[0048] like Fig.10 As shown, the fast decoding method comprises the following steps:

[0049] In step S101, a binary codeword to be decoded is obtained and input into a decoder.

[0050] In step S102, a binary codeword is input into a decoder module through a first input signal line of a decoder, and the decoder module decodes the binary codeword input through the first input signal line into a target codeword.

[0051] In step S103, the binary codeword is input into the shift number generator module through the first input signal line of the decoder. The shift number generator module adjusts the number of overlapping elements of the output codeword between two adjacent cycles through the pipeline and the finite state machine to control the number of bits of the output codeword switching.

[0052] In step S104, the first bit target codeword output by the decoder module, the output result of the shift number generator module and the second bit redundant codeword are input into the shifter module, the shifter module generates a full unit weight codeword, and outputs the full unit weight codeword through the first output signal line of the decoder.

[0053] It should be noted that some of the above explanations of the decoder embodiment with redundant codewords are also applicable to the fast decoding method of this embodiment, and they can be referenced to each other. To avoid redundancy, they will not be repeated here.

[0054] According to the fast decoding method proposed in the embodiment of the present application, the decoder ensures that the mean value of the number of output codeword switching times is constant and has nothing to do with the input signal by fine-tuning the number of overlapping elements of the output codewords between two adjacent cycles. This method effectively solves the problems of mismatch and inter-code crosstalk. Secondly, the output codeword activity range of the decoder is adjustable, which allows a balance to be achieved between amplitude mismatch, timing mismatch and inter-code crosstalk suppression, making it a general technology suitable for a variety of design scenarios.

[0055] An embodiment of the present application further provides an electronic device, comprising: a decoder with redundant codewords according to the above embodiment.

[0056] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0057] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0058] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or N executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0059] It should be understood that the various parts of the present application can be implemented in hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, the steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array, a field programmable gate array, etc.

[0060] A person of ordinary skill in the art may understand that all or part of the steps carried by the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the above-mentioned program may be stored in a computer-readable storage medium, which, when executed, includes one of the steps of the method embodiment or a combination thereof.

[0061] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A decoder with redundant codewords, characterized in that: include: a first input signal line and a first output signal line; A decoder module, decoding the binary codeword inputted by the first input signal line into a target codeword; A shift number generator module adjusts the number of overlapping elements of the output codeword between two adjacent cycles through a pipeline and a finite state machine to control the number of bits of the output codeword switching; The shifter module generates a full-unit weight codeword according to the first-bit target codeword output by the decoder module, the output result of the shift number generator module and the second-bit redundant codeword, and outputs the full-unit weight codeword through the first output signal line.

2. The decoder with redundant codewords according to claim 1, characterized in that: The shift number generator module includes a second input signal line, a second output signal line, a first adder unit, a second adder unit, a third adder unit, a subtractor unit, a divider unit, a first delay unit\a second delay unit, a pseudo-random number generator module, a first register unit, a second register unit 210, a multiplexer module and a modulo P counter module.

3. The decoder with redundant codewords according to claim 2, characterized in that: The second input signal line is connected to the input port of the first delay unit and the negative input port of the subtractor unit, the positive input port of the subtractor unit is connected to the output port of the first delay unit, the output port of the subtractor unit is connected to the first input port of the first adder unit, the first input port of the multiplexer module is connected to the output port of the pseudo-random number generator module, the second input port of the multiplexer module is connected to a 0 signal, the control port of the multiplexer module is connected to the output port of the first register unit, the output port of the multiplexer module is connected to the first input port of the second adder unit, and the second The second input port of the adder unit is connected to the output port of the second register, the output port of the second adder unit is connected to the second input port of the first adder unit, the output port of the first adder unit is connected to the input port of the divider unit, the output port of the divider unit is connected to the first input port of the third adder unit, the second input port of the third adder unit is connected to the output port of the second delay unit, the output port of the third adder unit is connected to the input port of the modulo-P counter module, and the output port of the modulo-P counter module is connected to the input port of the second delay unit and the second output signal line.

4. The decoder with redundant codewords according to claim 3, characterized in that: The shift number generator module determines the mean value and probability distribution variance of the output codeword switching times according to the frequency range of the binary codeword input by the first input signal line, and stores the mean value and probability distribution variance of the output codeword switching times in the first register unit and the second register unit respectively.

5. The decoder with redundant codewords according to claim 2, characterized in that: The modulo-P counter module includes a third input signal line, a third output signal line, a fourth adder unit, a fifth adder unit, a third delay unit and a finite state machine.

6. The decoder with redundant codewords according to claim 5, characterized in that: The three input signal lines are connected to the first input port of the fourth adder unit, the output port of the third delay unit is connected to the second input port of the fourth adder unit, the output port of the fourth adder unit is connected to the input port of the finite state machine, the input port of the third delay unit and the second input port of the fifth adder unit, the output port of the finite state machine module is connected to the first input port of the fifth adder unit, and the output port of the fifth adder unit is connected to the third output signal line.

7. The decoder with redundant codewords according to claim 5, characterized in that: The module P counter module is implemented by using a pipeline technology based on a finite state machine. The module P counter module includes a three-stage pipeline, wherein: The first stage of the pipeline is the fourth adding unit, which adds the input data to the output of the previous cycle; The second-stage pipeline is the finite state machine and the third delay unit, the result of the addition is input into the finite state machine for overflow compensation processing, and the data is forwarded back to the previous stage through the third delay unit; The third stage pipeline is the fifth addition unit, which adds the overflow compensation value to the addition result to obtain the final remainder result.

8. The decoder with redundant codewords according to any one of claims 5 to 7, characterized in that: The finite state machine is used to correct K-bit addition overflow. Each time a K-bit addition overflow occurs, the modulo 2 K The difference between the result of the operation and the correct output is a finite number of states. The final remainder result is corrected according to the number of overflows, and K is a positive integer.

9. The decoder with redundant codewords according to claim 1, characterized in that: In the second bit redundant codeword of the input port of the shifter module, the codewords of a part of the bit numbers are fixed to be all 1, and the codewords of the remaining bit numbers are fixed to be all 0.

10. An electronic device, characterized in that: A decoder with redundant codewords comprising any one of claims 1-9.

11. A fast decoding method, characterized in that: The method uses the decoder with redundant codewords according to any one of claims 1 to 9 to perform decoding, comprising the following steps: Obtaining a binary codeword to be decoded, and inputting the binary codeword into the decoder; The binary codeword is input into a decoder module through a first input signal line of the decoder, and the decoder module decodes the binary codeword input through the first input signal line into a target codeword; The binary codeword is input into a shift number generator module through a first input signal line of the decoder, and the shift number generator module adjusts the number of overlapping elements of the output codeword between two adjacent cycles through a pipeline and a finite state machine to control the number of bits of the output codeword switching; The first bit target codeword output by the decoder module, the output result of the shift number generator module and the second bit redundant codeword are input into the shifter module, the shifter module generates a full unit weight codeword, and the full unit weight codeword is output through the first output signal line of the decoder.

Images