Satellite communication link high dynamic time delay simulation system, method, device and medium

Abstract

The invention relates to a satellite communication link high-dynamic time delay simulation system, method, device and medium, the system comprises an upper computer parameter configuration module and an FPGA processing module, the upper computer parameter configuration module updates and issues time delay simulation parameter information, the FPGA processing module receives the time delay simulation parameter information through an FPGA board card, and the FPGA board card sends the time delay simulation parameter information to the upper computer parameter configuration module. The FPGA processing module comprises a parameter processing module, an integer time delay module, a fractional time delay module and a dynamic time delay control module, the dynamic time delay control module carries out hardware sharing on the up-sampling module and the fractional time delay module, two times of up-sampling is integrated into the fractional time delay module while dynamic time delay simulation is carried out, and the dynamic time delay control module carries out hardware sharing on the up-sampling module and the fractional time delay module. The original 1-path data is increased to 2-path parallel data through interpolation; the equipment and the medium are used for storing a computer program, and the time delay simulation method is completed when the program is executed; according to the system, resources occupied by up-sampling can be saved, and the problem that input and output data rates are not matched is solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of satellite communications, and in particular relates to a satellite communication link high-dynamic delay simulation system, method, equipment and medium. Background Art

[0002] Satellite communications have the advantages of wide coverage and being unaffected by land disasters. They can effectively make up for the insufficient coverage of ground cellular networks and have made important contributions to the development of integrated air-space-ground-sea technologies. In the process of satellite communication system development, it is necessary to simulate the channel environment of satellite communications to analyze the actual communication performance of satellites in orbit. Specifically, since satellite communication channel testing is costly and difficult to implement, performance testing usually relies on channel simulation systems. In satellite communication links, due to the long relative distance between transmitters and receivers, the signal propagation delay is much greater than that of land mobile communication systems. At the same time, since the satellite is in constant high-speed motion, the relative position of the transmitter and receiver is constantly changing, and the transmission delay of the satellite channel link is also constantly changing dynamically over time, which will affect the reliability and accuracy of the communication system.

[0003] Due to the dynamic change of delay, the input data rate and output data rate of the dynamic delay module may not match. However, in actual engineering, the output data still needs to be output according to the frequency of the sampling clock. Therefore, in the process of dynamic delay simulation, the problem of matching the input data rate and output data rate of the dynamic delay module must be solved to achieve the purpose of continuous output data.

[0004] In the prior art, the invention with the patent publication number of "CN111064503B" and the name of "A High Dynamic Delay Doppler Simulation System for Satellite Channels" proposes that the problem of mismatch between input data and output data rates can be solved by running the fractional delay module with a clock slightly higher than the sampling frequency; wherein, the higher the clock frequency used by the module, the higher the delay change rate can be achieved, and the delay change rate is determined by the ratio of the radial flight velocity of the satellite to the speed of light. Since the radial flight velocity of the satellite is much lower than the speed of light, the module operation clock only needs to be slightly higher than the sampling clock, so that it can be ensured that in the subsequent steps, when reading data at the sampling frequency, there will be no empty reading, thereby solving the problem of mismatch between input data and output data rates; however, the clock resources in the FPGA are limited, and running the module with a clock slightly higher than the sampling clock will consume additional clock resources, and cross-clock domain processing will bring additional resource loss.

[0005] In the prior art, a master's thesis entitled "Key Technologies and Verification of Long Dynamic Delay Satellite Channel Simulation" (Xu Mengran. Key Technologies and Verification of Long Dynamic Delay Satellite Channel Simulation [D]. University of Electronic Science and Technology of China, 2023.) proposes that when the integer delay part needs to be adjusted, the adjustment is made by changing the read address of the memory; when the integer delay increases, the adjustment is made by pausing data reading and keeping the read address of the memory unchanged; when the integer delay decreases, the adjustment is made by skipping reading the next data and jumping the read address of the memory forward; although this dynamic delay control algorithm solves the problem of mismatch between the input data and output data rates, the continuity of the phase between the output data is destroyed. Summary of the invention

[0006] In order to overcome the shortcomings of the above-mentioned prior art, the purpose of the present invention is to propose a high dynamic delay simulation system, method, device and medium for satellite communication link; the system designs hardware sharing of upsampling and fractional delay modules, integrates 2x upsampling into the fractional delay module while simulating dynamic delay, and increases the number of parallel paths from the original 1-way data to 2-way data through interpolation; 2x upsampling is 2x interpolation, which is combined with the extraction processing part of the slowly changing dynamic delay, and converts the extraction processing that causes the output data to be unable to be read continuously into interpolation processing, thereby solving the problem of mismatch between input data and output data rates caused by dynamic delay simulation, thereby accurately simulating the characteristics of high dynamic delay of satellite communication links.

[0007] In order to achieve the above technical objectives, the technical solutions adopted by the present invention are as follows:

[0008] In the first aspect, a high dynamic delay simulation system for a satellite communication link includes a host computer parameter configuration module and an FPGA processing module; the host computer parameter configuration module calculates and updates the delay simulation parameter information in real time through the host computer and sends the delay simulation parameter information to the FPGA processing module through the network port using the Ethernet UDP protocol, wherein the delay simulation parameter information includes integer delay, fractional delay, and delay change rate; the FPGA processing module receives the delay simulation parameter information through an FPGA board card and realizes the simulation of a dynamic delay channel of a satellite communication system, wherein the FPGA processing module includes a parameter processing module, an integer delay module, a fractional delay module, and a dynamic delay control module:

[0009] The parameter processing module is used to configure and update the integer delay, fractional delay, and delay change rate issued by the host computer, and respectively allocate the integer delay, fractional delay, and delay change rate to the integer delay module and the fractional delay module;

[0010] The integer delay module is used to simulate the integer delay part of the integer multiple sampling period of the satellite communication link delay;

[0011] The fractional delay module simulates the fractional delay part of the non-integer multiple sampling period of the satellite communication link delay through a Farrow structure filter;

[0012] The dynamic delay control module is designed by hardware sharing of upsampling and fractional delay modules, and integrates 2x upsampling into the fractional delay module while simulating dynamic delay, thereby increasing the number of parallel paths of the original 1-path data to 2-path data through interpolation, and dynamically adjusting the integer delay module and the fractional delay module through feedback signals, so as to dynamically adjust the integer delay part and the fractional delay part of the satellite communication link delay in real time.

[0013] In a second aspect, a method for simulating high dynamic delay of a satellite communication link comprises the following steps:

[0014] S1: The host computer parameter configuration module transmits the integer delay, fractional delay, and delay change rate to the FPGA processing module through the host computer;

[0015] S2: The parameter processing module receives the integer delay, fractional delay, and delay change rate issued by the upper computer in step S1 and stores them, wherein the integer delay, fractional delay, and delay change rate issued for the first time in step S1 are the integer delay initial value, the fractional delay initial value, and the delay change rate initial value, respectively, and the delay change rate not issued for the first time in step S1 is the delay change rate update value; the parameter processing module assigns the integer delay initial value to the integer delay module, and assigns the fractional delay initial value, the delay change rate initial value, and the delay change rate update value to the fractional delay module;

[0016] S3: after receiving the input baseband signal and the initial value of the integer delay in step S2, the integer delay module simulates the long delay characteristics of the delay through DDR, FIFO or RAM, and outputs the signal simulated by the integer delay;

[0017] S4: After the fractional delay module receives the signal simulated by the integer delay in step S3 and the initial value of the fractional delay, the initial value of the delay change rate and the update value of the delay change rate in step S2, the fractional delay module accumulates the initial value of the fractional delay and the initial value of the delay change rate through the NCO (digitally controlled oscillator) in the Farrow structure filter, updates them using the delay change rate update value, and then outputs a feedback signal;

[0018] S5: After the integer delay module receives the feedback signal described in step S4, the dynamic delay control module controls the dynamic duty cycle of the read enable in the integer delay module, and inputs the storage data of DDR, FIFO, and RAM in the integer delay module into the fractional delay module according to the dynamic duty cycle of the read enable. The fractional delay module performs fractional interpolation and finally outputs the data after dynamic delay simulation to the outside world.

[0019] Furthermore, step S1 specifically includes the following steps:

[0020] S11: The host computer calculates the real-time communication distance L(t) between the satellite and the ground terminal through the spatial geometric position relationship between the satellite trajectory and the ground terminal, thereby obtaining the satellite communication link transmission delay T(t), which is expressed as:

[0021]

[0022] Where c is the speed of light;

[0023] S12: Assuming that the multiple delay of the signal sampling period at the kth moment is τ(k), the satellite communication link transmission delay T(t) described in step S11 is converted into the multiple delay τ(k) of the signal sampling period, and its expression is:

[0024] τ(k)=T(t)·f s

[0025] Among them, f s is the sampling frequency in Hz;

[0026] S13: Divide the τ(k) in step S12 into integer delays τ int (k) and fractional delay τ frac (k) has two parts, and its expression is:

[0027] τ(k)=τ int (k)+τ frac (k)

[0028] S14: Assume that the multiple delay of the signal sampling period at the k+1th moment is τ(k+1), Δτ(k) is the delay variation from the kth moment to the k+1th moment, and its expression is:

[0029] Δτ(k)=τ(k+1)-τ(k)

[0030] S15: Assuming Δt(k) is the time difference from the kth moment to the k+1th moment, combined with τ(k) and τ(k+1) described in step S13 and step S14, the delay change rate τ var (k) can be expressed as:

[0031]

[0032] S16: Using Ethernet UDP protocol to transmit the integer delay, fractional delay, and delay change rate described in steps S13 and S15 to the FPGA processing module through the network port.

[0033] Furthermore, step S2 specifically includes the following steps:

[0034] S21: The parameter processing module receives the integer delay, fractional delay, and delay change rate sent by the host computer in step S1 and stores them, and assigns the initial value of the integer delay sent by the host computer for the first time to the integer delay module, and assigns the initial value of the fractional delay and the initial value of the delay change rate to the fractional delay module;

[0035] S22: The parameter processing module updates the delay change rate update value that is not sent for the first time in step S1 to the fractional delay module.

[0036] Furthermore, step S3 specifically includes the following steps:

[0037] S31: After the integer delay module receives the input baseband signal and the integer delay initial value in step S2, the baseband signal is subjected to bit width matching and cross-clock domain processing through the write cache in the FIFO1 of the integer delay module, and the processed baseband signal is sent to the DDR;

[0038] S32: The integer delay module completes the long delay characteristic simulation of the baseband signal processed in step S31 in DDR and FIFO2. Specifically, by controlling the write enable of FIFO1 and the read enable of FIFO2, an integer delay simulation accurate to one clock cycle is realized, and the simulated DDR integer delay signal is output to FIFO2.

[0039] S33: In the integer delay simulation, FIFO2 performs bit width matching and cross-clock domain processing on the DDR integer delay signal in step S32 through the read cache, obtains a signal after integer delay simulation, and outputs it to the fractional delay module.

[0040] Furthermore, step S4 specifically includes the following steps:

[0041] S41: After the fractional delay module receives the signal simulated by integer delay in step S3, the NCO changes the delay rate τ of the input var (k) is accumulated and the read enable v(k) of the data cache submodule in the fractional delay module is updated in real time. The specific process is as follows:

[0042] Assume that the fractional delay factor of the accumulator register at time k is R N (k), then the working principle of NCO can be expressed as:

[0043] R N (k) = mod(R N (k-1)+τ var ,1)=μ(k)

[0044] v(k)=R N (k-1)+τ var -mod(RN (k-1)+τ var ,1)

[0045] S42: The data cache submodule is controlled by the read enable v(k) updated in real time in step S41. The data cache submodule receives the signal simulated by integer delay in step S33, and generates and outputs a feedback signal according to the amount of data stored in the FIFO.

[0046] Furthermore, step S5 specifically includes the following steps:

[0047] S51: the integer delay module receives the feedback signal in step S4, and the dynamic delay control module realizes dynamic adjustment of the delay by controlling the dynamic duty cycle of the read enable in the integer delay module, and then inputs the storage data of the DDR, FIFO and RAM in the integer delay module into the fractional delay module according to the dynamic duty cycle of the read enable;

[0048] Specifically, when the amount of data stored in the data cache submodule of the fractional delay module is less than half of the maximum amount of data stored, the read enable of FIFO2 in the integer delay module is changed from 0 to 1 through the feedback signal; when the amount of data stored in the data cache submodule of the fractional delay module is greater than or equal to half of the maximum amount of data stored, the read enable of FIFO2 in the integer delay module is changed from 1 to 0 through the feedback signal; when the amount of data stored in FIFO2 in the integer delay module is less than half of the maximum amount of data stored, the read enable of DDR in the integer delay module is changed from 0 to 1 through the feedback signal; when the amount of data stored in FIFO2 in the integer delay module is greater than or equal to half of the maximum amount of data stored, the read enable of DDR in the integer delay module is changed from 1 to 0 through the feedback signal;

[0049] S52: NCO delay change rate to input τ var (k) Accumulate and calculate the fractional delay factor μ(k) of each clock in real time and update the read enable v(k) of the data cache submodule in the fractional delay module;

[0050] S53: the data buffer submodule receives the signal after integer delay simulation outputted in step S3, and outputs the interpolation base point and the stored data matching the fractional delay factor μ(k) at each clock.

[0051] S54: The fractional delay module receives the storage data of DDR, FIFO, and RAM according to the dynamic duty cycle enabled by the read in step S51. The Farrow structure filter in the fractional delay module uses μ(k) and v(k) output by step S52 and the interpolation base point and stored data output by step S53 to realize the fractional delay partial simulation through the Farrow structure filter and the third-order Lagrange cubic interpolation, and finally outputs the dynamic delay simulation data to the outside world.

[0052] Furthermore, in step S54, 2x upsampling is integrated into the fractional delay module while simulating the dynamic delay, so that the original 1-way data is interpolated to increase the number of parallel paths to 2-way data. 2x upsampling is 2x interpolation, which is combined with the extraction processing part of the slowly changing dynamic delay, thereby converting the extraction processing that causes the output data to be unable to be read continuously into interpolation processing, that is, there is no τ int (k+1)=τ int (k)-1 This situation.

[0053] In a third aspect, an electronic device includes a memory and a processor:

[0054] Memory: used for storing a computer program for implementing the high dynamic delay simulation method of the satellite communication link;

[0055] Processor: used to implement the satellite communication link high dynamic delay simulation method when executing the computer program.

[0056] In a fourth aspect, a computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method for simulating high dynamic delay of a satellite communication link is implemented.

[0057] Compared with the prior art, the present invention has the following beneficial effects:

[0058] 1. In the high dynamic delay simulation method of the satellite communication link of the present invention, the host computer sends down the configuration parameters in real time through step S1, so as to simulate the dynamic delay scenario of the satellite communication link in real time, which has high flexibility and wide application range.

[0059] 2. In the satellite communication link high dynamic delay simulation method of the present invention, through the Farrow structure filter used in step S4, the filter coefficient does not need to be changed when the fractional delay factor changes, so that a large amount of space is not required to store the filter coefficient, saving resource consumption.

[0060] 3. In the satellite communication link high dynamic delay simulation method of the present invention, the upsampling and fractional delay modules are designed for hardware sharing through step S5, and the 2x upsampling is integrated into the fractional delay module during the dynamic delay simulation. The original 1-way data is increased to 2-way data through interpolation in parallel. The 2x upsampling is 2x interpolation, which is combined with the extraction processing part of the slowly changing dynamic delay. The extraction processing that causes the output data to be unable to be read continuously is converted into an interpolation processing, which not only saves the resources occupied by upsampling, but also solves the problem of mismatch between the input data and output data rates caused by the dynamic delay simulation.

[0061] In summary, this method uses the collaborative processing among integer delay module, fractional delay module and dynamic delay control module to design hardware sharing between upsampling and fractional delay modules, integrates 2x upsampling into fractional delay module during dynamic delay simulation, increases the number of parallel paths from the original 1-way data to 2-way data through interpolation, and transforms the extraction processing into interpolation processing, which not only reduces resource consumption, but also solves the problem of input and output data rate mismatch caused by dynamic delay simulation, thereby accurately simulating the characteristics of high dynamic delay of satellite communication links. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 This is a principle block diagram of the satellite communication link high dynamic delay simulation system described in the present invention.

[0063] Figure 2 This is a flow chart of the high dynamic delay simulation method for satellite communication links described in the present invention.

[0064] Figure 3 This is a Farrow structure filter structure diagram of the fractional delay module in the satellite communication link high dynamic delay simulation method described in the present invention.

[0065] Figure 4 It is a Farrow structure diagram of the Lagrangian cubic interpolation filter of the fractional delay module in the satellite communication link high dynamic delay simulation method described in the present invention.

[0066] Figure 5 This is a structural diagram of a dynamic delay control module in a satellite communication link high dynamic delay simulation method described in the present invention.

[0067] Figure 6 This is a hardware structure diagram of a dynamic delay module in a satellite communication link high dynamic delay simulation method described in the present invention. DETAILED DESCRIPTION

[0068] Combine the following Figures 1 to 6 The present invention is described in further detail.

[0069] First, as Figure 1 As shown, a high dynamic delay simulation system for a satellite communication link includes a host computer parameter configuration module and an FPGA processing module; the host computer parameter configuration module calculates and updates the delay simulation parameter information in real time through the host computer and sends the delay simulation parameter information, and uses the Ethernet UDP protocol to transmit the delay simulation parameter information to the FPGA processing module through the network port, and the delay simulation parameter information includes integer delay, fractional delay, and delay change rate; the FPGA processing module receives the delay simulation parameter information through the FPGA board card, and realizes the simulation of the dynamic delay channel of the satellite communication system, and the FPGA processing module includes a parameter processing module, an integer delay module, a fractional delay module and a dynamic delay control module:

[0070] The parameter processing module is used to configure and update the integer delay, fractional delay, and delay change rate issued by the host computer, and respectively allocate the integer delay, fractional delay, and delay change rate to the integer delay module and the fractional delay module;

[0071] The integer delay module is used to simulate the integer delay part of the integer multiple sampling period of the satellite communication link delay;

[0072] The fractional delay module simulates the fractional delay part of the non-integer multiple sampling period of the satellite communication link delay through a Farrow structure filter;

[0073] The dynamic delay control module is designed by hardware sharing of upsampling and fractional delay modules, and integrates 2x upsampling into the fractional delay module while simulating dynamic delay, thereby increasing the number of parallel paths of the original 1-path data to 2-path data through interpolation, and dynamically adjusting the integer delay module and the fractional delay module through feedback signals, so as to dynamically adjust the integer delay part and the fractional delay part of the satellite communication link delay in real time.

[0074] Second, as Figure 2 As shown, a method for simulating high dynamic delay of a satellite communication link comprises the following steps:

[0075] S1: The host computer parameter configuration module calculates the real-time communication distance between the satellite and the ground terminal within the satellite visible window time through the host computer, thereby obtaining the transmission delay simulation parameter information of the satellite communication link, wherein the transmission delay simulation parameter information includes integer delay, fractional delay, and delay change rate. The host computer parameter configuration module transmits the integer delay, fractional delay, and delay change rate to the FPGA processing module through the host computer, specifically, the host computer uses the Ethernet UDP protocol to transmit the transmission delay simulation parameter information to the FPGA board of the FPGA processing module through the network port;

[0076] S2: The parameter processing module receives the integer delay, fractional delay, and delay change rate issued by the upper computer in step S1 and stores them, wherein the integer delay, fractional delay, and delay change rate issued for the first time in step S1 are the integer delay initial value, the fractional delay initial value, and the delay change rate initial value, respectively, and the delay change rate not issued for the first time in step S1 is the delay change rate update value; the parameter processing module assigns the integer delay initial value to the integer delay module, and assigns the fractional delay initial value, the delay change rate initial value, and the delay change rate update value to the fractional delay module;

[0077] S3: After the integer delay module receives the input baseband signal and the integer delay initial value described in step S2 through the analog-to-digital converter, it simulates the long delay characteristics of the delay through the DDR, FIFO or RAM memory, the delay length is the integer delay initial value, and outputs the signal simulated by the integer delay; Figure 6 As shown, the large-scale delay simulation of the input baseband signal is realized by reading and writing the DDR memory, and the other baseband input signals also complete the simulation of partial integer multiple delay in the FIFO;

[0078] S4: After the fractional delay module receives the signal after integer delay simulation in step S3 and the initial value of fractional delay, the initial value of delay change rate and the updated value of delay change rate in step S2, Figure 3 As shown, the fractional delay module accumulates the initial value of the fractional delay and the initial value of the delay change rate through the NCO (digitally controlled oscillator) in the Farrow structure filter (i.e., a variable fractional delay filter based on the Farrow structure) and updates them using the delay change rate update value. This process can achieve high-precision characteristics of the delay, thereby outputting a feedback signal;

[0079] S5: After the integer delay module receives the feedback signal described in step S4, the dynamic delay control module controls the dynamic duty cycle of the read enable of the two data outputs in the integer delay module, and inputs the storage data of DDR, FIFO, and RAM in the integer delay module into the fractional delay module according to the dynamic duty cycle of the read enable. The fractional delay module performs fractional interpolation and finally outputs the data after dynamic delay simulation to the outside world.

[0080] Furthermore, step S1 specifically includes the following steps:

[0081] S11: The host computer calculates the real-time communication distance L(t) between the satellite and the ground terminal through the spatial geometric position relationship between the satellite trajectory and the ground terminal, thereby obtaining the satellite communication link transmission delay T(t), which is expressed as:

[0082]

[0083] Where c is the speed of light, c = 3 × 10 8 m / s;

[0084] S12: The essence of digital signal delay is to change the position of the signal sampling point. Assuming that the multiple delay of the signal sampling period at the kth moment is τ(k), the satellite communication link transmission delay T(t) described in step S11 is converted into the multiple delay τ(k) of the signal sampling period. The expression is:

[0085] τ(k)=T(t)·f s

[0086] Among them, f s is the sampling frequency in Hz;

[0087] S13: Divide the τ(k) in step S12 into integer delays τ int (k) and fractional delay τ frac (k) has two parts, and its expression is:

[0088] τ(k)=τ int (k)+τ frac (k)

[0089] S14: Assume that the multiple delay of the signal sampling period at the k+1th moment is τ(k+1), Δτ(k) is the delay variation from the kth moment to the k+1th moment, and its expression is:

[0090] Δτ(k)=τ(k+1)-τ(k)

[0091] S15: Assuming Δt(k) is the time difference from the kth moment to the k+1th moment, combined with τ(k) and τ(k+1) described in step S13 and step S14, the delay change rate τ var (k) can be expressed as:

[0092]

[0093] S16: The integer delay, fractional delay, and delay change rate described in steps S13 and S15 are transmitted to the FPGA processing module through the network port using the Ethernet UDP protocol; wherein the one-time parameters sent by the host computer parameter configuration module include integer delay and fractional delay; and the real-time parameters sent by the host computer parameter configuration module include delay change rate.

[0094] Furthermore, step S2 specifically includes the following steps:

[0095] S21: The parameter processing module receives the integer delay, fractional delay, and delay change rate sent by the host computer in step S1 and stores them, and assigns the initial value of the integer delay sent by the host computer for the first time to the integer delay module, and assigns the initial value of the fractional delay and the initial value of the delay change rate to the fractional delay module;

[0096] S22: The parameter processing module updates the delay change rate update value that is not sent for the first time in step S1 to the fractional delay module.

[0097] Furthermore, step S3 specifically includes the following steps:

[0098] S31: After the integer delay module receives the input baseband signal and the integer delay initial value in step S2 through the analog-to-digital converter, the baseband signal is subjected to bit width matching and cross-clock domain processing through the write cache in the FIFO1 of the integer delay module, and the processed baseband signal is sent to the DDR;

[0099] S32: the integer delay module completes the long delay characteristic simulation of the baseband signal processed in step S31 in DDR and FIFO2;

[0100] Specifically, by controlling the write enable of FIFO1 and the read enable of FIFO2, an integer delay simulation accurate to one clock cycle is realized, and the simulated DDR integer delay signal is output to FIFO2;

[0101] The read and write operations of DDR memory are based on burst mode, which enables the memory to efficiently perform continuous data transmission tasks, but also causes unknown waiting time for DDR to read data. Since the simulation of integer delay is accurate to one clock cycle, the data is cached by FIFO2 to eliminate the impact of unknown waiting time for DDR to read data. The simulation of integer delay we need is achieved by controlling the write enable of FIFO1 and the read enable of FIFO2.

[0102] S33: In the integer delay simulation, FIFO2 performs bit width matching and cross-clock domain processing on the DDR integer delay signal in step S32 through the read cache, obtains a signal after integer delay simulation, and outputs it.

[0103] Further, such as Figure 3 As shown, step S4 specifically includes the following steps:

[0104] S41: NCO (digitally controlled oscillator) is the core control part of the fractional delay module. After the fractional delay module receives the signal simulated by integer delay in step S3, the NCO changes the delay rate τ of the input var (k) is accumulated and the read enable v(k) of the data cache submodule in the fractional delay module is updated in real time. The data cache submodule consists of a FIFO and a shift register. The specific process is as follows:

[0105] Assume that the fractional delay factor of the accumulator register at time k is R N (k), then the working principle of NCO can be expressed as:

[0106] R N (k) = mod(R N (k-1)+τ var ,1)=μ(k)

[0107] v(k)=RN (k-1)+τ var -mod(R N (k-1)+τ var ,1)

[0108] S42: The data cache submodule is controlled by the read enable v(k) updated in real time as described in step S41. The data cache submodule receives the signal simulated by the integer delay as described in step S33, and generates and outputs a feedback signal through the amount of data stored in the FIFO. Since the delay is constantly changing dynamically, the feedback signal is generated through the amount of data stored in the FIFO and fed back to the integer delay module, thereby completing the adjustment of the dynamic delay.

[0109] Furthermore, step S5 specifically includes the following steps:

[0110] S51: the integer delay module receives the feedback signal in step S4, and the dynamic delay control module realizes dynamic adjustment of the delay by controlling the dynamic duty cycle of the read enable in the integer delay module, and then inputs the storage data of the DDR, FIFO and RAM in the integer delay module into the fractional delay module according to the dynamic duty cycle of the read enable;

[0111] Specifically, when performing dynamic adjustment, when the amount of data stored in the data cache submodule of the fractional delay module is less than half of the maximum amount of data stored, the read enable of FIFO2 in the integer delay module is changed from 0 to 1 through the feedback signal, and data is continuously provided to the data cache submodule; when the amount of data stored in the data cache submodule of the fractional delay module is greater than or equal to half of the maximum amount of data stored, in order to prevent data loss caused by overflow, the read enable of FIFO2 in the integer delay module is changed from 1 to 0 through the feedback signal, and data is stopped from being provided to the data cache submodule in the fractional delay module; when the amount of data stored in the data cache submodule of the integer delay module is less than half of the maximum amount of data stored, the read enable of FIFO2 in the integer delay module is changed from 1 to 0 through the feedback signal, and data is stopped from being provided to the data cache submodule in the fractional delay module; When the amount of data stored in FIFO2 in the integer delay module is greater than or equal to half of the maximum amount of data stored, the read enable of DDR in the integer delay module is changed from 1 to 0 through the feedback signal; the supply of data to FIFO2 in the integer delay module is stopped; in this way, the dynamic adjustment of DDR, FIFO2 in the integer delay module and the data cache submodule in the fractional delay module is completed, thereby achieving the goal of dynamic delay simulation;

[0112] S52: NCO delay change rate to input τ var (k) Accumulate and calculate the fractional delay factor μ(k) of each clock in real time and update the read enable v(k) of the data cache submodule in the fractional delay module;

[0113] S53: The data cache submodule receives the signal after integer delay simulation outputted in step S3, and outputs the interpolation base point and the stored data matching the fractional delay factor μ(k) at each clock. Since the delay is constantly changing dynamically, the feedback signal is generated by the amount of data stored in the FIFO and fed back to the integer delay module, thereby completing the adjustment of the dynamic delay.

[0114] S54: Figure 4 As shown, in order to enable the output data to be read out continuously, the fractional delay module receives the storage data of DDR, FIFO, and RAM according to the dynamic duty cycle of the read enable described in step S51, and the Farrow structure filter in the fractional delay module uses μ(k) and v(k) output by step S52 and the interpolation base point and stored data output by step S53 to realize the fractional delay partial simulation through the Farrow structure filter and the third-order Lagrangian cubic interpolation, and finally outputs the dynamic delay simulation data to the outside world.

[0115] Further, such as Figure 5 and Figure 6 As shown, in step S54, 2x upsampling is integrated into the fractional delay module while simulating the dynamic delay, so that the original 1-way data is interpolated to increase the number of parallel paths to 2-way data. 2x upsampling is 2x interpolation, which is combined with the extraction processing part of the slowly changing dynamic delay, thereby converting the extraction processing that causes the output data to be unable to be read continuously into interpolation processing, that is, there is no τ int (k+1)=τ int (k)-1 This situation.

[0116] This process not only saves the resources occupied by upsampling, but also solves the problem that the output data cannot be read out continuously by designing the hardware sharing of upsampling and fractional delay modules, which has certain advantages.

[0117] The processing process of the dynamic delay control module is as follows:

[0118]

[0119] Because the delay range of the Farrow structure filter is (0,1], let 0<τ frac (k)≤1, when τ int (k+1)=τ int (k), the data cache submodule inputs new data to the Farrow structure filter, and the Farrow structure filter outputs data; under this condition, the input and output data are balanced;

[0120] When τ int (k+1)=τ intWhen (k)+1, the data cache submodule does not input new data to the Farrow structure filter, and the Farrow structure filter outputs data; this condition occurs when the distance between the transmitter and the receiver changes from near to far, and the data in the data cache unit will increase, which is equivalent to the interpolation process;

[0121] When τ int (k+1)=τ int When (k)-1, the data cache submodule inputs new data to the Farrow structure filter for two consecutive clock cycles, and the Farrow structure filter outputs data; this condition occurs when the distance between the transmitter and the receiver changes from far to near, which is equivalent to the extraction process, resulting in the inability to continuously read the output data.

[0122] The Farrow structure filter is composed of a direct FIR filter. One advantage of the Farrow structure filter is that the fractional delay factor μ(k) is separated from the specific filter coefficient. In this way, when the fractional delay factor μ(k) changes, the filter coefficient does not need to be changed, so a large amount of space is not required to store the filter coefficient, saving resource consumption. At the same time, if you want to change the delay accuracy, you only need to change the accuracy of the fractional delay factor μ(k). For example, μ(k) = 0.2 means a delay of 0.2 sampling cycles.

[0123] The implementation process of Farrow structure filter is:

[0124] In the communication system, the frequency response of the ideal fractional delay filter is expressed as:

[0125] H d (ω,μ)=e -jωμ

[0126] Among them, H d (ω,μ) is the frequency response of the ideal fractional delay filter, j represents the imaginary part of the complex number, e represents the base of the natural logarithm, ω represents the frequency, and μ∈(0,1] is the fractional delay factor; in order to approximate the frequency response of this ideal fractional delay filter, the transfer function of the fractional delay filter needs to be designed, and its expression is:

[0127]

[0128] Where H(z,μ) is the transfer function of the fractional delay filter, h n (μ) is the filter coefficient. The window function method can calculate the corresponding filter coefficient h according to different approximation criteria. n (μ), thus obtaining a fractional delay filter for a specific μ(k). If an M-order μ(k) polynomial is used to approximate the filter coefficient h n(μ), the fractional delay factor μ(k) can be extracted from the specific filter coefficients, and its expression is:

[0129]

[0130] Among them, M is the order of the polynomial, n is the number of filter coefficients, according to the above H(z,μ) and h n (μ) two formulas, we have:

[0131]

[0132] make:

[0133]

[0134] The expression of the filter transfer function can be simplified to:

[0135]

[0136] Commonly used interpolation algorithms in fractional delay filters based on Farrow structures include linear interpolation, piecewise parabolic interpolation, and Lagrange cubic interpolation. Lagrange cubic interpolation has the advantages of fast sidelobe attenuation and large attenuation degree. Figure 4 As shown, the present invention adopts third-order Lagrange cubic interpolation as the interpolation algorithm of the interpolator in the fractional delay module.

[0137] The implementation process of Lagrange interpolation method is:

[0138] The frequency domain error function can measure the approximation degree of the filter. The frequency domain error function E(e jω ) can be expressed as:

[0139] E(e jω )=H(e jω )-H id (e jω )

[0140] Among them, H(e jω ) is the frequency domain response of the actual FIR fractional delay filter h(n), H id (e jω ) is the ideal fractional delay filter h id (n) frequency domain response.

[0141] According to the maximum flatness criterion, the frequency domain error function E(e jω ) at a frequency of interest ω 0 As flat as possible, that is, at frequency ω 0 Nearby H(e jω ) id (e jω) has the best approximation, which can be expressed as follows:

[0142]

[0143] Generally choose ω 0 =0, we can get:

[0144]

[0145] Among them, μ is the fractional delay factor, which can be expressed by matrix simplification as follows:

[0146] Vh=v

[0147] Among them, the matrix V is a (N+1)×(N+1) Vandermonde matrix, h is a coefficient vector, and v is a fractional delay factor matrix. V, h, and v can be expressed as:

[0148]

[0149] h=[h(0),h(1),...,h(N)] T

[0150] v=[1,μ,μ 2 ,...,μ N ] T

[0151] The coefficient h(n) of the N-order FIR fractional delay filter can be obtained:

[0152]

[0153] Since the essence of digital signal delay is to change the position of the signal sampling point, sampling bias can be used here to describe the degree of change in the delay change rate.

[0154] The range of integer delay simulation depends on the sampling frequency of the signal and the storage capacity of the memory. In the embodiment of the present invention, under the conditions of 200MHz sampling frequency, 16bits quantization of real and imaginary parts, and 8GB DDR storage capacity, the maximum delay that can be simulated is 8GB / 32bits / 200M=10s. When the fractional delay factor μ(k) is 0.2, the accuracy of the sampling deviation can reach 2ppm, where the coefficient matrix is ​​as follows:

[0155]

[0156] In a third aspect, an electronic device includes a memory and a processor:

[0157] Memory: used to store a computer program for implementing the high dynamic delay simulation method of the satellite communication link;

[0158] Processor: used to implement the satellite communication link high dynamic delay simulation method when executing the computer program.

[0159] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the high-dynamic delay simulation method of the satellite communication link is implemented; the computer-readable storage medium includes: a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store program codes.

[0160] The working principle of the present invention is:

[0161] In this system, the host computer parameter configuration module transmits the integer delay, fractional delay and delay change rate to the parameter processing module, and the parameter processing module distributes and updates the above parameters to the integer delay module and the fractional delay module. The integer delay module realizes the simulation of the integer delay part of the integer multiple sampling period, and the fractional delay module realizes the simulation of the fractional delay part of the non-integer multiple sampling period through the Farrow structure filter; the dynamic delay control module designs the hardware sharing of the upsampling and fractional delay modules, and integrates the 2x upsampling into the fractional delay module while simulating the dynamic delay, thereby increasing the number of parallel paths from the original 1-way data to 2-way data through interpolation, and dynamically adjusts the integer delay module and the fractional delay module through the feedback signal, thereby solving the problem of mismatch between the input data and output data rates caused by the dynamic delay simulation.

Claims

1. A satellite communication link high dynamic delay simulation system, comprising a host computer parameter configuration module and an FPGA processing module, characterized in that: The host computer parameter configuration module calculates and updates the delay simulation parameter information in real time through the host computer and sends it down, and uses the Ethernet UDP protocol to transmit the delay simulation parameter information to the FPGA processing module through the network port, and the delay simulation parameter information includes integer delay, fractional delay, and delay change rate; the FPGA processing module receives the delay simulation parameter information through the FPGA board card, and realizes the simulation of the dynamic delay channel of the satellite communication system. The FPGA processing module includes a parameter processing module, an integer delay module, a fractional delay module and a dynamic delay control module: The parameter processing module is used to configure and update the integer delay, fractional delay, and delay change rate issued by the host computer, and respectively allocate the integer delay, fractional delay, and delay change rate to the integer delay module and the fractional delay module; The integer delay module is used to simulate the integer delay part of the integer multiple sampling period of the satellite communication link delay; The fractional delay module simulates the fractional delay part of the non-integer multiple sampling period of the satellite communication link delay through a Farrow structure filter; The dynamic delay control module is designed by hardware sharing of upsampling and fractional delay modules, and integrates 2x upsampling into the fractional delay module while simulating dynamic delay, thereby increasing the number of parallel paths of the original 1-path data to 2-path data through interpolation, and dynamically adjusting the integer delay module and the fractional delay module through feedback signals, so as to dynamically adjust the integer delay part and the fractional delay part of the satellite communication link delay in real time.

2. A method for simulating high dynamic delay of a satellite communication link, based on the high dynamic delay simulation system of a satellite communication link according to claim 1, characterized in that: The following steps are involved: S1: The host computer parameter configuration module transmits the integer delay, fractional delay, and delay change rate to the FPGA processing module through the host computer; S2: The parameter processing module receives the integer delay, fractional delay, and delay change rate issued by the upper computer in step S1 and stores them, wherein the integer delay, fractional delay, and delay change rate issued for the first time in step S1 are the integer delay initial value, the fractional delay initial value, and the delay change rate initial value, respectively, and the delay change rate not issued for the first time in step S1 is the delay change rate update value; the parameter processing module assigns the integer delay initial value to the integer delay module, and assigns the fractional delay initial value, the delay change rate initial value, and the delay change rate update value to the fractional delay module; S3: After receiving the input baseband signal and the initial value of the integer delay in step S2, the integer delay module simulates the long delay characteristics of the delay through DDR, FIFO or RAM, and outputs a signal simulated by the integer delay; S4: After the fractional delay module receives the signal simulated by the integer delay in step S3 and the initial value of the fractional delay, the initial value of the delay change rate and the update value of the delay change rate in step S2, the fractional delay module accumulates the initial value of the fractional delay and the initial value of the delay change rate through the NCO (digitally controlled oscillator) in the Farrow structure filter, updates them using the delay change rate update value, and then outputs a feedback signal; S5: After the integer delay module receives the feedback signal described in step S4, the dynamic delay control module controls the dynamic duty cycle of the read enable in the integer delay module, and inputs the storage data of DDR, FIFO, and RAM in the integer delay module into the fractional delay module according to the dynamic duty cycle of the read enable. The fractional delay module performs fractional interpolation and finally outputs the data after dynamic delay simulation to the outside world.

3. The satellite communication link high dynamic delay simulation method according to claim 2, characterized in that: Step S1 comprises the following steps: S11: The host computer calculates the real-time communication distance L(t) between the satellite and the ground terminal through the spatial geometric position relationship between the satellite trajectory and the ground terminal, thereby obtaining the satellite communication link transmission delay T(t), which is expressed as: Where c is the speed of light; S12: Assume that the multiple delay of the signal sampling period at the kth moment is τ(k) ， The satellite communication link transmission delay T(t) in step S11 is converted into a delay τ(k) which is a multiple of the signal sampling period. The expression is: τ(k)=T(t)·f s Among them, f s is the sampling frequency in Hz; S13: Divide the τ(k) in step S12 into integer delays τ int (k) and fractional delay τ frac (k) has two parts, and its expression is: τ(k)=τ int (k)+τ frac (k) S14: Assume that the multiple delay of the signal sampling period at the k+1th moment is τ(k+1), Δτ(k) is the delay variation from the kth moment to the k+1th moment, and its expression is: Δτ(k)=τ(k+1)-τ(k) S15: Assuming Δt(k) is the time difference from the kth moment to the k+1th moment, combined with τ(k) and τ(k+1) described in step S13 and step S14, the delay change rate τ var (k) can be expressed as: S16: Using Ethernet UDP protocol to transmit the integer delay, fractional delay, and delay change rate described in steps S13 and S15 to the FPGA processing module through the network port.

4. The satellite communication link high dynamic delay simulation method according to claim 2, characterized in that: Step S2 comprises the following steps: S21: The parameter processing module receives the integer delay, fractional delay, and delay change rate sent by the host computer in step S1 and stores them, and assigns the initial value of the integer delay sent by the host computer for the first time to the integer delay module, and assigns the initial value of the fractional delay and the initial value of the delay change rate to the fractional delay module; S22: The parameter processing module updates the delay change rate update value that is not sent for the first time in step S1 to the fractional delay module.

5. The satellite communication link high dynamic delay simulation method according to claim 2, characterized in that: Step S3 includes the following steps: S31: After the integer delay module receives the input baseband signal and the integer delay initial value in step S2, the baseband signal is subjected to bit width matching and cross-clock domain processing through the write cache in the FIFO1 of the integer delay module, and the processed baseband signal is sent to the DDR; S32: The integer delay module completes the long delay characteristic simulation of the baseband signal processed in step S31 in DDR and FIFO2. Specifically, by controlling the write enable of FIFO1 and the read enable of FIFO2, an integer delay simulation accurate to one clock cycle is realized, and the simulated DDR integer delay signal is output to FIFO2. S33: In the integer delay simulation, FIFO2 performs bit width matching and cross-clock domain processing on the DDR integer delay signal in step S32 through the read cache, obtains a signal after integer delay simulation, and outputs it to the fractional delay module.

6. The satellite communication link high dynamic delay simulation method according to claim 2, characterized in that: Step S4 comprises the following steps: S41: After the fractional delay module receives the signal simulated by integer delay in step S3, the NCO changes the delay rate τ of the input var (k) is accumulated and the read enable v(k) of the data cache submodule in the fractional delay module is updated in real time. The specific process is as follows: Assume that the fractional delay factor of the accumulator register at time k is R N (k), then the working principle of NCO can be expressed as: R N (k)=mod(R N (k-1)+τ var ,1)=μ(k) v(k)=R N (k-1)+τ var -mod(R N (k-1)+τ var ,1) S42: The data cache submodule is controlled by the read enable v(k) updated in real time in step S41. The data cache submodule receives the signal simulated by integer delay in step S33, and generates and outputs a feedback signal according to the amount of data stored in the FIFO.

7. The satellite communication link high dynamic delay simulation method according to claim 2, characterized in that: Step S5 comprises the following steps: S51: the integer delay module receives the feedback signal in step S4, and the dynamic delay control module realizes dynamic adjustment of the delay by controlling the dynamic duty cycle of the read enable in the integer delay module, and then inputs the storage data of the DDR, FIFO and RAM in the integer delay module into the fractional delay module according to the dynamic duty cycle of the read enable; When the amount of data stored in the data cache submodule of the fractional delay module is less than half of the maximum amount of data stored, the read enable of FIFO2 in the integer delay module is changed from 0 to 1 through the feedback signal; when the amount of data stored in the data cache submodule of the fractional delay module is greater than or equal to half of the maximum amount of data stored, the read enable of FIFO2 in the integer delay module is changed from 1 to 0 through the feedback signal; when the amount of data stored in FIFO2 in the integer delay module is less than half of the maximum amount of data stored, the read enable of DDR in the integer delay module is changed from 0 to 1 through the feedback signal; when the amount of data stored in FIFO2 in the integer delay module is greater than or equal to half of the maximum amount of data stored, the read enable of DDR in the integer delay module is changed from 1 to 0 through the feedback signal; S52: NCO delay change rate to input τ var (k) Accumulate and calculate the fractional delay factor μ(k) of each clock in real time and update the read enable v(k) of the data cache submodule in the fractional delay module; S53: the data buffer submodule receives the signal after integer delay simulation outputted in step S3, and outputs the interpolation base point and the stored data matching the fractional delay factor μ(k) at each clock. S54: The fractional delay module receives the storage data of DDR, FIFO, and RAM according to the dynamic duty cycle enabled by the read in step S51. The Farrow structure filter in the fractional delay module uses μ(k) and v(k) output by step S52 and the interpolation base point and stored data output by step S53 to realize the fractional delay partial simulation through the Farrow structure filter and the third-order Lagrange cubic interpolation, and finally outputs the dynamic delay simulation data to the outside world.

8. The satellite communication link high dynamic delay simulation method according to claim 7, characterized in that: In step S54, 2x upsampling is integrated into the fractional delay module while simulating the dynamic delay, thereby increasing the number of parallel paths from the original 1-path data to 2-path data through interpolation. 2x upsampling is 2x interpolation, which is combined with the extraction processing part of the slowly changing dynamic delay, thereby converting the extraction processing that causes the output data to be unable to be read continuously into interpolation processing.

9. An electronic device, comprising a memory and a processor, characterized in that: Memory: used to store a computer program for implementing the high dynamic delay simulation method of the satellite communication link; Processor: used to implement the satellite communication link high dynamic delay simulation method when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the satellite communication link high dynamic delay simulation method is implemented.

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