NMOS device structure and method of forming the same

Abstract

An NMOS device structure and a forming method thereof, the device comprising: an SOI substrate, the SOI substrate comprising a top silicon layer, a source region, a drain region and a body contact region distributed in the top silicon layer, the source region and the drain region arranged along a first direction, the body contact region located at least on one side of the top silicon layer between the source region and the drain region along a second direction, the first direction being perpendicular to the second direction; a first isolation structure located at least between the top silicon layer between the source region and the drain region and the body contact region and penetrating the top silicon layer, and the first isolation structure partially overlapping with a gate structure, two ends of the first isolation structure along the first direction being a first isolation end and a second isolation end respectively, the first isolation end being located between the source region and the drain region, and the second isolation end being flush with or exceeding a boundary of the body contact region in the first direction; and the gate structure being located on a surface of the top silicon layer, the source region and the drain region being located on two sides of the gate structure respectively, and the first isolation structure partially overlapping with the gate structure. The parasitic capacitance is reduced and the floating body effect is inhibited.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to an NMOS device structure and a method for forming the same. Background Technology

[0002] Compared to bulk silicon devices, PD-SOI devices (partially depleted SOI devices) fabricated on SOI substrates are widely used in radio frequency, MEMS and other fields due to their superior performance, such as good device isolation, no latch-up effect, and reduced coupling effect between active and passive devices and the substrate.

[0003] However, the kink effect caused by the floating body effect of PD-SOI devices is detrimental in analog circuits. To suppress the floating body effect, the body is usually connected to a fixed potential, thereby controlling the change in body potential; this method is called body contact.

[0004] like Figure 1 and Figure 2 As shown, in a traditional T-gate structure, P+ ions are implanted downwards from the top portion of the T-gate 10 to form a P+ implantation region 20. The P+ implantation region 20 is connected to the P-type body region 30 below the T-gate 10. When the MOS device is operating, the hole carriers accumulated in the P-type body region 30 are discharged through the P+ implantation region 20, thereby reducing the body potential. However, the additional T-gate extension region has significant parasitic capacitance and resistance with the underlying oxide and top silicon layers, causing device performance delay and resulting in degraded circuit performance. Summary of the Invention

[0005] The technical problem solved by this invention is to provide an NMOS device structure and its formation method, which reduces parasitic capacitance and parasitic resistance and has a good floating body effect suppression effect.

[0006] To solve the above-mentioned technical problems, the present invention provides an NMOS device structure, comprising: an SOI substrate, the SOI substrate including a top silicon layer, a source region, a drain region, and a body contact region distributed within the top silicon layer, the source region and the drain region being arranged along a first direction, the body contact region being located at least on one side of the top silicon layer between the source region and the drain region along a second direction, the first direction being perpendicular to the second direction; a first isolation structure located between the top silicon layer and the body contact region between the source region and the drain region, and penetrating the top silicon layer, the two ends of the first isolation structure along the first direction being a first isolation end and a second isolation end, the first isolation end being closer to the source region than the second isolation end, and the first isolation end being located between the source region and the drain region, the second isolation end being flush with or extending beyond the boundary of the body contact region in the first direction; and a gate structure located on the surface of the top silicon layer, the source region and the drain region being located on opposite sides of the gate structure, and the first isolation structure partially overlapping the gate structure.

[0007] Optionally, the body contact area is also located on one side of the leak area along the second direction.

[0008] Optionally, the gate structure is a line-shaped structure extending along the second direction, and one end of the gate structure extends to the surface of the first isolation structure.

[0009] Optionally, the gate structure includes a first partial gate and a second partial gate connected and forming an "L"-shaped structure. The source region and the drain region are located on both sides of the first partial gate. The second partial gate is located on the surface of the first isolation structure and the surfaces of the drain region and the body contact region on both sides of the first isolation structure along the second direction. The second partial gate includes an adjacent first region and a second region. The first region is located on the surface of the drain region. The doped ion type of the first region is the same as that of the drain region. The second region is located on the surface of the body contact region. The doped ion type of the second region is the same as that of the body contact region.

[0010] Optionally, the source region and the body contact region are in contact; the NMOS device structure further includes a silicide barrier layer located on the surface of the source region and the body contact region, and the silicide barrier layer covers the surface at the junction of the source region and the body contact region.

[0011] Optionally, the gate structure includes a first partial gate and a third partial gate connected to form an "L"-shaped structure. The source region and the drain region are located on both sides of the first partial gate. The third partial gate is located on the surface of the first isolation structure, the source region, and the body contact region. The third partial gate includes an adjacent third region and a fourth region. The third region is located on the surface of the source region. The doped ion type of the third region is the same as that of the source region. The fourth region is located on the surface of the body contact region. The doped ion type of the fourth region is the same as that of the body contact region.

[0012] Optionally, the source region and the body contact region are spaced apart.

[0013] Optionally, it further includes: a second isolation structure located within and extending through the top silicon layer, and the second isolation structure surrounding the source region, the drain region, and the body contact region.

[0014] Optionally, the gate structure, the source region, the drain region, and the body contact region have metal silicide films on their surfaces.

[0015] Accordingly, the present invention also provides a method for forming the above-mentioned NMOS device structure, comprising: providing an SOI substrate; forming a plurality of isolation openings in the top silicon layer of the SOI substrate based on a photomask, wherein the bottom of the isolation openings exposes the buried oxide layer surface of the SOI substrate; filling the plurality of isolation openings with material to form a first isolation structure and a shallow trench isolation structure other than the first isolation structure, wherein the first isolation structure and the shallow trench isolation structure other than the first isolation structure penetrate the top silicon layer and contact the buried oxide layer; after forming the first isolation structure and the shallow trench isolation structure other than the first isolation structure, forming a source region, a drain region and a body contact region respectively in the top silicon layer, wherein the source region and the drain region are arranged along a first direction, and the body contact region is located at least in the source region and the drain region. The top silicon layer between the source region and the drain region is located on one side along a second direction, the first direction being perpendicular to the second direction; after forming the source region, the drain region, and the body contact region, a gate structure is formed on the surface of the top silicon layer, the source region and the drain region being located on opposite sides of the gate structure; wherein, the first isolation structure is also located at least between the top silicon layer and the body contact region between the source region and the drain region, and the first isolation structure partially overlaps with the gate structure, the two ends of the first isolation structure along the first direction are a first isolation end and a second isolation end, the first isolation end being closer to the source region than the second isolation end, and the first isolation end being located between the source region and the drain region, the second isolation end being flush with or extending beyond the boundary of the body contact region in the first direction.

[0016] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0017] In the NMOS device structure and its formation method provided by the technical solution of the present invention, since the first isolation structure penetrates the top silicon layer and partially overlaps with the gate structure, the portion of the gate structure overlapping with the first isolation structure is below the first isolation structure rather than the top silicon layer. Therefore, the parasitic capacitance generated between the gate structure and the top silicon layer is reduced. Furthermore, since the first isolation structure is located at least between the top silicon layer and the body contact region between the source and drain regions, and the first isolation terminal is located between the source and drain regions, while the second isolation terminal is flush with or extends beyond the boundary of the body contact region in the first direction, the first isolation structure completely isolates the contact or coupling between the drain region and the body contact region. This reduces the depletion layer width generated between the body contact region and the source / drain, resulting in a smaller resistance between them. This ensures the extraction efficiency of the body contact region and improves the floating body effect suppression effect of the NMOS device. In summary, parasitic capacitance is reduced, the turn-off performance of the device at high frequencies is improved, RF performance is enhanced, and the extraction efficiency of the body contact region is high, resulting in good floating body effect suppression of the NMOS device. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a PD-SOI device.

[0019] Figure 2 yes Figure 1 A schematic diagram of the cross-sectional structure along the A1-A2 direction;

[0020] Figure 3 This is a top view of the NMOS device structure in the first embodiment of the present invention;

[0021] Figure 4 yes Figure 3 A schematic diagram of the cross-sectional structure along the A3-A4 direction;

[0022] Figure 5 This is a top view of the NMOS device structure in the second embodiment of the present invention;

[0023] Figure 6 yes Figure 5 A schematic diagram of the cross-sectional structure along the B1-B2 direction;

[0024] Figure 7 This is a top view of the NMOS device structure in the third embodiment of the present invention;

[0025] Figure 8 yes Figure 7 A schematic diagram of the cross-sectional structure along the A3-A4 direction;

[0026] Figure 9This is a top view of the NMOS device structure in another embodiment of the present invention;

[0027] Figure 10 This is a top view of the NMOS device structure in the fourth embodiment of the present invention;

[0028] Figure 11 yes Figure 10 A schematic diagram of the cross-sectional structure along the A3-A4 direction;

[0029] Figure 12 This is a top view of the NMOS device structure in the fifth embodiment of the present invention;

[0030] Figure 13 yes Figure 12 A schematic diagram of the cross-sectional structure along the B1-B2 direction;

[0031] Figure 14 This is a top view of the NMOS device structure in the fifth embodiment of the present invention;

[0032] Figure 15 yes Figure 14 A schematic diagram of the cross-sectional structure along the B1-B2 direction.

[0033] Explanation of reference numerals in the attached figures:

[0034] 10-T-type gate; 20-P+ injection region; 30-P-type body region;

[0035] 100 - SOI substrate; 101 - Bottom silicon layer; 102 - Buried oxide layer; 103 - Top silicon layer; 110, 210, 310 - Gate structure; 211, 311 - First partial gate; 212 - Second partial gate; 313 - Third partial gate; 120, 220, 320 - First isolation structure; 121, 321 - First isolation terminal; 122, 222, 322 - Second isolation terminal; 130 - Second isolation structure; 140 - Metal silicide film; 150, 151 - Conductive structure; 160 - Silicide barrier layer; I - First region; II - Second region; III - Third region; IV - Fourth region; S - Source region; D - Drain region; B - Body contact region. Detailed Implementation

[0036] As described in the background section, in existing PD-SOI device structures, there is a large parasitic capacitance and resistance between the bulk contact and the bottom silicon of the SOI substrate, which causes delay in the circuit device and reduces RF performance.

[0037] To solve the above-mentioned technical problems, the present invention provides an NMOS device structure and its formation method. By setting a first isolation structure, and making the first isolation structure penetrate through the top silicon layer and partially overlap with the gate structure, the first isolation structure isolates the drain region from the body contact region. The length of the first isolation structure along the first direction is less than the length of the body contact region along the first direction, thereby achieving isolation between the parasitic device and the main device to reduce parasitic resistance and reduce parasitic capacitance, and achieving good floating body effect suppression.

[0038] To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. Additionally, directional terms such as above, below, up, down, upward, downward, left, right, etc., are used relative to exemplary embodiments as they are shown in the figures, with upward or upper directions pointing towards the top of the corresponding figure and downward or lower directions pointing towards the bottom of the corresponding figure.

[0040] [First Embodiment]

[0041] Please refer to Figure 3 and Figure 4 The NMOS device structure includes: an SOI substrate 100, a gate structure 110, and a first isolation structure 120.

[0042] It should be noted that, Figure 3 For ease of understanding, the position of the first isolation structure 120 below the gate structure 110 is indicated by a dashed line.

[0043] SOI substrate 100 includes a bottom silicon layer 101, a buried oxide layer 102, and a top silicon layer 103 stacked sequentially.

[0044] The top silicon layer 103 contains the source region S, the drain region D, and the body contact region B.

[0045] The source region S and drain region D have the opposite doped ion types to the bulk contact region B.

[0046] In this embodiment, the source region S and the drain region D are both N-type heavily doped regions, and the bulk contact region B is a P-type heavily doped region.

[0047] It should be noted that, Figure 1 , Figure 3 , Figure 5 , Figure 7 , Figure 9 , Figure 10 , Figure 12 and Figure 14 In the above embodiments, blue dashed lines represent N+ regions (heavily doped N-type regions), and red dashed lines represent P+ regions (heavily doped P-type regions) to facilitate understanding of the embodiments.

[0048] The source region S and drain region D are arranged along the first direction X, and the body contact region B is located at least on one side of the top silicon layer 103 between the source region S and the drain region D along the second direction Y. The first direction X and the second direction Y are perpendicular to each other.

[0049] In one embodiment, a diode is formed between the body contact region B and the source region to attract holes generated in the float region, thereby achieving pickup.

[0050] In this embodiment, the thickness of the top silicon layer 103 is greater than the depth of the depletion layer. Accordingly, the body contact region B is able to extract holes generated in the floating body region by attracting them through the top silicon layer 103 below the source region S, and has a higher extraction efficiency.

[0051] In one embodiment, the body contact area is located only on one side of the top silicon layer 103 between the source region S and the drain region D along the second direction Y.

[0052] In this embodiment, the body contact region B is located not only on one side of the top silicon layer 103 between the source region S and the drain region D along the second direction Y, but also on one side of the drain region D along the second direction Y. Therefore, the surface of the body contact region B exposed by the top silicon layer 103 is expanded, allowing multiple conductive structures 151 to be formed on the surface of the body contact region B, thereby further improving the extraction efficiency.

[0053] The gate structure 110 is located on the surface of the top silicon layer 103, and the source region S and the drain region D are located on both sides of the gate structure 110.

[0054] Specifically, the gate structure 110 includes: a gate dielectric layer (not shown) located on the surface of the top silicon layer 103, and a gate electrode located on the surface of the gate dielectric layer.

[0055] The gate electrode material includes N-type heavily doped polycrystalline silicon.

[0056] The first isolation structure 120 is located between the top silicon layer 103 and the body contact region B between the source region S and the drain region D, and extends through the top silicon layer 103. In the direction from the gate structure 110 to the SOI substrate 100, the first isolation structure 120 partially overlaps with the gate structure 110.

[0057] The first isolation structure 120 has a first isolation end 121 and a second isolation end 122 at its two ends along the first direction X. The first isolation end 121 is closer to the source region S than the second isolation end 122. The first isolation end 121 is located between the source region S and the drain region D. The second isolation end 122 is flush with the boundary of the body contact region B in the first direction X.

[0058] Since the first isolation structure 120 penetrates the top silicon layer 103 and partially overlaps with the gate structure 110, the portion of the gate structure 110 that overlaps with the first isolation structure 120 is below the first isolation structure 120 rather than the top silicon layer 103. Therefore, the parasitic capacitance generated between the gate structure 110 and the top silicon layer 103 is reduced.

[0059] Furthermore, since the first isolation structure 120 is located at least between the top silicon layer 103 and the body contact region B between the source region S and the drain region D, and the first isolation end 121 is located between the source region S and the drain region D, and the second isolation end 122 is flush with the boundary of the body contact region B in the first direction X, on the one hand, the first isolation structure 120 completely isolates the contact or coupling between the drain region D and the body contact region B, reducing the width of the depletion layer generated between the body contact region B and the source / drain, thus reducing the resistance from the N+ region to the P+ region. On the other hand, the first isolation structure 120 does not overlap with the source region S in the first direction X, providing sufficient channels for the hole to be led out between the source region S and the body contact region B, thereby ensuring the lead-out efficiency of the body contact region B and making the floating body effect of the NMOS device well suppressed.

[0060] In summary, the parasitic capacitance is reduced, the turn-off performance of the device at high frequencies is improved, the RF performance is enhanced, and the output efficiency of the body contact region B is high, resulting in good suppression of the floating body effect of the NMOS device.

[0061] Furthermore, since the first isolation structure 120 penetrates the top silicon layer 103, the first isolation structure 120 is separate from other STI structures (shallow trench isolation structures, e.g.) Figure 4The second isolation structure 130 shown has the same depth, so that during the formation of the NMOS device structure, the first isolation structure 120 can be formed with other shallow trench isolation structures using the same photomask without the need for an additional photomask. Thus, the process of the first isolation structure 120 is simple and the manufacturing cost is low.

[0062] It should be understood that although the first isolation terminal 121 is located between the source region S and the drain region D, in order to ensure that the first isolation structure 120 partially overlaps with the gate structure 110, the distance between the first isolation terminal 121 and the source region S in the first direction X is greater than or equal to zero, but the distance between the first isolation terminal 121 and the drain region D in the first direction X is greater than zero.

[0063] In this embodiment, the first isolation terminal 121 extends to the boundary of the source region S. Therefore, the parasitic capacitance generated between the gate structure 110 and the top silicon layer 103 is minimized to the greatest extent.

[0064] In other embodiments, the first isolation end may also be located at any other position between the source region S boundary and the drain region D boundary.

[0065] The first isolation structure 120 is made of dielectric material.

[0066] Furthermore, the gate structure 110 is a line-shaped structure extending along the second direction Y, and one end of the gate structure 110 extends to the surface of the first isolation structure 120. Therefore, on the one hand, a structure in which the gate structure 110 and the first isolation structure 120 partially overlap can be realized; on the other hand, there is no additional T-shaped extension, thereby greatly reducing parasitic capacitance and improving the suppression effect of floating body effect compared with the conventional T-shaped gate structure contact.

[0067] Furthermore, the source region S and the body contact region B make contact, which helps to improve the device integration density.

[0068] Furthermore, the gate structure 110, source region S, drain region D, and body contact region B all have a metal silicide film 140 on their surfaces. Independent conductive structures are formed on each of these structures, with the bottom of each conductive structure contacting the metal silicide film 140. This further reduces the resistance between each of the gate structure 110, source region S, drain region D, and body contact region B and the conductive structures, thus improving device performance.

[0069] Among them, each conductive structure 150 is located in the gate structure 110, the source region S and the drain region D respectively, and the conductive structure 151 is located on the body contact region B.

[0070] The material of the metal silicide film 140 is, for example, nickel silicide (NiSi) or other CoSi.

[0071] It should be noted that, for ease of understanding and explanation, Figure 3 The metal silicide film 140 is not shown in the figure.

[0072] In this embodiment, the NMOS device structure further includes a second isolation structure 130.

[0073] The second isolation structure 130 is located within and extends through the top silicon layer 103. The second isolation structure 130 surrounds the source region S, the drain region D, and the body contact region B, thereby isolating the device surrounded by the second isolation structure 130 from other devices. In other words, the second isolation structure 130 is used for isolation between devices.

[0074] The material of the second isolation structure 130 is a dielectric material.

[0075] Accordingly, embodiments of the present invention provide a method for forming an NMOS device structure, to form such a structure. Figure 3 and Figure 4 The NMOS device structure in the illustrated embodiment may include:

[0076] SOI substrate 100 is provided.

[0077] Based on a photomask, a plurality of isolation openings (not shown) penetrating the top silicon layer 103 are formed in the top silicon layer 103 of the SOI substrate 100, and the bottom of the isolation openings exposes part of the buried oxide layer 102 surface of the SOI substrate 100.

[0078] Material is filled into several isolation openings to form a first isolation structure 120 and a shallow trench isolation structure other than the first isolation structure 120 (not shown), so that the first isolation structure 120 and the shallow trench isolation structure other than the first isolation structure 120 penetrate the top silicon layer 103 and contact the buried oxide layer 102.

[0079] After forming the first isolation structure 120 and the shallow trench isolation structure other than the first isolation structure 120, the source region S, the drain region D and the body contact region B are formed in the top silicon layer 103, respectively.

[0080] After forming the source region S, drain region D and body contact region B, a gate structure 110 is formed on the surface of the SOI substrate 100, with the source region S and drain region D located on both sides of the gate structure 110.

[0081] It should be noted that for a detailed description of each feature in the embodiments of this formation method, please refer to the detailed explanation and description of each feature in the aforementioned NMOS device structure embodiments, which will not be repeated here.

[0082] In one embodiment, after the gate structure 110 is formed, a metal silicide film 140 is formed on the surface of the gate structure 110, the source region S, the drain region D, and the body contact region B.

[0083] In one embodiment, after the gate structure 110 is formed, a plurality of conductive structures are also formed located in the gate structure 110, the source region S and the drain region D, respectively.

[0084] In one embodiment, the conductive structure can be formed on the metal silicide film 140, that is, the conductive structure is connected to the gate structure 110, the source region S, the drain region D and the body contact region B through the metal silicide film 140.

[0085] In one embodiment, after forming the source region S, the drain region D, and the body contact region B, a second isolation structure 130 is also formed within and through the top silicon layer 103. The second isolation structure 130 surrounds the source region S, the drain region D, and the body contact region B, thereby isolating the device surrounded by the second isolation structure 130 from other devices.

[0086] [Second Embodiment]

[0087] This embodiment is a modified version of the first embodiment. Please refer to [the original text]. Figure 5 and Figure 6 The difference between this embodiment and the first embodiment is that the NMOS device structure further includes a silicide barrier layer 160 (SAB).

[0088] The silicide barrier layer 160 is located on the surface of the source region S and the bulk contact region B, and the silicide barrier layer 160 covers the surface at the junction of the source region S and the bulk contact region B.

[0089] By using the silicide barrier layer 160 to make the surface at the junction of the source region S and the body contact region B a high impedance region, it is beneficial for the hole carriers generated by the device to be discharged from the lightly doped silicon layer under the silicide, thereby further improving the pick-up efficiency of the body contact region B.

[0090] In this embodiment, the depth of the source region S below the silicide barrier layer 160 is the same as the depth of the source region S not covered by the silicide barrier layer 160.

[0091] In other embodiments, when the silicide barrier layer 160 is formed before the source region S and the body contact region B, it can also block implanted ions, resulting in a smaller depth between the source region S and the body contact region B below the silicide barrier layer 160. Correspondingly, the depth of the source region S below the silicide barrier layer 160 is less than the depth of the source region S not covered by the silicide barrier layer 160. This further improves the pick-up efficiency of the body contact region B.

[0092] The material of the silicide barrier layer 160 includes, but is not limited to, silicon oxide or silicon nitride.

[0093] Accordingly, embodiments of the present invention provide a method for forming an NMOS device structure, to form such a structure. Figure 5 and Figure 6 The NMOS device structure shown in the embodiment differs from the embodiment of the above-described method for forming NMOS device structure in that a silicide barrier layer 160 is also formed on the surface of the source region S and the body contact region B.

[0094] In this embodiment, a silicide barrier layer 160 is formed after the source region S and the bulk contact region B are formed.

[0095] In other embodiments, a silicide barrier layer 160 is formed after the formation of the first isolation structure 120 and before the formation of the source region S and the body contact region B.

[0096] [Third Embodiment]

[0097] This embodiment is a modified version of the second embodiment. Please refer to [the original text]. Figure 7 and Figure 8 The difference between this embodiment and the second embodiment is that in this embodiment, the gate structure 110 and the first isolation structure 120 in the second embodiment are replaced by the gate structure 210 and the first isolation structure 220.

[0098] It should be noted that, for ease of understanding, Figure 7 The portion of the gate structure 210 above the first isolation structure 220 is not shown.

[0099] The difference between the first isolation structure 220 and the first isolation structure 120 is that the second isolation end 222 of the first isolation structure 220 extends beyond the boundary between the body contact area B and the drain area D in the first direction X. This further ensures the isolation between the body contact area B and the drain area D.

[0100] In this embodiment, the gate structure 210 includes a first partial gate 211 and a second partial gate 212.

[0101] The first part of the gate 211 and the second part of the gate 212 are connected to form an "L" shaped structure.

[0102] The source region S and the drain region D are located on both sides of the first part of the gate 211.

[0103] The second part of the gate 212 is located on the surface of the first isolation structure 220, and on the surfaces of the drain area D and the body contact area B on both sides of the first isolation structure 220 along the second direction Y.

[0104] The second part of the gate 212 includes adjacent first region I and second region II.

[0105] Specifically, the first region I is located on the surface of the drain region D on the side of the first isolation structure 220 along the second direction Y, and the dopant ion type of the first region I is the same as that of the drain region D. Furthermore, the first region I is heavily N-type doped.

[0106] The second region II is located on the surface of the bulk contact region B on the other side of the first isolation structure 220 along the second direction Y. The doping ion type of the second region II is the same as that of the bulk contact region B. Furthermore, the second region II is heavily p-type doped.

[0107] Specifically, the gate structure 210 includes: a gate dielectric layer (not shown) located on the surface of the top silicon layer 103, and a gate electrode located on the surface of the gate dielectric layer. The gate electrode is made of polysilicon, and the gate electrode in the first region I is heavily N-type doped, while the gate electrode in the second region II is heavily P-type doped.

[0108] In another embodiment, the silicide barrier layer 160 can also be removed based on this embodiment (e.g. Figure 9 (as shown in the image).

[0109] [Fourth Embodiment]

[0110] This embodiment is a modified version of the first embodiment. Please refer to [the original text]. Figure 10 and Figure 11 The difference between this embodiment and the first embodiment is that in this embodiment, the gate structure 110 and the first isolation structure 120 in the second embodiment are replaced by the gate structure 310 and the first isolation structure 320.

[0111] It should be noted that, for ease of understanding, Figure 10 The portion of the gate structure 310 above the first isolation structure 320 is not shown.

[0112] The difference between the first isolation structure 320 and the first isolation structure 120 is that the first isolation end 321 of the first isolation structure 320 is located in the middle region between the source region S and the drain region D.

[0113] Furthermore, the second isolation end 322 of the first isolation structure 320 extends beyond the boundary between the body contact area B and the drain area D in the first direction X. This further ensures the isolation between the body contact area B and the drain area D.

[0114] In this embodiment, the gate structure 310 includes a first partial gate 311 and a third partial gate 313.

[0115] The first part of the gate 311 and the third part of the gate 313 are connected to form an "L" shaped structure.

[0116] The source region S and the drain region D are located on both sides of the first part of the gate 311.

[0117] The third part, gate 313, is located on the surface of the source region S and the body contact region B of the first isolation structure 320.

[0118] The third section of the gate 313 includes adjacent third zone III and fourth zone IV.

[0119] In this region, region III is located on the surface of source region S, and the dopant ion type of region III is the same as that of source region S. Furthermore, region III is heavily N-type doped.

[0120] Region IV is located on the surface of bulk contact region B, and the dopant ion type of Region IV is the same as that of bulk contact region B. Furthermore, Region IV is heavily p-type doped.

[0121] Specifically, the gate structure 310 includes: a gate dielectric layer (not shown) located on the surface of the top silicon layer 103, and a gate electrode located on the surface of the gate dielectric layer. The gate electrode is made of polysilicon, and the gate electrode in region III is heavily N-type doped, while the gate electrode in region IV is heavily P-type doped.

[0122] [Fifth Embodiment]

[0123] This embodiment is a modified version of the first embodiment. Please refer to [the original text]. Figure 12 and Figure 13 The difference between this embodiment and the first embodiment is that in this embodiment, there is a gap between the source region S and the body contact region B.

[0124] By creating a gap between the source region S and the body contact region B, the depletion layer width between them is further reduced. This further reduces the resistance from the N+ region to the P+ region, thereby further improving the pickup efficiency of the body contact region B and enhancing the floating body effect suppression effect of the NMOS device.

[0125] [Sixth Embodiment]

[0126] This embodiment is a modified version of the fifth embodiment. Please refer to [the original text]. Figure 14 and Figure 15 The difference between this embodiment and the fifth embodiment is that in this embodiment, the gate structure 110 and the first isolation structure 120 in the fifth embodiment are replaced by the gate structure 310 and the first isolation structure 320.

[0127] It should be noted that, for ease of understanding, Figure 14 The location of the body contact region B below the gate structure 310 is shown in dashed line.

[0128] For a detailed description of the gate structure 310 and the first isolation structure 320, please refer to the relevant explanations and descriptions in the aforementioned fourth embodiment, which will not be repeated here.

[0129] In other embodiments, gate structure 210 may be used instead of gate structure 110 in the fifth embodiment. Although the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An NMOS device structure, characterized in that, include: The SOI substrate includes a top silicon layer, in which source regions, drain regions, and body contact regions are distributed. The source regions and drain regions are arranged along a first direction, and the body contact regions are located at least on one side of the top silicon layer between the source regions and the drain regions along a second direction, wherein the first direction is perpendicular to the second direction. A first isolation structure is located between the top silicon layer and the body contact region between the source region and the drain region, and extends through the top silicon layer. The two ends of the first isolation structure along the first direction are a first isolation end and a second isolation end, respectively. The first isolation end is closer to the source region than the second isolation end, and the first isolation end is located between the source region and the drain region. The second isolation end is flush with or extends beyond the boundary of the body contact region in the first direction. A gate structure is located on the surface of the top silicon layer, the source region and the drain region are located on both sides of the gate structure, and the first isolation structure partially overlaps with the gate structure.

2. The NMOS device structure according to claim 1, characterized in that, The body contact area is also located on one side of the leak area along the second direction.

3. The NMOS device structure according to claim 1, characterized in that, The gate structure is a line-shaped structure extending along the second direction, and one end of the gate structure extends to the surface of the first isolation structure.

4. The NMOS device structure according to claim 1, characterized in that, The gate structure includes a first partial gate and a second partial gate connected to form an "L"-shaped structure. The source region and the drain region are located on both sides of the first partial gate. The second partial gate is located on the surface of the first isolation structure and the surfaces of the drain region and the body contact region on both sides of the first isolation structure along the second direction. The second partial gate includes an adjacent first region and a second region. The first region is located on the surface of the drain region. The doped ion type of the first region is the same as that of the drain region. The second region is located on the surface of the body contact region. The doped ion type of the second region is the same as that of the body contact region.

5. The NMOS device structure according to any one of claims 3 or 4, characterized in that, The source region is in contact with the body contact region; the NMOS device structure further includes a silicide barrier layer located on the surface of the source region and the body contact region, and the silicide barrier layer covers the surface at the junction of the source region and the body contact region.

6. The NMOS device structure according to claim 1, characterized in that, The gate structure includes a first gate portion and a third gate portion connected to form an "L"-shaped structure. The source region and the drain region are located on both sides of the first gate portion. The third gate portion is located on the surface of the first isolation structure, the source region, and the body contact region. The third gate portion includes an adjacent third region and a fourth region. The third region is located on the surface of the source region, and the doped ion type of the third region is the same as that of the source region. The fourth region is located on the surface of the body contact region, and the doped ion type of the fourth region is the same as that of the body contact region.

7. The NMOS device structure according to claim 1, characterized in that, The source region is spaced apart from the body contact region.

8. The NMOS device structure according to claim 1, characterized in that, Also includes: A second isolation structure is located within and extends through the top silicon layer, and surrounds the source region, the drain region, and the body contact region.

9. The NMOS device structure according to claim 1, characterized in that, The gate structure, the source region, the drain region, and the body contact region have metal silicide films on their surfaces.

10. A method for forming an NMOS device structure, characterized in that, include: Provide SOI substrates; Based on a photomask, a plurality of isolation openings are formed in the top silicon layer of the SOI substrate, and the bottom of the isolation openings exposes the buried oxide layer surface of the SOI substrate. Material is filled into the plurality of isolation openings to form a first isolation structure and a shallow trench isolation structure other than the first isolation structure. The first isolation structure and the shallow trench isolation structure other than the first isolation structure penetrate the top silicon layer and contact the buried oxide layer. After forming the first isolation structure and the shallow trench isolation structure other than the first isolation structure, a source region, a drain region and a body contact region are formed in the top silicon layer, respectively. The source region and the drain region are arranged along a first direction, and the body contact region is located at least on one side of the top silicon layer between the source region and the source region and the drain region along a second direction. The first direction is perpendicular to the second direction. After forming the source region, the drain region, and the body contact region, a gate structure is formed on the surface of the top silicon layer, with the source region and the drain region located on opposite sides of the gate structure, respectively. The first isolation structure is located at least between the top silicon layer and the body contact region between the source region and the drain region, and the first isolation structure partially overlaps with the gate structure. The two ends of the first isolation structure along the first direction are a first isolation end and a second isolation end, respectively. The first isolation end is closer to the source region than the second isolation end, and the first isolation end is located between the source region and the drain region. The second isolation end is flush with or extends beyond the boundary of the body contact region in the first direction.

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