Semiconductor device manufacturing method using stress memorization technique and semiconductor device
By reducing the sidewall thickness after photoresist back etching, the stress distribution in stress memory technology is improved, solving the problem of low electron mobility in the prior art and improving the electron mobility of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHENGDU ZIGUANG SEMICON TECH CO LTD
- Filing Date
- 2023-11-16
- Publication Date
- 2026-07-03
AI Technical Summary
Existing stress memory technology does not take into account the influence of sidewall structures in semiconductor device manufacturing, resulting in low electron mobility.
By performing stress memory technology after photoresist etching, the sidewall thickness is reduced, the contact area between the trench and the silicon nitride layer is increased, thereby improving stress distribution and increasing electron mobility.
It improves the electron mobility of semiconductor devices and enhances electron movement capabilities.
Smart Images
Figure CN120035197B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor device manufacturing technology, and more specifically, to a semiconductor device manufacturing method and semiconductor device employing stress memory technology. Background Technology
[0002] Stress memory technology (SMT) is a stress engineering technique that emerged below the 90nm logic technology node, aiming to improve the speed of NMOS devices. The key feature of SMT is that it significantly accelerates the electron mobility of NMOS devices through tensile stress, thereby increasing the drive current. However, SMT operates like an "invisible man" in integrated circuit manufacturing technology; after the entire process is completed, this technology does not cause any structural changes to the device.
[0003] However, the semiconductor device manufacturing method using stress memory technology in related technologies does not consider the structural influence of sidewalls when applying SMT, resulting in a still low electron mobility of the manufactured semiconductor devices. Summary of the Invention
[0004] The purpose of this disclosure is to provide a semiconductor device manufacturing method and a semiconductor device employing stress memory technology, in order to solve the problems in the aforementioned related technologies.
[0005] To achieve the above objectives, one aspect of this disclosure provides a method for manufacturing a semiconductor device using stress memory technology, the method comprising:
[0006] S101. Take a semiconductor substrate, form a gate structure on the front side of the semiconductor substrate, and form at least two trenches on the front side of the semiconductor substrate, with the gate structure located between two adjacent trenches.
[0007] S102, A sidewall is formed on the side of the gate structure;
[0008] S103. Source / drain regions are formed on both sides of the gate structure, respectively;
[0009] S104, forming a metal silicide barrier region;
[0010] S105, forming a metal silicide layer;
[0011] S106, Perform photoresist back etching;
[0012] The photoresist back etching process includes: covering the front side of the semiconductor substrate with a photoresist layer, exposing and developing it to expose a portion of the sidewalls, etching back to reduce the thickness of the sidewalls, and peeling off the photoresist layer.
[0013] S107. Implement stress memory technology;
[0014] The stress memory technology includes: depositing a first silicon nitride layer on the front side of the semiconductor substrate using ultraviolet light to achieve the stress memory technology; the first silicon nitride layer covers the trench, the sidewall, and the gate structure; and after stress transfer, etching away the first silicon nitride layer.
[0015] Optionally, in step S104, forming the metal silicide barrier region includes:
[0016] S1041. A metal silicide barrier film is deposited on the front side of the semiconductor substrate, the metal silicide barrier film covering the top of the gate structure, the sidewalls, and the area on the semiconductor substrate where the gate structure is not disposed.
[0017] S1042. Etch the metal silicide barrier film layer on the front side of the semiconductor substrate to remove the metal silicide barrier film layer covering a portion of the semiconductor substrate where the gate structure is not provided, thereby forming a metal silicide barrier region.
[0018] Optionally, in step S105, forming the metal silicide layer includes:
[0019] S1051. A metal silicide is deposited on the front side of the semiconductor substrate, and the metal silicide covers the metal silicide barrier film layer and the metal silicide barrier region.
[0020] S1052. Etch the metal silicide on the front side of the semiconductor substrate, retaining the metal silicide in the metal silicide barrier region, and anneal.
[0021] S1053. Etch the metal silicide barrier film layer on the front side of the semiconductor substrate to remove all of the metal silicide barrier film layer on the front side of the semiconductor substrate, and obtain a metal silicide layer.
[0022] Optionally, the manufacturing method further includes:
[0023] S108. A second silicon nitride layer is deposited on the front side of the semiconductor substrate using a dual-frequency radio frequency power supply. The second silicon nitride layer covers the trench, the sidewall, and the gate structure. After stress transfer, the second silicon nitride layer is etched away.
[0024] Optionally, the manufacturing method further includes:
[0025] S109. An insulating layer is deposited on the front side of the semiconductor substrate.
[0026] Optionally, the semiconductor substrate includes a silicon substrate.
[0027] Optionally, in step S102, forming a sidewall on the side of the gate structure includes:
[0028] S1021. A third silicon nitride layer is deposited on the front side of the semiconductor substrate, the third silicon nitride layer covering the top and side of the gate structure, as well as the area on the semiconductor substrate where the gate structure is not disposed.
[0029] S1022, Etch the third silicon nitride layer on the front side of the semiconductor substrate, retaining the third silicon nitride layer covering the side of the gate structure to form a first sidewall;
[0030] S1023. A silicon oxide layer is deposited on the front side of the semiconductor substrate, the silicon oxide layer covering the top of the gate structure and the first sidewall, as well as the area on the semiconductor substrate where the gate structure is not disposed.
[0031] S1024. Etch the silicon oxide layer on the front side of the semiconductor substrate, retaining the silicon oxide layer covering the first sidewall to form the second sidewall.
[0032] Optionally, in step S102, forming a sidewall on the side of the gate structure further includes:
[0033] S1025. A fourth silicon nitride layer is deposited on the front side of the semiconductor substrate, the fourth silicon nitride layer covering the top of the gate structure and the second sidewall, as well as the area on the semiconductor substrate where the gate structure is not disposed.
[0034] S1026. Etch the fourth silicon nitride layer on the front side of the semiconductor substrate, retaining the fourth silicon nitride layer covering the second sidewall to form the third sidewall.
[0035] Optionally, the thickness of the sidewall before reduction is 225A-275A, and the thickness of the sidewall after reduction is 45A-55A.
[0036] A second aspect of this disclosure also provides a semiconductor device manufactured using the above-described semiconductor device manufacturing method employing stress memory technology.
[0037] The above technical solution involves first performing photoresist back etching, followed by stress memory technology (SMT) after that. Photoresist back etching can reduce the thickness of the sidewalls. When the sidewall thickness is reduced, the area of the sidewalls blocking the trench is reduced, which increases the contact area between the first silicon nitride layer and the trench when it is covered. This improves the stress in the trench. Compared with the existing SMT using stress memory technology, it can improve electron mobility, thereby increasing the electron mobility of the manufactured semiconductor device.
[0038] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description
[0039] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:
[0040] Figure 1 This is a schematic flowchart of a manufacturing method according to one embodiment of the present disclosure;
[0041] Figure 2 This is a schematic diagram of step S101 of a manufacturing method according to one embodiment of the present disclosure;
[0042] Figure 3 This is a schematic diagram of step S102 of a manufacturing method according to one embodiment of the present disclosure;
[0043] Figure 4 This is a schematic diagram of step S1041 of a manufacturing method according to one embodiment of the present disclosure;
[0044] Figure 5 This is a schematic diagram of step S1042 of a manufacturing method according to one embodiment of the present disclosure;
[0045] Figure 6 This is a schematic diagram of step S105 of a manufacturing method according to one embodiment of the present disclosure;
[0046] Figure 7 This is a schematic diagram of the structure of the photoresist layer covering step S106 of the manufacturing method of one embodiment of the present disclosure;
[0047] Figure 8 This is a schematic diagram of the structure after etching the photoresist layer in step S106 of the manufacturing method of one embodiment of the present disclosure.
[0048] Figure 9 This is a schematic diagram of the structure covering the first silicon nitride layer in step S107 of the manufacturing method of one embodiment of the present disclosure;
[0049] Figure 10 This is a schematic diagram of the structure of etching the first silicon nitride layer in step S107 of the manufacturing method of one embodiment of the present disclosure;
[0050] Figure 11 This is a schematic diagram of step S108 of a manufacturing method according to one embodiment of the present disclosure;
[0051] Figure 12 This is a schematic diagram of step S109 of a manufacturing method according to one embodiment of the present disclosure.
[0052] Explanation of reference numerals in the attached figures
[0053] 1. Semiconductor substrate; 2. Gate structure; 3. Trench; 4. Sidewall; 41. First sidewall; 42. Second sidewall; 43. Third sidewall; 5. Metal silicide barrier region; 6. Metal silicide layer; 7. Photoresist layer; 8. First silicon nitride layer; 9. Metal silicide barrier film layer; 10. Second silicon nitride layer; 11. Insulating layer; 12. Third silicon nitride layer; 14. Silicon oxide layer; 16. Fourth silicon nitride layer. Detailed Implementation
[0054] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.
[0055] In this disclosure, unless otherwise stated, directional terms such as "upper," "lower," "left," and "right" are generally used to define the orientation of the accompanying drawings, and "inner" and "outer" refer to the inner and outer parts of the relevant components. Furthermore, terms such as "first" and "second" are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0056] In the description of this disclosure, it should also be noted that, unless otherwise expressly specified and limited, the terms "setup" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can be a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.
[0057] like Figures 1-12 As shown, one aspect of this disclosure provides a method for manufacturing a semiconductor device using stress memory technology, the method comprising:
[0058] S101. Take a semiconductor substrate 1, form a gate structure 2 on the front side of the semiconductor substrate 1, and form at least two trenches 3 on the front side of the semiconductor substrate 1, with the gate structure 2 located between two adjacent trenches 3.
[0059] In this design, trenches 3 are respectively formed on both sides of a gate structure 2. Multiple gate structures 2 can be formed on the front side of the semiconductor substrate 1, thus the number of trenches 3 can also be multiple. Adjacent gate structures 2 are separated by trenches 3. The semiconductor substrate 1 may have PMOS regions and NMOS regions, and each PMOS region and NMOS region has a gate structure 2. The gate structure 2 may include multiple layers of material, and the specific configuration can be determined according to actual needs, without further restrictions.
[0060] S102, A sidewall 4 is formed on the side of the gate structure 2. The sidewall 4 will partially block the trench 3.
[0061] S103. Source / drain regions are formed on both sides of the gate structure 2.
[0062] The source / drain regions are located on both sides of the gate structure 2 and on the front side of the semiconductor substrate 1.
[0063] S104, forming a metal silicide barrier region 5;
[0064] S105, Forming a metal silicide layer 6;
[0065] S106, Perform photoresist back etching;
[0066] The photoresist back etching process includes: covering the front side of the semiconductor substrate 1 with a photoresist layer 7 and exposing the sidewalls 4, exposing and developing the substrate, etching back to reduce the thickness of the sidewalls 4, and peeling off the photoresist layer 7.
[0067] S107. Implement stress memory technology;
[0068] The stress memory technology includes: depositing a first silicon nitride layer 8 on the front side of a semiconductor substrate 1 using ultraviolet light to achieve the stress memory technology. The first silicon nitride layer 8 covers the trench 3, sidewall 4 and gate structure 2. After stress transfer, the first silicon nitride layer 8 is etched away.
[0069] In the above technical solution, by first performing photoresist back etching and then performing stress memory technology SMT, the thickness of the sidewall 4 can be reduced. When the thickness of the sidewall 4 is reduced, the shielding range of the sidewall 4 on the trench 3 is reduced, which increases the contact area between the first silicon nitride layer 8 and the trench 3 when it is covered, thereby improving the stress of the trench 3. Compared with the existing SMT using stress memory technology, it can improve the electron mobility, thereby increasing the electron mobility of the manufactured semiconductor device.
[0070] Optionally, the semiconductor substrate 1 includes a silicon substrate. Of course, the semiconductor substrate 1 can also be a substrate of other materials, which are not limited here.
[0071] Optionally, in one embodiment of this disclosure, in step S102, forming a sidewall 4 on the side of the gate structure 2 includes:
[0072] S1021. A third silicon nitride layer 12 is deposited on the front side of the semiconductor substrate 1. The third silicon nitride layer 12 covers the top and side of the gate structure 2, as well as the area on the semiconductor substrate 1 where the gate structure 2 is not disposed.
[0073] S1022, Etch the third silicon nitride layer 12 on the front side of the semiconductor substrate 1, and retain the third silicon nitride layer 12 covering the side of the gate structure 2 to form the first sidewall 41.
[0074] S1023. A silicon oxide layer 14 is deposited on the front side of the semiconductor substrate 1. The silicon oxide layer 14 covers the top of the gate structure 2 and the first sidewall 41, as well as the area on the semiconductor substrate 1 where the gate structure 2 is not disposed.
[0075] S1024. Etch the silicon oxide layer 14 on the front side of the semiconductor substrate 1, leaving the silicon oxide layer 14 covering the first sidewall 41 to form the second sidewall 42.
[0076] S1025. A fourth silicon nitride layer 14 is deposited on the front side of the semiconductor substrate 1. The fourth silicon nitride layer 14 covers the top of the gate structure 2 and the second sidewall 42, as well as the area on the semiconductor substrate 1 where the gate structure 2 is not disposed.
[0077] S1026, Etch the fourth silicon nitride layer 14 on the front side of the semiconductor substrate 1, retaining the fourth silicon nitride layer 14 covering the second sidewall 42 to form the third sidewall 43.
[0078] In this process, the photoresist back etching mainly reduces the thickness of the second sidewall 42. During the photoresist back etching process, the third sidewall 43 is peeled off, and part of the second sidewall 42 is also peeled off, leaving only the first sidewall 41 and part of the second sidewall 42, thereby reducing the thickness of the entire sidewall 4.
[0079] Optionally, in one embodiment of this disclosure, the thickness of the front sidewall 4 is reduced to 225A-275A, and the thickness of the reduced sidewall 4 is 45A-55A. Therefore, the thickness can be reduced by approximately 80%.
[0080] Optionally, in one embodiment of this disclosure, in step S104, forming the metal silicide barrier region 5 includes:
[0081] S1041. A metal silicide barrier film 9 is deposited on the front side of the semiconductor substrate 1. The metal silicide barrier film 9 covers the top of the gate structure 2, the sidewalls 4, and the area on the semiconductor substrate 1 where the gate structure 2 is not provided.
[0082] S1042. Etch the metal silicide barrier film 9 on the front side of the semiconductor substrate 1 to remove the metal silicide barrier film 9 covering a portion of the semiconductor substrate 1 where the gate structure 2 is not provided, so as to form a metal silicide barrier region 5.
[0083] The metal silicide barrier region 5 formed can accommodate metal silicides so that metal silicides can be formed at the desired locations.
[0084] Optionally, in one embodiment of this disclosure, in step S105, forming the metal silicide layer 6 includes:
[0085] S1051. A metal silicide is deposited on the front side of the semiconductor substrate 1, and the metal silicide covers the metal silicide barrier film layer 9 and the metal silicide barrier region 5.
[0086] S1052, Etch the metal silicide on the front side of the semiconductor substrate 1, retain the metal silicide in the metal silicide barrier region 5, and anneal;
[0087] S1053. Etch the metal silicide barrier layer 9 on the front side of the semiconductor substrate 1 to remove all the metal silicide barrier layer 9 on the front side of the semiconductor substrate 1, and obtain the metal silicide layer 6.
[0088] The metal silicide is nickel silicide. After etching away the excess metal silicide and the metal silicide barrier layer 9, only the metal silicide layer 6 in the metal silicide barrier region 5 is retained.
[0089] Optionally, in one embodiment of this disclosure, the manufacturing method further includes:
[0090] S108. A second silicon nitride layer 10 is deposited on the front side of the semiconductor substrate 1 using a dual-frequency radio frequency power supply. The second silicon nitride layer 10 covers the trench 3, sidewalls 4, and gate structure 2. After stress transfer, the second silicon nitride layer 10 is etched away. By using a dual-frequency radio frequency power supply to deposit the second silicon nitride layer 10, tensile stress can be generated, which can better improve electron mobility.
[0091] Optionally, in one embodiment of this disclosure, the manufacturing method further includes:
[0092] S109. An insulating layer 11 is deposited on the front side of the semiconductor substrate 1.
[0093] A second aspect of this disclosure also provides a semiconductor device manufactured using the above-described semiconductor device manufacturing method employing stress memory technology.
[0094] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.
[0095] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.
[0096] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.
Claims
1. A method for manufacturing a semiconductor device using stress memory technology, characterized in that, The manufacturing method includes: S101. Take a semiconductor substrate, form a gate structure on the front side of the semiconductor substrate, and form at least two trenches on the front side of the semiconductor substrate, with the gate structure located between two adjacent trenches. S102, A sidewall is formed on the side of the gate structure; S103. Source / drain regions are formed on both sides of the gate structure, respectively; S104, forming a metal silicide barrier region; S105, forming a metal silicide layer; S106, Perform photoresist back etching; The photoresist back etching process includes: covering the front side of the semiconductor substrate with a photoresist layer, exposing and developing it to expose a portion of the sidewalls, etching back to reduce the thickness of the sidewalls, and peeling off the photoresist layer. S107. Implement stress memory technology; The stress memory technology includes: depositing a first silicon nitride layer on the front side of the semiconductor substrate using ultraviolet light to realize the stress memory technology, wherein the first silicon nitride layer covers the trench, the sidewall and the gate structure, and after stress transfer, the first silicon nitride layer is etched away. S108. A second silicon nitride layer is deposited on the front side of the semiconductor substrate using a dual-frequency radio frequency power supply. The second silicon nitride layer covers the trench, the sidewall, and the gate structure. After stress transfer, the second silicon nitride layer is etched away. S109. An insulating layer is deposited on the front side of the semiconductor substrate.
2. The semiconductor device manufacturing method using stress memory technology according to claim 1, characterized in that, In step S104, forming the metal silicide barrier region includes: S1041. A metal silicide barrier film is deposited on the front side of the semiconductor substrate, the metal silicide barrier film covering the top of the gate structure, the sidewalls, and the area on the semiconductor substrate where the gate structure is not disposed. S1042. Etch the metal silicide barrier film layer on the front side of the semiconductor substrate to remove the metal silicide barrier film layer covering a portion of the semiconductor substrate where the gate structure is not provided, thereby forming a metal silicide barrier region.
3. The semiconductor device manufacturing method employing stress memory technology according to claim 2, characterized in that, In step S105, forming the metal silicide layer includes: S1051. A metal silicide is deposited on the front side of the semiconductor substrate, and the metal silicide covers the metal silicide barrier film layer and the metal silicide barrier region. S1052. Etch the metal silicide on the front side of the semiconductor substrate, retaining the metal silicide in the metal silicide barrier region, and anneal. S1053. Etch the metal silicide barrier film layer on the front side of the semiconductor substrate to remove all of the metal silicide barrier film layer on the front side of the semiconductor substrate, and obtain a metal silicide layer.
4. The semiconductor device manufacturing method employing stress memory technology according to claim 1, characterized in that, The semiconductor substrate includes a silicon substrate.
5. The semiconductor device manufacturing method employing stress memory technology according to any one of claims 1-4, characterized in that, In step S102, forming a sidewall on the side of the gate structure includes: S1021. A third silicon nitride layer is deposited on the front side of the semiconductor substrate, the third silicon nitride layer covering the top and sides of the gate structure, as well as the area on the semiconductor substrate where the gate structure is not disposed. S1022, Etch the third silicon nitride layer on the front side of the semiconductor substrate, retaining the third silicon nitride layer covering the side of the gate structure to form a first sidewall; S1023. A silicon oxide layer is deposited on the front side of the semiconductor substrate, the silicon oxide layer covering the top of the gate structure and the first sidewall, as well as the area on the semiconductor substrate where the gate structure is not disposed. S1024. Etch the silicon oxide layer on the front side of the semiconductor substrate, retaining the silicon oxide layer covering the first sidewall to form the second sidewall.
6. The semiconductor device manufacturing method employing stress memory technology according to claim 5, characterized in that, In step S102, forming a sidewall on the side of the gate structure further includes: S1025. A fourth silicon nitride layer is deposited on the front side of the semiconductor substrate, the fourth silicon nitride layer covering the top of the gate structure and the second sidewall, as well as the area on the semiconductor substrate where the gate structure is not disposed. S1026. Etch the fourth silicon nitride layer on the front side of the semiconductor substrate, retaining the fourth silicon nitride layer covering the second sidewall to form the third sidewall.
7. The semiconductor device manufacturing method employing stress memory technology according to any one of claims 1-4, characterized in that, The thickness of the sidewall before reduction was 225A-275A, and the thickness of the sidewall after reduction was 45A-55A.
8. A semiconductor device manufactured using the semiconductor device manufacturing method employing stress memory technology as described in any one of claims 1-7.