Bonding method of light-emitting chip and display panel

Abstract

The invention relates to the technical field of LED display, in particular to a bonding method of light-emitting chips and a display panel, and the method comprises the steps: providing a growth substrate which is provided with a plurality of light-emitting chips; providing a driving substrate, wherein a plurality of metal bonding pads are arranged on the driving substrate; applying a predetermined pressure at a first temperature, performing counterpoint bonding on the electrodes of the plurality of light-emitting chips and the plurality of metal bonding pads, continuously applying the predetermined pressure at a second temperature greater than the first temperature, and performing counterpoint bonding on the electrodes of the plurality of light-emitting chips and the metal bonding pads; according to the display panel and the manufacturing method thereof, the first temperature and second temperature segmented bonding mode is adopted, the bonding yield between the light-emitting chip and the metal bonding pad is improved, the light-emitting chip can be made smaller, and the finally obtained display panel is better in visual effect and higher in resolution ratio.

Description

Technical Field

[0001] The present invention relates to the field of LED display technology, and in particular to a bonding method for a light-emitting chip and a display panel. Background Art

[0002] The next-generation display technology Micro LED display device has attracted much attention due to its advantages such as high brightness, high contrast and high luminous efficiency. However, due to many problems in its manufacturing process, the product yield cannot be quickly improved. For example, due to the small size of Micro LED itself, the distance between its two PN poles is also very small. When Micro LED is bonded to the metal pad on the backplane, it is easy to cause the PN pole of Micro LED to short-circuit. At the same time, due to process limitations, it is difficult to further reduce the chip electrode size, making it difficult to improve the PPI of display products and affecting the chip's luminous area, which restricts the full commercialization process of Micro LED display products. Summary of the invention

[0003] The purpose of the present invention is to provide a bonding method for a light-emitting chip, which can improve the bonding yield, further reduce the size of the light-emitting chip, and improve the resolution of the terminal product by bonding the light-emitting chip to a driving backplane through different temperature segmentation adjustments.

[0004] Another object of the present invention is to provide a display panel having a higher resolution by bonding a plurality of light-emitting chips using the above method.

[0005] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows:

[0006] In a first aspect, a bonding method for light-emitting chips comprises: providing a growth substrate on which a plurality of light-emitting chips are arranged; providing a driving backplane on which a plurality of metal pads are arranged; applying a predetermined pressure at a first temperature to align and bond the electrodes of the plurality of light-emitting chips to the plurality of metal pads; and continuously applying the predetermined pressure at a second temperature to align and bond the electrodes of the plurality of light-emitting chips to the plurality of metal pads, wherein the second temperature is greater than the first temperature.

[0007] The bonding of the light emitting chip to the metal pad is controlled by the first temperature and the second temperature segmentation, thereby improving the bonding yield.

[0008] Furthermore, providing a growth substrate, on which a plurality of light-emitting chips are arranged, further comprises the step of: forming a first passivation layer between the plurality of light-emitting chips, wherein the first passivation layer covers the plurality of light-emitting chips and only exposes electrodes of the plurality of light-emitting chips away from the surface of the growth substrate.

[0009] By setting a first passivation layer between multiple light-emitting chips and exposing only the electrodes, when the light-emitting chip is bonded to the metal pad, the first passivation layer can limit the flow range of the metal pad or electrode to a certain extent to avoid causing a short circuit.

[0010] Furthermore, the method further comprises: performing a planarization process on a surface of the first passivation layer away from the growth substrate, so that the surface of the first passivation layer away from the growth substrate is at the same height as the electrodes of the plurality of light-emitting chips.

[0011] By arranging the first passivation layer and the electrode of the light-emitting chip at the same height, the electrode of the light-emitting chip can be better contacted with the metal pad later.

[0012] Furthermore, the provision of a driving backplane, on which a plurality of metal pads are arranged, further comprises the step of: forming a second passivation layer between the plurality of metal pads, wherein the second passivation layer covers the plurality of metal pads and only exposes the surface of the plurality of metal pads away from the driving backplane.

[0013] By arranging the second passivation layer between the plurality of metal pads and leaking out of the surface of the metal pads, the second passivation layer can limit the flow range between the metal pads and the electrodes of the light-emitting chip under heating to a certain extent to avoid short circuit.

[0014] Furthermore, the method further comprises: performing a planarization process on a side of the second passivation layer away from the driving backplane, so that the side of the second passivation layer away from the driving backplane is at the same height as the plurality of metal pads.

[0015] The second passivation layer is planarized to facilitate better contact between the metal pad and the electrode of the light-emitting chip.

[0016] Furthermore, before applying a predetermined pressure at the first temperature to align and bond the electrodes of the multiple light-emitting chips to the multiple metal pads, the method also includes the step of aligning the electrodes of the multiple light-emitting chips to the multiple metal pads at room temperature.

[0017] The electrodes of the light-emitting chip are aligned with the multiple metal pads. Due to the van der Waals force between metal atoms, the electrodes of the light-emitting chip and the multiple metal pads will have a certain bonding strength, which is more convenient for subsequent bonding.

[0018] Furthermore, the method further comprises: removing the growth substrate by laser lift-off.

[0019] The growth substrate has poor light transmittance, and the visual effect is better after it is removed.

[0020] In a second aspect, a display panel is provided, comprising a driving backplane and a plurality of light-emitting chips, wherein a plurality of metal pads are arranged on the driving backplane, and the plurality of light-emitting chips are bonded to the plurality of metal pads by the bonding method of the light-emitting chips.

[0021] By adopting the above-mentioned light-emitting chip bonding method, the yield is higher and the display panel resolution is higher.

[0022] Furthermore, the display panel also includes a first passivation layer and a second passivation layer, the first passivation layer covers the outer wall of each of the light-emitting chips and only exposes the electrode surface and the light-emitting surface of each of the light-emitting chips, the second passivation layer covers the outer walls of the multiple metal pads and only exposes the surfaces of the multiple metal pads away from the driving backplane, and the exposed electrode surfaces of the multiple light-emitting chips are aligned and bonded to the exposed surfaces of the multiple metal pads.

[0023] By setting a first passivation layer on the outside of the light-emitting chip and a second passivation layer on the metal pad at the same time, when the electrode of the light-emitting chip is bonded to the metal pad, the electrode and the outside of the metal pad are both wrapped by the first passivation layer or the second passivation layer, which is not easy to short-circuit, and the electrode can be made smaller. Correspondingly, the overall size of the light-emitting chip can be smaller, and the final display panel resolution can be higher.

[0024] Furthermore, the thermal expansion coefficients of the electrodes of the light-emitting chip and the plurality of metal pads are greater than those of the first passivation layer or the second passivation layer.

[0025] The electrodes and metal pads of the light-emitting chip are made of metal, and their thermal expansion coefficients are greater than the first passivation layer and the second passivation layer of the non-conductive material. When heated, the diffusion speed of the electrodes and the metal pads of the light-emitting chip is greater than the first passivation layer and the second passivation layer, which can make the bonding effect of the light-emitting chip and the metal pad better.

[0026] An embodiment of the present invention provides a bonding method for a light-emitting chip and a display panel, the method comprising providing a growth substrate on which a plurality of light-emitting chips are arranged; providing a driving substrate on which a plurality of metal pads are arranged; applying a predetermined pressure at a first temperature to align and bond the electrodes of the plurality of light-emitting chips to the plurality of metal pads, and continuously applying the predetermined pressure at a second temperature greater than the first temperature to align and bond the electrodes of the plurality of light-emitting chips to the metal pads; adopting a segmented bonding method of the first temperature and the second temperature to improve the bonding yield between the light-emitting chip and the metal pad, so that the light-emitting chip can be made smaller, so that the final display panel has a better visual effect and a higher resolution.

[0027] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 A schematic flow chart of a light-emitting chip bonding method provided in an embodiment of the present invention is shown.

[0030] Figure 2 A schematic diagram showing a light-emitting chip disposed on a growth substrate provided by an embodiment of the present invention is shown.

[0031] Figure 3 A schematic structural diagram of a driving backplane provided by an embodiment of the present invention is shown.

[0032] Figure 4 A schematic diagram showing bonding of a light-emitting chip and a metal pad provided by an embodiment of the present invention is shown.

[0033] Figure 5 A schematic flow chart of another light-emitting chip bonding method provided in an embodiment of the present invention is shown.

[0034] Figure 6 A schematic diagram of forming a first passivation layer provided by an embodiment of the present invention is shown.

[0035] Figure 7 A schematic diagram of processing a first passivation layer provided by an embodiment of the present invention is shown.

[0036] Figure 8 A schematic diagram of forming a second passivation layer provided by an embodiment of the present invention is shown.

[0037] Fig. 9 A schematic diagram of processing the second passivation layer provided by an embodiment of the present invention is shown.

[0038] Fig.10 A schematic diagram showing bonding of another light emitting chip to a metal pad provided by an embodiment of the present invention is shown.

[0039] Fig.11 A schematic structural diagram of a peeling growth substrate provided by an embodiment of the present invention is shown.

[0040] Fig.12 A schematic diagram showing a method of providing only a first passivation layer on a light-emitting chip according to an embodiment of the present invention is shown.

[0041] Fig.13 A schematic diagram of providing a second passivation layer only on a metal pad according to an embodiment of the present invention is shown.

[0042] Fig.14 A schematic diagram of setting a first passivation layer and a second passivation layer provided by an embodiment of the present invention is shown.

[0043] Fig.15 A schematic structural diagram of a display panel provided by an embodiment of the present invention is shown.

[0044] Diagram:

[0045] 100 - growth substrate; 110 - light-emitting chip; 111 - epitaxial layer; 112 - electrode; 200 - driving backplane; 210 - metal pad; 120 - first passivation layer; 220 - second passivation layer; 121 - first groove; 122 - second groove; 300 - display panel. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present invention.

[0047] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0048] Please refer to Figure 1 , is a schematic flow chart of a light-emitting chip bonding method provided by an embodiment of the present invention, the method comprising:

[0049] S110, providing a growth substrate, on which a plurality of light-emitting chips are arranged.

[0050] For details, please refer to Figure 2As shown, it is a schematic diagram of a growth substrate 100 provided by an embodiment of the present invention, on which a plurality of light-emitting chips 110 are arranged in an array, that is, an epitaxial layer is first formed on the growth substrate 100 using epitaxy technology, and then the epitaxial layer is etched into a plurality of light-emitting chips 110. The growth substrate 100 may be a sapphire substrate or a silicon substrate, etc., and the light-emitting chip 110 may be one of a red light chip, a green light chip, and a blue light chip. Further, the light-emitting chip 110 includes an epitaxial layer 111 (the epitaxial layer further includes an N-type semiconductor layer, a quantum well layer, and a P-type semiconductor layer), and electrodes 112 are respectively formed on the epitaxial layer 111, and the electrode 112 includes a P electrode and an N electrode, wherein the N electrode is in direct contact with the N-type semiconductor layer, and the P electrode is in direct contact with the P-type semiconductor layer.

[0051] S120, providing a driving backplane, wherein a plurality of metal pads are disposed on the driving backplane.

[0052] Please refer to Figure 3 , is a schematic structural diagram of a driving backplane 200 provided in an embodiment of the present invention. A plurality of metal pads 210 are provided on the driving backplane 200. The plurality of metal pads 210 are used for respectively aligning and bonding with the electrodes 112 of the light-emitting chip 110. The driving backplane 200 can be a PCB substrate or a TFT substrate.

[0053] It should be noted that the electrode 112 of the light emitting chip 110 and the metal pad 210 are made of metal, which may be copper, gold, indium, etc., which has a relatively high thermal expansion coefficient.

[0054] S130, applying a predetermined pressure at a first temperature to align and bond the electrodes of the plurality of light-emitting chips to the plurality of metal pads.

[0055] like Figure 4 As shown, it is a schematic diagram of bonding the light emitting chip 110 and the metal pad 210 provided by an embodiment of the present invention. First, at room temperature, the electrodes 112 of the plurality of light emitting chips 110 are aligned one by one with the plurality of metal pads 210. Since the electrodes 112 of the light emitting chip 110 and the metal pads 210 are made of the same metal, when the two are in direct contact, at a close distance, van der Waals forces will be generated between the metal atoms, thereby generating a certain bonding strength between the electrodes 112 of the light emitting chip 110 and the metal pads 210. Further, a predetermined pressure is applied at a first temperature, and the first temperature is maintained, so that the electrodes 112 of the light emitting chip 110 and the metal pads 210 form a strong covalent bond to improve the bonding strength. Preferably, the first temperature can be 100 degrees Celsius.

[0056] S140, continuously applying the predetermined pressure at a second temperature to align and bond the electrodes of the plurality of light-emitting chips to the plurality of metal pads, wherein the second temperature is greater than the first temperature.

[0057] Please continue to refer to Figure 4 , based on S130, the temperature is further increased to a second temperature, which is greater than the first temperature, that is, if the first temperature is 100 degrees Celsius, the second temperature is greater than 100 degrees Celsius, such as the second temperature can be 300 degrees Celsius to 400 degrees Celsius. And while maintaining the second temperature, a predetermined pressure is continuously applied to align and bond the electrodes 112 of the plurality of light-emitting chips 110 with the plurality of metal pads 210. At this time, the contact points of the electrodes 112 of the light-emitting chips 110 and the metal pads 210 are further diffused and bonded at high temperature. For example, when the materials are both copper, due to the good ductility of copper, atomic diffusion will occur under the action of temperature, thereby making the electrodes 112 of the light-emitting chips 110 and the metal pads 210 more firmly bonded. Finally, the growth substrate 100 is removed by laser stripping to complete the transfer and fixation of the light-emitting chips 110 on the driving backplane 200.

[0058] It can be seen that the embodiment of the present invention uses segmented temperature control, including a first temperature and a second temperature higher than the first temperature, to gradually bond the electrode 112 of the light-emitting chip 110 to the metal pad 210. Since the bonding process is gradual, the electrode 112 of the light-emitting chip 110 is more firmly bonded to the metal pad 210, and the problem of metal melting and short circuit caused by direct high-temperature bonding is avoided. Furthermore, the bonding method of the light-emitting chip 110 provided in the embodiment of the present invention can make the electrode 112 smaller, and the overall size of the light-emitting chip 110 will also be smaller, so that the resolution of the final product is greatly improved.

[0059] As another implementation, please refer to Figure 5 , is a flow chart of another light-emitting chip bonding method provided by an embodiment of the present invention, the method comprising:

[0060] S210, providing a growth substrate, on which a plurality of light-emitting chips are arranged.

[0061] like Figure 2 2 is a schematic diagram showing a growth substrate 100 provided by an embodiment of the present invention, on which a plurality of light-emitting chips 110 are arranged in an array.

[0062] S220, forming a first passivation layer between the plurality of light-emitting chips, wherein the first passivation layer covers the plurality of light-emitting chips and only exposes surfaces of the electrodes of the plurality of light-emitting chips away from the growth substrate.

[0063] like Figure 6 As shown, it is a schematic diagram of the formation of a first passivation layer 120 provided in an embodiment of the present invention. The first passivation layer 120 is entirely formed on a plurality of light-emitting chips 110 and covers the gaps and side walls of the plurality of light-emitting chips 110, with only the surface of the electrode away from the growth substrate 100 exposed to facilitate contact with the metal pad 210 of the driving backplane 200.

[0064] S230: performing a planarization process on a surface of the first passivation layer away from the growth substrate, so that the surface of the first passivation layer away from the growth substrate is at the same height as the electrodes of the plurality of light-emitting chips.

[0065] like Figure 7 As shown, it is a schematic diagram of processing the first passivation layer 120 provided by an embodiment of the present invention. That is to say, when the first passivation layer 120 is formed on the light-emitting chip 110, the first passivation layer 120 may be uneven, and it has an uneven surface. In order to facilitate the subsequent contact between the electrode 112 of the light-emitting chip 110 and the metal pad 210 and avoid poor contact due to the uneven contact surface, the CMP (Chemical Mechanical Plamarization) technology is used to planarize the side of the first passivation layer 120 away from the growth substrate 100, so that the surface of the first passivation layer 120 is the same height as the electrode 112 of the light-emitting chip 110, that is, on the same plane. It should be noted that the more consistent the height of the first passivation layer 120 and the electrode 112 is, the lower the subsequent process temperature can be, so that the bonding efficiency is better.

[0066] S240, providing a driving backplane, wherein a plurality of metal pads are disposed on the driving backplane.

[0067] like Figure 3 , is a schematic diagram of the structure of a driving backplane 200 provided in an embodiment of the present invention. A plurality of metal pads 210 are provided on the driving backplane 200 , and the plurality of metal pads 210 are used for aligning and bonding with the electrodes 112 of the light-emitting chip 110 , respectively.

[0068] S250 , forming a second passivation layer between the plurality of metal pads, wherein the second passivation layer covers the plurality of metal pads and only exposes the surfaces of the plurality of metal pads away from the driving backplane.

[0069] like Figure 8 As shown, it is a schematic diagram of the formation of a second passivation layer 220 provided in an embodiment of the present invention. The second passivation layer 220 is formed between multiple metal pads 210 and covers the side walls of multiple metal pads 210, with only the surface of multiple metal pads 210 away from the driving backplane 200 exposed to facilitate bonding with the electrode 112 of the light-emitting chip 110.

[0070] S260, performing a planarization process on a side of the second passivation layer away from the driving backplane, so that the side of the second passivation layer away from the driving backplane is at the same height as the plurality of metal pads.

[0071] like Fig. 9 As shown, it is a schematic diagram of processing the second passivation layer 220 provided by an embodiment of the present invention. That is, when the second passivation layer 220 is formed on a plurality of metal pads 210, it may be uneven and have an uneven surface. In order to facilitate better contact between the electrode 112 of the light-emitting chip 110 and the metal pad 210 in the future and avoid poor contact due to an uneven contact surface, the CMP (Chemical Mechanical Plamarization) technology is also used to planarize the side of the second passivation layer 220 away from the driving backplane 200, so that the surface of the second passivation layer 220 is at the same height as the metal pad 210, that is, on the same plane.

[0072] S270, applying a predetermined pressure at a first temperature to align and bond the electrodes of the plurality of light-emitting chips to the plurality of metal pads.

[0073] like Fig.10 As shown, it is a schematic diagram of bonding another light-emitting chip 110 and a metal pad 210 provided by an embodiment of the present invention. First, at room temperature, the electrodes 112 of multiple light-emitting chips 110 are aligned one by one with multiple metal pads 210. Since the electrodes 112 of the light-emitting chip 110 and the metal pads 210 are made of the same metal, when the two are in direct contact, at a close distance, van der Waals forces will be generated between the metal atoms, thereby generating a certain bonding strength between the electrodes 112 of the light-emitting chip 110 and the metal pads 210.

[0074] Furthermore, since the first passivation layer 120 is disposed around the light emitting chip 110 and the second passivation layer 220 is disposed around the metal pad 210, the first passivation layer 120 and the second passivation layer 220 are both made of non-conductive materials, such as silicon dioxide or silicon nitride, and their thermal expansion coefficients are smaller than the expansion coefficients of conductive materials such as the electrode 112 of the light emitting chip 110 and the metal pad 210. For example, when the first passivation layer 120 and the second passivation layer 220 are both made of silicon dioxide, their thermal expansion coefficients are 0.5×10^-6 / °C, and when the electrode 112 of the light emitting chip 110 and the metal pad 210 are both made of copper, their thermal expansion coefficients are 18.7x 10^-6 / °C, and at this time, the thermal expansion coefficients of the two differ by 37 times.

[0075] Therefore, when a predetermined pressure is applied at the first temperature to align and bond the electrode 112 of the light-emitting chip 110 with the metal pad 210, on the one hand, the metal atoms of the electrode 112 and the metal pad 210 will further diffuse under the action of temperature and pressure, promoting the bonding of the electrode 112 and the metal pad 210; on the other hand, under the action of heating, the diffusion speed of the electrode 112 and the metal pad 210 is greater than the diffusion speed of the first passivation layer 120 and the second passivation layer 220. In other words, the metal atoms of the electrode 112 and the metal pad 210 will be blocked by the side edges of the first passivation layer 120 and the second passivation layer 220 during the diffusion process, thereby forming a strong covalent bond to improve the bonding strength. At the same time, since the first passivation layer 120 protects the side wall of the electrode 112 and only exposes the bonding surface of the electrode 112, and the second passivation layer 220 also protects the side wall of the metal pad 210 and only exposes the bonding surface of the metal pad 210, it is also better to prevent metal overflow and short circuit problems caused by it.

[0076] S280, continuously applying the predetermined pressure at a second temperature to align and bond the electrodes of the plurality of light-emitting chips to the plurality of metal pads, wherein the second temperature is greater than the first temperature.

[0077] Please continue to refer to Fig.10 On the basis of S270, the temperature is further raised to a second temperature, which is greater than the first temperature, that is, if the first temperature is 100 degrees Celsius, the second temperature is greater than 100 degrees Celsius, such as 300 degrees Celsius to 400 degrees Celsius. And while maintaining the second temperature, a predetermined pressure is continuously applied to align and bond the electrodes 112 of the plurality of light-emitting chips 110 with the plurality of metal pads 210. At this time, the contact points between the electrodes 112 of the light-emitting chips 110 and the metal pads 210 are further diffused and bonded at high temperature.

[0078] That is to say, in S270, at the first temperature, atomic diffusion has occurred in the first passivation layer 120 and the second passivation layer 220, forming a side "enclosure barrier", and the electrode 112 and the metal pad 210 have also had a certain strength of bonding. Therefore, on this basis, the first temperature is further increased to the second temperature to increase the diffusion rate of metal atoms in the electrode 112 of the light-emitting chip 110 and the metal pad 210, thereby further improving the bonding strength.

[0079] like Fig.11 , which is a schematic structural diagram of a stripping growth substrate 100 provided in an embodiment of the present invention. After bonding is completed, the growth substrate 100 is removed by laser stripping.

[0080] It can be seen that in the embodiment of the present invention, the bonding method of the light-emitting chip, on the one hand, respectively sets the first passivation layer 120 around the light-emitting chip 110, and sets the second passivation layer 220 around the metal pad 210. By virtue of the thermal expansion coefficients of the first passivation layer 120 and the second passivation layer 220 being smaller than the electrode 112 and the metal pad 210 of the light-emitting chip 110, during the heating process, the electrode 112 and the metal pad 210 are subjected to the side force of the first passivation layer 120 and the second passivation layer 220 to diffuse faster, and the bonding effect is better; at the same time, the first passivation layer 120 and the second passivation layer 220 also better limit the metal flow range to avoid the problem of short circuit, thereby, the electrode 112 can be made smaller, and the size of the corresponding light-emitting chip 110 can also be made smaller, thereby improving the resolution of the final terminal product. On the other hand, by adjusting the temperature in stages at the first temperature and the second temperature and bonding step by step, the bonding yield is improved to achieve a higher product yield.

[0081] It should be noted that, as another embodiment, the first passivation layer 120 may not be provided on the outside of the light-emitting chip 110 and the second passivation layer 220 may not be provided on the outside of the metal pad 210 at the same time. That is, there may be different combinations, such as providing the first passivation layer 120 on the outside of the light-emitting chip 110, but not providing the second passivation layer 220 on the outside of the metal pad 210; or not providing the first passivation layer 120 on the outside of the light-emitting chip 110, but providing the second passivation layer 220 on the outside of the metal pad 210. The method of providing the passivation layer only at one end may also limit the metal flow to a certain extent, and provide a certain force from the side to improve the bonding effect.

[0082] Furthermore, before bonding the electrode 112 of the light emitting chip 110 to the metal pad 210, the bonding surface between the electrode 112 and the metal pad 210 may not be planarized. Fig.12 As shown, if the first passivation layer 120 is only provided on the outer side of the light-emitting chip 110, when the first passivation layer 120 is provided on the light-emitting chip 110, only the surface of the electrode 112 away from the growth substrate 100 is exposed for bonding. At this time, if the first passivation layer 120 has a certain thickness, after the surface of the electrode 112 for bonding is exposed, a first groove 121 with a certain depth will be formed; simultaneously, the size of the metal pad 210 is set to be smaller than the first groove 121. During bonding, the metal pad 210 will be accommodated in the first groove 121. Based on the heating effect, the diffusion of metal atoms will realize the bonding between the electrode 112 and the metal pad 210. At the same time, since the first passivation layer 120 is enclosed from the side, the short circuit problem that may be caused by metal overflow is also avoided.

[0083] like Fig.13As shown, if only the second passivation layer 220 is set on the outside of the metal pad 210, based on the same reason, after the metal pad 210 is etched to expose the surface facing the light-emitting chip 110, a second groove 122 with a certain depth will be formed. If the size of the electrode 112 of the light-emitting chip 110 is set to be smaller than the second groove 122, when the two are bonded, the electrode 112 will be completely accommodated in the second groove 122, and under the action of heating, based on the diffusion of metal atoms, bonding with the metal pad 210 is achieved. At the same time, due to the side blocking effect of the second passivation layer 220, the short circuit problem that may be caused by metal overflow is avoided.

[0084] like Fig.14 As shown, a first passivation layer 120 is arranged on the outside of the light-emitting chip 110, and a second passivation layer 220 is also arranged on the outside of the metal pad 210. At this time, a first groove 121 will be formed after the first passivation layer 120 is etched to expose the surface of the electrode 112, and a second groove 122 will be formed after the second passivation layer 220 is etched to expose the surface of the metal pad 210. During bonding, the electrode 112 and the metal pad 210 are heated to generate metal flow to achieve bonding, and the flow range is limited to the first groove 121 and the second groove 122, which better avoids the short circuit problem caused by metal overflow.

[0085] In addition, if Fig.15 As shown, an embodiment of the present invention further provides a display panel 300, which includes a driving backplane 200 and a plurality of light-emitting chips 110. A plurality of metal pads 210 are arranged on the driving backplane 200, and the plurality of light-emitting chips 110 are fixed on the plurality of metal pads 210 by the above-mentioned bonding method.

[0086] Furthermore, the display panel 300 further includes a first passivation layer 120 and a second passivation layer 220, wherein the first passivation layer 120 covers the outer side wall of each light-emitting chip 110 and only exposes the surface of its electrode 112 and the light-emitting surface of the light-emitting chip 110. The second passivation layer 220 covers the outer side walls of the plurality of metal pads 210 and only exposes the surface of the plurality of metal pads 210 away from the driving backplane 200, and then the plurality of light-emitting chips 110 are fixed by aligning and bonding the exposed electrode surface with the exposed surface of the plurality of metal pads 210. It should be noted that the thermal expansion coefficients of the electrode 112 and the metal pad 210 are greater than the thermal expansion coefficients of the first passivation layer 120 and the second passivation layer 220, so that the light-emitting chip 110 and the metal pad 210 are bonded under heating.

[0087] In summary, an embodiment of the present invention provides a bonding method for a light-emitting chip and a display panel, the method comprising providing a growth substrate on which a plurality of light-emitting chips are arranged; providing a driving substrate on which a plurality of metal pads are arranged; applying a predetermined pressure at a first temperature to align and bond the electrodes of the plurality of light-emitting chips to the plurality of metal pads, and continuously applying the predetermined pressure at a second temperature greater than the first temperature to align and bond the electrodes of the plurality of light-emitting chips to the metal pads; adopting a segmented bonding method of the first temperature and the second temperature to improve the bonding yield between the light-emitting chip and the metal pad, so that the light-emitting chip can be made smaller, so that the final display panel has better visual effects and higher resolution.

[0088] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0089] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention. It should be noted that similar numbers and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0090] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A bonding method for a light-emitting chip, It is characterized in that The method comprises: Providing a growth substrate, on which a plurality of light-emitting chips are arranged; Providing a driving backplane, wherein a plurality of metal pads are arranged on the driving backplane; Applying a predetermined pressure at a first temperature to align and bond the electrodes of the plurality of light-emitting chips to the plurality of metal pads; The predetermined pressure is continuously applied at a second temperature to align and bond the electrodes of the plurality of light-emitting chips to the plurality of metal pads, wherein the second temperature is greater than the first temperature.

2. The light-emitting chip bonding method according to claim 1, It is characterized in that The step of providing a growth substrate on which a plurality of light-emitting chips are arranged further comprises the following steps: A first passivation layer is formed between the plurality of light-emitting chips, wherein the first passivation layer covers the plurality of light-emitting chips and only exposes surfaces of the electrodes of the plurality of light-emitting chips away from the growth substrate.

3. The light-emitting chip bonding method according to claim 2, It is characterized in that The method further comprises: A planarization process is performed on a surface of the first passivation layer away from the growth substrate, so that the surface of the first passivation layer away from the growth substrate is at the same height as the electrodes of the plurality of light-emitting chips.

4. The light-emitting chip bonding method according to claim 1, It is characterized in that The method further comprises the steps of providing a driving backplane, wherein a plurality of metal pads are arranged on the driving backplane: A second passivation layer is formed between the plurality of metal pads, wherein the second passivation layer covers the plurality of metal pads and only exposes surfaces of the plurality of metal pads away from the driving backplane.

5. The light emitting chip bonding method according to claim 4, It is characterized in that The method further comprises: A planarization process is performed on a surface of the second passivation layer away from the driving backplane, so that the surface of the second passivation layer away from the driving backplane is at the same height as the plurality of metal pads.

6. The light-emitting chip bonding method according to claim 1, It is characterized in that Before applying a predetermined pressure at the first temperature to align and bond the electrodes of the plurality of light-emitting chips to the plurality of metal pads, the method further includes: At room temperature, the electrodes of the plurality of light-emitting chips are aligned with the plurality of metal pads.

7. The light-emitting chip bonding method according to claim 1, It is characterized in that The method further comprises: The growth substrate is removed by laser lift-off.

8. A display panel, It is characterized in that The display panel includes a driving backplane and a plurality of light-emitting chips, wherein a plurality of metal pads are arranged on the driving backplane, and the plurality of light-emitting chips are bonded to the plurality of metal pads by the bonding method for light-emitting chips as described in any one of claims 1 to 7.

9. The display panel according to claim 8, It is characterized in that The display panel further includes a first passivation layer and a second passivation layer. The first passivation layer covers the outer side wall of each of the light-emitting chips and only exposes the electrode surface and the light-emitting surface of each of the light-emitting chips. The second passivation layer covers the outer sidewalls of the plurality of metal pads and only exposes the surfaces of the plurality of metal pads away from the driving backplane. The exposed electrode surfaces of the plurality of light-emitting chips are aligned and bonded to the exposed surfaces of the plurality of metal pads.

10. The display panel according to claim 9, It is characterized in that The thermal expansion coefficients of the electrodes of the light emitting chip and the plurality of metal pads are greater than those of the first passivation layer or the second passivation layer.

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