A shift register, a driving method, a gate driving circuit and a display device

Abstract

A shift register, a driving method, a gate driving circuit and a display device, wherein the shift register comprises: a shift module (1), the shift module (1) is configured to make a cascade signal output end (GP(n)) output a cascade signal in response to a signal of an input signal end (IP); a reverse output module (2), the reverse output module (2) is configured to make a reverse signal output end (Anti-GP(n)) output a signal opposite to the signal of the cascade signal output end (GP(n)) in response to the signal of the cascade signal output end (GP(n)); a latch module (3), the latch module (3) is configured to make an output end of the latch module (3) output a control signal of a mask signal end (Vms) in response to the signals of the cascade signal output end (GP(n)) and a previous stage reverse signal output end (Anti-GP(n)); and a selection output module (4), the selection output module (4) is configured to provide a signal of a first power supply end (VGH) or a second power supply end (VGL) to a driving signal output end (OP(n)) in response to the signal of the output end of the latch module (3).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register, a driving method, a gate driving circuit, and a display device. Background Technology

[0002] With the rapid development of display technology, display devices are increasingly moving towards higher integration and lower cost. Among these technologies, GOA (Gate Driver on Array) integrates TFT (Thin Film Transistor) gate driving circuitry onto the array substrate of the display device to form a scanning drive for the display. This gate driving circuit typically consists of multiple cascaded shift registers. However, existing shift register driving modes cannot achieve different refresh rates within the same display area. Summary of the Invention

[0003] This disclosure provides a shift register, comprising:

[0004] A shift module is coupled to an input signal terminal and a cascaded signal output terminal, respectively; the shift module is configured to respond to a signal at the input signal terminal and cause the cascaded signal output terminal to output a cascaded signal.

[0005] An inverting output module is coupled to the cascaded signal output terminal, the first power supply terminal, the second power supply terminal, and the inverting signal output terminal, respectively. The inverting output module is configured to respond to the signal at the cascaded signal output terminal and cause the inverting signal output terminal to output a signal opposite to that at the cascaded signal output terminal.

[0006] A latch module is coupled to a masking signal terminal, a cascaded signal output terminal, and a reverse signal output terminal of the preceding stage, respectively. The latch module is configured to respond to signals from the cascaded signal output terminal and the reverse signal output terminal of the preceding stage, causing the output terminal of the latch module to output a control signal from the masking signal terminal.

[0007] The selected output module is coupled to the first power supply terminal, the second power supply terminal, the output terminal of the latch module, and the drive signal output terminal, respectively. The selected output module is configured to provide the signal from the first power supply terminal or the second power supply terminal to the drive signal output terminal in response to the signal from the output terminal of the latch module.

[0008] Optionally, in this embodiment of the disclosure, the inverted output module includes: a first switching transistor and a second switching transistor; the first switching transistor and the second switching transistor are of different types; wherein,

[0009] The gate of the first switching transistor is coupled to the cascaded signal output terminal, the first terminal of the first switching transistor is coupled to the first power supply terminal, and the second terminal of the first switching transistor is coupled to the reverse signal output terminal.

[0010] The gate of the second switching transistor is coupled to the cascaded signal output terminal, the first terminal of the second switching transistor is coupled to the second power supply terminal, and the second terminal of the second switching transistor is coupled to the inverted signal output terminal.

[0011] Optionally, in an embodiment of this disclosure, the latch module includes: a third switching transistor and a fourth switching transistor; wherein,

[0012] The gate of the third switching transistor is coupled to the cascaded signal output terminal, the first terminal of the third switching transistor is coupled to the masking signal terminal, and the second terminal of the third switching transistor is coupled to the first terminal of the fourth switching transistor.

[0013] The gate of the fourth switching transistor is coupled to the reverse signal output terminal of the previous stage, and the second electrode of the fourth switching transistor is the output terminal of the latch module.

[0014] Optionally, in this embodiment of the disclosure, the selection output module includes: a fifth switching transistor, a sixth switching transistor, and a first capacitor; the fifth switching transistor and the sixth switching transistor are of different types; wherein,

[0015] The gate of the fifth switching transistor is coupled to the second terminal of the fourth switching transistor, and the first terminal of the fifth switching transistor is coupled to the drive signal output terminal.

[0016] The gate of the sixth switching transistor is coupled to the second terminal of the fourth switching transistor, the first terminal of the sixth switching transistor is coupled to the second power supply terminal, and the second terminal of the sixth switching transistor is coupled to the drive signal output terminal.

[0017] The first terminal of the first capacitor is coupled to the first power supply terminal, and the second terminal of the first capacitor is coupled to the second terminal of the fourth switching transistor.

[0018] Optionally, in an embodiment of this disclosure, the second terminal of the fifth switching transistor is coupled to the cascaded signal output terminal.

[0019] Optionally, in this embodiment of the disclosure, the selection output module further includes: a seventh switching transistor; the type of the seventh switching transistor is the same as that of the fifth switching transistor; the gate of the seventh switching transistor is coupled to the shift module, the first terminal of the seventh switching transistor is coupled to the first power supply terminal, and the second terminal of the seventh switching transistor is coupled to the second terminal of the fifth switching transistor.

[0020] Optionally, in this embodiment of the present disclosure, an eighth switching transistor is further included, the gate of which is coupled to the shift module, the first terminal of which is coupled to the second power supply terminal, and the second terminal of which is coupled to the drive signal output terminal.

[0021] Optionally, in this embodiment of the disclosure, the first switching transistor, the third switching transistor, the fourth switching transistor, the fifth switching transistor, and the eighth switching transistor are all P-type transistors, and the second switching transistor and the sixth switching transistor are both N-type transistors.

[0022] Optionally, in this embodiment of the disclosure, the shifting module includes:

[0023] An input circuit is coupled to the input signal terminal, the first clock signal terminal, the second power supply terminal, the first node, and the second node, respectively; the input circuit is configured to provide the signal from the input signal terminal to the first node and the second node in response to the signal from the first clock signal terminal.

[0024] A node control circuit is coupled to the first node, the second node, the third node, the fourth node, the fifth node, the first power supply terminal, the second power supply terminal, the first clock signal terminal, and the second clock signal terminal, respectively. The node control circuit is configured to adjust the signals of the first node, the second node, the third node, the fourth node, and the fifth node so that the cascaded signal output terminal outputs the signal of the first power supply terminal or the signal of the second power supply terminal.

[0025] A reset circuit is coupled to the first power supply terminal, the reset signal terminal, the first node, the fourth node, and the fifth node, respectively; the reset circuit is configured to reset the cascaded signal output by the cascaded signal output terminal in response to a signal from the reset signal terminal.

[0026] The first cascaded output circuit is coupled to the fourth node, the first power supply terminal, and the cascaded signal output terminal, respectively; the first cascaded output circuit is configured to provide the signal from the first power supply terminal to the cascaded signal output terminal in response to the signal from the fourth node; the gate of the seventh switching transistor is coupled to the fourth node.

[0027] The second cascaded output circuit is coupled to the fifth node, the second power supply terminal, and the cascaded signal output terminal, respectively; the second cascaded output circuit is configured to provide the signal from the second power supply terminal to the cascaded signal output terminal in response to the signal from the fifth node; the gate of the eighth switching transistor is coupled to the fifth node.

[0028] Optionally, in an embodiment of this disclosure, the input circuit includes: a ninth switching transistor, a tenth switching transistor, and an eleventh switching transistor;

[0029] The gate of the ninth switching transistor is coupled to the first clock signal terminal, the first terminal of the ninth switching transistor is coupled to the input signal terminal, and the second terminal of the ninth switching transistor is coupled to the first node.

[0030] The gate of the tenth switching transistor is coupled to the first clock signal terminal, the first terminal of the tenth switching transistor is coupled to the input signal terminal, and the second terminal of the tenth switching transistor is coupled to the first terminal of the eleventh switching transistor.

[0031] The gate of the eleventh switching transistor is coupled to the second power supply terminal, and the second terminal of the eleventh switching transistor is coupled to the second node.

[0032] Optionally, in this embodiment of the disclosure, the node control circuit includes: a twelfth switching transistor, a thirteenth switching transistor, a fourteenth switching transistor, a fifteenth switching transistor, a sixteenth switching transistor, a seventeenth switching transistor, an eighteenth switching transistor, a nineteenth switching transistor, a second capacitor, and a third capacitor; wherein,

[0033] The gate of the twelfth switching transistor is coupled to the first clock signal terminal, the first terminal of the twelfth switching transistor is coupled to the second power supply terminal, and the second terminal of the twelfth switching transistor is coupled to the third node;

[0034] The gate of the thirteenth switching transistor is coupled to the first node, the first terminal of the thirteenth switching transistor is coupled to the first clock signal terminal, and the second terminal of the thirteenth switching transistor is coupled to the third node.

[0035] The gate and first terminal of the fourteenth switching transistor are both coupled to the second node, and the second terminal of the fourteenth switching transistor is coupled to the fifth node;

[0036] The gate of the fifteenth switching transistor is coupled to the second node, the first terminal of the fifteenth switching transistor is coupled to the second clock signal terminal, and the second terminal of the fifteenth switching transistor is coupled to the first terminal of the sixteenth switching transistor.

[0037] The gate of the sixteenth switching transistor is coupled to the third node, and the second terminal of the sixteenth switching transistor is coupled to the first power supply terminal.

[0038] The first terminal of the second capacitor is coupled to the second node, and the second terminal of the second capacitor is coupled to the first terminal of the sixteenth switching transistor.

[0039] The gate of the seventeenth switching transistor is coupled to the second power supply terminal, the first terminal of the seventeenth switching transistor is coupled to the third node, and the second terminal of the seventeenth switching transistor is coupled to the gate of the eighteenth switching transistor.

[0040] The first terminal of the eighteenth switching transistor is coupled to the second clock signal terminal, and the second terminal of the eighteenth switching transistor is coupled to the first terminal of the nineteenth switching transistor;

[0041] The gate of the nineteenth switching transistor is coupled to the second clock signal terminal, and the second terminal of the nineteenth switching transistor is coupled to the fourth node;

[0042] The first terminal of the third capacitor is coupled to the gate of the eighteenth switching transistor, and the second terminal of the third capacitor is coupled to the second terminal of the eighteenth switching transistor.

[0043] Optionally, in an embodiment of this disclosure, the reset circuit includes: a twentieth switching transistor, a twenty-first switching transistor, and a twenty-second switching transistor; wherein,

[0044] The gate of the twentieth switching transistor is coupled to the reset signal terminal, the first terminal of the twentieth switching transistor is coupled to the first power supply terminal, and the second terminal of the twentieth switching transistor is coupled to the first node and the gate of the twentieth switching transistor.

[0045] The first terminal of the 21st switching transistor is coupled to the first power supply terminal, and the second terminal of the 21st switching transistor is coupled to the fourth node;

[0046] The gate of the twelfth switching transistor is coupled to the second power supply terminal, the first terminal of the twelfth switching transistor is coupled to the first node, and the second terminal of the twelfth switching transistor is coupled to the fifth node.

[0047] Optionally, in this embodiment of the disclosure, the first cascaded output circuit includes: a twenty-third switching transistor and a fourth capacitor; wherein,

[0048] The gate of the 23rd switching transistor is coupled to the fourth node, the first terminal of the 23rd switching transistor is coupled to the first power supply terminal, and the second terminal of the 23rd switching transistor is coupled to the cascaded signal output terminal.

[0049] The first end of the fourth capacitor is coupled to the fourth node, and the second end of the fourth capacitor is coupled to the first power supply terminal.

[0050] Optionally, in an embodiment of this disclosure, the second cascaded output circuit includes a twenty-fourth switching transistor, the gate of the twenty-fourth switching transistor being coupled to the fifth node, the first terminal of the twenty-fourth switching transistor being coupled to the second power supply terminal, and the second terminal of the twenty-fourth switching transistor being coupled to the cascaded signal output terminal.

[0051] The gate driving circuit provided in this disclosure includes multiple cascaded shift registers as described above;

[0052] The input signal terminal of the first-stage shift register is configured to be coupled to the frame trigger signal terminal;

[0053] In each pair of adjacent shift registers, the input signal terminal of the subsequent shift register is configured to be coupled to the cascaded signal output terminal of the preceding shift register.

[0054] The display device provided in this disclosure includes the gate driving circuit described above.

[0055] The driving method for the shift register provided in this embodiment includes:

[0056] In the first refresh rate stage, the latch module provides the control signal of the masking signal terminal to the selection output module based on the signal from the cascaded signal output terminal and the inverted signal output terminal of the previous stage; the selection output module responds to the control signal from the masking signal terminal and provides the signal from the first power supply terminal to the drive signal output terminal.

[0057] In the second refresh rate stage, the latch module provides the control signal of the masking signal terminal to the selection output module based on the signals of the cascaded signal output terminal and the reverse signal output terminal of the previous stage; the selection output module responds to the control signal of the masking signal terminal and provides the signal of the second power supply terminal to the drive signal output terminal. Attached Figure Description

[0058] Figure 1This is a schematic diagram of the structure of a shift register provided in an embodiment of the present disclosure;

[0059] Figure 2 This is a schematic diagram of another shift register provided in an embodiment of the present disclosure;

[0060] Figure 3 This is a schematic diagram of another shift register provided in an embodiment of the present disclosure;

[0061] Figure 4 This is a schematic diagram of a pixel circuit provided in an embodiment of the present disclosure;

[0062] Figure 5 For the corresponding Figure 4 The signal timing diagram for the operation of the pixel circuit is shown below.

[0063] Figure 6 The signal timing diagram for the operation of the shift register provided in the embodiments of this disclosure;

[0064] Figure 7 For the corresponding Figure 6 The simulation diagram of the drive signal output terminal of the shift register is shown.

[0065] Figure 8 A flowchart of the driving method provided in the embodiments of this disclosure;

[0066] Figure 9 This is a schematic diagram of the gate drive circuit provided in an embodiment of the present disclosure;

[0067] Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0068] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0069] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0070] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0071] This disclosure provides a shift register, such as Figure 1 and Figure 2 As shown, it may include:

[0072] The shift module 1 is coupled to the input signal terminal IP and the cascaded signal output terminal GP(n) respectively; the shift module 1 is configured to respond to the signal of the input signal terminal IP and cause the cascaded signal output terminal GP(n) to output the cascaded signal.

[0073] The inverting output module 2 is coupled to the cascaded signal output terminal GP(n), the first power supply terminal VGH, the second power supply terminal VGL, and the inverting signal output terminal Anti-GP(n), respectively. The inverting output module 2 is configured to respond to the signal of the cascaded signal output terminal GP(n) so that the inverting signal output terminal Anti-GP(n) outputs a signal opposite to that of the cascaded signal output terminal GP(n).

[0074] The latch module 3 is coupled to the masking signal terminal Vms, the cascaded signal output terminal GP(n), and the previous stage inverted signal output terminal Anti-GP(n-1), respectively. The latch module 3 is configured to respond to the signals of the cascaded signal output terminal GP(n) and the previous stage inverted signal output terminal Anti-GP(n-1) so that the output terminal of the latch module 3 outputs the signal of the masking signal terminal Vms.

[0075] The selected output module 4 is coupled to the first power supply terminal VGH, the second power supply terminal VGL, the output terminal of the latch module 3, and the drive signal output terminal OP(n), respectively. The selected output module 4 is configured to provide the signal of the first power supply terminal VGH or the second power supply terminal VGL to the drive signal output terminal OP(n) in response to the signal of the output terminal of the latch module 3.

[0076] The shift register provided in this embodiment, by adding an inverted output module, a latch module, and a selection output module coupled to the shift module, and through the cooperation of these modules, locks the control signal of the corresponding masking signal terminal into the selection output module according to the refresh rate requirements of the display area. This enables control of the signal output from the drive signal output terminal, allowing different refresh rates to be achieved in different areas of the display panel. That is, high and low refresh rates can coexist within the same frame. Furthermore, this embodiment is not limited to achieving different refresh rates in a fixed area of ​​the display panel; it can achieve dynamic refresh in any area, thereby reducing the power consumption of the display panel. Simultaneously, the latch module can utilize the phase difference of the cascaded signals output from the preceding and following stages of the shift module to store the control signal of the masking signal terminal into each stage of the shift register, thereby ensuring continuous and correct output from that stage of the shift register. Moreover, only a single control line electrically connected to the masking signal terminal is needed to control the adaptive refresh rate of the entire screen. This not only reduces the difficulty of LayOP wiring and the width of the bezel, but also further reduces the control power consumption of the additional drive chip required for multi-frequency driving due to the use of multiple control lines.

[0077] The specific structure of the shift module 1 provided in the embodiments of this disclosure is described below:

[0078] In one possible implementation, in the shift register provided in the embodiments of this disclosure, such as Figure 1 and Figure 2 As shown, the shift module 1 may include:

[0079] Input circuit 11 is coupled to input signal terminal IP, first clock signal terminal CK, second power supply terminal VGL, first node P1, and second node P2, respectively. Input circuit 11 is configured to provide the signal of input signal terminal IP to first node P1 and second node P2 in response to the signal of first clock signal terminal CK. For example, input circuit 11 may include: a ninth switching transistor T9, a tenth switching transistor T10, and an eleventh switching transistor T11. The gate of the ninth switching transistor T9 is coupled to the first clock signal terminal CK, the first terminal of the ninth switching transistor T9 is coupled to input signal terminal IP, and the second terminal of the ninth switching transistor T9 is coupled to first node P1. The gate of the tenth switching transistor T10 is coupled to the first clock signal terminal CK, the first terminal of the tenth switching transistor T10 is coupled to input signal terminal IP, and the second terminal of the tenth switching transistor T10 is coupled to the first terminal of the eleventh switching transistor T11. The gate of the eleventh switching transistor T11 is coupled to the second power supply terminal VGL, and the second terminal of the eleventh switching transistor T11 is coupled to second node P2.

[0080] Node control circuit 12 is coupled to the first node P1, the second node P2, the third node P3, the fourth node P4, the fifth node P5, the first power supply terminal VGH, the second power supply terminal VGL, the first clock signal terminal CK, and the second clock signal terminal CB, respectively. Node control circuit 12 is configured to adjust the signals of the first node P1, the second node P2, the third node P3, the fourth node P4, and the fifth node P5, so that the cascaded signal output terminal GP(n) outputs the signal of the first power supply terminal VGH or the signal of the second power supply terminal VGL. For example, node control circuit 12 may include: a twelfth switching transistor T12, a thirteenth switching transistor T13, a fourteenth switching transistor T14, a fifteenth switching transistor T15, a sixteenth switching transistor T16, a seventeenth switching transistor T17, an eighteenth switching transistor T18, a nineteenth switching transistor T19, a second capacitor C2, and a third capacitor C3.

[0081] The gate of the twelfth switching transistor T12 is coupled to the first clock signal terminal CK, the first terminal of the twelfth switching transistor T12 is coupled to the second power supply terminal VGL, and the second terminal of the twelfth switching transistor T12 is coupled to the third node P3.

[0082] The gate of the thirteenth switching transistor T13 is coupled to the first node P1, the first terminal of the thirteenth switching transistor T13 is coupled to the first clock signal terminal CK, and the second terminal of the thirteenth switching transistor T13 is coupled to the third node P3.

[0083] The gate and first terminal of the fourteenth switching transistor T14 are both coupled to the second node P2, and the second terminal of the fourteenth switching transistor T14 is coupled to the fifth node P5.

[0084] The gate of the fifteenth switching transistor T15 is coupled to the second node P2, the first terminal of the fifteenth switching transistor T15 is coupled to the second clock signal terminal CB, and the second terminal of the fifteenth switching transistor T15 is coupled to the first terminal of the sixteenth switching transistor T16.

[0085] The gate of the sixteenth switching transistor T16 is coupled to the third node P3, and the second terminal of the sixteenth switching transistor T16 is coupled to the first power supply terminal VGH.

[0086] The first terminal of the second capacitor C2 is coupled to the second node P2, and the second terminal of the second capacitor C2 is coupled to the first terminal of the sixteenth switching transistor T16.

[0087] The gate of the seventeenth switching transistor T17 is coupled to the second power supply terminal VGL, the first terminal of the seventeenth switching transistor T17 is coupled to the third node P3, and the second terminal of the seventeenth switching transistor T17 is coupled to the gate of the eighteenth switching transistor T18.

[0088] The first terminal of the eighteenth switching transistor T18 is coupled to the second clock signal terminal CB, and the second terminal of the eighteenth switching transistor T18 is coupled to the first terminal of the nineteenth switching transistor T19.

[0089] The gate of the nineteenth switching transistor T19 is coupled to the second clock signal terminal CB, and the second terminal of the nineteenth switching transistor T19 is coupled to the fourth node P4.

[0090] The first terminal of the third capacitor C3 is coupled to the gate of the eighteenth switching transistor T18, and the second terminal of the third capacitor C3 is coupled to the second terminal of the eighteenth switching transistor T18.

[0091] Reset circuit 13 is coupled to the first power supply terminal VGH, the reset signal terminal VEL, the first node P1, the fourth node P4, and the fifth node P5, respectively. Reset circuit 13 is configured to reset the cascaded signal output from the cascaded signal output terminal GP(n) in response to the signal from the reset signal terminal VEL. Specifically, reset circuit 13 is configured to reset the voltages of the fourth node P4 and the fifth node P5 in response to the signal from the reset signal terminal VEL, thereby resetting the cascaded signal output from the cascaded signal output terminal GP(n). For example, reset circuit 13 may include: a twentieth switching transistor T20, a twenty-first switching transistor T21, and a twenty-second switching transistor T22.

[0092] The gate of the twentieth switching transistor T20 is coupled to the reset signal terminal VEL, the first terminal of the twentieth switching transistor T20 is coupled to the first power supply terminal VGH, and the second terminal of the twentieth switching transistor T20 is coupled to the first node P1 and the gate of the twenty-first switching transistor T21.

[0093] The first terminal of the twenty-first switching transistor T21 is coupled to the first power supply terminal VGH, and the second terminal of the twenty-first switching transistor T21 is coupled to the fourth node P4.

[0094] The gate of the 22nd switching transistor T22 is coupled to the second power supply terminal VGL, the first terminal of the 22nd switching transistor T22 is coupled to the first node P1, and the second terminal of the 22nd switching transistor T22 is coupled to the fifth node P5.

[0095] The first cascaded output circuit 14 is coupled to the fourth node P4, the first power supply terminal VGH, and the cascaded signal output terminal GP(n), respectively. The first cascaded output circuit 14 is configured to provide the signal from the first power supply terminal VGH to the cascaded signal output terminal GP(n) in response to the signal from the fourth node P4. For example, the first cascaded output circuit 14 may include a twenty-third switching transistor T23 and a fourth capacitor C4.

[0096] The gate of the 23rd switching transistor T23 is coupled to the fourth node P4, the first terminal of the 23rd switching transistor T23 is coupled to the first power supply terminal VGH, and the second terminal of the 23rd switching transistor T23 is coupled to the cascaded signal output terminal GP(n).

[0097] The first terminal of the fourth capacitor C4 is coupled to the fourth node P4, and the second terminal of the fourth capacitor C4 is coupled to the first power supply terminal VGH.

[0098] The second cascaded output circuit 15 is coupled to the fifth node P5, the second power supply terminal VGL, and the cascaded signal output terminal GP(n), respectively. The second cascaded output circuit 15 is configured to provide the signal of the second power supply terminal VGL to the cascaded signal output terminal GP(n) in response to the signal of the fifth node P5. For example, the second cascaded output circuit 15 may include a twenty-fourth switching transistor T24, the gate of which is coupled to the fifth node P5, the first terminal of which is coupled to the second power supply terminal VGL, and the second terminal of which is coupled to the cascaded signal output terminal GP(n).

[0099] To simplify the preparation process, in specific implementations, as described in the embodiments of this disclosure, Figure 1 and Figure 2 As shown, all switching transistors in shift module 1 can be P-type transistors.

[0100] The above are merely examples illustrating the specific structure of the shift module in the shift register provided in the embodiments of this disclosure. In specific implementations, the specific structures of the circuits described above are not limited to the structures provided in the embodiments of this disclosure, and may also be other structures known to those skilled in the art, which are not limited here.

[0101] It should be noted that the above-described embodiments provided in this disclosure... Figure 1 and Figure 2 The working principle of the shift module 1 shown is the same as that in related technologies. It mainly generates cascaded signals through the cascaded signal output terminal GP(n) to realize the signal shifting function, which will not be described in detail here.

[0102] It should be noted that the main function of the shift module 1 provided in this embodiment is to implement the timing shift function from top to bottom. This embodiment selects a 16T3C shift module 1 for more stable signal transmission. However, the shift module 1 is not limited to the 16T3C structure provided in this embodiment; it can be other shift registers capable of performing shift functions, such as the 10T3C, 12T3C, and 13T3C commonly used in OLED display panels. Optionally, such as... Figure 3 As shown, Figure 3This is a schematic diagram of another shift module 1 provided in an embodiment of the present disclosure. The shift module 1 is related to... Figure 1 and Figure 2 The shift module 1 in the middle has the same function, and will not be described in detail here.

[0103] In specific implementation, in the shift register provided in the embodiments of this disclosure, such as Figures 1-3 As shown, the inverting output module 2 may include: a first switching transistor T1 and a second switching transistor T2; the first switching transistor T1 and the second switching transistor T2 are of different types, for example, the first switching transistor T1 is a P-type transistor and the second switching transistor T2 is an N-type transistor; wherein,

[0104] The gate of the first switching transistor T1 is coupled to the cascaded signal output terminal GP(n), the first terminal of the first switching transistor T1 is coupled to the first power supply terminal VGH, and the second terminal of the first switching transistor T1 is coupled to the reverse signal output terminal Anti-GP(n).

[0105] The gate of the second switching transistor T2 is coupled to the cascaded signal output terminal GP(n), the first terminal of the second switching transistor T2 is coupled to the second power supply terminal VGL, and the second terminal of the second switching transistor T2 is coupled to the reverse signal output terminal Anti-GP(n).

[0106] Specifically, such as Figures 1-3 As shown, the inverted output module 2 uses the circuit structure of N-type transistors and P-type transistors to construct the inverted signal of GP(n-1), thereby enabling the latch module to use the phase difference of the cascaded signals output by the shift module to pre-write the control signal of the required masking signal terminal, so that one control signal can control the output of multiple effective level signals (high level).

[0107] In specific implementation, in the shift register provided in the embodiments of this disclosure, such as Figures 1-3 As shown, the latch module 3 may include: a third switching transistor T3 and a fourth switching transistor T4; wherein,

[0108] The gate of the third switching transistor T3 is coupled to the cascaded signal output terminal GP(n), the first terminal of the third switching transistor T3 is coupled to the masking signal terminal Vms, and the second terminal of the third switching transistor T3 is coupled to the first terminal of the fourth switching transistor T4.

[0109] The gate of the fourth switching transistor T4 is coupled to the anti-GP(n-1) output terminal of the previous stage, and the second electrode of the fourth switching transistor T4 is the output terminal of the latch module 3.

[0110] Optionally, the latch module 3 may include: a third switching transistor T3 and a fourth switching transistor T4; wherein,

[0111] The gate of the fourth switching transistor T4 is coupled to the cascaded signal output terminal GP(n), the first terminal of the fourth switching transistor T4 is coupled to the masking signal terminal Vms, and the second terminal of the fourth switching transistor T4 is coupled to the first terminal of the third switching transistor T3.

[0112] The gate of the third switching transistor T3 is coupled to the anti-GP(n-1) output terminal of the previous stage, and the second electrode of the third switching transistor T3 is the output terminal of the latch module 3.

[0113] Specifically, such as Figures 1-3 As shown, latch module 3 utilizes the phase difference between the signal of the previous stage inverted signal output terminal Anti-GP(n-1) and the signal of the cascaded signal output terminal GP(n) to pre-write and store the control signal of the masking signal terminal Vms in the selection output module 4, thereby enabling the signal of the first power supply terminal VGH to be consistent with the GP(n) signal, and realizing the long-term output of multiple effective level signals (high level).

[0114] In specific implementation, in the shift register provided in the embodiments of this disclosure, such as Figures 1-3 As shown, the output selection module 4 may include: a fifth switching transistor T5, a sixth switching transistor T6, and a first capacitor C1; the fifth switching transistor T5 and the sixth switching transistor T6 are of different types, for example, the fifth switching transistor T5 is a P-type transistor, and the sixth switching transistor T6 is an N-type transistor; wherein,

[0115] The gate of the fifth switching transistor T5 is coupled to the second terminal of the fourth switching transistor T4, and the first terminal of the fifth switching transistor T5 is coupled to the drive signal output terminal OP(n).

[0116] The gate of the sixth switching transistor T6 is coupled to the second terminal of the fourth switching transistor T4, the first terminal of the sixth switching transistor T6 is coupled to the second power supply terminal VGL, and the second terminal of the sixth switching transistor T6 is coupled to the drive signal output terminal OP(n).

[0117] The first terminal of the first capacitor C1 is coupled to the first power supply terminal VGH, and the second terminal of the first capacitor C1 is coupled to the second terminal of the fourth switching transistor T4.

[0118] Specifically, the output module 4 selects the high-level signal or low-level signal written by the masking signal terminal Vms to change the high-level signal output by the drive signal output terminal OP(n) into a low-level signal, or maintain the normal output high-level signal, so as to meet the requirements of different refresh rates in the display area.

[0119] In specific implementation, in the shift register provided in the embodiments of this disclosure, such as Figure 1 and Figure 3 As shown, the output selection module 4 may further include: a seventh switching transistor T7; the type of the seventh switching transistor T7 is the same as that of the fifth switching transistor T5, for example, the seventh switching transistor T7 is a P-type transistor; the gate of the seventh switching transistor T7 is coupled to the shift module 1 (fourth node P4), the first terminal of the seventh switching transistor T7 is coupled to the first power supply terminal VGH, and the second terminal of the seventh switching transistor T7 is coupled to the second terminal of the fifth switching transistor T5.

[0120] Specifically, such as Figure 1 and Figure 3 As shown, when the signal at the fourth node P4 is a low-level signal, the control signal of the masking signal terminal Vms can be controlled to be high or low according to the display refresh rate requirements, so that the drive signal output terminal OP(n) outputs low or high level, thereby realizing different refresh rates in different areas of the display panel.

[0121] In specific implementation, in the shift register provided in the embodiments of this disclosure, such as Figure 2 As shown, the second terminal of the fifth switching transistor T5 can be directly coupled to the cascaded signal output terminal GP(n). Specifically, Figure 2 The structure of the selected output module 4 shown is relatively... Figure 1 The structure of the selected output module 4 shown reduces the number of seventh switching transistors T7 that share a common gate with the twenty-third switching transistor T23. This is because the fifth switching transistor T5 can lock the voltage of the cascaded signal output terminal GP(n), and the high-level signal output from the cascaded signal output terminal GP(n) can be directly output to the drive signal output terminal OP(n). This reduces the number of seventh switching transistors T7 (buffer transistors) and saves LayOP wiring space.

[0122] In specific implementation, in the shift register provided in the embodiments of this disclosure, such as Figures 1-3 As shown, it also includes an eighth switching transistor T8. The gate of the eighth switching transistor T8 is coupled to the shift module (the fifth node P5), the first terminal of the eighth switching transistor T8 is coupled to the second power supply terminal VGL, and the second terminal of the eighth switching transistor T8 is coupled to the drive signal output terminal OP(n).

[0123] Specifically, the main function of the eighth switching transistor T8 is to distinguish the signal of the second power supply terminal VGL output to the drive signal output terminal OP(n) from the normal cascade signal of the cascade signal output terminal GP(n), so as to avoid signal disorder caused by the difference between the signal of the drive signal output terminal OP(n) and the signal of the cascade signal output terminal GP(n) when the control signal is written to the masking signal terminal Vms, and realize the normal shift function of the shift register.

[0124] In specific implementation, in the shift register provided in the embodiments of this disclosure, such as Figures 1-3 As shown, the first switching transistor T1, the third switching transistor T3, the fourth switching transistor T4, the fifth switching transistor T5 and the eighth switching transistor T8 are all P-type transistors, and the second switching transistor T2 and the sixth switching transistor T6 are both N-type transistors.

[0125] Furthermore, in specific implementations, P-type transistors are cut off under high-level signals and turn on under low-level signals. N-type transistors turn on under high-level signals and cut off under low-level signals.

[0126] In specific implementation, such as Figures 1-3 As shown, when the control signal of the masking signal terminal Vms is a low-level signal, it can be -20V to -5V; when it is a high-level signal, it can be 5V to 20V.

[0127] In specific implementation, such as Figures 1-3 As shown, the signal at the first power supply terminal VGH is a high-level signal, for example, it can be 5V to 10V; the signal at the second power supply terminal VGL is a low-level signal, for example, it can be -10V to -5V.

[0128] In specific implementation, such as Figures 1-3 As shown, the signals at the first clock signal terminal CK and the second clock signal terminal CB are AC signals with the same period but opposite potentials.

[0129] In practical implementation, depending on the direction of signal flow, the first terminal of each of the above-mentioned switching transistors can be used as its source and the second terminal as its drain; or, the first terminal can be used as its drain and the second terminal as its source. No specific distinction is made here.

[0130] It should be noted that the switching transistor mentioned in the above embodiments of this disclosure can be a TFT or a metal oxide semiconductor field-effect transistor (MOS), and is not limited thereto.

[0131] Optionally, the shift register provided in this embodiment can be used to provide driving signals to an organic light-emitting display panel. The display area of ​​the organic light-emitting display panel includes multiple sub-pixels, and each sub-pixel generally has multiple organic light-emitting diodes and pixel circuits connected to each organic light-emitting diode. The pixel circuit can be a 6T1C, 7T1C, or similar structure. Figure 4 As shown, Figure 4 This disclosure provides a 7T1C pixel circuit structure. Figures 1-3The drive signal output terminal OP(n) of the shift register shown is mainly used to control the oxide switching transistors (used to input signals to the pixel circuits in a row of the display panel) in the display panel. Figure 4 The gate of the first scanning transistor M2 provides the scanning signal. When a frame needs to be refreshed, the drive signal output terminal OP(n) outputs a high level for a period of time and a low level for the rest of the time within a frame, controlling the first scanning transistor M2 to be turned on, thereby refreshing the data voltage. When there is no refresh frame, the drive signal output terminal OP(n) always outputs a low level, and the first scanning transistor M2 cannot be turned on, thereby preventing the data voltage from being refreshed.

[0132] The pixel circuits provided in the embodiments of this disclosure are not limited to... Figure 4 The pixel circuits shown, which require both the initialization transistor M1 and the scanning transistor M2 to be turned on simultaneously to provide initialization signals to the N1 node, are all pixel circuit structures protected by the embodiments of this disclosure.

[0133] First combine Figure 5 The signal timing diagram shown is for Figure 4 The operation of the pixel circuit shown will be explained. Specifically, the following will be selected: Figure 5 The signal timing diagram shown consists of four stages in a frame time period: the first initialization stage T1', the data writing stage T2', the second initialization stage T3', and the emission stage T4'.

[0134] In the first initialization phase T1': the first control terminal PSR1 inputs a low-level signal, the first initialization transistor M1 is turned on, and the first initialization signal terminal Vint1 provides an initialization signal to node N3 to initialize node N3.

[0135] During the data writing phase T2', the first scan control terminal P_Scan inputs a low-level signal, and the second scan control terminal N_Scan inputs a high-level signal. Both the first scan transistor M2 and the second scan transistor M4 are turned on, and the driving transistor M3 maintains the on state of the previous frame's light emission phase. Therefore, the data voltage of the data signal terminal D is written to node N1.

[0136] During the second initialization phase T3', a low-level signal is input to the second control terminal PSR2, the second initialization transistor M7 is turned on, and the second initialization signal terminal Vint2 provides an initialization signal to the anode of the OLED to initialize the anode.

[0137] During the light-emitting stage T4', a low-level signal is input to the light-emitting control terminal EM, and both the first light-emitting control transistors M5 and M6 are turned on. The signal of the first power supply terminal VDD generates current through the driving transistor M3, driving the OLED to emit light.

[0138] For example, if the working timing of the pixel circuit described above is the first frame, and the refresh rate of the first frame needs to be maintained in the second frame (i.e., the second frame does not need to be refreshed), then during the data writing stage T2', the first scanning transistor M2 needs to be turned off. This requires the shift register's drive signal output terminal OP(n) provided in this embodiment to input a low-level signal, i.e. Figure 5 The second scan control terminal N_Scan, which originally input a high-level signal (dashed line A), needs to be changed to a low-level signal to achieve a refresh rate maintenance frame where the second frame is the same as the first frame. However, the embodiment provided in this disclosure... Figures 1-3 The shift register shown can achieve different refresh rates in different areas of the display panel.

[0139] The following is based on Figure 1 Taking the shift register shown as an example, combined with Figure 6 The signal timing diagram shown illustrates the working principle of the shift register provided in the embodiments of this disclosure, which enables the control of the display panel to achieve different refresh rates in different areas.

[0140] Specifically, Figure 6The signal timing diagram shown only takes the input (IP) and output (OP(1), OP(2), OP(3), OP(4)) of the first four-stage shift registers as an example. For example, when the area corresponding to the second and third rows of pixels in the display panel is a low refresh rate area, and the area corresponding to the first and fourth rows of pixels is a high refresh rate area, when the signal of the cascaded signal output terminal GP(1) of the first-stage shift register and the signal of the reverse signal output terminal Anti-GP(0) of the previous stage are both low level signals (at time t1), the third switching transistor T3 and the fourth switching transistor T4 are both turned on, that is, at time t1, the low level signal of the masking signal terminal Vms is latched in the first capacitor C1 of the selection output module 4. When the first-stage cascaded signal output terminal GP(1) outputs a high level (at time T1"), then the fourth node When the signal at P4 is low and the signal at the fifth node P5 is high, the seventh switching transistor T7 is turned on. Since the first capacitor C1 maintains the low-level signal at the masking signal terminal Vms at time t1, the fifth switching transistor T5 is turned on and the sixth switching transistor T6 is turned off. At time T1", the drive signal output terminal OP(1) of the first-stage shift register outputs the high-level signal at the first power supply terminal VGH, thereby achieving a high refresh rate for the first row of pixels in the display area. Of course, the duration of the high-level signal at the first power supply terminal VGH output by the drive signal output terminal OP(1) of the first-stage shift register can be set as needed. For example, the duration of the high-level signal at the first power supply terminal VGH output by the drive signal output terminal OP(1) of the first-stage shift register overlaps with the high-level signal at the first power supply terminal VGH output by the drive signal output terminal OP(4) of the fourth-stage shift register, which can precharge the pixel circuit corresponding to the drive signal output terminal OP(4) of the fourth-stage shift register. Similarly, the duration of the output level signal at the drive signal output terminal OP(n) of other shift registers is similar and will not be described further.

[0141] When the signal at the cascaded signal output terminal GP(2) of the second-stage shift register and the signal at the reverse signal output terminal Anti-GP(1) of the previous stage are both low-level signals (at time t2), the third switching transistor T3 and the fourth switching transistor T4 are both turned on, that is, at time t2, the high-level signal of the masking signal terminal Vms is latched in the first capacitor C1 of the selection output module 4; when the second-stage cascaded signal output terminal GP(2) outputs a high level (at time T2"), the signal of the fourth node P4 is a low-level signal and the signal of the fifth node P5 is a high-level signal, then the seventh switching transistor T7 is turned on. Since the first capacitor C1 maintains the high-level signal of the masking signal terminal Vms at time t1, the fifth switching transistor T5 is turned off and the sixth switching transistor T6 is turned on. Then at time T2", the drive signal output terminal OP(2) of the second-stage shift register outputs a low-level signal of the second power supply terminal VGL, realizing the low refresh rate of the second row of pixels in the display area;

[0142] When the signal at the cascaded signal output terminal GP(3) of the third-stage shift register and the signal at the anti-GP(2) of the previous stage are both low-level signals (at time t3), the third switching transistor T3 and the fourth switching transistor T4 are both turned on, that is, at time T3, the high-level signal of the masking signal terminal Vms is latched in the first capacitor C1 of the selection output module 4; when the third-stage cascaded signal output terminal GP(3) outputs a high level (at time T3”), the signal of the fourth node P4 is a low-level signal and the signal of the fifth node P5 is a high-level signal, then the seventh switching transistor T7 is turned on. Since the first capacitor C1 maintains the high-level signal of the masking signal terminal Vms at time t1, the fifth switching transistor T5 is turned off and the sixth switching transistor T6 is turned on. Then at time T3”, the drive signal output terminal OP(3) of the third-stage shift register outputs a low-level signal of the second power supply terminal VGL, realizing the low refresh rate of the third row of pixels in the display area;

[0143] When the signal at the cascaded signal output terminal GP(4) of the fourth-stage shift register and the signal at the reverse signal output terminal Anti-GP(3) of the previous stage are both low-level signals (at time t4), the third switching transistor T3 and the fourth switching transistor T4 are both turned on. That is, at time t4, the low-level signal of the masking signal terminal Vms is latched into the first capacitor C1 of the selection output module 4. When the fourth-stage cascaded signal output terminal GP(4) outputs a high level (at time T4"), the signal of the fourth node P4 is a low-level signal and the signal of the fifth node P5 is a high-level signal. Then the seventh switching transistor T7 is turned on. Since the first capacitor C1 maintains the low-level signal of the masking signal terminal Vms at time t1, the fifth switching transistor T5 is turned on and the sixth switching transistor T6 is turned off. Then at time T4", the drive signal output terminal OP(4) of the fourth-stage shift register outputs a high-level signal of the first power supply terminal VGH, realizing a high refresh rate of the fourth row of pixels in the display area.

[0144] Therefore, when a low refresh rate is required in a certain area of ​​the display panel, a high-level signal is supplied through the masking signal terminal Vms, and the drive signal output terminal continuously outputs a low level, corresponding to the oxide switching transistors of the pixel circuit in the display panel. Figure 3 If M2 is cut off, the data voltage in the display panel will not be charged, and the state of the previous frame will be maintained, thereby achieving a low refresh rate in this area.

[0145] Optionally, based on the duration of the high-level signal input at the masking signal terminal Vms (e.g., the working time of 2-3 rows of pixel circuits), and combined with the signals from the cascaded signal output terminal and the reverse signal output terminal of the previous stage, the oxide switching transistors of the pixel circuits in different rows of the same frame can be selectively turned on or off, thereby achieving the refresh rate of different rows of the display panel.

[0146] Furthermore, according to Figure 6 The signal timing diagram shown is for Figure 1 The signal output from the drive signal output terminal OP(n) of the shift register shown is simulated, and the simulation diagram is as follows. Figure 7 As shown in the figure, the horizontal axis represents time and the vertical axis represents voltage. It can be seen that the embodiments of this disclosure can control the signal output by the drive signal output terminal OP(n), enabling different refresh rates in different areas of the display panel. That is, high and low refresh rates can coexist within the same frame. Furthermore, the embodiments of this disclosure are not limited to implementing different refresh rates in a fixed area of ​​the display panel; they can achieve dynamic refresh in any area, thereby reducing the power consumption of the display panel.

[0147] It should be noted that the embodiments disclosed herein only use the area corresponding to the second row of pixels and the third row of pixels in the display panel as an example to illustrate the working process of the shift register. Of course, a low refresh rate can be achieved for any area in the display panel.

[0148] It should be noted that in practical applications, the specific voltage values ​​of the above signals can be designed and determined according to the actual application environment, and are not limited here.

[0149] Based on the same inventive concept, this disclosure also provides a driving method for the above-mentioned shift register, wherein, as Figure 8 As shown, it may include:

[0150] S801, In the first refresh rate stage, the latch module provides the control signal of the masking signal terminal to the selection output module based on the signal from the cascaded signal output terminal and the inverted signal output terminal of the previous stage; the selection output module, in response to the control signal of the masking signal terminal, provides the signal of the first power supply terminal to the drive signal output terminal; for example, in the first refresh rate stage, the latch module provides the low-level control signal of the masking signal terminal to the selection output module based on the signal from the cascaded signal output terminal of this stage and the inverted signal output terminal of the previous stage; the selection output module, in response to the low-level control signal of the masking signal terminal, provides the high-level signal of the first power supply terminal to the drive signal output terminal.

[0151] S802, Second refresh rate stage: The latch module provides the control signal of the masking signal terminal to the selection output module based on the signal of the cascaded signal output terminal and the reverse signal output terminal of the previous stage; the selection output module responds to the control signal of the masking signal terminal and provides the signal of the second power supply terminal to the drive signal output terminal.

[0152] For example, in the second refresh rate stage, the latch module provides a high-level control signal from the masking signal terminal to the selection output module based on the signals from the cascaded signal output terminal of this stage and the inverted signal output terminal of the previous stage; the selection output module responds to the high-level control signal from the masking signal terminal by providing a low-level signal from the first power supply terminal to the drive signal output terminal.

[0153] Specifically, the first refresh rate stage corresponds to the high refresh rate stage in the aforementioned shift register, and the second refresh rate stage corresponds to the low refresh rate stage in the aforementioned shift register.

[0154] The driving principle and specific implementation of this driving method are the same as those of the shift register in the above embodiments. Therefore, this driving method can be implemented by referring to the specific implementation of the shift register in the above embodiments, and will not be repeated here.

[0155] Based on the same inventive concept, this disclosure also provides a gate driving circuit, such as... Figure 9 As shown, the present disclosure includes multiple cascaded shift registers SR(1), SR(2)...SR(n-1), SR(n)...SR(N-1), SR(N) (a total of N shift registers, 1≤n≤N, where n is an integer); wherein, the input signal terminal IP of the first-stage shift register SR(1) is configured to be coupled to the frame trigger signal terminal STV;

[0156] In each pair of adjacent shift registers, the input signal terminal IP of the subsequent shift register SR(n) is configured to be coupled to the cascaded signal output terminal GP(n) of the preceding shift register SR(n-1).

[0157] Specifically, the specific structure of each shift register in the gate driving circuit described above is the same as that of the shift registers described in this disclosure in terms of function and structure, and the repetitions will not be repeated. This gate driving circuit can be configured in a liquid crystal display panel or in an electroluminescent display panel, and is not limited thereto.

[0158] Based on the same inventive concept, this disclosure also provides a display device, including the gate driving circuit described above. The principle by which this display device solves the problem is similar to that of the aforementioned shift register; therefore, the implementation of this display device can refer to the implementation of the aforementioned shift register, and the repetitions will not be repeated here.

[0159] In specific implementation, the display device provided in the embodiments of this disclosure can be as follows: Figure 10 The mobile phone shown is an example. Of course, the display device provided in this embodiment can also be any product or component with display function, such as a tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0160] In specific implementations, the display device provided in the embodiments of this disclosure can be a liquid crystal display device or an organic light-emitting display device.

[0161] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0162] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A shift register, wherein, The application relates to a shift module, a reverse output module, a latch module and a selection output module. The shift module is coupled with an input signal end and a cascade signal output end respectively; the shift module is configured to make the cascade signal output end output a cascade signal in response to a signal of the input signal end; The reverse output module is coupled with the cascade signal output end, a first power supply end, a second power supply end and a reverse signal output end respectively; the reverse output module is configured to make the reverse signal output end output a signal opposite to the cascade signal output end in response to a signal of the cascade signal output end; The latch module is coupled with a masking signal end, the cascade signal output end and a reverse signal output end of a previous stage respectively; the latch module is configured to make an output end of the latch module output a control signal of the masking signal end in response to signals of the cascade signal output end and the reverse signal output end of the previous stage; The selection output module is coupled with the first power supply end, the second power supply end, the output end of the latch module and a driving signal output end respectively; the selection output module is configured to provide a signal of the first power supply end or the second power supply end to the driving signal output end in response to a signal of the output end of the latch module.

2. The shift register of claim 1, wherein, The reverse output module comprises a first switch transistor and a second switch transistor; the first switch transistor and the second switch transistor are different in type; wherein a gate of the first switch transistor is coupled with the cascade signal output end, a first pole of the first switch transistor is coupled with the first power supply end, and a second pole of the first switch transistor is coupled with the reverse signal output end; a gate of the second switch transistor is coupled with the cascade signal output end, a first pole of the second switch transistor is coupled with the second power supply end, and a second pole of the second switch transistor is coupled with the reverse signal output end.

3. The shift register of claim 2, wherein, The latch module comprises a third switch transistor and a fourth switch transistor; wherein a gate of the third switch transistor is coupled with the cascade signal output end, a first pole of the third switch transistor is coupled with the masking signal end, and a second pole of the third switch transistor is coupled with a first pole of the fourth switch transistor; a gate of the fourth switch transistor is coupled with the reverse signal output end of the previous stage, and a second pole of the fourth switch transistor is the output end of the latch module.

4. The shift register of claim 3, wherein, The selection output module comprises a fifth switch transistor, a sixth switch transistor and a first capacitor; the fifth switch transistor and the sixth switch transistor are different in type; wherein a gate of the fifth switch transistor is coupled with the second pole of the fourth switch transistor, and a first pole of the fifth switch transistor is coupled with the driving signal output end; a gate of the sixth switch transistor is coupled with the second pole of the fourth switch transistor, a first pole of the sixth switch transistor is coupled with the second power supply end, and a second pole of the sixth switch transistor is coupled with the driving signal output end; a first end of the first capacitor is coupled with the first power supply end, and a second end of the first capacitor is coupled with the second pole of the fourth switch transistor.

5. The shift register of claim 4, wherein, The second electrode of the fifth switch transistor is coupled with the cascade signal output end.

6. The shift register of claim 4, wherein, The selection output module further comprises a seventh switch transistor; the type of the seventh switch transistor is the same as that of the fifth switch transistor; the gate electrode of the seventh switch transistor is coupled with the shift module; the first electrode of the seventh switch transistor is coupled with the first power supply end; and the second electrode of the seventh switch transistor is coupled with the second electrode of the fifth switch transistor.

7. The shift register of claim 5 or 6, wherein, Further comprising an eighth switch transistor; the gate electrode of the eighth switch transistor is coupled with the shift module; the first electrode of the eighth switch transistor is coupled with the second power supply end; and the second electrode of the eighth switch transistor is coupled with the driving signal output end.

8. The shift register of claim 7, wherein, The first switch transistor, the third switch transistor, the fourth switch transistor, the fifth switch transistor and the eighth switch transistor are all P-type transistors; and the second switch transistor and the sixth switch transistor are both N-type transistors.

9. The shift register of claim 7, wherein, The shift module comprises: An input circuit is coupled with the input signal end, the first clock signal end, the second power supply end, the first node and the second node respectively; the input circuit is configured to provide the signal of the input signal end to the first node and the second node in response to the signal of the first clock signal end; A node control circuit is coupled with the first node, the second node, the third node, the fourth node, the fifth node, the first power supply end, the second power supply end, the first clock signal end and the second clock signal end respectively; the node control circuit is configured to adjust the signals of the first node, the second node, the third node, the fourth node and the fifth node, so that the cascade signal output end outputs the signal of the first power supply end or the signal of the second power supply end; A reset circuit is coupled with the first power supply end, a reset signal end, the first node, the fourth node and the fifth node respectively; the reset circuit is configured to reset the cascade signal output by the cascade signal output end in response to the signal of the reset signal end; A first cascade output circuit is coupled with the fourth node, the first power supply end and the cascade signal output end respectively; the first cascade output circuit is configured to provide the signal of the first power supply end to the cascade signal output end in response to the signal of the fourth node; and the gate electrode of the seventh switch transistor is coupled with the fourth node. A second cascade output circuit is coupled with the fifth node, the second power supply end and the cascade signal output end respectively; the second cascade output circuit is configured to provide the signal of the second power supply end to the cascade signal output end in response to the signal of the fifth node; and the gate electrode of the eighth switch transistor is coupled with the fifth node.

10. The shift register of claim 9, wherein, The input circuit comprises a ninth switch transistor, a tenth switch transistor and an eleventh switch transistor. A gate of the ninth switch transistor is coupled with the first clock signal end, a first pole of the ninth switch transistor is coupled with the input signal end, and a second pole of the ninth switch transistor is coupled with the first node; A gate of the tenth switch transistor is coupled with the first clock signal end, a first pole of the tenth switch transistor is coupled with the input signal end, and a second pole of the tenth switch transistor is coupled with a first pole of the eleventh switch transistor; A gate of the eleventh switch transistor is coupled with the second power supply end, and a second pole of the eleventh switch transistor is coupled with the second node.

11. The shift register of claim 9, wherein, The node control circuit comprises a twelfth switch transistor, a thirteenth switch transistor, a fourteenth switch transistor, a fifteenth switch transistor, a sixteenth switch transistor, a seventeenth switch transistor, an eighteenth switch transistor, a nineteenth switch transistor, a second capacitor and a third capacitor; wherein A gate of the twelfth switch transistor is coupled with the first clock signal end, a first pole of the twelfth switch transistor is coupled with the second power supply end, and a second pole of the twelfth switch transistor is coupled with a third node; A gate of the thirteenth switch transistor is coupled with the first node, a first pole of the thirteenth switch transistor is coupled with the first clock signal end, and a second pole of the thirteenth switch transistor is coupled with the third node; A gate and a first pole of the fourteenth switch transistor are both coupled with the second node, and a second pole of the fourteenth switch transistor is coupled with a fifth node; A gate of the fifteenth switch transistor is coupled with the second node, a first pole of the fifteenth switch transistor is coupled with the second clock signal end, and a second pole of the fifteenth switch transistor is coupled with a first pole of the sixteenth switch transistor; A gate of the sixteenth switch transistor is coupled with the third node, and a second pole of the sixteenth switch transistor is coupled with the first power supply end; A first end of the second capacitor is coupled with the second node, and a second end of the second capacitor is coupled with the first pole of the sixteenth switch transistor; A gate of the seventeenth switch transistor is coupled with the second power supply end, a first pole of the seventeenth switch transistor is coupled with the third node, and a second pole of the seventeenth switch transistor is coupled with a gate of the eighteenth switch transistor; A first pole of the eighteenth switch transistor is coupled with the second clock signal end, and a second pole of the eighteenth switch transistor is coupled with a first pole of the nineteenth switch transistor; A gate of the nineteenth switch transistor is coupled with the second clock signal end, and a second pole of the nineteenth switch transistor is coupled with the fourth node; A first end of the third capacitor is coupled with the gate of the eighteenth switch transistor, and a second end of the third capacitor is coupled with the second pole of the eighteenth switch transistor.

12. The shift register of claim 9, wherein, The reset circuit comprises a twentieth switch transistor, a twenty-first switch transistor and a twenty-second switch transistor; wherein A gate of the twentieth switch transistor is coupled with the reset signal terminal, a first electrode of the twentieth switch transistor is coupled with the first power supply terminal, and a second electrode of the twentieth switch transistor is coupled with the first node and a gate of the twenty-first switch transistor; A first electrode of the twenty-first switch transistor is coupled with the first power supply terminal, and a second electrode of the twenty-first switch transistor is coupled with the fourth node; A gate of the twenty-second switch transistor is coupled with the second power supply terminal, a first electrode of the twenty-second switch transistor is coupled with the first node, and a second electrode of the twenty-second switch transistor is coupled with the fifth node.

13. The shift register of claim 9, wherein, The first cascade output circuit comprises a twenty-third switch transistor and a fourth capacitor; A gate of the twenty-third switch transistor is coupled with the fourth node, a first electrode of the twenty-third switch transistor is coupled with the first power supply terminal, and a second electrode of the twenty-third switch transistor is coupled with the cascade signal output terminal; A first terminal of the fourth capacitor is coupled with the fourth node, and a second terminal of the fourth capacitor is coupled with the first power supply terminal.

14. The shift register of claim 9, wherein, The second cascade output circuit comprises a twenty-fourth switch transistor, a gate of the twenty-fourth switch transistor is coupled with the fifth node, a first electrode of the twenty-fourth switch transistor is coupled with the second power supply terminal, and a second electrode of the twenty-fourth switch transistor is coupled with the cascade signal output terminal.

15. A gate drive circuit, wherein, The shift register comprises a plurality of cascades of the shift register according to any one of claims 1-14. The input signal terminal of the first stage shift register is configured to be coupled with the frame trigger signal terminal. In every two adjacent shift registers, the input signal terminal of the next stage shift register is configured to be coupled with the cascade signal output terminal of the previous stage shift register.

16. A display device, wherein, The gate drive circuit comprises the shift register according to claim 15.

17. A driving method of a shift register as claimed in any one of claims 1 to 14, wherein, The gate drive circuit comprises: In a first refresh rate stage, the latch module provides the control signal of the masking signal terminal to the selection output module according to the signals of the cascade signal output terminal and the reverse signal output terminal of the previous stage; The selection output module provides the signal of the first power supply terminal to the drive signal output terminal in response to the control signal of the masking signal terminal; In a second refresh rate stage, the latch module provides the control signal of the masking signal terminal to the selection output module according to the signals of the cascade signal output terminal and the reverse signal output terminal of the previous stage; and the selection output module provides the signal of the second power supply terminal to the drive signal output terminal in response to the control signal of the masking signal terminal.

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