Electroencephalogram signal multistage conditioning and amplifying device, equipment and system

Abstract

The embodiment of the invention relates to the field of electroencephalogram signal processing and brain-computer interfaces, and provides an electroencephalogram signal multi-stage conditioning and amplifying device, equipment and a system. The device comprises a reference signal buffer distribution module, a first-stage filtering module, eight paths of first-stage differential amplification modules, a second-stage filtering module, eight paths of second-stage differential amplification modules, a bias driving signal generation module and a differential ADC (Analog to Digital Converter) module, and the reference signal is combined for common conditioning, so that the signal-to-noise ratio of the electroencephalogram signal obtained by conditioning is improved.

Description

Technical Field

[0001] This application relates to the technical fields of electroencephalogram (EEG) signal processing and brain-computer interface, and particularly relates to a multi-stage conditioning and amplifying device, equipment and system for EEG signals. Background Art

[0002] Obtaining stable and reliable EEG signals is a prerequisite for scalp EEG-based brain-computer interface technology. Electroencephalogram (EEG) signals are spontaneous bioelectrical activities at the scale of brain cell populations. EEG signals are usually very weak, with amplitudes generally between 1 and 100 μV, and are easily affected by various physiological and environmental noises, resulting in a reduced signal-to-noise ratio. Among them, electromagnetic interference is the most critical noise, such as the 1 / f noise of components themselves, thermal noise generated by circuits, 50 Hz mains power frequency noise, differential mode noise caused by circuit asymmetry, DC bias error, etc. In order to reduce the influence of these noises and improve the signal-to-noise ratio, it is necessary to continuously improve the EEG signal conditioning and acquisition system, which is crucial for improving the accuracy and reliability of EEG signal research.

[0003] In existing EEG signal conditioning circuits, the collected EEG signals are usually directly subjected to AD conversion after only passing through a simple filtering circuit. The utilization rate of the AD dynamic range is low, the influence of AD quantization noise is large, and the common-mode rejection ratio of the AD circuit is not high, resulting in a large common-mode noise and a low signal-to-noise ratio, and the EEG signal acquisition effect is not ideal. Summary of the Invention

[0004] Embodiments of this application provide a multi-stage conditioning and amplifying device, equipment and system for EEG signals, which can perform two-stage filtering and two-stage amplification processing on EEG signals, and perform common conditioning in combination with reference signals, improving the signal-to-noise ratio of the conditioned EEG signals.

[0005] In a first aspect of the embodiments of this application, a multi-stage conditioning and amplifying device for EEG signals is provided. The device includes a reference signal buffer and distribution module, a first-stage filtering module, an 8-channel first-stage differential amplification module, a second-stage filtering module, an 8-channel second-stage differential amplification module, a bias drive signal generation module, and a differential ADC module, where,

[0006] The signal output port of the reference signal buffer and distribution module is connected to the first type of input port of the first filtering module, and the second type of input port of the first filtering module is the signal receiving port for 8-channel EEG signals;

[0007] The 8-channel first type of signal output ports of the first-stage filtering module are respectively and correspondingly connected to the first input ports of the 8-channel first-stage differential amplification module, and the 8-channel second type of signal output ports of the first-stage filtering module are respectively and correspondingly connected to the second input ports of the 8-channel first-stage differential amplification module,

[0008] The output ports of the 8-channel first-stage differential amplification module are connected to the corresponding 8-channel input ports of the second-stage filtering module. The 8-channel output ports of the second-stage filtering module are respectively and correspondingly connected to the input ports of the 8-channel second-stage differential amplification module. The first type of output ports of the 8-channel second-stage differential amplification module are connected to the corresponding signal input ports in the differential ADC module. The second type of output ports of the 8-channel second-stage differential amplification module are connected to the input port of the bias driving signal generating module. The corresponding signal output ports in the differential ADC module are connected to the microprocessor; the output port of the bias driving signal generating module is connected to the bias driving electrode;

[0009] The reference signal buffer and distribution module is used to receive the reference signal of the collected electroencephalogram (EEG) signal and generate 8 identical and independent reference signals according to the reference signal;

[0010] The gain of the first-stage differential amplification module is less than the gain of the second-stage differential amplification module.

[0011] In this example, the EEG signal is filtered by the first-stage filtering module to retain the EEG signal in the effective frequency band. At the same time, the reference signal passes through the buffer distribution circuit to generate 8 identical and independent reference signals, which are respectively used as the differential reference input signals of the 8-channel EEG signals. After the same filtering and conditioning as the electrical parameters of the EEG signal, the processed EEG signal and the corresponding reference signal of each channel are used as a differential pair and input into the first-stage differential amplification circuit of the corresponding channel for amplification to improve the signal-to-noise ratio. The output differential signal passes through the second-stage low-pass filtering circuit to further attenuate the high-frequency noise in the signal, and then enters the second-stage differential amplification circuit for further amplification. Finally, the 8-channel parallel differential ADC circuit realizes the analog-to-digital conversion of the 8-channel EEG signals. Finally, the MCU controller realizes the acquisition, transmission and processing of the EEG signals. At the same time, the output of the bias driving signal is also realized, that is, the DC bias of the signal output by the second-stage differential amplification circuit generates a common-mode voltage signal with the opposite polarity through the bias driving signal generating module. This signal is connected to the human body through the bias driving electrode to provide a common-mode reference voltage for the human body, and limits the common-mode interference noise within a very narrow range, reducing the common-mode interference of the EEG signal and further improving the signal-to-noise ratio of the EEG signal.

[0012] In a specific implementation manner, the reference signal buffer and distribution module includes a first unity-gain buffer, a second unity-gain buffer, a capacitor C60, a capacitor C61, a capacitor C62 and a capacitor C63, where,

[0013] The first port, fifth port, sixth port, and tenth port of the first unity-gain buffer are used to receive the reference signal of the EEG signal. The third port of the first unity-gain buffer is connected to the positive power supply port and the first end of the 60th capacitor. The second end of the 60th capacitor is grounded. The eighth port of the first unity-gain buffer is connected to the negative power supply port and the first end of the 61st capacitor. The second end of the 61st capacitor is grounded. The second port, fourth port, seventh port, and ninth port of the first unity-gain buffer are respectively connected to the corresponding first-type input ports in the first filtering module;

[0014] The first port, fifth port, sixth port, and tenth port of the second unity-gain buffer are used to receive the reference signal of the EEG signal. The third port of the second unity-gain buffer is connected to the positive power supply port and the first end of the 62nd capacitor. The second end of the 62nd capacitor is grounded. The eighth port of the second unity-gain buffer is connected to the negative power supply port and the first end of the 63rd capacitor. The second end of the 63rd capacitor is grounded. The second port, fourth port, seventh port, and ninth port of the second unity-gain buffer are respectively connected to the corresponding first-type input ports in the first filtering module.

[0015] In a specific implementation manner, the first-stage differential amplification module includes a first amplifier chip, a 168th capacitor, a 112th resistor, a 169th capacitor, a 170th capacitor, a 171st capacitor, a 172nd capacitor, a 173rd capacitor, and a 113th resistor. Among them,

[0016] After a 168th capacitor is connected in parallel between the first signal input port and the second signal input port of the first-stage differential amplification module, they are respectively connected to the first port and the fourth port of the first amplifier chip. A 112th resistor is connected in series between the second port and the third port of the first amplifier chip;

[0017] The fifth port of the first amplifier chip is connected to the first end of the 169th capacitor and the positive power supply port. The second end of the 169th capacitor is grounded;

[0018] The sixth port of the first amplifier chip is connected to the fourteenth port. The fourteenth port of the first amplifier chip is the second output port of the first-stage differential amplification module;

[0019] The seventh port of the first amplifier chip is grounded. The eighth port of the first amplifier chip is connected to the negative power supply port, the zero port, and the first end of the 170th capacitor. The second end of the 170th capacitor is grounded. The ninth port of the first amplifier chip is grounded;

[0020] The twelfth port of the first amplification chip is connected to the first end of the 173rd capacitor and the first end of the 113th resistor. The second end of the 173rd capacitor is grounded. The second end of the 113th resistor is connected to the fifteenth port of the first amplification chip. The fifteenth port of the first amplification chip is the second output port of the first-stage differential amplification module;

[0021] The thirteenth port of the first amplification chip is connected to the first end of the 172nd capacitor and the negative power supply port. The second end of the 172nd capacitor is grounded. The sixteenth port of the first amplification chip is connected to the first end of the 171st capacitor and the positive power supply port. The second end of the 171st capacitor is grounded.

[0022] In a specific implementation, the second-stage filtering module includes 8 second sub-filtering modules. The electrical parameters of the 8 second sub-filtering modules are the same. The input ports of the 8 second sub-filtering modules are respectively connected to the output ports of the corresponding first-stage differential amplification modules. The output ports of the 8 second sub-filtering modules are respectively connected to the input ports of the corresponding second-stage differential amplification modules;

[0023] The second sub-filtering module includes the 114th resistor, the 115th resistor, the 174th capacitor, and the 175th capacitor. The 114th resistor is connected in series between the first output port of the first-stage differential amplification module and the first end of the 174th capacitor. The first output port of the second sub-filtering module is connected between the first end of the 174th capacitor and the 114th resistor. The second end of the 174th capacitor is grounded;

[0024] The 115th resistor is connected in series between the second output port of the first-stage differential amplification module and the first end of the 175th capacitor. The second output port of the second sub-filtering module is connected between the first end of the 175th capacitor and the 115th resistor. The second end of the 175th capacitor is grounded.

[0025] In a specific implementation, the bias drive signal generation module includes a bias drive amplifier, a drive signal source network, an external resistor, a compensation capacitor, a first resistor, and a second resistor, where,

[0026] The driving signal source network is connected to the second - type output ports of the eight - way second - stage differential amplification module. The output port of the driving signal source network is connected to the first end of the external resistor, the first end of the compensation capacitor, and the inverting input terminal of the bias driving amplifier. The second end of the external resistor and the second end of the compensation capacitor are connected to the output terminal of the bias driving amplifier. The non - inverting input terminal of the bias driving amplifier is connected to the first end of the first resistor and the first end of the second resistor. The second end of the first resistor is connected to the positive power supply port, and the second end of the second resistor is connected to the negative power supply port.

[0027] In a specific implementation, the capacitance value of the compensation capacitor ranges from 1.5 nF to 500 pF.

[0028] In a specific implementation, the first - stage filtering module includes a low - pass filtering circuit and a high - pass filtering circuit. The cut - off frequency of the low - pass filtering circuit is a frequency value between 1.5 KHz and 40 kHz, and the cut - off frequency of the high - pass filtering circuit is less than 0.5 Hz.

[0029] In a specific implementation, the amplification gain value of the first - stage differential amplification module is an amplification gain value between 2 and 10.

[0030] In a second aspect of the embodiments of the present application, a multi - stage conditioning and amplifying device for electroencephalogram signals is provided, including a housing and the multi - stage conditioning and amplifying device for electroencephalogram signals as described in any item of the first aspect. The multi - stage conditioning and amplifying device for electroencephalogram signals is arranged inside the housing.

[0031] In a third aspect of the embodiments of the present application, a high - signal - to - noise - ratio dry - electrode electroencephalogram signal acquisition system is provided. The high - signal - to - noise - ratio dry - electrode electroencephalogram signal acquisition system includes a rigid - flex active electrode device and the multi - stage conditioning and amplifying device for electroencephalogram signals as described in any item of the first aspect. The rigid - flex active electrode device is connected to the multi - stage conditioning and amplifying device for electroencephalogram signals. The rigid - flex active electrode device is used to send the collected electroencephalogram signals, reference signals, and common - mode bias voltage signals to the multi - stage conditioning and amplifying device for electroencephalogram signals, and the multi - stage conditioning and amplifying device for electroencephalogram signals is used to amplify and condition the received electroencephalogram signals. Description of the Drawings

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0033] Figure 1This application provides a structural schematic diagram of a high signal-to-noise ratio dry electrode electroencephalogram (EEG) signal acquisition system in an embodiment of the present application;

[0034] Figure 2 This application provides a structural schematic diagram of a multi-stage conditioning and amplification device for EEG signals in an embodiment of the present application;

[0035] Figure 3 This application provides a structural schematic diagram of a reference signal buffer and distribution module in an embodiment of the present application;

[0036] Figure 4 This application provides a structural schematic diagram of a first-stage differential amplification module in an embodiment of the present application;

[0037] Figure 5 This application provides a circuit structural schematic diagram of a second-stage differential amplification module and a differential ADC module in an embodiment of the present application;

[0038] Figure 6 This application provides a circuit structural schematic diagram of a bias drive signal generation module in an embodiment of the present application;

[0039] Figure 7 This application provides a PCB layer stack architecture diagram of a circuit board of a multi-stage conditioning and amplification device for EEG signals in an embodiment of the present application. Detailed implementation manners

[0040] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0041] The terms "first", "second", etc. in the specification, claims and drawings of the present application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products or devices.

[0042] References to "embodiments" in this application mean that specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of this application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described in this application can be combined with other embodiments.

[0043] To better understand a multi-level conditioning and amplifying device for electroencephalogram (EEG) signals provided in an embodiment of this application, a brief introduction to the existing EEG signal acquisition scheme will be given first.

[0044] The EEG acquisition and amplification circuit based on wet electrodes has been relatively mature. However, wet electrodes have problems such as long preparation time and inconvenient wearing, which severely restrict the practical application of brain-computer interfaces. For the EEG signal acquisition based on dry electrodes, due to the relatively high contact impedance between the dry electrodes and the skin, more noise interference is easily introduced, resulting in a relatively low signal-to-noise ratio (SNR) of the acquired EEG signals, and the clarity and accuracy of the signals are affected to a certain extent. Moreover, the contact state between the electrodes and the skin may be affected by various factors, such as sweating, oil secretion of the skin, and interference from hair, etc., leading to large fluctuations in the signals, which pose higher requirements for the filtering, amplification, and acquisition of EEG signals.

[0045] Currently, various control algorithms have emerged in software design, which have improved the SNR of EEG signals to a certain extent, but have prolonged the data processing time and reduced the real-time performance of the system. In hardware design, the structure of an EEG acquisition device using active electrodes + conditioning and acquisition circuits has emerged. Although this structure is relatively complex, it can enhance the anti-interference ability at the source of EEG signals, which helps to improve its SNR and is a very promising technical means. However, for active electrodes, especially under the application conditions of dry electrodes, the circuit principle and structure, PCB layout and wiring, and stack-up structure design directly affect the integrity and anti-interference ability of EEG signals; while for the front-end analog conditioning circuit of an EEG acquisition device, such as low-pass filtering, high-pass filtering, multi-level amplification, AD conversion and other circuits, factors such as circuit principle, front-back interconnection relationship, and electrical parameter matching also affect the transmission integrity and noise suppression ability of EEG signals, and a comprehensive design of the system is required to ensure signal quality. Therefore, the research on high-SNR EEG acquisition devices still faces various technical challenges.

[0046] In the existing EEG signal conditioning circuit, the acquired EEG signals are usually directly subjected to AD conversion only after passing through a simple filtering circuit. The utilization rate of the AD dynamic range is low, the AD quantization noise has a great impact, and the common-mode rejection ratio of the AD circuit is not high, resulting in a large common-mode noise and a relatively low SNR, and the EEG signal acquisition effect is not ideal.

[0047] To solve the above technical problems, the present application provides an electroencephalogram (EEG) signal multi-stage conditioning and amplification device, which can perform two-stage filtering and two-stage amplification processing on EEG signals, and jointly condition them in combination with reference signals, improving the signal-to-noise ratio of the conditioned EEG signals.

[0048] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of a high signal-to-noise ratio dry electrode EEG signal acquisition system provided by an embodiment of the present application. As Figure 1 shown, the high signal-to-noise ratio dry electrode EEG signal acquisition system 100 includes an EEG signal multi-stage conditioning and amplification device 200 and a rigid-flex active electrode device 300. The rigid-flex active electrode device is connected to the EEG signal multi-stage conditioning and amplification device. The rigid-flex active electrode device is used to send the collected EEG signals and reference signals to the EEG signal multi-stage conditioning and amplification device. The EEG signal multi-stage conditioning and amplification device is used to amplify and condition the received EEG signals, and generate a common-mode bias voltage signal and send it to the EEG signal multi-stage conditioning and amplification device.

[0049] Among them, after receiving the EEG signals and reference signals, the EEG signal multi-stage conditioning and amplification device 200 performs filtering and differential amplification processing to obtain the finally available EEG signals, greatly improving the signal quality and signal-to-noise ratio of the acquired EEG signals.

[0050] Specifically, the EEG signal multi-stage conditioning and amplification device 200 and the rigid-flex active electrode device 300 are interconnected by plugging in with high-density ultra-low-height board connectors AXT616124 and AXT516124. The terminals of the connectors are made of copper alloy and are subjected to bottom-layer electroplating of Ni and surface-layer electroplating of Au, improving the contact stability and durability.

[0051] Please refer to Figure 2 , Figure 2 which is a schematic structural diagram of an EEG signal multi-stage conditioning and amplification device provided by an embodiment of the present application. As Figure 2 shown, this method is applied to a high signal-to-noise ratio dry electrode EEG signal acquisition system. The device includes a reference signal buffer and distribution module 1, a first-stage filtering module 2, an 8-channel first-stage differential amplification module 3, a second-stage filtering module 4, an 8-channel second-stage differential amplification module 5, a bias drive signal generation module 6, and a differential ADC module 7. Among them,

[0052] the signal output port of the reference signal buffer and distribution module 1 is connected to the first type of input port of the first filtering module, and the second type of input port of the first filtering module is the signal receiving port for 8-channel EEG signals;

[0053] The eight first - type signal output ports of the first - stage filtering module are respectively and correspondingly connected to the first input ports of the eight first - stage differential amplification modules. The eight second - type signal output ports of the first - stage filtering module 2 are respectively and correspondingly connected to the second input ports of the eight first - stage differential amplification modules 3.

[0054] The output ports of the eight first - stage differential amplification modules 3 are connected to the corresponding eight input ports of the second - stage filtering module. The eight output ports of the second - stage filtering module 4 are respectively and correspondingly connected to the input ports of the eight second - stage differential amplification modules 5. The first - type output ports of the eight second - stage differential amplification modules 5 are connected to the corresponding signal input ports in the differential ADC module 7. The second - type output ports of the eight second - stage differential amplification modules 5 are connected to the input port of the bias driving signal generation module. The corresponding signal output ports in the differential ADC module 7 are connected to the microprocessor; the output port of the bias driving signal generation module 6 is connected to the bias driving electrode.

[0055] The reference signal buffer and distribution module 1 is used to receive the reference signal of the collected electroencephalogram signal and generate eight identical and independent reference signals according to the reference signal.

[0056] The gain of the first - stage differential amplification module 3 is less than the gain of the second - stage differential amplification module 5.

[0057] The first - stage filtering module 2 includes 16 first - stage sub - filtering modules. Each first - stage sub - filtering module includes a first - stage low - pass filtering circuit and a first - stage high - pass filtering circuit. Among the 16 first - stage sub - filtering modules, the signal input ports of 8 of them are first - type input ports, and the signal input ports of the other 8 are second - type input ports. The 8 first - stage sub - filtering modules with second - type input ports respectively receive the corresponding electroencephalogram signals. There are 8 electroencephalogram signals in total. The 8 first - stage sub - filtering modules with first - type input ports respectively receive the reference signals of the corresponding electroencephalogram signals. The electrical parameters of the 16 first - stage sub - filtering modules are the same. The first - stage low - pass filtering circuit is a passive RC low - pass filtering circuit. The resistance value of the resistor in the first - stage low - pass filtering circuit can be 4.02 kΩ, and the capacitance value can be 10 nF; the first - stage high - pass filtering circuit can be a passive RC high - pass filtering circuit. The resistance value of the resistor can be 220 kΩ, and the capacitance value is 4.7 μF. The output end of the first - stage low - pass filtering circuit is connected to the input end of the first - stage high - pass filtering circuit.

[0058] The electroencephalogram (EEG) signal passes through the first-stage low-pass filter circuit to attenuate high-frequency interference, and then passes through the first-stage high-pass filter circuit to filter out the DC bias component in the signal, thereby retaining the EEG signal in the effective frequency band. At the same time, the reference signal passes through the buffer distribution circuit to generate 8 identical and independent reference signals, which are respectively used as the differential reference input signals for the 8 EEG signals. Similarly, they are then conditioned by the low-pass and high-pass filter circuits with the same electrical parameters as the EEG signal. Then, the processed EEG signal of each channel and the corresponding reference signal are used as a differential pair and input into the first-stage differential amplification module 3 of the corresponding channel for amplification to improve the signal-to-noise ratio. The output differential signal then passes through the second-stage filter module 4 to further attenuate the high-frequency noise in the signal, and then enters the second-stage differential amplification module 5 for further amplification. Finally, the 8-channel parallel differential ADC circuit realizes the analog-to-digital conversion of the 8 EEG signals, and finally the MCU controller realizes the acquisition, transmission, and processing of the EEG signals.

[0059] The device also realizes the generation and output of the bias drive signal, that is, the DC bias of the signal output by the second-stage differential amplification module 5 generates a common-mode voltage signal with the opposite polarity through the bias drive circuit. This signal is connected to the human body through the bias drive electrode to provide a common-mode reference voltage for the human body, and limits the common-mode interference noise within a very narrow range, which helps to reduce the common-mode interference of the EEG signals on the active electrode and the reference electrode. This signal is extremely weak and will not cause adverse effects on the human body.

[0060] In this example, the EEG signal passes through the first-stage filter module 2 for filtering to retain the EEG signal in the effective frequency band. At the same time, the reference signal passes through the buffer distribution circuit to generate 8 identical and independent reference signals, which are respectively used as the differential reference input signals for the 8 EEG signals. Similarly, they are then conditioned by the filter with the same electrical parameters as the EEG signal. The processed EEG signal of each channel and the corresponding reference signal are used as a differential pair and input into the first-stage differential amplification circuit of the corresponding channel for amplification to improve the signal-to-noise ratio. The output differential signal then passes through the second-stage low-pass filter circuit to further attenuate the high-frequency noise in the signal, and then enters the second-stage differential amplification circuit for further amplification. Finally, the 8-channel parallel differential ADC circuit realizes the analog-to-digital conversion of the 8 EEG signals, and finally the MCU controller realizes the acquisition, transmission, and processing of the EEG signals. At the same time, the generation and output of the bias drive signal are also realized, that is, the DC bias of the signal output by the second-stage differential amplification circuit generates a common-mode voltage signal with the opposite polarity through the bias drive signal generation module 6. This signal is connected to the human body through the bias drive electrode to provide a common-mode reference voltage for the human body, and limits the common-mode interference noise within a very narrow range, reducing the common-mode interference of the EEG signal and further improving the signal-to-noise ratio of the EEG signal.

[0061] In a specific implementation, such as Figure 3As shown, the reference signal buffer distribution module 1 includes a first unity-gain buffer 11, a second unity-gain buffer 12, a sixtieth capacitor C60, a sixty-first capacitor C61, a sixty-second capacitor C62, and a sixty-third capacitor C63. Among them,

[0062] The first port, fifth port, sixth port, and tenth port of the first unity-gain buffer 11 are used to receive the reference signal of the electroencephalogram signal. The third port of the first unity-gain buffer 11 is connected to the positive power supply port and the first end of the sixtieth capacitor C60. The second end of the sixtieth capacitor C60 is grounded. The eighth port of the first unity-gain buffer 11 is connected to the negative power supply port and the first end of the sixty-first capacitor C61. The second end of the sixty-first capacitor C61 is grounded. The second port, fourth port, seventh port, and ninth port of the first unity-gain buffer 11 are respectively connected to the corresponding first-type input ports in the first filtering module;

[0063] The first port, fifth port, sixth port, and tenth port of the second unity-gain buffer are used to receive the reference signal of the electroencephalogram signal. The third port of the second unity-gain buffer 12 is connected to the positive power supply port and the first end of the sixty-second capacitor. The second end of the sixty-second capacitor C62 is grounded. The eighth port of the second unity-gain buffer 12 is connected to the negative power supply port and the first end of the sixty-third capacitor C63. The second end of the sixty-third capacitor C63 is grounded. The second port, fourth port, seventh port, and ninth port of the second unity-gain buffer 12 are respectively connected to the corresponding first-type input ports in the first filtering module.

[0064] Among them, the input signal of the reference signal buffer distribution module 1 is the reference signal of the electroencephalogram signal. After receiving this reference signal, 8 identical and independent reference signals are generated through the first unity-gain buffer 11, the second unity-gain buffer 12, and their peripheral circuits. These 8 identical and independent reference signals are respectively input into the subsequent corresponding 8 first-stage differential amplification modules 3. The first unity-gain buffer 11 and the second unity-gain buffer 12 are the same unity-gain buffer, and specifically can be an AD8244 unity-gain buffer. Since 8 identical and independent reference signals can be generated, the driving ability of the reference signal is improved, and the coupling interference between channels is reduced.

[0065] In a specific implementation manner, such as Figure 4As shown, the first-stage differential amplification module 3 includes a first amplification chip 31, a one-hundred-and-sixty-eighth capacitor C168, a one-hundred-and-twelfth resistor R112, a one-hundred-and-sixty-ninth capacitor C169, a one-hundred-and-seventieth capacitor C170, a one-hundred-and-seventy-first capacitor C171, a one-hundred-and-seventy-second capacitor C172, a one-hundred-and-seventy-third capacitor C173, and a one-hundred-and-thirteenth resistor R113. Among them,

[0066] After a one-hundred-and-sixty-eighth capacitor C168 is connected in parallel between the first signal input port and the second signal input port of the first-stage differential amplification module 3, they are respectively connected to the first port and the fourth port of the first amplification chip 31. A one-hundred-and-twelfth resistor R112 is connected in series between the second port and the third port of the first amplification chip 31;

[0067] The fifth port of the first amplification chip 31 is connected to the first end of the one-hundred-and-sixty-ninth capacitor C169 and the positive power supply port, and the second end of the one-hundred-and-sixty-ninth capacitor C169 is grounded;

[0068] The sixth port of the first amplification chip 31 is connected to the fourteenth port, and the fourteenth port of the first amplification chip 31 is the second output port of the first-stage differential amplification module 3;

[0069] The seventh port of the first amplification chip 31 is grounded. The eighth port of the first amplification chip 31 is connected to the negative power supply port, the zero port, and the first end of the one-hundred-and-seventieth capacitor C170. The second end of the one-hundred-and-seventieth capacitor C170 is grounded, and the ninth port of the first amplification chip 31 is grounded;

[0070] The twelfth port of the first amplification chip 31 is connected to the first end of the one-hundred-and-seventy-third capacitor C173 and the first end of the one-hundred-and-thirteenth resistor R113. The second end of the one-hundred-and-seventy-third capacitor C173 is grounded, and the second end of the one-hundred-and-thirteenth resistor R113 is connected to the fifteenth port of the first amplification chip 31. The fifteenth port of the first amplification chip 31 is the second output port of the first-stage differential amplification module 3;

[0071] The thirteenth port of the first amplification chip 31 is connected to the first end of the one-hundred-and-seventy-second capacitor C172 and the negative power supply port. The second end of the one-hundred-and-seventy-second capacitor C172 is grounded. The sixteenth port of the first amplification chip 31 is connected to the first end of the one-hundred-and-seventy-first capacitor C171 and the positive power supply port. The second end of the one-hundred-and-seventy-first capacitor C171 is grounded.

[0072] Among them, the first amplification chip 31 can be a dual-channel precision instrumentation amplifier. The electrical parameters of the 8-channel first-stage differential amplification modules 3 are the same. In the single-channel fully differential amplification circuit formed, an RC low-pass filter circuit composed of R113 and C173 is designed to ensure the stability of the negative feedback loop.

[0073] In a specific implementation manner, such as Figure 2 shown, the second-stage filtering module 4 includes 8-channel second sub-filtering modules 41. The electrical parameters of the 8-channel second sub-filtering modules 41 are the same. The input ports of the 8-channel second sub-filtering modules 41 are respectively connected to the output ports of the corresponding first-stage differential amplification modules 3, and the output ports of the 8-channel second sub-filtering modules 41 are respectively connected to the input ports of the corresponding second-stage differential amplification modules 5.

[0074] Such as Figure 4 shown, the second sub-filtering module 41 includes the one hundred and fourteenth resistor R114, the one hundred and fifteenth resistor R115, the one hundred and seventy-fourth capacitor C174, and the one hundred and seventy-fifth capacitor C175. The first output port of the first-stage differential amplification module 3 is connected in series with the one hundred and fourteenth resistor R114 between the first end of the one hundred and seventy-fourth capacitor C174. The first output port of the second sub-filtering module (represented by AIN7P) is connected between the first end of the one hundred and seventy-fourth capacitor C174 and the one hundred and fourteenth resistor R114. The second end of the one hundred and seventy-fourth capacitor C174 is grounded;

[0075] The second output port of the first-stage differential amplification module 3 is connected in series with the one hundred and fifteenth resistor R115 between the first end of the one hundred and seventy-fifth capacitor C175. The second output port of the second sub-filtering module (represented by AIN7N) is connected between the first end of the one hundred and seventy-fifth capacitor C175 and the one hundred and fifteenth resistor R115. The second end of the one hundred and seventy-fifth capacitor C175 is grounded.

[0076] The differential output signal passes through the second-stage passive RC low-pass filter circuit (green frame) and can further attenuate the high-frequency noise in the differential signal.

[0077] In a specific implementation manner, such as Figure 5 shown, Figure 5 shows the circuit structure schematic diagrams of the second-stage differential amplification module 5 and the differential ADC module 7. The differential ADC module 7 includes 8-channel differential ADC circuits, which respectively correspond to the 8-channel second-stage differential amplification modules 5. Such as Figure 5 shown, a schematic diagram of one-channel second-stage differential amplification module 5 and differential ADC circuit. The second-stage differential amplification module 5 and the differential ADC circuit are implemented by the analog front-end integrated circuit ADS1299, and its circuit diagram is as Figure 5As shown in the figure. The ADS1299 is a high-performance integrated chip for physiological signal acquisition, which contains 8 low-noise programmable gain amplifiers (PGAs) and 8 synchronous sampling analog-to-digital converters (ADCs) inside. The input terminal can be configured as differential input, the common-mode rejection ratio (CMRR) is as high as 110 dB, and the DC input impedance is as high as 1 GΩ. The amplification gain of the PGA can be arbitrarily selected from the specifications of 1, 2, 4, 6, 8, 12, and 24. The conversion accuracy of the ADC is as high as 24 bits, and the sampling rate can be selected in the range of 250 SPS to 16 k SPS, which is very suitable for the acquisition of weak electroencephalogram signals.

[0078] In a specific implementation manner, as Figure 6 shown, the bias drive signal generation module 6 includes a bias drive amplifier 61, a drive signal source network 62, an external resistor R f , a compensation capacitor C f , a first resistor R1, and a second resistor R2, where

[0079] the drive signal source network 62 is connected to the second type of output ports of the 8-channel second-stage differential amplification module 5, and the output port of the drive signal source network 62 is connected to the first end of the external resistor R f , the first end of the compensation capacitor C f , and the inverting input terminal of the bias drive amplifier 61. The second end of the external resistor R f , the second end of the compensation capacitor C f is connected to the output terminal of the bias drive amplifier 61. The non-inverting input terminal of the bias drive amplifier 61 is connected to the first end of the first resistor R1 and the first end of the second resistor R2. The second end of the first resistor R1 is connected to the positive power supply port, and the second end of the second resistor R2 is connected to the negative power supply port.

[0080] The drive signal source network 62 includes 8 pairs of R p 1, R n 1, which are respectively connected to the corresponding electroencephalogram signal differential pairs, and the electroencephalogram signal differential pairs are represented as electroencephalogram signal 1 differential pair to electroencephalogram signal 8 differential pair.

[0081] The bias drive amplifier 61 (BIAS amp) is an in-built bias drive amplifier of the ADS1299. The drive signal source of the drive signal source network 62 comes from the differential signals of 8 channels of the second-stage differential amplification circuit, that is, the DC bias amounts in the EEG signals of 8 channels are superimposed, and a common-mode voltage amount BIAS_OUT with the opposite polarity is generated through the inverting proportional amplification circuit, and then connected to the human skin surface through the bias drive electrode to provide a common-mode reference voltage with the opposite polarity for the human body. In this way, most of the common-mode interference signals can be cancelled out, so as to suppress the common-mode noise on the EEG signals at the input end, and greatly improve the signal-to-noise ratio of the entire circuit.

[0082] The C in the circuit f is a compensation capacitor, which compensates the phase of the amplification circuit to prevent the circuit from self-exciting oscillation. The positive input terminal of the operational amplifier is one-half of the sum of the positive power supply AVDD and the negative power supply AVSS, thus forming a closed-loop circuit.

[0083] In a specific implementation manner, the capacitance value of the compensation capacitor ranges from 1.5 nF to 500 pF.

[0084] In a specific implementation manner, the first-stage filtering module 2 includes a low-pass filtering circuit and a high-pass filtering circuit. The cut-off frequency of the low-pass filtering circuit is a frequency value between 1.5 kHz and 40 kHz, and the cut-off frequency of the high-pass filtering circuit is less than 0.5 Hz.

[0085] In a specific implementation manner, the amplification gain value of the first-stage differential amplification module 3 is an amplification gain value between 2 and 10.

[0086] In a specific implementation manner, the present application embodiment also provides a circuit parameter design solution for the first-stage filtering module 2, the first-stage differential amplification module 3, the second-stage filtering module 4, the second-stage differential amplification module 5, the bias drive signal generation module 6, and the differential ADC module 7, which is specifically as follows:

[0087] 1) Electrical parameter design of the first-stage filtering module 2:

[0088] The first-stage filtering module 2 includes a low-pass filtering circuit and a high-pass filtering circuit. According to the actual engineering application experience, in this design, the passband of the band-pass filtering circuit composed of the low-pass and high-pass filtering circuits is set to be larger, so as to ensure that the EEG signals in a relatively wide frequency band enter the subsequent amplification circuit for processing without attenuation or with less attenuation.

[0089] From Figure 7 it can be seen that in the pre-stage RC low-pass filtering circuit, the resistor R is selected as 4.02 kΩ, and the capacitor C is selected as 10 nF. From the cut-off frequency calculation formula The cut-off frequency of the low-pass filter circuit can be obtained to be approximately 3.9 kHz. According to engineering experience, signals within 0.1 times the cut-off frequency can be considered to pass through without attenuation. That is, the non-attenuated signal frequency of the low-pass filter circuit is set to 390 Hz, which covers the effective frequency band range of EEG signals. Experimental verification shows that when the low-pass cut-off frequency fc is in the range of 1.5 kHz to 40 kHz, the acquisition quality of EEG signals can be guaranteed.

[0090] In the pre-stage RC high-pass filter circuit, the resistor R is selected as 220 kΩ, and the capacitor C is selected as 4.7 μF. From the cut-off frequency calculation formula The cut-off frequency of the high-pass filter circuit can be obtained to be approximately 0.15 Hz. According to engineering experience, signals above 10 times the cut-off frequency can be considered to pass through without attenuation. That is, the non-attenuated signal frequency of the high-pass filter circuit is set to 1.5 Hz, which covers the effective frequency band range of EEG signals. Experimental verification shows that when the high-pass cut-off frequency fc is less than 0.5 Hz, the acquisition quality of EEG signals can be guaranteed.

[0091] Through the comparison of experimental effects, the non-attenuated frequency range of the band-pass filter circuit composed of the low-pass and high-pass filter circuits is finally set to 1.5 Hz to 390 Hz.

[0092] 2) Electrical parameter design of the first-stage differential amplification module 3

[0093] In this design, a two-stage amplification circuit is adopted. In order to avoid reducing the signal-to-noise ratio of the circuit due to excessive amplification noise, the gain of the first-stage amplification circuit is set lower. The amplification gain of the first-stage differential amplification circuit is uniquely determined by the one hundred and twelfth resistor R112. The one hundred and twelfth resistor R112 is set to 12.4 kΩ. According to the gain formula: The calculated amplification gain is approximately 5. Experimental verification shows that when the gain of the first-stage amplification circuit is between 2 and 10, the signal-to-noise ratio index can maintain a high level.

[0094] 3) Electrical parameter design of the second-stage filter module 4

[0095] In order to further filter out high-frequency interference in the effective signal, the one hundred and fourteenth resistor R114 and the one hundred and fifteenth resistor R115 in the second sub-filter module of the second-stage filter module 4 are set to 8.2 kΩ, and the one hundred and seventy-fourth capacitor C174 and the one hundred and seventy-fifth capacitor C175 are set to 10 nF. From the cut-off frequency calculation formula The cut-off frequency of the second sub-filter module can be obtained as approximately 1.9 kHz. According to engineering experience, signals within 0.1 times the cut-off frequency can be considered to pass through without attenuation. That is, the non-attenuated signal frequency of the second sub-filter module is set to 190 Hz, which can meet the requirements for EEG signal acquisition in the effective frequency band. Experimental verification shows that when the low-pass cut-off frequency fc is in the range of 1.5 kHz to 10 kHz, the acquisition quality of EEG signals can be guaranteed. The second sub-filter module is a low-pass filter circuit.

[0096] 4) Electrical parameter design of the second-stage differential amplification module 5

[0097] The second-stage differential amplification module 5 is a programmable gain amplifier circuit. Setting the amplification gain of this stage of the circuit larger increases the dynamic application range of the subsequent AD conversion circuit, improves the accuracy of signal acquisition, and at the same time, the differential amplification circuit can also further improve the signal-to-noise ratio. It can be seen from the technical manual of ADS1299 that when the amplification gain is set to 24, the -3dB bandwidth of the ADC circuit is the lowest, approximately 27 kHz, which can, to a certain extent, suppress high-frequency noise interference. In this way, the total amplification gain of the two-stage amplification circuit is 5×24 = 120. Experimental verification shows that when the gain of the second-stage differential amplification module 5 is selected from four specifications of 6, 8, 12, and 24, and combined with the gain of the first-stage differential amplification module 3 set between 2 and 10, ensuring that the total amplification gain of the two-stage amplification circuit is greater than 40 can effectively guarantee the signal acquisition quality.

[0098] 5) Electrical parameter design of the differential ADC module 7

[0099] In this design, it is considered that the effective signals in EEG are in the lower frequency range, and the throughput of 8 parallel 24-bit AD acquisition channels is relatively large. If the AD sampling rate is set too high, it will cause a great communication pressure on the Bluetooth transmission channel in the system, easily resulting in channel blockage and data loss phenomena, and causing instability in the operation of the entire system. Finally, the AD sampling rate is set to 500 SPS, which can make the overall parameters of the system match, ensuring high-precision and high-reliability data acquisition and transmission. Experimental verification shows that when the AD sampling rate is set within 200 SPS to 1000 SPS, the integrity of effective data acquisition and the reliability of data transmission can be guaranteed.

[0100] 6) Electrical parameter design of the bias drive signal generation module 6

[0101] In order to fully consider and apply the DC bias of 8 EEG signals, the drive signal source of the bias drive circuit is configured as differential signals from 8 channels of the second-stage differential amplification module 5. In this way, the DC biases in the 8-channel EEG signals are superimposed, and a common-mode voltage with the opposite polarity is generated through the inverting proportional amplification circuit. For an AC signal with a frequency of f, the gain formula of the proportional amplification circuit is: Where Z F is: To cancel out most of the common-mode interference, the amplification gain of the bias drive circuit is required to be 1, that is, A = -1.

[0102] According to the ADS1299 manual, R in is 220 kΩ. Select R F to be 1 MΩ, and the cut-off frequency of the second-stage low-pass filter circuit is set to 1.9 kHz. Then, the compensation capacitor C F can be calculated to be 750 pF. Such parameter settings can provide a common-mode reference voltage with the opposite polarity for the human body, effectively suppressing most of the common-mode interference signals and improving the signal-to-noise ratio of the entire circuit. Experimental verification shows that when the compensation capacitor C F is in the range of 1.5 nF to 500 pF, the circuit can work normally.

[0103] In a specific implementation manner, such as Figure 7 shows the PCB layer stack architecture diagram of the circuit board of the multi-stage conditioning and amplification device for electroencephalogram signals. As Figure 7 shown, it includes a top layer, a first GND layer, an intermediate signal layer, a power supply layer, a second GND layer, and a bottom layer. Among them,

[0104] the first GND layer, the intermediate signal layer, the power supply layer, and the second GND layer are sequentially stacked between the top layer and the bottom layer. The first GND layer is adjacent to the top layer, and the second GND layer is adjacent to the bottom layer. The top layer, the intermediate signal layer, and the bottom layer are all used for signal transmission.

[0105] It should be noted that for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that this application is not limited by the described action sequence, because according to this application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0106] In the above embodiments, the descriptions of each embodiment have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0107] In several embodiments provided by the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces. The indirect coupling or communication connection of the device or unit can be in an electrical or other form.

[0108] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0109] The embodiments of the present application have been introduced in detail above. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. At the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A multi-stage electroencephalogram signal conditioning and amplification device, characterized in that: The device comprises a reference signal buffer distribution module, a first-stage filtering module, an 8-way first-stage differential amplification module, a second-stage filtering module, an 8-way second-stage differential amplification module, a bias drive signal generation module and a differential ADC module, wherein: The signal output port of the reference signal buffer distribution module is connected to the first type input port of the first filtering module, and the second type input port of the first filtering module is a signal receiving port of 8-channel EEG signals; The 8 first-class signal output ports of the first-stage filtering module are respectively connected to the first input ports of the 8 first-stage differential amplification modules, and the 8 second-class signal output ports of the first-stage filtering module are respectively connected to the second input ports of the 8 first-stage differential amplification modules. The output ports of the 8-way first-stage differential amplifier module are connected to the 8-way input ports corresponding to the second-stage filter module, the 8-way output ports of the second-stage filter module are respectively connected to the input ports of the 8-way second-stage differential amplifier module, the first-type output ports of the 8-way second-stage differential amplifier module are connected to the corresponding signal input ports in the differential ADC module, the second-type output ports of the 8-way second-stage differential amplifier module are connected to the input port of the bias drive signal generating module, and the corresponding signal output port in the differential ADC module is connected to the microprocessor; the output port of the bias drive signal generating module is connected to the bias drive electrode; The reference signal buffer distribution module is used to receive the reference signal of the collected EEG signal, and generate 8 identical and independent reference signals according to the reference signal; The gain of the first-stage differential amplifier module is smaller than the gain of the second-stage differential amplifier module.

2. The multi-stage electroencephalogram signal conditioning and amplification device according to claim 1, characterized in that: The reference signal buffer distribution module includes a first unit gain buffer, a second unit gain buffer, a sixtieth capacitor, a sixty-first capacitor, a sixty-second capacitor and a sixty-third capacitor, wherein: The first port, the fifth port, the sixth port, and the tenth port of the first unit gain buffer are used to receive a reference signal of an electroencephalogram signal, the third port of the first unit gain buffer is connected to a positive power supply port and a first end of the sixtieth capacitor, the second end of the sixtieth capacitor is grounded, the eighth port of the first unit gain buffer is connected to a negative power supply port and a first end of the sixtieth capacitor, the second end of the sixtieth capacitor is grounded, and the second port, the fourth port, the seventh port, and the ninth port of the first unit gain buffer are respectively connected to corresponding first-class input ports in the first filtering module; The first port, the fifth port, the sixth port and the tenth port of the second unit gain buffer are used to receive a reference signal of the EEG signal, the third port of the second unit gain buffer is connected to the positive power supply port and the first end of the sixty-second capacitor, the second end of the sixty-second capacitor is grounded, the eighth port of the second unit gain buffer is connected to the negative power supply port and the first end of the sixty-third capacitor, the second end of the sixty-third capacitor is grounded, the second port, the fourth port, the seventh port and the ninth port of the second unit gain buffer are respectively connected to the corresponding first-class input ports in the first filtering module.

3. The multi-stage electroencephalogram signal conditioning and amplification device according to claim 2, characterized in that: The first-stage differential amplifier module includes a first amplifier chip, a 168th capacitor, a 112th resistor, a 169th capacitor, a 170th capacitor, a 171st capacitor, a 172nd capacitor, a 173rd capacitor, and a 113th resistor, wherein: A 168th capacitor is connected in parallel between the first signal input port and the second signal input port of the first-stage differential amplifier module, and then connected to the first port of the first amplifier chip and the fourth port of the first amplifier chip respectively, and a 112th resistor is connected in series between the second port and the third port of the first amplifier chip; The fifth port of the first amplifier chip is connected to the first end of the first one hundred and sixty-ninth capacitor and the positive power supply port, and the second end of the first one hundred and sixty-ninth capacitor is grounded; The sixth port of the first amplifier chip is connected to the fourteenth port, and the fourteenth port of the first amplifier chip is the second output port of the first-stage differential amplifier module; The seventh port of the first amplifier chip is grounded, the eighth port of the first amplifier chip is connected to the negative power supply port, the zeroth port, and the first end of the 170th capacitor, the second end of the 170th capacitor is grounded, and the ninth port of the first amplifier chip is grounded; The twelfth port of the first amplifier chip is connected to the first end of the first one hundred and seventy-third capacitor and the first end of the first one hundred and thirteenth resistor, the second end of the first one hundred and seventy-third capacitor is grounded, the second end of the first one hundred and thirteenth resistor is connected to the fifteenth port of the first amplifier chip, and the fifteenth port of the first amplifier chip is the second output port of the first-stage differential amplifier module; The thirteenth port of the first amplifier chip is connected to the first end of the first-hundred-and-seventy-second capacitor and the negative power supply port, and the second end of the first-hundred-and-seventy-second capacitor is grounded. The sixteenth port of the first amplifier chip is connected to the first end of the first-hundred-and-seventy-first capacitor and the positive power supply port, and the second end of the first-hundred-and-seventy-first capacitor is grounded.

4. The multi-stage electroencephalogram signal conditioning and amplification device according to claim 3, characterized in that: The second-stage filtering module includes 8 second sub-filtering modules, the electrical parameters of the 8 second sub-filtering modules are the same, the input ports of the 8 second sub-filtering modules are respectively connected to the output ports of the corresponding first-stage differential amplification modules, and the output ports of the 8 second sub-filtering modules are respectively connected to the input ports of the corresponding second-stage differential amplification modules; The second sub-filtering module includes a 114th resistor, a 115th resistor, a 174th capacitor and a 175th capacitor, the 114th resistor is connected in series between the first output port of the first-stage differential amplifier module and the first end of the 174th capacitor, the first end of the 174th capacitor and the 114th resistor are connected to the first output port of the second sub-filtering module, and the second end of the 174th capacitor is grounded; The first one hundred and fifteenth resistor is connected in series between the second output port of the first-stage differential amplifier module and the first end of the first one hundred and seventy-fifth capacitor, the second output port of the second sub-filtering module is connected between the first end of the first one hundred and seventy-fifth capacitor and the first one hundred and fifteenth resistor, and the second end of the first one hundred and seventy-fifth capacitor is grounded.

5. The multi-stage electroencephalogram signal conditioning and amplification device according to any one of claims 1 to 4, characterized in that: The bias drive signal generating module includes a bias drive amplifier, a drive signal source network, an external resistor, a compensation capacitor, a first resistor and a second resistor, wherein: The drive signal source network is connected to the second type of output ports of the 8-way second-stage differential amplifier module, the output port of the drive signal source network is connected to the first end of the external resistor, the first end of the compensation capacitor, and the inverting input end of the bias drive amplifier, the second end of the external resistor and the second end of the compensation capacitor are connected to the output end of the bias drive amplifier, the non-inverting input end of the bias drive amplifier is connected to the first end of the first resistor and the first end of the second resistor, the second end of the first resistor is connected to the positive power supply port, and the second end of the second resistor is connected to the negative power supply port.

6. The multi-stage electroencephalogram signal conditioning and amplification device according to claim 5, characterized in that: The capacitance value of the compensation capacitor ranges from 1.5 nF to 500 pF.

7. The multi-stage electroencephalogram signal conditioning and amplification device according to claim 5, characterized in that: The first-stage filtering module includes a low-pass filtering circuit and a high-pass filtering circuit. The cut-off frequency of the low-pass filtering circuit is a frequency value between 1.5KHz and 40kHz, and the cut-off frequency of the high-pass filtering circuit is less than 0.5Hz.

8. The multi-stage electroencephalogram signal conditioning and amplification device according to claim 6, characterized in that: The amplification gain value of the first-stage differential amplification module is an amplification gain value between 2 and 10.

9. A multi-stage electroencephalogram signal conditioning and amplification device, characterized in that: It comprises a shell and the multi-stage EEG signal conditioning and amplification device as described in any one of claims 1 to 7, wherein the multi-stage EEG signal conditioning and amplification device is arranged inside the shell.

10. A high signal-to-noise ratio dry electrode EEG signal acquisition system, characterized in that: The high signal-to-noise ratio dry electrode EEG signal acquisition system includes a rigid-flexible active electrode device and an EEG signal multi-stage conditioning and amplification device as described in any one of claims 1 to 7, wherein the rigid-flexible active electrode device is connected to the EEG signal multi-stage conditioning and amplification device, and the rigid-flexible active electrode device is used to send the collected EEG signal, reference signal and common-mode bias voltage signal to the EEG signal multi-stage conditioning and amplification device, and the EEG signal multi-stage conditioning and amplification device is used to amplify and condition the received EEG signal.

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