Detector time amplitude signal acquisition method and system
By designing a high-speed acquisition system for time amplitude signals of detectors, using sensitive preamplifiers, card threshold circuits, peak holding and amplitude acquisition modules and time acquisition modules, the problem of insufficient detection signal acquisition accuracy in the prior art is solved, and high-precision GHz-level time amplitude signal acquisition is achieved.
Patent Information
- Application Number
- CN202510204781.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-24
- Publication Date
- 2025-05-27
AI Technical Summary
The existing detector post-processing circuits are difficult to achieve accurate response when the rising edge of the signal output by the detector reaches 3 ns, and the acquisition accuracy can only reach the microsecond level, making it difficult to meet the requirements of high-speed amplitude acquisition.
A detector time amplitude signal high-speed acquisition system is designed, including a sensitive preamplifier circuit, a card threshold circuit, a peak holding and amplitude acquisition module and a time acquisition module. Through these modules, the weak signals output by the detector are amplified, denoised, and collected their amplitude and time information to generate two-dimensional information related to time amplitude.
It realizes high-precision acquisition of detector signals, with the accuracy reaching GHz level, significantly shortening the acquisition time, meeting the requirements of high-speed amplitude acquisition, and at the same time reducing costs, avoiding the expensive and procurement difficulties when using high-speed ADC to acquire full waveforms.
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Figure CN120044580A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of nuclear electronics circuit design, and particularly relates to a method and system for high-speed acquisition of detector time-amplitude signals. Background Art
[0002] In current detector designs, the accuracy of the post-processing circuit no longer meets the response time of the detector. When the rising edge of the signal output by the detector reaches 3 ns, the current post-processing readout circuit is difficult to achieve such an accurate response time. To achieve such a fast response time, it is required that the dynamic range of the ADC for acquisition reaches the GHz level.
[0003] In order to accurately acquire the pulse signal output by the detector, it is necessary for the post-processing circuit to convert the charge pulse signal output by the detector into two-dimensional information related to time and amplitude.
[0004] However, the currently common detector post-processing circuit mainly acquires energy spectrum information. The energy spectrum information requires the acquisition of the full waveform, and its acquisition process is easily affected by parasitic capacitance and has a large external interference, making the acquisition accuracy only reach the microsecond level and difficult to meet the requirements of high-speed time-amplitude acquisition. Summary of the Invention
[0005] Based on this, it is necessary to provide a method and system for high-speed acquisition of detector time-amplitude signals in view of the above technical problems.
[0006] The present invention adopts the following technical solutions:
[0007] A system for high-speed acquisition of detector time-amplitude signals includes:
[0008] A sensitive preamplifier circuit, a threshold circuit, a peak holding and amplitude acquisition module, a time acquisition module, and a host computer;
[0009] The sensitive preamplifier circuit is connected to the threshold circuit; the threshold circuit is respectively connected to the peak holding and amplitude acquisition module and the time acquisition module; the host computer is respectively connected to the data transmission module of the peak holding and amplitude acquisition module and the data output end of the time acquisition module;
[0010] The sensitive preamplifier circuit is used for collecting charges of the weak signal output by the detector and performing preliminary amplification to obtain a measurable high-speed pulse signal;
[0011] The threshold circuit is used for removing noise signals above the upper threshold and below the lower threshold and background interference signals above the upper threshold on the high-speed pulse signal;
[0012] The peak holding and amplitude acquisition module is used to hold the peak of the high-speed pulse signal after removing the noise signal and the background interference signal, and sample it using an ADC to obtain the amplitude information of the high-speed pulse signal;
[0013] The time acquisition module is used to acquire the time at the amplitude of the high-speed pulse signal using the TDC module in the FPGA to obtain the high-resolution time information of the high-speed pulse signal;
[0014] The host computer is used to convert the amplitude information and high-resolution time information of the high-speed pulse signal into two-dimensional information related to the time amplitude of the high-speed pulse signal.
[0015] Preferably, the sensitive amplifier used in the sensitive preamplifier circuit is a voltage-sensitive preamplifier, and the gain-bandwidth product of the operational amplifier is at the GHz level.
[0016] Preferably, the threshold clamping circuit includes:
[0017] An upper threshold reference voltage circuit, a lower threshold reference voltage circuit, an upper threshold comparator, a lower threshold comparator, a NAND gate, and a threshold clamping MOS switch;
[0018] The inverting input terminal of the upper threshold comparator is connected to the upper threshold reference voltage circuit; the non-inverting input terminal of the upper threshold comparator is connected to the output terminal of the sensitive preamplifier; the output terminal of the upper threshold comparator is connected to the first input terminal of the NAND gate; the non-inverting input terminal of the lower threshold comparator is connected to the lower threshold reference voltage circuit; the inverting input terminal of the lower threshold comparator is connected to the output terminal of the sensitive preamplifier; the output terminal of the lower threshold comparator is connected to the second input terminal of the NAND gate; the input terminal of the threshold clamping MOS switch is connected to the output terminal of the sensitive preamplifier; the control terminal of the threshold clamping MOS switch is connected to the output terminal of the NAND gate.
[0019] Preferably, the peak holding and amplitude acquisition module includes:
[0020] A Schottky diode, a high-speed comparator, a first buffer, a second buffer, a third buffer, an acquisition MOS switch, and an ADC acquisition circuit;
[0021] The input end of the Schottky diode is connected to the output end of the clamping threshold MOS switch, and its output end is connected to the non-inverting input end of the high-speed comparator, the input end of the ADC acquisition circuit, and the input end of the acquisition MOS switch; the inverting input end of the high-speed comparator is connected to the output end of the clamping threshold MOS switch; the output end of the high-speed comparator is connected to the input end of the first buffer and the control end of the ADC acquisition circuit; the control ends of the first buffer, the second buffer, the third buffer, and the acquisition MOS switch are connected in sequence; the output end of the ADC acquisition circuit is connected to the data output end.
[0022] Preferably, the time acquisition module includes:
[0023] A coarse measurement circuit and a fine measurement circuit;
[0024] The coarse measurement circuit is used to measure the input time interval of the high-speed pulse signal;
[0025] The fine measurement circuit is used to obtain the high-resolution time information of the high-speed pulse signal.
[0026] Preferably, the coarse measurement circuit includes:
[0027] A comparator, an FPGA, and a crystal oscillator;
[0028] The output end of the comparator is connected to the data input end of the FPGA; the output end of the crystal oscillator is connected to the clock input end of the FPGA.
[0029] Preferably, the fine measurement circuit includes: a comparator, a delay carry chain, a rising edge detection circuit, a sampling flip-flop array, an encoding circuit, and a calibration circuit;
[0030] The comparator is connected to the rising edge detection circuit; the rising edge detection circuit is connected to the delay carry chain; the rising edge detection circuit is connected to the sampling flip-flop array; the sampling flip-flop array is connected to the encoding circuit; the encoding circuit is connected to the calibration circuit.
[0031] Preferably, the amplitude information of the high-speed pulse signal is the sum of the voltage drop across the Schottky diode and the peak voltage collected by the peak hold circuit;
[0032] A acquisition method for a detector time-amplitude signal acquisition system, characterized by comprising the following steps:
[0033] Collect and preliminarily amplify the weak signal output by the detector through a sensitive preamplifier circuit to obtain a high-speed pulse signal;
[0034] The noise signals above the upper threshold and below the lower threshold, as well as the background interference signals above the upper threshold, on the high-speed pulse signal are removed by the card threshold circuit;
[0035] Through the peak holding and amplitude acquisition circuit, the peak of the high-speed pulse signal output by the sensitive preamplifier circuit is held for a period of time and an enable signal is output. The enable signal activates the ADC to sample the amplitude of the high-speed pulse signal, obtaining the amplitude information of the high-speed pulse signal;
[0036] Through the time acquisition circuit, the time at the amplitude of the high-speed pulse electrical signal output by the sensitive preamplifier circuit is acquired, obtaining the high-resolution time information of the high-speed pulse signal.
[0037] The above at least one technical solution adopted by the present invention can achieve the following beneficial effects:
[0038] In the present invention, the weak signal generated by the detector is amplified into a measurable high-speed pulse signal through the sensitive preamplifier circuit, and the noise signals and local interference signals of the high-speed pulse signal are filtered out by the card threshold circuit; through the peak holding and amplitude acquisition module, the amplitude of the high-speed pulse electrical signal output by the sensitive preamplifier circuit is held and an enable signal is output, activating the analog-to-digital converter sampling circuit to sample the amplitude of the high-speed pulse signal, obtaining the amplitude information of the high-speed pulse electrical signal; through the time acquisition circuit, the peak time of the high-speed pulse signal is acquired, encoded, and corrected, obtaining the time information of the high-speed pulse signal; by transmitting the amplitude information of the high-speed pulse signal and the time information of the high-speed pulse signal to the host computer, two-dimensional information related to the time amplitude of the high-speed pulse signal is obtained.
[0039] In summary, aiming at the problems existing in the prior art: currently, the main thing collected by the general detector post-processing circuit is the energy spectrum. Since the collection of the energy spectrum requires the collection of the full waveform, the collection process is easily affected by external interference, making the collection accuracy only reach the microsecond level and difficult to meet the requirements of high-speed time-amplitude acquisition. However, the present invention does not collect the energy spectrum, but through the designed detector time-amplitude signal acquisition system. First, a sensitive preamplifier is used to replace the charge-sensitive amplifier used in collecting the energy spectrum, solving the problem that the collection process is easily affected by parasitic capacitance. Through the card threshold circuit, the noise signals and local interference signals of the high-speed pulse signal are filtered out, reducing the external interference during the collection process. By using the peak holding and amplitude acquisition module and the time acquisition module, it is not necessary to collect the full waveform, but only the signal amplitude and the signal time are collected. Thus, the high-speed pulse signal output by the detector is converted into two-dimensional information related to time amplitude, enabling the detector collection accuracy to reach GHz while significantly shortening the collection time, and further meeting the requirements of high-speed time-amplitude acquisition, achieving high-precision acquisition of the detector high-speed pulse signal while saving costs.
[0040] In addition, if a high-speed ADC with a sampling accuracy reaching GHz is directly adopted, the full waveform needs to be collected, and an ADC with a sampling rate of 1 GHz to 4 GHz is required for collecting the full waveform. This not only incurs high costs but also poses difficulties in procurement. However, for the detector time-amplitude acquisition circuit proposed in the present invention, the full waveform does not need to be collected. By only collecting the time information and amplitude information, a sampling accuracy at the GHz level can be achieved, thus solving the problems of high cost and procurement difficulties when using a high-speed ADC to collect the full waveform. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not unduly limit the present invention. In the drawings:
[0042] Figure 1 is a schematic circuit structure diagram of a high-speed acquisition system for detector time-amplitude signals provided by the present invention;
[0043] Figure 2 is a schematic circuit structure diagram of a sensitive preamplifier for a high-speed acquisition system for detector time-amplitude signals provided by the present invention;
[0044] Figure 3 is a schematic circuit structure diagram of a threshold circuit for a high-speed acquisition system for detector time-amplitude signals provided by the present invention;
[0045] Figure 4 is a schematic circuit structure diagram of a peak hold and amplitude acquisition circuit for a high-speed acquisition system for detector time-amplitude signals provided by the present invention;
[0046] Figure 5 is a schematic flow diagram of a method for high-speed acquisition of detector time-amplitude signals provided by the present invention;
[0047] Figure 6 is the test result of a peak hold and amplitude acquisition circuit for a high-speed acquisition system for detector time-amplitude signals provided by the present invention;
[0048] Figure 7 is a schematic circuit structure diagram of a fine measurement circuit in a time acquisition circuit for a high-speed acquisition system for detector time-amplitude signals provided by the present invention;
[0049] Figure 8 is a schematic circuit structure diagram of an encoding circuit in a time acquisition circuit for a high-speed acquisition system for detector time-amplitude signals provided by the present invention;
[0050] Figure 9 is a schematic circuit structure diagram of a calibration circuit in a time acquisition circuit for a high-speed acquisition system for detector time-amplitude signals provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0051] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with specific embodiments of the present invention and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.
[0052] The following will detail the technical solutions provided by each embodiment of the present invention with reference to the drawings.
[0053] For a high-speed acquisition system of detector time-amplitude signals, please refer to Figure 1 which includes:
[0054] A signal input terminal, a sensitive preamplifier circuit, a threshold comparison circuit, a peak hold and amplitude acquisition module, a time acquisition module, and a data output terminal;
[0055] The sensitive preamplifier circuit is used to amplify the high-speed pulse electrical signal generated by the detector into a pulse signal that can be measured;
[0056] The threshold comparison circuit is used to filter out noise signals above the upper threshold and below the lower threshold, as well as background interference signals above the upper threshold, and then enter the acquisition module for acquisition;
[0057] The peak hold and amplitude acquisition module is used to hold the amplitude of the high-speed pulse electrical signal output by the sensitive preamplifier circuit and give a trigger signal, and the ADC performs hold sampling acquisition;
[0058] The time acquisition module is used to acquire the time at the amplitude of the high-speed pulse electrical signal output by the sensitive preamplifier circuit, and the entire acquisition end uses the FPGA as the core processing component.
[0059] The sensitive preamplifier circuit is connected to the threshold comparison circuit; the threshold comparison circuit is respectively connected to the peak hold and amplitude acquisition module and the time acquisition module; the signal input terminal is connected to the sensitive preamplifier circuit; the data output terminal is respectively connected to the peak hold and amplitude acquisition module and the time acquisition module;
[0060] Refer to Figure 2 for Figure 2 the structural schematic diagram of the sensitive preamplifier circuit provided by this embodiment. Among them, the sensitive preamplifier used is a voltage-sensitive preamplifier; among them, the sensitive preamplifier circuit is a voltage-sensitive preamplifier, and the gain-bandwidth product of the operational amplifier is at the GHz level.
[0061] Refer to Figure 3 forFigure 3 Schematic diagram of the card threshold circuit provided in this embodiment, including:
[0062] Upper threshold reference voltage circuit, lower threshold reference voltage circuit, upper threshold comparator, lower threshold comparator, NAND gate, card threshold MOS switch;
[0063] Among them, the inverting input terminal of the upper threshold comparator is connected to the upper threshold reference voltage circuit; the non-inverting input terminal of the upper threshold comparator is connected to the output terminal of the sensitive preamplifier; the output terminal of the upper threshold comparator is connected to the first input terminal of the NAND gate; the non-inverting input terminal of the lower threshold comparator is connected to the lower threshold reference voltage circuit; the inverting input terminal of the lower threshold comparator is connected to the output terminal of the sensitive preamplifier; the output terminal of the lower threshold comparator is connected to the second input terminal of the NAND gate; the input terminal of the card threshold MOS switch is connected to the output terminal of the sensitive preamplifier; the control terminal of the card threshold MOS switch is connected to the output terminal of the NAND gate.
[0064] See Figure 4 , Figure 4 Schematic diagram of the peak holding and amplitude acquisition circuit provided in this embodiment, including: Schottky diode, high-speed comparator, first buffer, second buffer, third buffer, acquisition MOS switch, ADC acquisition circuit;
[0065] Among them, the input terminal of the Schottky diode is connected to the output terminal of the card threshold MOS switch, and its output terminal is connected to the non-inverting input terminal of the high-speed comparator, the input terminal of the ADC acquisition circuit, and the input terminal of the acquisition MOS switch; the inverting input terminal of the high-speed comparator is connected to the output terminal of the card threshold MOS switch; the output terminal of the high-speed comparator is connected to the input terminal of the first buffer and the control terminal of the ADC acquisition circuit; the control terminals of the first buffer, second buffer, third buffer, and acquisition MOS switch are connected in sequence; the output terminal of the ADC acquisition circuit is connected to the data output terminal.
[0066] Schematic diagram of the time acquisition circuit, including: coarse measurement circuit and fine measurement circuit;
[0067] Coarse measurement circuit, including: comparator, FPGA, and crystal oscillator;
[0068] The comparator is connected to the FPGA; the FPGA is connected to the crystal oscillator.
[0069] Fine measurement circuit, including: comparator, delay carry chain, rising edge detection circuit, sampling flip-flop array, encoding circuit, and calibration circuit;
[0070] The comparator is connected to the rising edge detection circuit; the rising edge detection circuit is connected to the delay carry chain; the rising edge detection circuit is connected to the sampling flip-flop array; the sampling flip-flop array is connected to the encoding circuit; the encoding circuit is connected to the calibration circuit.
[0071] Figure 5 The following is a schematic flow diagram of a high-speed acquisition method for the detector time-amplitude signal provided in this embodiment, including the following steps:
[0072] S101: Collect and preliminarily amplify the weak signal output by the detector through a sensitive preamplifier circuit to obtain a high-speed pulse signal.
[0073] S102: Remove the noise signals above the upper threshold and below the lower threshold and the background interference signals above the upper threshold on the high-speed pulse signal through a threshold comparison circuit.
[0074] S103: Through the peak hold and amplitude acquisition circuit, hold the peak of the high-speed pulse signal output by the sensitive preamplifier circuit for a period of time and output an enable signal. The enable signal activates the analog-to-digital converter to sample the amplitude of the high-speed pulse signal to obtain the amplitude information of the high-speed pulse signal.
[0075] Among them, the amplitude information of the high-speed pulse signal is the sum of the voltage drop across the Schottky diode and the peak voltage collected by the peak hold circuit in the peak hold and amplitude acquisition circuit.
[0076] S104: Through the time acquisition circuit, collect the time at the amplitude of the high-speed pulse electrical signal output by the sensitive preamplifier circuit to obtain the high-resolution time information of the high-speed pulse signal, specifically including:
[0077] Through the time acquisition circuit, using the FPGA as the core processing component, adopt a combination of direct counting method and delay chain interpolation method for time measurement and encoding and correction to obtain the high-resolution time information at the amplitude of the high-speed pulse signal.
[0078] S105: Through the data output terminal, transmit the amplitude information and the high-resolution time information of the high-speed pulse signal to the host computer to obtain the two-dimensional information related to the time amplitude of the high-speed pulse signal.
[0079] A high-speed acquisition system circuit for the detector time-amplitude signal designed in this embodiment includes:
[0080] A high-speed acquisition method and system for the detector time-amplitude signal, including:
[0081] A signal input terminal, a sensitive preamplifier circuit, a threshold comparison circuit, a peak hold and amplitude acquisition module, a time acquisition module, and a data output terminal;
[0082] Among them, the sensitive preamplifier circuit is connected to the threshold comparison circuit; the threshold comparison circuit is respectively connected to the peak hold and amplitude acquisition module and the time acquisition module;
[0083] The signal input terminal is connected to the sensitive preamplifier circuit; the data output terminal is respectively connected to the peak holding and amplitude acquisition module and the time acquisition module.
[0084] Among them, the function of the sensitive preamplifier circuit is to collect charges and preliminarily amplify the weak signal output by the detector.
[0085] In addition, since the preamplifier is the first-stage circuit in the front-end readout circuit and its input signal is only a few thousand electrons at the minimum, the noise performance of the circuit is an issue that needs to be considered seriously for the preamplification module.
[0086] In addition, in order to minimize the influence of the noise of the subsequent circuit on the overall system noise, the gain of the preamplifier should also be large enough. By using the preamplifier, the purpose of improving the signal-to-noise ratio of the system, realizing impedance conversion and matching, and reducing external interference can be achieved ultimately. The sensitive preamplifier circuit proposes a voltage-sensitive preamplifier scheme to collect charges and preliminarily amplify the weak signal output by the detector. The gain-bandwidth product of the operational amplifier adopted in the embodiment of the present invention is at the GHz level, which can meet the requirements of collecting high-speed pulse signals output by the detector.
[0087] The function of the pulse threshold circuit is to remove the noise signals above the upper threshold and below the lower threshold and the background interference signals above the upper threshold on the high-speed pulse signal;
[0088] It should be noted that the pulse threshold circuit is divided into a reference voltage circuit, a threshold comparison circuit, and a switching circuit; the reference voltage circuit is responsible for determining the values of the upper threshold voltage and the lower threshold voltage required by the circuit; the threshold comparison circuit is responsible for comparing the peak value of the high-speed pulse signal output by the sensitive preamplifier with the upper threshold and the lower threshold to determine that the peak value of the high-speed pulse signal output by the sensitive preamplifier is between the upper threshold voltage and the lower threshold voltage determined by the reference voltage circuit; the switching circuit is responsible for removing the noise signals above the upper threshold and below the lower threshold and the background interference signals above the upper threshold. When the peak value of the high-speed pulse signal output by the sensitive preamplifier is between the upper threshold voltage and the lower threshold voltage, the switch is turned on, and at this time, the high-speed pulse signal output by the sensitive preamplifier normally flows into the peak holding and amplitude acquisition circuit. When the peak value of the high-speed pulse signal output by the sensitive preamplifier is above the upper threshold and below the lower threshold, the switch is turned off, and at this time, the noise signals and background interference signals that do not meet the requirements output by the sensitive preamplifier are blocked before the peak holding and amplitude acquisition circuit and will not affect the subsequent circuits.
[0089] In addition, the reference voltage circuit part of the pulse threshold circuit realizes the simultaneous discrimination of the upper and lower thresholds and the adjustable threshold by adding a potentiometer; by adjusting the resistance value of the potentiometer, the function of adjustable voltage threshold is realized.
[0090] Additionally, the threshold comparison circuit part of the card threshold circuit uses a dual-channel comparator to compare the upper threshold voltage and the lower threshold voltage simultaneously, and outputs an enable signal through a NAND gate to control the conduction and disconnection of the switch circuit.
[0091] The function of the time-amplitude high-speed acquisition circuit is to hold the peak value of the high-speed pulse signal output by the sensitive preamplifier circuit for a period of time. At the same time, the peak detection module will give a trigger signal, and the ADC will perform hold sampling acquisition.
[0092] It should be noted that the peak hold and amplitude acquisition circuit is divided into a peak hold circuit, a buffer circuit, and an ADC sampling circuit. The peak hold circuit is responsible for holding the peak value of the high-speed pulse signal output by the sensitive preamplifier circuit for a period of time and outputting an enable signal to activate the ADC sampling circuit for acquisition; the buffer circuit is responsible for pulling the peak value fixed by the peak hold circuit to the value of the lower threshold voltage after a period of time; the ADC sampling circuit is responsible for sampling the peak value of the high-speed pulse signal output by the sensitive preamplifier circuit after receiving the enable signal output by the peak hold circuit.
[0093] Additionally, the peak hold circuit in the peak hold and amplitude acquisition circuit divides the high-speed pulse signal output by the sensitive preamplifier circuit into two paths. One path of the signal enters the non-inverting terminal of the high-speed comparator after passing through a Schottky diode, and the other path directly enters the inverting terminal of the high-speed comparator. At this time, the high-speed comparator compares the two paths of signals; due to the presence of the Schottky diode, the peak value drop speed of the pulse signal is greatly slowed down, and a difference appears between the two paths of signals. At this time, the high-speed comparator will output an enable signal to the ADC sampling circuit to sample the peak value of the signal after the Schottky diode.
[0094] Among them, due to the signal accuracy requirements, the comparator used in the peak hold circuit of the peak hold and amplitude acquisition circuit needs to use a high-speed comparator with a short delay time.
[0095] Additionally, the buffer circuit in the peak hold and amplitude acquisition circuit cascades several buffers and connects them to the output terminal of the comparator and the lower threshold voltage switch control terminal respectively. When the comparator outputs an enable signal, the enable signal is delayed for a period of time through the buffer and then input to the lower threshold voltage switch control terminal. The lower threshold voltage switch conducts, and the peak hold signal output by the Schottky diode is pulled down to the lower threshold voltage; this buffer circuit can avoid the problem of peak leakage caused by the peak value of the subsequent high-speed pulse signal not reaching the peak value output by the previous Schottky diode.
[0096] It should be noted that for the peak value held by the peak hold circuit in the peak hold and amplitude acquisition circuit, since it passes through a Schottky diode, the peak voltage obtained needs to add the voltage drop across the diode to obtain the accurate actual amplitude.
[0097] See Figure 6 , Figure 6 which is the test result of the peak hold and amplitude acquisition circuit provided by the embodiment of the present invention; in the test result, the blue signal is the peak hold signal after the high-speed pulse signal output by the sensitive preamplifier circuit is chopped by the Schottky diode, and the green signal is the high-speed pulse signal output by the sensitive preamplifier circuit; after the two signals are compared by the high-speed comparator, a red enable signal is output to activate the ADC for sampling; in the test result, after the two signals are compared by the high-speed comparator, the high-speed comparator can normally output the enable signal.
[0098] The function of the time-amplitude high-speed acquisition circuit is to collect the time at the peak of the high-speed pulse signal output by the sensitive preamplifier circuit through the TDC module in the FPGA. The measurement method adopted by the TDC module in the FPGA used by the time acquisition circuit is the "coarse + fine" time measurement method;
[0099] In this embodiment, the coarse measurement uses a direct counting type TDC, which measures the input time interval by using a counter driven by a reference clock; after the input Start signal, the counter increments by 1 at each clock rising edge, and after the input Stop signal, the counting stops. The measured time interval △T = m * Tc; the fine measurement uses the delay line interpolation method, which uses very small delay units to interpolate the time signal to be measured, so as to achieve a higher time resolution; since the direct counting type TDC can only measure the time interval that is an integer multiple of the reference clock, the error is large. Combining the delay line interpolation method with the direct counting method can realize a time measurement method with a large measurement range and high time resolution, and this combination is called the "coarse" counting and "fine" time measurement method.
[0100] In addition, the coarse time measurement method in the time-amplitude high-speed acquisition circuit counts the rising edges of the reference clock between the Start and Stop signals, and then multiplies the counting result by the clock period to obtain the "coarse" time interval between the Start and Stop signals. The number of bits of the "coarse" counter determines the dynamic range of the TDC measurement. Under the condition that the FPGA clock frequency and logic resources permit, the number of bits can be flexibly set according to the application requirements.
[0101] It should be noted that in order to avoid the phenomenon of multiple-bit flips of the binary counter, a Gray code counter is used in this design.
[0102] Please see Figure 7 , Figure 7Schematic diagram of the fine measurement circuit in the time acquisition circuit provided by the embodiment of the present invention. The fine time measurement circuit structure in the time amplitude high-speed acquisition circuit mainly consists of a carry delay chain, a rising edge detection circuit, a sampling flip-flop array, an encoding circuit, a calibration circuit, etc. The input signal or the random calibration signal propagates on the tapped delay line through the holding circuit. When the next clock rising edge arrives, the sampling flip-flop array samples the taps of the delay chain. Subsequently, through an encoding circuit including 1-0 conversion detection logic and one-hot code to binary conversion, the thermometer code with a "bubbling" property is converted into a binary code convenient for storage and operation. The address of the calibration RAM is obtained using the binary code, and then the "fine" time stored in the address is extracted.
[0103] It should be noted that the "fine" time extracted from the address is the result of the calibration circuit calibrating the delay chain before time measurement, which can reduce the time measurement error.
[0104] The carry delay chain in this embodiment uses the dedicated carry chain in the Slice unit of the FPGA and runs from bottom to top. Each dedicated carry chain structure consists of 4 carry multiplexers (MUXCY), 4 exclusive OR gates (XOR), and 1 multiplexer (MUX). There are 10 inputs and 8 outputs. Among them, 4 inputs come from the output of function generator 1 and are used for the "propagation" signal of the look-ahead carry logic; 4 inputs come from the output of function generator 2 and are used for the "generation" signal of the look-ahead carry logic; 1 input is the first-stage input of the carry chain, where "0" represents an addition operation and "1" represents a subtraction operation; 4 outputs represent the result of addition or subtraction of the carry chain; 4 outputs are the carry calculated for each bit; the inputs and outputs can be used to cascade Slices to form a longer delay chain. By connecting the signal signal input to the delay chain to the input at the bottom of the delay chain, the first 4 ports are configured as 1 and the last 4 are configured as 0, and the dedicated look-ahead carry operation chain is configured as a delay chain.
[0105] See Figure 8 , Figure 8 Schematic diagram of the encoding circuit in the time acquisition circuit provided by the embodiment of the present invention; when the input signal propagates in the delay chain, the tap signal changes from 0 to 1 step by step from the input end (low bit) to the other end (high bit) of the input signal and outputs the result in the form of a thermometer code. According to the position of the tap signal where the last bit changes to 1 before the trigger sampling at the clock rising edge, it can be judged how many delay units the input signal has propagated within the "fine" time. When the signal propagates in an ideal tapped delay line, a standard thermometer code such as (00…011…11) form will be output, where the number of "1"s is the valid information.
[0106] It should be noted that since the thermometer code requires a large amount of space, the encoding scheme used in this design is to first use a combinational logic circuit to detect the 1-0 transition points in the thermometer code, and then convert the obtained one-hot code into a binary code through an encoding circuit with a pipeline structure.
[0107] Furthermore, please refer to Figure 9 , Figure 9 , which is a schematic diagram of the calibration circuit structure in the time acquisition circuit provided by the embodiment of the present invention; in this embodiment, the circuit adopts the code density calibration method, and the delay time of each delay unit can be obtained by statistically calculating the number c(i) of random signals falling in each delay unit; it mainly includes a random signal generation circuit, a hold circuit, a calibration RAM (Cal_RAM) and its control state machine, a lookup table RAM (Lut_RAM) and its control state machine, an adder, an accumulator, a reset circuit, etc.
[0108] In addition, since the random signal generation circuit in the calibration circuit needs to generate a random signal Hit to calibrate the delay unit when using the code density method, a ring oscillator is used to generate the random signal; the ring oscillator is composed of an odd number of inverters connected in series, and the last inverter forms a feedback loop with the first inverter.
[0109] In addition, since the hold circuit and the reset circuit in the calibration circuit each calibration process requires a certain amount of time, and before each calibration is completed, the next random signal cannot be introduced into the delay chain, it is necessary to hold the random signal until the end of this calibration. In the calibration mode, the random signal generated by the ring oscillator serves as the driving clock of the hold circuit, and the time interval between the random signal and the rising edge of the clock is the random time interval of this calibration. After each random signal calibration is completed, the reset circuit generates a reset signal for the hold circuit to start the next calibration until the total number of calibrations is reached.
[0110] In addition, in the Cal_RAM control state machine in the calibration circuit, since the data obtained from the encoding module in each calibration should be stored in the Cal_RAM, the read and write operations of the Cal_RAM are controlled by the state machine. The Cal_RAM has a total of 256 addresses, and its read and write operation process is as follows: perform a reset and clear operation on each address space of the Cal_RAM; use the encoding result obtained in each calibration as the read address of the Cal_RAM, extract the data stored at this address, then add 1 with an adder, and write the obtained result back to the original address; after each calibration is completed, send a reset enable signal to the reset circuit to perform the next calibration; stop calibrating until the total number of specified calibrations is reached. In the finally obtained Cal_RAM, the data stored at the i-th address represents the number of times the random signal falls in the i-th delay unit.
[0111] Additionally, in the Lut_RAM control state machine of the calibration circuit, the data stored in Cal_RAM should be converted into time information through operations and stored in Lut_RAM. Lut_RAM also has a total of 256 addresses, and its read and write operation process is as follows: The data stored at the i-th address in Cal_RAM is sent to the adder and accumulator respectively. The adder adds half of the data stored at the i-th address in Cal_RAM and the data in the accumulator register (acc_reg) to obtain the calibration value from the start of the delay chain to the i-th tap. The result is stored in the adder register (lut_reg); the accumulator calculates the total number of random signals falling from the start of the delay chain to the i-th tap, and the result is stored in acc_reg; the data in lut_reg is stored at the i-th address in Lut_RAM; and so on in a loop until all the data in Cal_RAM is processed. Finally, the data stored at the i-th address in Lut_RAM represents the "fine" time obtained by calibration when the measured signal falls on the i-th tap.
[0112] In summary, the present invention amplifies the weak signal generated by the detector into a measurable high-speed pulse signal through a sensitive preamplifier circuit, and filters out the noise signal and local interference signal of the high-speed pulse signal through a card threshold circuit; the peak holding and amplitude acquisition module holds the amplitude of the high-speed pulse electrical signal output by the sensitive preamplifier circuit and outputs an enable signal to activate the analog-to-digital converter sampling circuit to sample the amplitude of the high-speed pulse signal, obtaining the amplitude information of the high-speed pulse electrical signal; the time acquisition circuit acquires, encodes, and corrects the peak time of the high-speed pulse signal, obtaining the time information of the high-speed pulse signal; the amplitude information and time information of the high-speed pulse signal are transmitted to the host computer, obtaining two-dimensional information related to the time amplitude of the high-speed pulse signal. In short, through the high-speed acquisition method and system for detector time amplitude signals provided by the present invention, the high-speed pulse signal is converted into two-dimensional information related to time amplitude, enabling the acquisition accuracy of the detector to reach GHz, thus meeting the requirements of time-amplitude acquisition. While saving costs, high-precision acquisition of the high-speed pulse signal of the detector is achieved.
[0113] The technical solution of the present invention is not limited to the limitations of the above specific embodiments. Any technical deformation made according to the technical solution of the present invention falls within the protection scope of the present invention.
Claims
1. A detector time amplitude signal acquisition system, characterized in that: include: Sensitive preamplifier circuit, card threshold circuit, peak hold and amplitude acquisition module and time acquisition module, host computer; The sensitive preamplifier circuit is connected to the card threshold circuit; the card threshold circuit is respectively connected to the peak hold and amplitude acquisition module and the time acquisition module; the host computer is respectively connected to the data transmission module of the peak hold and amplitude acquisition module and the data output end of the time acquisition module; The sensitive preamplifier circuit is used to collect and preliminarily amplify the weak signal output by the detector to obtain a measurable high-speed pulse signal; The card threshold circuit is used to remove noise signals above the upper threshold and below the lower threshold of the high-speed pulse signal and background interference signals above the upper threshold; The peak hold and amplitude acquisition module is used to hold the peak value of the high-speed pulse signal after removing the noise signal and the background interference signal, and use the ADC to perform sampling to obtain the amplitude information of the high-speed pulse signal; The time acquisition module is used to acquire the time at the amplitude of the high-speed pulse signal using the TDC module in the FPGA to obtain high-resolution time information of the high-speed pulse signal; The host computer is used to convert the amplitude information and high-resolution time information of the high-speed pulse signal into two-dimensional information related to the time amplitude of the high-speed pulse signal.
2. A detector time amplitude signal acquisition system as claimed in claim 1, characterized in that: The sensitive amplifier used in the sensitive preamplifier circuit is a voltage sensitive preamplifier, and the operational amplifier gain-bandwidth product is at the GHz level.
3. A detector time amplitude signal acquisition system as claimed in claim 1, characterized in that: The card threshold circuit comprises: Upper threshold reference voltage circuit, lower threshold reference voltage circuit, upper threshold comparator, lower threshold comparator, NAND gate, card threshold MOS switch; The inverting input of the upper threshold comparator is connected to the upper threshold reference voltage circuit; the non-inverting input of the upper threshold comparator is connected to the output of the sensitive preamplifier; the output of the upper threshold comparator is connected to the first input of the NAND gate; the non-inverting input of the lower threshold comparator is connected to the lower threshold reference voltage circuit; the inverting input of the lower threshold comparator is connected to the output of the sensitive preamplifier; the output of the lower threshold comparator is connected to the second input of the NAND gate; the input of the card threshold MOS switch is connected to the output of the sensitive preamplifier; and the control end of the card threshold MOS switch is connected to the output of the NAND gate.
4. A detector time amplitude signal acquisition system as claimed in claim 1, characterized in that: The peak hold and amplitude acquisition module comprises: Schottky diode, high-speed comparator, first buffer, second buffer, third buffer, acquisition MOS switch, ADC acquisition circuit; The input end of the Schottky diode is connected to the output end of the card threshold MOS switch, and the output end of the Schottky diode is connected to the non-inverting input end of the high-speed comparator, the input end of the ADC acquisition circuit, and the input end of the acquisition MOS switch; the inverting input end of the high-speed comparator is connected to the output end of the card threshold MOS switch; the output end of the high-speed comparator is connected to the input end of the first buffer and the control end of the ADC acquisition circuit; the first buffer, the second buffer, the third buffer, and the control end of the acquisition MOS switch are connected in sequence; the output end of the ADC acquisition circuit is connected to the data output end.
5. A detector time amplitude signal acquisition system as claimed in claim 1, characterized in that: The time acquisition module comprises: Coarse measurement circuit and fine measurement circuit; The coarse measurement circuit is used to measure the input time interval of the high-speed pulse signal; The fine measurement circuit is used to obtain high-resolution time information of high-speed pulse signals.
6. A detector time amplitude signal acquisition system as claimed in claim 5, characterized in that: The coarse measurement circuit comprises: Comparator, FPGA and crystal oscillator; The output end of the comparator is connected to the data input end of the FPGA; the output end of the crystal oscillator is connected to the clock input end of the FPGA.
7. A detector time amplitude signal acquisition system as claimed in claim 5, characterized in that: The fine measurement circuit includes: a comparator, a delayed carry chain, a rising edge detection circuit, a sampling trigger array, an encoding circuit and a calibration circuit; The comparator is connected to the rising edge detection circuit; the rising edge detection circuit is connected to the delayed carry chain; the rising edge detection circuit is connected to the sampling trigger array; the sampling trigger array is connected to the encoding circuit; the encoding circuit is connected to the calibration circuit.
8. A detector time amplitude signal acquisition system as claimed in claim 5, characterized in that: The amplitude information of the high-speed pulse signal is the sum of the voltage drop on the Schottky diode and the peak voltage collected by the peak holding circuit.
9. A method for collecting detector time amplitude signal according to any one of claims 1 to 8, characterized in that: The following steps are involved: The sensitive preamplifier circuit collects the charge and preliminarily amplifies the weak signal output by the detector to obtain a high-speed pulse signal; The card threshold circuit is used to remove the noise signals above the upper threshold and below the lower threshold of the high-speed pulse signal and the background interference signals above the upper threshold; Through the peak holding and amplitude acquisition circuit, the peak value of the high-speed pulse signal output by the sensitive preamplifier circuit is held for a period of time and an enable signal is output. The enable signal activates the ADC to perform amplitude sampling on the high-speed pulse signal to obtain the amplitude information of the high-speed pulse signal; The time at the amplitude of the high-speed pulse electrical signal output by the sensitive preamplifier circuit is collected through the time acquisition circuit to obtain high-resolution time information of the high-speed pulse signal.