Memory management method and memory controller

Abstract

The invention provides a memory management method and a memory controller thereof. The invention provides a memory management method of a memory device and a memory controller thereof. The method comprises the following steps: acquiring a host write-in instruction and corresponding host write-in data, and storing the host write-in data to a write-in cache of a memory controller; judging to execute the first garbage collection operation or the second garbage collection operation based on the working state of the storage device; if it is judged that the first garbage collection operation is executed, obtaining a source data block in the multiple entity blocks, reading effective source data from the source data block, storing the effective source data into a write-in cache, and writing the effective source data in the write-in cache and host write-in data into an open data block in the multiple entity blocks. By optimizing the data flow direction of the garbage collection operation, resource competition is avoided, the write-in performance and the garbage collection efficiency of the storage device are improved, and the service life of the storage device is effectively prolonged by reducing the data rewriting and block erasing times.

Description

Technical Field

[0001] The present disclosure relates to the technical field of memory, and particularly to a memory management method and a memory controller thereof. Background Art

[0002] In modern storage technologies, rewritable non-volatile memories (NAND Flash) have been widely used in storage devices such as solid state drives (SSDs).

[0003] In the field of storage technologies, garbage collection (GC) technology plays an important role in improving the performance of storage devices and extending their service life. With the increase in data volume and the wide application of storage devices, how to effectively manage storage space and improve data writing efficiency has become increasingly important.

[0004] In the prior art, when a storage device performs a garbage collection operation, it is usually necessary to read the valid data in the source data block into a random access memory, and then write this valid data into the target data block. However, during this process, if the host system simultaneously sends a write instruction, since resource conflicts will occur when the garbage collection operation and the write operation are performed on different physical blocks pointing to the same chip enable (CE), it is necessary to wait for one of the operations to complete before performing the other operation, thereby affecting the write performance and garbage collection efficiency. Especially when the storage device is in an emergency state (for example, the number of available blank physical blocks for writing data is insufficient), this impact is more significant. Summary of the Invention

[0005] In view of this, the present disclosure provides a memory management method and a memory controller for a storage device, which change the data flow direction of the garbage collection operation, and uniformly store the valid source data generated by the garbage collection operation and the host write data into a write cache and write them into open data blocks, thereby improving the write performance and garbage collection efficiency of the storage device.

[0006] One or more embodiments of the present invention provide a memory management method for a storage device, which is applicable to a storage device configured with a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical blocks. The method includes: obtaining a host write instruction and host write data corresponding to the host write instruction, and storing the host write data in a write cache of a memory controller of the storage device; based on a working state of the storage device, determining whether to perform a first garbage collection operation or a second garbage collection operation; if it is determined to perform the first garbage collection operation: obtaining a source data block among the plurality of physical blocks; reading valid source data from the source data block, and storing the valid source data in the write cache; and writing the valid source data in the write cache and the host write data into an open data block among the plurality of physical blocks.

[0007] In one or more embodiments of the present invention, if it is determined to perform the second garbage collection operation, the method further includes: obtaining the source data block among the plurality of physical blocks; reading the valid source data from the source data block, and storing the valid source data in a random access memory of the storage device; and writing the valid source data in the random access memory into a target data block among the plurality of physical blocks, where the target data block is different from the open data block.

[0008] In one or more embodiments of the present invention, the working state includes: the number of physical blocks in the storage device that are full of data; and the number of blank physical blocks in the storage device available for writing data.

[0009] In one or more embodiments of the present invention, the open data block includes the physical block that has stored data; the target data block is the physical block that has not stored data.

[0010] In one or more embodiments of the present invention, the method further includes: when the number of physical blocks full of data is greater than a first threshold, determining to perform the first garbage collection operation; and when the number of physical blocks full of data is greater than a second threshold and not greater than the first threshold, determining to perform the second garbage collection operation, where the first threshold is greater than the second threshold.

[0011] In one or more embodiments of the present invention, the method further includes: when the number of blank physical blocks is less than a third threshold, determining to perform the first garbage collection operation; and when the number of blank physical blocks is less than a fourth threshold and not less than the third threshold, determining to perform the second garbage collection operation, where the fourth threshold is greater than the third threshold.

[0012] In one or more embodiments of the present invention, the operating state further includes the current write speed of the storage device, and the method further includes: when the current write speed is less than a preset speed threshold, determining to perform the first garbage collection operation; and when the current write speed is not less than the preset speed threshold, determining to perform the second garbage collection operation.

[0013] In one or more embodiments of the present invention, the method further includes: recording a first logical address corresponding to the valid source data and a first physical address in the open data block for storing the valid source data; and recording a second logical address corresponding to the host-written data and a second physical address in the open data block for storing the host-written data.

[0014] In one or more embodiments of the present invention, the step of writing the valid source data and the host-written data in the write cache into the open data block among the plurality of physical blocks includes: after writing the host-written data, writing the valid source data; when the open data block is full and there is remaining valid source data in the valid source data that has not been written into the open data block, allocating another new open data block from the plurality of physical blocks; and writing the remaining valid source data into the other open data block.

[0015] In one or more embodiments of the present invention, the step of writing the valid source data and the host-written data in the write cache into the open data block among the plurality of physical blocks includes: obtaining a first data amount of the host-written data and a second data amount of the valid source data; detecting the number of continuously writable pages of the open data block; and when the number of continuously writable pages is greater than or equal to the sum of the first data amount and the second data amount, writing the host-written data and the valid source data into the open data block in a continuous writing manner.

[0016] One or more embodiments of the present invention provide a memory controller for controlling a storage device configured with a rewritable non-volatile memory module. The memory controller includes: a memory interface control circuit for electrically connecting to the rewritable non-volatile memory module, the rewritable non-volatile memory module including a plurality of physical blocks; and a processor electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to a connection interface circuit of the storage device to electrically connect to a host system. Wherein, the processor is configured to: obtain a host write instruction and host write data corresponding to the host write instruction, and store the host write data in a write cache of the memory controller; based on a working state of the storage device, determine to perform a first garbage collection operation or a second garbage collection operation; if it is determined to perform the first garbage collection operation: obtain a source data block from the plurality of physical blocks; read valid source data from the source data block, and store the valid source data in the write cache; and write the valid source data and the host write data in the write cache into an open data block among the plurality of physical blocks.

[0017] Based on the above, for the memory management method of the storage device and its memory controller provided by the present disclosure, by uniformly storing the host write data and the valid source data in the write cache and writing them into the open data block, the resource competition problem between the garbage collection operation and the write operation in different physical blocks at the same chip enable terminal in the conventional technology is avoided. In addition, since no additional target data block needs to be allocated when performing the first garbage collection operation, the write amplification of the storage device can be reduced, and the number of erase and write operations of the storage device can be reduced. At the same time, the present disclosure can also adopt a continuous write method according to the writable state of the open data block to write the host write data and the valid source data into the open data block, further improving the write efficiency of the storage device. Therefore, the present disclosure not only improves the overall performance of the storage device, but also effectively extends the service life of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention.

[0019] Figure 1 It is a block diagram of a host system and a storage device shown according to an embodiment of the present invention;

[0020] Figure 2 It is a flowchart of a memory management method shown according to an embodiment of the present disclosure;

[0021] Figure 3A 、 Figure 3BSchematic diagram of the first garbage collection operation shown in an embodiment according to the present disclosure.

[0022] Explanation of reference numerals in the drawings

[0023] 10: Host system

[0024] 20: Storage device

[0025] 110: Processor (second processor)

[0026] 120: Host memory

[0027] 130: Data transfer interface circuit

[0028] 210: Memory controller

[0029] 211: Processor (first processor)

[0030] 212: Data management circuit

[0031] 213: Memory interface control circuit

[0032] 214: Buffer memory

[0033] 220: Rewritable non-volatile memory module

[0034] 230: Connection interface circuit

[0035] SB: Source data block

[0036] OB: Open data block

[0037] WD: Host write data

[0038] SD: Valid source data

[0039] S210 - S280: Steps

[0040] A31 - A34: Arrows Detailed implementation manners

[0041] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and the description to denote the same or similar parts.

[0042] Figure 1 Block diagram of a host system and a storage device shown in an embodiment according to the present invention. Please refer to Figure 1, the host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also referred to as the second processor), a host memory 120, and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other using a system bus. In this embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 may be disposed on the motherboard of the host system 10.

[0043] The storage device 20 includes a memory controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. Among them, the memory controller 210 includes a processor 211 (also referred to as the first processor), a data management circuit 212, and a memory interface control circuit 213.

[0044] In this embodiment, the host system 10 accesses data by being electrically connected to the storage device 20 through the connection interface circuit 230 of the storage device 20 via the data transfer interface circuit 130. For example, the host system 10 can store data in the storage device 20 or read data from the storage device 20 via the data transfer interface circuit 130.

[0045] In this embodiment, the number of data transmission interface circuits 130 may be one or more. Through the data transmission interface circuit 130, the motherboard can be electrically connected to the storage device 20 in a wired or wireless manner. The storage device 20 may be, for example, a USB flash drive, a memory card, a solid state drive (SSD), or a wireless memory storage device. The wireless memory storage device may be, for example, a near field communication (NFC) memory storage device, a wireless fidelity (WiFi) memory storage device, a Bluetooth memory storage device, or a low energy Bluetooth memory storage device (e.g., iBeacon), etc., which are memory storage devices based on various wireless communication technologies. In addition, the motherboard can also be electrically connected to various I / O devices such as a global positioning system (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, etc. through a system bus.

[0046] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the peripheral component interconnect express (PCI Express) standard. Moreover, data is transmitted between the data transmission interface circuit 130 and the connection interface circuit 230 using the non-volatile memory express (NVMe) communication protocol.

[0047] In addition, in another embodiment, the connection interface circuit 230 may be encapsulated in a chip with the memory controller 210, or the connection interface circuit 230 is disposed outside a chip including the memory controller 210.

[0048] In this embodiment, the host memory 120 is used to temporarily store the instructions or data executed by the processor 110. For example, in this embodiment, the host memory 120 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. However, it must be understood that the present invention is not limited thereto, and the host memory 120 may also be other suitable memories.

[0049] The memory controller 210 is used to execute a plurality of logic gates or control instructions implemented in hardware form or firmware form and perform operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 220 according to the instructions of the host system 10.

[0050] More specifically, the processor 211 in the memory controller 210 is a hardware with computing capabilities, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed by a plurality of control instructions / program codes, and when the storage device 20 operates, these control instructions / program codes will be executed to perform operations such as data writing, reading, and erasing. In addition, in this embodiment, the control instructions / program codes can be further executed to perform specific garbage collection operations to implement the memory management method for different working states of the storage device provided by the present invention. The control instructions / program codes corresponding to the memory management method can be further implemented as a circuit unit in the form of hardware to implement the memory management method provided by the present invention.

[0051] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a Central Processing Unit (CPU), a micro-processor, or other programmable processing units (Microprocessor), a Digital Signal Processor (DSP), a programmable controller, an Application Specific Integrated Circuits (ASIC), a Programmable Logic Device (PLD), or other similar circuit components. The present invention is not limited thereto.

[0052] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by each component of the memory controller 210 can also be regarded as the operations performed by the memory controller 210.

[0053] Among them, the data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is used to accept the instructions of the processor 211 to perform data transmission. For example, read data from the host system 10 (such as the host memory 120) via the connection interface circuit 230, and write the read data into the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (such as performing a write operation according to a write instruction from the host system 10). Another example is to read data from one or more physical units of the rewritable non-volatile memory module 220 (the data can be read from one or more storage units in one or more physical units), and write the read data into the host system 10 (such as the host memory 120) via the connection interface circuit 230 (such as performing a read operation according to a read instruction from the host system 10). In another embodiment, the data management circuit 212 can also be integrated into the processor 211.

[0054] The memory interface control circuit 213 is used to accept the instructions of the processor 211 and cooperate with the data management circuit 212 to perform write (also known as programming), read, or erase operations on the rewritable non-volatile memory module 220.

[0055] In addition, the data to be written into the rewritable non-volatile memory module 220 will be converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 will send a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences can include a write instruction sequence for instructing writing data, a read instruction sequence for instructing reading data, an erase instruction sequence for instructing erasing data, and corresponding instruction sequences for instructing various memory operations. These instruction sequences can include one or more signals, or data on the bus. These signals or data can include instruction codes or program codes. For example, in the read instruction sequence, information such as a read identification code, a memory address, and a physical address will be included.

[0056] In addition, the memory controller 210 establishes a logical to physical address mapping table and a physical to logical address mapping table to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages) allocated to the rewritable non-volatile memory module 220 and the physical addresses (physical addresses) of physical units (e.g., physical erase units / physical blocks, physical pages). In other words, the memory controller 210 can look up the physical unit mapped by a logical unit (e.g., look up the physical page mapped by a logical page; look up the physical address mapped by a logical address) through the logical to physical address mapping table (also referred to as the logical to physical mapping table), and the memory controller 210 can look up the logical unit mapped by a physical unit (e.g., look up the logical page mapped by a physical page; look up the logical address mapped by a physical address) through the physical to logical address mapping table (also referred to as the physical to logical mapping table).

[0057] In one embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory 214 is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data for managing the storage device 20. Specifically, the buffer memory 214 can be configured with a write cache area, which can be used to temporarily store the data to be processed received by the processor 211 from the host system 10 and the data to be migrated read from the source data block during the execution of the garbage collection operation. In addition, the buffer memory 214 can also be used to store various mapping tables (e.g., the logical to physical address mapping table and the physical to logical address mapping table) so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 214.

[0058] In addition, the buffer memory 214 can also be configured with another cache area and determine this cache area as a random access memory, which is used to temporarily store the data to be migrated read from the source data block during the execution of the garbage collection operation; or the random access memory can also be another electronic module independent of the buffer memory 214.

[0059] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213) and is used to store the user data sent by the host system 10.

[0060] In this embodiment, each memory die (chip) among the multiple memory dies of the rewritable non-volatile memory module 220 has multiple planes, and each plane has multiple physical blocks. Each physical block includes multiple physical programmed units (also referred to as physical pages). Each physical page has multiple memory cells (also referred to as physical bytes or bytes), and each memory cell corresponds to a physical address. The physical address is used to record the physical location of the data stored in the memory cell. It should be noted that the present invention is not limited to the sizes of each physical page and logical page.

[0061] In this embodiment, when the rewritable non-volatile memory module 220 performs a garbage collection operation, the memory controller 210 selects one or more source data blocks from the multiple physical blocks. The source data blocks generally refer to the physical blocks in which the amount of valid data stored is relatively small, and there may be both valid data and invalid data in these physical blocks. Specifically, when the storage device 20 performs a traditional garbage collection operation (also referred to as the second garbage collection operation), the memory controller 210 reads the valid source data in the source data blocks and temporarily stores it in the random access memory, and then writes this valid source data into a newly allocated target data block. The target data block is a physical block specifically used to store the valid source data collected from the source data blocks. The target data block is an idle data block without data stored. After the valid source data is completely transferred to the target data block, the source data block can be marked as an erasable state, and thus can be reused in subsequent write operations after being erased.

[0062] In this embodiment, the memory controller 210 configures a write cache area (which can also be simply referred to as a write cache) in the buffer memory 214 for temporarily storing the data to be written into the rewritable non-volatile memory module 220. Specifically, when the memory controller 210 receives a write instruction from the host system 10, it temporarily stores the corresponding host write data in the write cache. In addition, based on the memory management method provided in the present disclosure, the memory controller 210 can also use the write cache to temporarily store the valid source data read from the source data blocks when performing the first garbage collection operation.

[0063] In this embodiment, when the memory controller 210 performs a write operation, it allocates a physical block from the multiple physical blocks of the rewritable non-volatile memory module 220 as an open data block. The open data block can be a data block that has data stored and can still write data. The open data block is used to receive the data from the write cache, and these data can be host write data or valid source data. Specifically, when the memory controller 210 writes data into the open data block, it writes the physical pages in the open data block in page order until the open data block is full or meets a preset closing condition.

[0064] In some embodiments, the timing for the memory controller 210 to close an open data block may include the following situations: when all the physical pages in the open data block have been written with data; when the number of remaining writable physical pages in the open data block is less than a preset threshold and cannot accommodate the next data to be written; or when the storage device 20 receives a forced close instruction. After the open data block is closed, the memory controller 210 updates the management information of the open data block (for example, updates the valid page count value of the physical block), and marks the physical block as being full. Subsequently, the memory controller 210 allocates a new physical block from multiple physical blocks as a new open data block to ensure the continuity of the write operation.

[0065] It should be noted that the size of the write cache affects the write performance of the storage device 20. Therefore, the memory controller 210 adjusts the usage mode of the write cache according to the operating state of the storage device 20.

[0066] Figure 2 A flowchart of a memory management method according to an embodiment of the present disclosure is shown.

[0067] Referring to Figure 2 , in step S210, the memory controller 210 obtains a host write instruction and host write data corresponding to the host write instruction, and stores the host write data in a write cache configured in the buffer memory 214. Specifically, when the host system 10 sends a write instruction to the storage device 20 through the data transfer interface circuit 130, the connection interface circuit 230 receives the write instruction and its corresponding host write data. Subsequently, under the control of the processor 211, the data management circuit 212 temporarily stores the host write data in the write cache.

[0068] In step S220, the memory controller 210 determines whether to perform the first garbage collection operation or the second garbage collection operation based on the working state of the storage device 20. Specifically, the memory controller 210 can make a determination according to working state parameters such as the number of physical blocks in the storage device 20 that are already full of data, the number of blank physical blocks available for writing data, and the current writing speed of the storage device 20. For example, when the number of physical blocks full of data is greater than a first threshold, the memory controller 210 determines to perform the first garbage collection operation; when the number of physical blocks full of data is greater than a second threshold and not greater than the first threshold, the memory controller 210 determines to perform the second garbage collection operation. Wherein the first threshold is greater than the second threshold. In addition, when the number of blank physical blocks is less than a third threshold, the memory controller 210 may also determine to perform the first garbage collection operation; when the number of blank physical blocks is greater than a fourth threshold and not greater than the third threshold, the memory controller 210 determines to perform the second garbage collection operation. Wherein the fourth threshold is greater than the third threshold.

[0069] In one embodiment, the memory controller 210 monitors the working state of the storage device 20, and this working state includes the number of physical blocks in the storage device 20 that are already full of data and the number of blank physical blocks available for writing data. Specifically, the memory controller 210 counts in real time the number of physical blocks in the rewritable non-volatile memory module 220 that are in a full state, and the number of blank physical blocks that have not been written with data. By monitoring these quantities, the memory controller 210 can accurately grasp the usage of the storage space of the storage device 20 and provide a basis for subsequent storage management decisions.

[0070] In another embodiment, the memory controller 210 compares the number of physical blocks full of data with a preset threshold to determine which garbage collection operation to perform. Specifically, when the number of physical blocks full of data is greater than a first threshold, the memory controller 210 determines to perform the first garbage collection operation. This situation usually indicates that the available space of the storage device 20 is already relatively tight and a more efficient garbage collection method needs to be adopted. In contrast, when the number of physical blocks full of data is greater than a second threshold and not greater than the first threshold, the memory controller 210 determines to perform the second garbage collection operation, where the first threshold is greater than the second threshold. In this case, although the storage device 20 needs to perform garbage collection, it is not in an emergency state, so a traditional garbage collection method can be adopted to maintain the stability of the system.

[0071] In one embodiment, the memory controller 210 also uses the current write speed of the storage device 20 as an important reference indicator for the working state. Specifically, when it is detected that the current write speed is less than the preset speed threshold, it indicates that the write performance of the storage device 20 has deteriorated. This performance degradation is usually caused by resource competition between traditional garbage collection operations and write operations among different physical blocks at the same chip enable terminal, or due to the disorder of data stored in the rewritable non-volatile memory module. At this time, the space occupied by the host-written data in the write cache is not large, and there is still sufficient space to receive data from the executed garbage collection. Therefore, the memory controller 210 determines to execute the first garbage collection operation. By storing the valid source data and the host-written data together in the write cache and writing them to the open data block, resource competition is avoided, thereby improving the write performance. On the contrary, when the current write speed is not less than the preset speed threshold, it indicates that the write performance of the storage device 20 is in a normal state. At this time, to fully meet the host write speed, the space occupied by the host-written data in the write cache is relatively large. Therefore, the memory controller 210 determines to execute the second garbage collection operation, and completes the garbage collection by temporarily storing the valid source data in the random access memory and writing it to an independent target data block. Through this dynamic adjustment strategy based on the write speed, the memory controller 210 can optimize the data processing path in a timely manner when the write performance bottleneck occurs, ensuring that the storage device 20 maintains a high write efficiency.

[0072] Next, if it is determined to execute the first garbage collection operation, in step S230, the memory controller 210 obtains the source data blocks in the multiple physical blocks. Specifically, the memory controller 210 can select the source data blocks based on a preset selection rule. For example, it selects the physical block with less valid data volume as the source data block. In some embodiments, the memory controller 210 can also comprehensively evaluate and select appropriate source data blocks according to parameters such as the number of erasure times and write time of the physical blocks.

[0073] In step S240, the memory controller 210 reads the valid source data from the source data blocks and stores the valid source data in the write cache. Specifically, the memory interface control circuit 213 reads the valid source data in the source data blocks under the control of the processor 211. To determine which data is valid data, the memory controller 210 can query the physical-to-logical address mapping table to determine whether the data stored in each physical page in the source data block is still valid. Subsequently, the data management circuit 212 temporarily stores the read valid source data in the write cache.

[0074] In step S250, the memory controller 210 writes the valid source data in the write cache and the host write data into the open data block among the multiple physical blocks. Specifically, the memory controller 210 may first write the host write data and then write the valid source data. When the number of consecutive writable pages in the open data block is greater than or equal to the sum of the data volumes of the host write data and the valid source data, the memory controller 210 may adopt a consecutive write method to improve the write efficiency. In addition, when the open data block is full and the valid source data has not been completely written, the memory controller 210 allocates a new open data block from the multiple physical blocks and writes the remaining valid source data into the new open data block. During this process, the memory controller 210 correspondingly updates the logical-to-physical address mapping table to record the corresponding relationships between the logical addresses and physical addresses of the valid source data and the host write data respectively.

[0075] In one embodiment, the memory controller 210 records the address mapping relationships of the valid source data and the host write data stored in the open data block by maintaining a mapping table. Specifically, when the memory controller 210 writes the valid source data in the write cache into the open data block, it records the first logical address corresponding to the valid source data and the first physical address in the open data block used to store the valid source data. Similarly, when the memory controller 210 writes the host write data into the open data block, it also records the second logical address corresponding to the host write data and the second physical address in the open data block used to store the host write data.

[0076] For example, when the memory controller 210 reads the valid source data from the source data block, it retains the original logical address (i.e., the first logical address) corresponding to the valid source data. Subsequently, when the valid source data is written into a specific physical page in the open data block, the memory controller 210 takes the physical address corresponding to the physical page as the first physical address and establishes a mapping relationship between the first logical address and the first physical address in the mapping table. For the host write data, the memory controller 210 establishes a mapping relationship between the logical address (i.e., the second logical address) specified in the host write instruction and the physical address (i.e., the second physical address) of the actual storage location of the host write data in the open data block.

[0077] Through this mapping mechanism, even if the valid source data and the host write data are written into the same open data block, the memory controller 210 can still accurately track the storage location of each piece of data, ensuring that subsequent data access requests can accurately locate the corresponding physical location. In addition, the maintenance of this mapping relationship also provides the necessary management information for subsequent garbage collection operations, helping to identify the validity status of the data in the physical block.

[0078] In one embodiment, when the memory controller 210 performs the first garbage collection operation, it will adopt a specific data writing order and strategy. Specifically, the memory controller 210 first writes the host write data in the write cache into the open data block, and then writes the valid source data. This arrangement of the writing order can ensure that the host write requests are given priority, thus maintaining good host response performance.

[0079] During the writing process, the memory controller 210 closely monitors the usage status of the open data block. When the open data block is full of data and there is still remaining valid source data in the write cache that has not been written, the memory controller 210 allocates a new open data block (i.e., another open data block) from multiple physical blocks of the rewritable non-volatile memory module 220. Subsequently, the memory controller 210 writes the remaining valid source data into this newly allocated open data block. Through this dynamic allocation mechanism, the continuity of the data writing process is ensured, avoiding write interruptions caused by the open data block being full.

[0080] In another embodiment, in order to further optimize the data writing efficiency, the memory controller 210 performs a capacity evaluation and a selection of the writing method before writing the data. Specifically, the memory controller 210 first obtains a first data volume of the host write data to be written in the write cache and a second data volume of the valid source data. For example, the memory controller 210 can determine these two data volumes by calculating the number of storage pages occupied by the host write data and the valid source data respectively.

[0081] Then, the memory controller 210 detects the number of consecutive writable pages in the current open data block. When it is detected that the number of consecutive writable pages in the open data block is greater than or equal to the sum of the first data volume and the second data volume, the memory controller 210 will adopt a continuous writing method to sequentially write the host write data and the valid source data into the open data block. This continuous writing method can make full use of the internal cache mechanism of the rewritable non-volatile memory module 220, significantly improving the data writing speed. For example, when there are 16 consecutive writable pages in the open data block, and the host write data requires 6 pages and the valid source data requires 8 pages, the memory controller 210 can enable the continuous writing mode and write the data of these 14 pages into the open data block at one time.

[0082] By implementing the above writing strategy, the memory controller 210 not only ensures the orderly progress of the data writing process, but also can use the continuous writing method to improve the writing efficiency under appropriate conditions, thereby improving the overall performance of the storage device 20.

[0083] On the other hand, if it is determined to perform the second garbage collection operation, in step S260, the memory controller 210 obtains the source data blocks among the multiple physical blocks. Specifically, the way the memory controller 210 obtains the source data blocks in this step is similar to that in step S230, and the source data blocks can be selected based on a preset selection rule. However, since the second garbage collection operation is usually performed when the working state of the storage device 20 is relatively less urgent, the memory controller 210 can adopt a more conservative selection strategy when selecting the source data blocks, such as selecting physical blocks with a higher proportion of valid data, so as to balance the garbage collection efficiency and the system resource overhead.

[0084] In step S270, the memory controller 210 reads the valid source data from the source data blocks and stores the valid source data in the random access memory. Specifically, under the control of the processor 211, the memory interface control circuit 213 identifies the valid source data in the source data blocks by querying the physical-to-logical address mapping table. Different from step S240, in this step, the data management circuit 212 temporarily stores the read valid source data in the random access memory instead of writing it into the cache. This design can avoid occupying the space of the write cache, enabling the write cache to focus more on processing host write data, thereby maintaining a high host write performance when the storage device 20 is in a normal working state.

[0085] In step S280, the memory controller 210 writes the valid source data in the random access memory into the target data blocks among the multiple physical blocks, where the target data blocks are different from the open data blocks. Specifically, the memory controller 210 will specifically allocate a physical block from the multiple physical blocks as the target data block for storing the valid source data read from the source data blocks. Although this traditional garbage collection method may cause write amplification, when the storage device 20 is in a normal working state, it can avoid affecting the normal write process of the host write data. During the writing process, the memory controller 210 also needs to update the logical-to-physical address mapping table to maintain the mapping relationship between the logical address of the valid source data and the new physical address. After the valid source data is completely written into the target data blocks, the memory controller 210 can mark the source data blocks as erasable states to release storage space for subsequent write operations.

[0086] Through the above steps, the memory management method provided in this embodiment can flexibly select an appropriate garbage collection operation mode according to the working state of the storage device 20, improving the write performance in an emergency state while ensuring stable operation in a normal state.

[0087] Figure 3A 、 Figure 3B Schematic diagram of the first garbage collection operation shown in an embodiment according to the present disclosure.

[0088] Refer to Figure 3A , in one embodiment, Figure 3A shows a schematic diagram of the data flow when the storage device 20 performs the first garbage collection operation. The memory controller 210 temporarily stores data from different sources through the write cache 2141 configured in the buffer memory 214. Specifically, as shown by arrow A31, the memory controller 210 stores the host write data (labeled WD in the figure) into the write cache 2141. At the same time, as shown by arrow A32, the valid source data (labeled SD in the figure) read from the source data block SB is also stored into the same write cache 2141.

[0089] In this embodiment, the source data block SB is an entity block selected by the memory controller 210 from multiple entity blocks of the rewritable non-volatile memory module 220 for performing the garbage collection operation. When the memory controller 210 determines to perform the first garbage collection operation on the source data block SB, it will first read the valid source data in the source data block SB through the memory interface control circuit 213. Specifically, the memory controller 210 identifies which data in the source data block SB is still valid by querying the entity-to-logical address mapping table, and as shown by arrow A32, reads this valid source data into the write cache 2141.

[0090] By uniformly storing the host write data WD and the valid source data SD into the write cache 2141, the memory controller 210 can uniformly manage these data to be written. This data management method not only simplifies the data write process but also avoids the resource competition problem that may occur in the traditional garbage collection method. In addition, since the write cache 2141 can accommodate both types of data at the same time, the memory controller 210 can more flexibly arrange the subsequent data write order, thereby improving the data write efficiency.

[0091] Refer to Figure 3B , in one embodiment, Figure 3B shows a schematic diagram of how the memory controller 210 writes the data in the write cache 2141 into the open data block when performing the first garbage collection operation. Specifically, there are two types of data temporarily stored in the write cache 2141: the host write data (labeled WD in the figure) and the valid source data (labeled SD in the figure). The memory controller 210 writes the host write data WD into the open data block OB through the data stream A33, and writes the valid source data SD into the same open data block OB through the data stream A34.

[0092] In this embodiment, the open data block OB is a physical block allocated by the memory controller 210 from multiple physical blocks of the rewritable non-volatile memory module 220 for receiving data writes. When the memory controller 210 determines to perform a data write operation, it will first check the number of writable pages in the open data block OB.

[0093] In one embodiment, the memory controller 210 calculates the sum of the first data volume of the host write data WD and the second data volume of the valid source data SD, and compares it with the number of consecutive writable pages in the open data block OB. When the number of consecutive writable pages in the open data block OB is sufficient to accommodate this data, the memory controller 210 can adopt a consecutive write method, as shown by arrows A33 and A34, and sequentially write the host write data WD and the valid source data SD in the write cache 2141 into the open data block OB. This write method makes full use of the internal cache mechanism of the rewritable non-volatile memory module 220 and can significantly improve the data write speed. Compared with the traditional garbage collection method that needs to write the valid source data into a dedicated target data block, the method of writing the host write data WD and the valid source data SD into the same open data block OB in this embodiment not only avoids resource competition between different physical blocks at the same chip enable end but also does not require an additional physical block configured for the valid source data SD, thus improving the utilization efficiency of the storage space and reducing the consumption of system resources.

[0094] This embodiment also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor, the processor executes the steps of the above storage device test method. This computer program product can be specifically implemented in a manner of hardware, firmware, software, or a combination thereof. In an alternative embodiment, the computer program product is specifically embodied as a computer storage medium. In another alternative embodiment, the computer program product is specifically embodied as a software product, such as a Software Development Kit (SDK), etc.

[0095] Based on the above, the memory management method and its memory controller of the storage device provided by the present disclosure first prepare for subsequent data write operations by obtaining a host write instruction and its corresponding host write data and storing the host write data in the write cache. Then, by determining to execute the first garbage collection operation or the second garbage collection operation based on the working state of the storage device, the most suitable garbage collection method can be selected according to the actual operating conditions of the storage device, improving the operating efficiency of the storage device.

[0096] Specifically, when it is determined to perform the first garbage collection operation, the memory controller reads valid source data from the source data block and stores it in the write cache, and then writes the valid source data in the write cache and the host write data into the open data block. This data processing method avoids the resource competition problem between the garbage collection operation and the write operation in different entity blocks at the same chip enable end in the traditional technology, and effectively improves the write performance of the storage device in an emergency state.

[0097] In addition, since the present disclosure does not need to additionally allocate a target data block to store valid source data when performing the first garbage collection operation, the write amplification factor of the storage device can be reduced, thereby reducing the number of erase and write operations of the storage device and effectively extending the service life of the storage device. At the same time, the present disclosure also ensures the accurate access of data and improves the reliability of the storage device by recording the mapping relationship between the logical address and the physical address corresponding to the valid source data and the host write data respectively.

[0098] Furthermore, the present disclosure realizes the continuity and efficiency of the data writing process by writing the valid source data after writing the host write data and timely allocating a new open data block when the open data block is full. When appropriate conditions are met, the present disclosure can also adopt a continuous write method to write the host write data and the valid source data into the open data block, further improving the write efficiency of the storage device.

[0099] In summary, the present disclosure not only improves the overall performance and reliability of the storage device, but also extends the service life of the storage device.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method for a storage device, applicable to a storage device equipped with a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical blocks, characterized in that: The method comprises: Acquire a host write instruction and host write data corresponding to the host write instruction, and store the host write data in a write cache of a memory controller of the storage device; Based on the working state of the storage device, determining to perform a first garbage collection operation or a second garbage collection operation; If it is determined to execute the first garbage collection operation: Acquire a source data block from the plurality of entity blocks; Reading valid source data from the source data block and storing the valid source data in the write buffer; and The valid source data and the host write data in the write cache are written to an open data block in the plurality of physical blocks.

2. The memory management method according to claim 1, characterized in that: If it is determined that the second garbage collection operation is to be performed, the method further includes: Acquire the source data block from the multiple entity blocks; Reading the valid source data from the source data block and storing the valid source data in a random access memory of the storage device; and The valid source data in the random access memory is written to a target data block among the plurality of physical blocks, wherein the target data block is different from the open data block.

3. The memory management method according to claim 2, characterized in that: The open data block includes the entity block in which data has been stored; The target data block is the physical block that does not store data.

4. The memory management method according to claim 1, characterized in that: The working status includes: The number of physical blocks in the storage device that are fully written with data; and The number of blank physical blocks in the storage device that can be used to write data.

5. The memory management method according to claim 4, characterized in that: The method further comprises: When the number of the physical blocks that are fully written with data is greater than a first threshold, determining to execute the first garbage collection operation; and When the number of physical blocks that are fully written with data is greater than a second threshold and not greater than the first threshold, it is determined to perform the second garbage collection operation, wherein the first threshold is greater than the second threshold.

6. The memory management method according to claim 4, characterized in that: The method further comprises: When the number of the blank physical blocks is less than a third threshold, determining to perform the first garbage collection operation; and When the number of blank physical blocks is less than a fourth threshold and not less than the third threshold, it is determined to perform the second garbage collection operation, wherein the fourth threshold is greater than the third threshold.

7. The memory management method according to claim 4, characterized in that: The working status also includes a current writing speed of the storage device, wherein the method further includes: When the current writing speed is less than a preset speed threshold, determining to execute the first garbage collection operation; and When the current writing speed is not less than the preset speed threshold, it is determined to execute the second garbage collection operation.

8. The memory management method according to claim 1, characterized in that: The method further comprises: Recording a first logical address corresponding to the valid source data and a first physical address in the open data block for storing the valid source data; and A second logical address corresponding to the host write data and a second physical address in the open data block for storing the host write data are recorded.

9. The memory management method according to claim 1, characterized in that: The step of writing the valid source data and the host write data in the write cache to the open data block in the plurality of physical blocks comprises: After writing the host write data, writing the valid source data; When the open data block is full and the valid source data has remaining valid source data that has not been written to the open data block, allocating another new open data block from the plurality of physical blocks; and The remaining valid source data is written to the another open data block.

10. The memory management method according to claim 9, characterized in that: The step of writing the valid source data and the host write data in the write cache to the open data block in the plurality of physical blocks comprises: Acquire a first data amount of the host write data and a second data amount of the valid source data; detecting the number of consecutive writable pages of the open data block; and When the number of consecutive writable pages is greater than or equal to the sum of the first data amount and the second data amount, the host write data and the valid source data are written to the open data block in a consecutive write manner.

11. A memory controller for controlling a storage device equipped with a rewritable non-volatile memory module, characterized in that: The memory controller comprises: A memory interface control circuit, for electrically connecting to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical blocks; and A processor electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to the connection interface circuit of the storage device to electrically connect to the host system, wherein the processor is configured to: Acquire a host write instruction and host write data corresponding to the host write instruction, and store the host write data in a write cache of the memory controller; Based on the working state of the storage device, determining to perform a first garbage collection operation or a second garbage collection operation; If it is determined to execute the first garbage collection operation: Acquire a source data block from the plurality of entity blocks; Reading valid source data from the source data block and storing the valid source data in the write buffer; and The valid source data and the host write data in the write cache are written to an open data block in the plurality of physical blocks.

12. The memory controller according to claim 11, wherein: The processor is also configured to: If it is determined to execute the second garbage collection operation: Acquire the source data block from the multiple entity blocks; Read the valid source data from the source data block and store the valid source data in a random access memory of the storage device; as well as The valid source data in the random access memory is written to a target data block among the plurality of physical blocks, wherein the target data block is different from the open data block.

13. The memory controller according to claim 12, wherein: The open data block includes the entity block in which data has been stored; The target data block is the physical block that does not store data.

14. The memory controller according to claim 12, wherein: The working status includes: The number of physical blocks in the storage device that are fully written with data; and The number of blank physical blocks in the storage device that can be used to write data.

15. The memory controller according to claim 14, wherein: The processor is also configured to: When the number of the physical blocks that are full of data is greater than a first threshold, determining to execute the first garbage collection operation; as well as When the number of physical blocks that are fully written with data is greater than a second threshold and not greater than the first threshold, it is determined to perform the second garbage collection operation, wherein the first threshold is greater than the second threshold.

16. The memory controller according to claim 14, wherein: The processor is also configured to: When the number of the blank physical blocks is less than a third threshold, determining to perform the first garbage collection operation; and When the number of blank physical blocks is less than a fourth threshold and not less than the third threshold, it is determined to perform the second garbage collection operation, wherein the fourth threshold is greater than the third threshold.

17. The memory controller according to claim 14, wherein: The working status also includes a current write speed of the storage device, wherein the processor is further configured to: When the current writing speed is less than a preset speed threshold, determining to perform the first garbage collection operation; as well as When the current writing speed is not less than the preset speed threshold, it is determined to execute the second garbage collection operation.

18. The memory controller according to claim 11, wherein: The processor is also configured to: Recording a first logical address corresponding to the valid source data and a first physical address in the open data block for storing the valid source data; as well as A second logical address corresponding to the host write data and a second physical address in the open data block for storing the host write data are recorded.

19. The memory controller according to claim 11, wherein: When the processor writes the valid source data and the host write data in the write cache to the open data block in the plurality of physical blocks, the processor is configured to: After writing the host write data, writing the valid source data; When the open data block is full and the valid source data has remaining valid source data that has not been written to the open data block, allocating another new open data block from the multiple physical blocks; as well as The remaining valid source data is written to the another open data block.

20. The memory controller according to claim 19, wherein: When the processor writes the valid source data and the host write data in the write cache to the open data block in the plurality of physical blocks, the processor is configured to: Acquire a first data amount of the host write data and a second data amount of the valid source data; Detecting the number of consecutive writable pages of the open data block; as well as When the number of consecutive writable pages is greater than or equal to the sum of the first data amount and the second data amount, the host write data and the valid source data are written to the open data block in a consecutive write manner.

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