SDIO bus host interface module, communication method and communication system
By designing the SDIO bus host interface module, including the main control module, CMD control module and bus interface conversion module, the problem of complex implementation methods, high hardware costs and many interface signals when FPGA is an SDIO bus host, and the FPGA independently implements the SDIO bus host protocol, saving hardware costs, reducing power consumption, and concise interfaces.
Patent Information
- Application Number
- CN202510195228.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-21
- Publication Date
- 2025-05-27
AI Technical Summary
In the prior art, when the FPGA is an SDIO bus host, there are problems such as complex implementation methods, high hardware costs, and many interface signals.
A SDIO bus host interface module is designed, including a main control module, a CMD control module and a bus interface conversion module. Through the WISHBONE bus and the interface conversion module, the conversion between the WISHBONE bus and the LOCAL_BUS bus is realized, and the FPGA is supported to independently implement the SDIO bus host protocol.
It effectively solves the problem of interoperability between FPGA as an SDIO bus master and CPU as a slave, saving hardware costs, reducing power consumption, concise interfaces, and increasing the universality of the module.
Smart Images
Figure CN120045487A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of data transmission, and specifically to an SDIO bus host interface module, a communication method, and a communication system. Background Art
[0002] SDIO (Secure Digital Input and Output) is a peripheral interface defined on the SD standard and is widely used in application scenarios such as wireless communication, positioning and navigation, camera shooting, and audio playback. The SDIO bus consists of a total of 9 wires: a clock wire, a CMD wire, 4 data wires, a power wire, and 2 ground wires. The transmission modes are divided into SPI mode, 1-bit mode, and 4-bit mode. The SDIO bus has been widely used in the field of the interaction bus between an embedded CPU and an FPGA due to its simple hardware structure and relatively high transmission rate. In traditional embedded SDIO bus application scenarios, a CPU is often used as the host and an FPGA is used as the slave; when using an FPGA as the host, the SDIO interface part is often only implemented inside the FPGA and an external CPU is used to implement the interface protocol of the SDIO bus, resulting in high hardware costs and problems such as many interface signals and complex control timings. Summary of the Invention
[0003] To overcome the deficiencies of the prior art, the present invention provides an SDIO bus host interface module, a communication method, and a communication system, which solve the problems existing in the prior art such as complex implementation methods, high hardware costs, and many interface signals.
[0004] The technical solutions adopted by the present invention to solve the above problems are as follows:
[0005] An SDIO bus host interface module includes a main control module, a CMD control module, and a bus interface conversion module that communicate with each other in pairs.
[0006] As a preferred technical solution, the main control module is used to implement the protocol processing of the SDIO host interface, the CMD control module is used to generate CMD commands and receive CMD response signals, and the bus interface conversion module is used to implement the conversion of different bus protocol interfaces.
[0007] As a preferred technical solution, the main control module and the interface conversion module are communicatively connected through a WISHBONE bus.
[0008] As a preferred technical solution, the bus interface conversion module is used to implement the conversion between the WISHBONE bus and the LOCAL_BUS bus. The main control module is also used to communicate with the slave through the SDIO bus, and the bus interface conversion module is also used to communicate with the user side of the host through the LOCAL_BUS bus.
[0009] An SDIO bus communication method uses the described SDIO bus host interface module to communicate between the host and the slave, and between the host and the user.
[0010] As a preferred technical solution, when the slave needs to send a communication request for the host to read the slave's data, an external interrupt signal pulse is provided to the main control module; after receiving the interrupt signal pulse, the main control module first performs the required CMD data interaction with the CMD control module, and then reads the slave's data and sends it to the user side.
[0011] As a preferred technical solution, when the host needs to send data, the user side of the host inputs the data to be sent into the bus interface conversion module; the bus interface conversion module first performs the required CMD data interaction with the CMD control module, and then transmits the data to be sent to the slave through the main control module.
[0012] As a preferred technical solution, after the host is powered on, the CMD control module sends the following CMD commands: CMD0, CMD8, CMD5. After receiving CMD0, CMD8, and CMD5, the main control module generates the corresponding CMD data and sends it to the slave; after the slave receives the CMD data and replies with a correct CMD5 response packet, the CMD control module sequentially sends the following CMD commands: CMD3, CMD7, CMD52. After receiving CMD3, CMD7, and CMD52, the main control module generates the corresponding CMD data and sends it to the slave; after the slave receives the CMD data and replies with the CMD3, CMD7, and CMD52 response packets, the power-on initialization of the SDIO bus is completed; where CMD0 represents the GO_IDLE_STATE command, CMD8 represents the SEND_IF_COND command, CMD5 represents the IO_SEND_OP_COND command, CMD3 represents the SEND_RELATIVE_ADDR command, CMD7 represents the SELECT / DESELECT_CARD command, and CMD52 represents the IO_RW_DIRECT command.
[0013] An SDIO bus communication system includes a host and a slave. The host includes the described SDIO bus host interface module and the user side. The slave, the main control module, the bus interface conversion module, and the user side are communicatively connected in sequence.
[0014] As a preferred technical solution, the host is an FPGA and the slave is a CPU.
[0015] Compared with the prior art, the present invention has the following beneficial effects:
[0016] (1) In the design solution proposed by the present invention, the FPGA can independently implement the host protocol of the SDIO bus, effectively solving the interoperability problem between the FPGA as the host and the CPU as the slave when using the SDIO bus, saving hardware costs, reducing power consumption, and having a simple interface;
[0017] (2) The present invention uses the LOCAL_BUS interface as the user-side interface of the IP core module, greatly increasing the versatility of the module and reducing the adaptation work required for calling the IP core. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 is the structural block diagram of the SDIO bus host interface module;
[0019] Figure 2 is the timing diagram for the SDIO bus host interface module to receive data;
[0020] Figure 3 is Figure 2 one of the partial enlarged views of;
[0021] Figure 4 is Figure 2 the second partial enlarged view of;
[0022] Figure 5 is the timing diagram for the SDIO bus host interface module to send data;
[0023] Figure 6 is Figure 5 one of the partial enlarged views of;
[0024] Figure 7 is Figure 5 the second partial enlarged view of;
[0025] Figure 8 is the data reception flowchart of the SDIO bus host interface module;
[0026] Figure 9 is the data transmission flowchart of the SDIO bus host interface module. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0027] The present invention will be further described in detail below in conjunction with the embodiments and the drawings, but the embodiments of the present invention are not limited thereto.
[0028] Embodiment 1
[0029] As Figures 1 to 9 shown, the present invention is applicable to embedded systems and complete machines, and the technical problems to be solved are:
[0030] 1. Implement the IP core of the SDIO bus host interface module using FPGA, achieving the host interface function of the SDIO bus protocol: the initialization after power-on of the SDIO bus protocol and the functions of the host reading and writing the slave. Currently, the module supports a maximum operating frequency of 100MHZ, that is, the maximum transmission rate can reach 400Mbps.
[0031] 2. All the host interface functions of the SDIO bus are implemented by the IP core software, without relying on the hardware structure of the external CPU of the FPGA to implement the SDIO bus protocol, saving hardware costs and reducing power consumption.
[0032] 3. The IP core software provides input and output ports for external calls, and this interface is as simple and general as possible.
[0033] 4. The slave CPU side can actively initiate a communication request, that is, the slave can inform the host to initiate a read operation, and at the same time, the waiting time is as little as possible, so as to realize the instant data interaction between the FPGA and the CPU through the SDIO bus.
[0034] More specifically, as follows:
[0035] (1) Design scheme
[0036] The framework of the SDIO bus host interface module is as Figure 1 shown. The top-level module of the SDIO bus host interface module is TEST_SD_TOP1, which contains three sub-modules: the SDIO main control module SD_CONTROLLER_TOP, the CMD control module sdio_reg_ctr of the SDIO, and the bus interface conversion module sddata_top1. The main control module is used to implement the protocol processing of the SDIO host interface. The CMD (Command, a bidirectional command / response signal. In the protocol "Part_E1_SDIO_Speciifcation_Ver3.0", the explanation of the CMD signal is Bidirectional Command / Response signal) control module is used to generate the CMD commands to be sent to the main control module through the CMD logic state machine (after receiving the CMD commands, the main control module generates CMD data and sends it to the slave), receive the CMD response signal (the CMD response signal is generated by the slave and then sent to the CMD control module through the main control module) and perform parsing and processing. The bus interface conversion module is used to implement the conversion of different bus protocol interfaces.
[0037] As shown in Table 1, when developers use the SDIO bus host interface module, they do not need to care about the implementation method of the code inside the module. After connecting to the external interface of the SDIO bus, it can be called through the simple LOCAL_BUS interface. In Table 1: The 400K clock required for SDIO initialization is generated by the SDIO host module itself by dividing the sdio_clk frequency; the direction is referenced by the SDIO host module. The receiving data and transmitting data timing diagrams of the SDIO bus host interface module are respectively as Figure 2 and Figure 5 shown.
[0038] Table 1 SDIO Bus Host Interface Module Interface Signal Description Table
[0039]
[0040] (2) Processing Flow
[0041] After power-on, the SDIO bus host interface module will periodically send CMD0, CMD8, and CMD5 until the slave replies with a correct CMD5 response packet, and then start to execute the subsequent processes of SDIO bus power-on initialization to complete the power-on initialization of the SDIO bus.
[0042] More specifically: The CMD control module sends the following CMD commands: CMD0, CMD8, CMD5. After the master control module receives CMD0, CMD8, and CMD5, it generates corresponding CMD data and sends it to the slave device; after the slave device receives the CMD data and replies with a correct CMD5 response packet, the CMD control module sequentially sends the following CMD commands: CMD3, CMD7, CMD52. After the master control module receives CMD3, CMD7, and CMD52, it generates corresponding CMD data and sends it to the slave device; after the slave device receives the CMD data and replies with CMD3, CMD7, and CMD52 response packets, the power-on initialization of the SDIO bus is completed; among them, CMD0 represents the GO_IDLE_STATE (soft reset) command, CMD8 represents the SEND_IF_COND (card status detection) command, CMD5 represents the IO_SEND_OP_COND (obtain card operation conditions) command, CMD3 represents the SEND_RELATIVE_ADDR (obtain device slave address) command, CMD7 represents the SELECT / DESELECT_CARD (select card) command, and CMD52 represents the IO_RW_DIRECT (configure slave device) command. Regarding "reply with a correct CMD5 response packet": The value of the Number of l / O Functions (indicating the l / O functions supported by the card) field in the CMD5 response packet is greater than 0, and the voltage range represented by the value of the I / 0OCR (maximum / minimum voltage range supported) field matches the voltage range supported by the host interface module, that is, it is considered correct. This is a method that can be achieved by existing technologies, so the specific working principle and process are not elaborated here.
[0043] When the slave device needs to send a communication request for the host to read data, it needs to provide an external interrupt signal pulse (where the data line is multiplexed in 1bit-mode) to the SDIO bus host interface module; after the master control module receives the interrupt signal pulse, the SDIO bus host interface module will actively read the data on the slave device side (after receiving the interrupt signal pulse, it first conducts the required CMD data interaction with the CMD control module, and then reads the data of the slave device and sends it to the user side). For example Figure 2 , after the SDIO bus host interface module receives a packet of SDIO data, it will output it to the next-level module of the FPGA through the LOCAL_BUS interface. Figure 2 The example in it is 342B of data that the slave device needs to let the host read, and the block size used by SDIO in the example is 256B. The data reception process of the SDIO bus host interface module is as Figure 8 shown.
[0044] When the host needs to send data, it can directly input the data to be sent into the SDIO bus host interface module according to the LOCAL_BUS. More specifically: the user side of the host inputs the data to be sent into the bus interface conversion module; the bus interface conversion module first conducts the required CMD data interaction with the CMD control module, and then transmits the data to be sent to the slave through the SDIO bus via the main control module. As Figure 5 , after the SDIO bus host interface module receives a packet of data to be sent from the LOCAL_BUS interface, it will send it by itself. During the sending process, no new data to be sent can be input again. It is necessary to wait for the o_prot_tx_ready signal to be valid before sending the next packet of data. Figure 5 The example in Figure 9 shows that the host sends 342B of data to the slave, and the block size used by the SDIO in the example is 256B. The data sending process of the SDIO bus host interface module is as
[0045] The present invention has the following advantages:
[0046] (1) In the design scheme proposed by the present invention, the FPGA can independently implement the host protocol of the SDIO bus, effectively solving the problem of intercommunication between the FPGA as the host and the CPU as the slave when using the SDIO bus, saving hardware costs, reducing power consumption, and having a simple interface;
[0047] (2) The present invention uses the LOCAL_BUS interface as the user side interface of the IP core module, greatly increasing the versatility of the module and reducing the adaptation work required for calling the IP core.
[0048] As described above, the present invention can be preferably implemented.
[0049] All the features disclosed in all the embodiments in this specification, or all the steps in the methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or extended and replaced in any way.
[0050] The above description is only a preferred embodiment of the present invention, and does not impose any form of limitation on the present invention. Based on the technical essence of the present invention, any simple modification, equivalent replacement, and improvement made to the above embodiments within the spirit and principle of the present invention still fall within the protection scope of the technical solution of the present invention.
Claims
1. A SDIO bus host interface module, characterized in that: It includes a main control module, a CMD control module and a bus interface conversion module which are connected in pairs for communication.
2. The SDIO bus host interface module according to claim 1, characterized in that: The main control module is used to implement the protocol processing of the SDIO host interface, the CMD control module is used to generate CMD commands and receive CMD response signals, and the bus interface conversion module is used to implement the conversion of different bus protocol interfaces.
3. An SDIO bus host interface module according to claim 1 or 2, characterized in that: The main control module and the interface conversion module are connected via the WISHBONE bus communication.
4. The SDIO bus host interface module according to claim 3, characterized in that: The bus interface conversion module is used to realize the conversion between the WISHBONE bus and the LOCAL_BUS bus. The main control module is also used to communicate with the slave through the SDIO bus. The bus interface conversion module is also used to communicate with the user side of the host through the LOCAL_BUS bus.
5. A SDIO bus communication method, characterized in that: The SDIO bus host interface module according to any one of claims 1 to 4 is used to perform communication between a host and a slave, or between a host and a user.
6. The SDIO bus communication method according to claim 5, characterized in that: When the slave needs to send a communication request to let the host read the slave's data, it provides an external interrupt signal pulse to the main control module; after receiving the interrupt signal pulse, the main control module first interacts with the CMD control module for the required CMD data, then reads the slave's data and sends it to the user side.
7. The SDIO bus communication method according to claim 5, characterized in that: When the host needs to send data, the user side of the host inputs the data to be sent into the bus interface conversion module; The bus interface conversion module first interacts with the CMD control module to exchange the required CMD data, and then transmits the data to be sent to the slave via the master control module.
8. The SDIO bus communication method according to any one of claims 5 to 7, characterized in that: After the host is powered on, the CMD control module sends the following CMD commands: CMD0, CMD8, CMD5. After receiving CMD0, CMD8, and CMD5, the main control module generates corresponding CMD data and sends it to the slave; after the slave receives the CMD data and replies to the correct CMD5 response packet, the CMD control module sends the following CMD commands in sequence: CMD3, CMD7, and CMD52. After receiving CMD3, CMD7, and CMD52, the main control module generates corresponding CMD data and sends it to the slave; after the slave receives the CMD data and replies to the CMD3, CMD7, and CMD52 response packets, the power-on initialization of the SDIO bus is completed; among them, CMD0 represents the GO_IDLE_STATE command, CMD8 represents the SEND_IF_COND command, CMD5 represents the IO_SEND_OP_COND command, CMD3 represents the SEND_RELATIVE_ADDR command, CMD7 represents the SELECT / DESELECT_CARD command, and CMD52 represents the IO_RW_DIRECT command.
9. An SDIO bus communication system, characterized in that: The invention comprises a host and a slave, wherein the host comprises an SDIO bus host interface module and a user side as claimed in any one of claims 1 to 4, and the slave, a main control module, a bus interface conversion module and a user side are sequentially connected in communication.
10. The SDIO bus communication system according to claim 9, characterized in that: The host is FPGA and the slave is CPU.