Signal preprocessing circuit

Abstract

The invention discloses a signal preprocessing circuit, and relates to the technical field of electronic circuits. The circuit comprises a primary multiplexer, a secondary multiplexer, a signal processing module and an information source receiving end, the first-stage multiplexer is provided with a first-stage signal gating port and a first-stage signal output port; the second-stage multiplexer is provided with a second-stage signal gating port and a second-stage signal output port; the signal processing module is provided with a module input port and a module output port; the signal source receiving ends are connected with primary signal gating ports of the primary multiplexer in a one-to-one correspondence manner, primary signal output ports are connected with module input ports in a one-to-one correspondence manner, and module output ports are connected with secondary signal gating ports of the secondary multiplexer in a one-to-one correspondence manner; by setting the on or off state of the first-stage signal gating port and the second-stage signal gating port, a signal obtained by the signal source receiving end is processed by the signal processing module and then transmitted to the preset second-stage signal output port.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and particularly relates to a signal preprocessing circuit. Background Art

[0002] With the development of electronic technology, chips are widely applied in electronic circuits to process input signals. In order to obtain high-quality signals and improve signal processing effects, signals need to be preprocessed before being input into chip pins. Generally, signals are filtered before being processed by chips, and digital filters are commonly used. However, the setting method of digital filters is relatively single, and it can only filter signals input from fixed signal input ends; if digital filters are set for each signal input end, the circuit area and cost are unacceptable. Similarly, in some scenarios, logical operations need to be performed on input signals before they are input into chip pins, and existing circuits need to be designed for specific scenarios, which increases the R & D cycle and is not conducive to product miniaturization. Aiming at the problem of inflexible preprocessing methods before signals are input into pins, a signal preprocessing circuit is urgently needed to solve the above technical problems. Summary of the Invention

[0003] In order to solve the problem that it is difficult to flexibly perform preprocessing before signals are input into chip pins, the present application provides the following technical solutions: Provide a signal preprocessing circuit, including: at least one first-level multiplexer, at least one second-level multiplexer, a signal processing module, and a plurality of signal source receiving ends.

[0004] Any one of the at least one first-level multiplexers has: a first-level signal selection port and a first-level signal output port.

[0005] Any one of the at least one second-level multiplexers has: a second-level signal selection port and a second-level signal output port.

[0006] The signal processing module has: a module input port and a module output port.

[0007] Any one of the plurality of signal source receiving ends is correspondingly connected to the first-level signal selection port of any one of the at least one first-level multiplexers one by one, any one of the first-level signal output ports is correspondingly connected to the module input port one by one, and the module output port is correspondingly connected to the second-level signal selection port of any one of the at least one second-level multiplexers one by one.

[0008] By setting the on or off state of the first-level signal selection port and the second-level signal selection port, the signal obtained by any one of the plurality of signal source receiving ends is processed by the signal processing module and then transmitted to a preset second-level signal output port.

[0009] Further, the signal processing module includes at least one signal processing unit.

[0010] Any one of at least one signal processing unit has a signal processing input port and a signal processing output port.

[0011] The signal processing input ports respectively serve as module input ports one by one, and the signal processing output ports respectively serve as module output ports one by one.

[0012] The signal processing unit processes the signal obtained by the corresponding signal processing input port and outputs it from the corresponding signal processing output port.

[0013] Furthermore, the secondary multiplexer further includes a source input port, and the source input port is connected to a plurality of source receivers one by one.

[0014] Furthermore, the circuit further includes at least one tertiary multiplexer.

[0015] Any one of at least one tertiary multiplexer has: a tertiary signal input port and a tertiary signal gating port.

[0016] The tertiary signal input ports are connected to the secondary signal output ports one by one.

[0017] The tertiary signal gating port outputs the signal transmitted by the secondary signal gating port that is set to be conducting among the secondary signal gating ports of the corresponding connected secondary multiplexer.

[0018] Furthermore, the number of tertiary multiplexers is equal to the number of secondary multiplexers.

[0019] Furthermore, the circuit further includes: a channel selection module.

[0020] The channel selection module is connected to the primary multiplexer, the secondary multiplexer, and the tertiary multiplexer, and is used to set the conducting or non-conducting states of the primary signal gating port, the secondary signal gating port, and the tertiary signal gating port.

[0021] Furthermore, the signal processing module includes a first signal processing unit.

[0022] The first signal processing unit has at least two first unit signal input ports and a first unit signal output port.

[0023] At least two of the first unit signal input ports respectively serve as module input ports one by one.

[0024] The first unit signal output port serves as the module output port.

[0025] Furthermore, the first signal processing unit is a logic operation unit.

[0026] The logic operation unit includes one or a combination of at least two of the following: basic logic gates, arithmetic units, numerical comparators, selectors, distributors, parity checkers, shift operation units, encoders, decoders, and numerical converters.

[0027] Further, the signal processing module includes a second signal processing unit and a third signal processing unit.

[0028] The second signal processing unit has a second unit signal output port, and the third signal processing unit has a third unit signal output port.

[0029] The first-level multiplexer also has a processing signal receiving port.

[0030] The second unit signal output port is connected to the processing signal receiving port of the first-level multiplexer connected to the third unit signal processing unit.

[0031] The third unit signal output port is connected to the processing signal receiving port of the first-level multiplexer connected to the second unit signal processing unit.

[0032] Further, the second signal processing unit is a low-pass filter, and the third signal processing unit is a high-pass filter.

[0033] By setting the conduction or cutoff of the selection ports of the signal preprocessing circuit described in the embodiments of the present application, a group of signal processing modules are used to process the input signals of any signal source and output them to the corresponding subsequent chip modules. This saves circuit area and improves the multiplexing degree of the signal processing modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0035] Figure 1 is a schematic diagram of a signal preprocessing circuit module provided by an embodiment of the present application; Figure 2 is a schematic diagram of a signal preprocessing module provided by an embodiment of the present application; Figure 3 is a schematic diagram of a signal and processing circuit module including a three-level multiplexer provided by an embodiment of the present application; Figure 4 is another schematic diagram of a signal preprocessing circuit provided by an embodiment of the present application; Figure 5It is a schematic diagram of a signal preprocessing circuit provided by an embodiment of the present application, including a source input port; Figure 6 It is a schematic diagram of a signal preprocessing circuit provided by an embodiment of the present application, including second and third signal processing units; Figure 7 It is a schematic diagram of a signal AND processing circuit provided by an embodiment of the present application, including a first signal processing unit. Specific Embodiments

[0036] To make the objectives, technical solutions, and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present application.

[0037] Unless otherwise defined, the technical terms or scientific terms used in this disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which this disclosure pertains. The "first", "second", and similar terms used in this disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. Similarly, the terms such as "a", "an", or "the" do not denote a quantity limitation, but mean that there is at least one. The numbers in the accompanying drawings of the specification only represent the distinction between various functional components or modules, and do not represent the logical relationship between the components or modules. The terms such as "including" or "comprising" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0038] Next, various embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that in the drawings, the same reference numerals are assigned to components that are substantially the same or have similar structures and functions, and repeated descriptions thereof will be omitted.

[0039] In view of the problem that it is difficult to flexibly perform signal preprocessing before the signal enters the chip pin, the present application provides the following embodiments.

[0040] In some embodiments, as Figure 1As shown in the figure, a signal preprocessing circuit is provided at the front stage of the chip pin. It includes: at least one first-level multiplexer 100, at least one second-level multiplexer 200, a signal processing module 300, and several signal source receiving ends S n , where n is a natural number used to distinguish several signal source receiving ends.

[0041] Any one of the at least one first-level multiplexers, the first-level multiplexer 100, has: a first-level signal selection port 100 si and a first-level signal output port 100 so .

[0042] Any one of the at least one second-level multiplexers, the second-level multiplexer 200, has: a second-level signal selection port 200 si and a second-level signal output port 200 so .

[0043] The signal processing module 300 has: a module input port 300 i and a module output port 300 o .

[0044] Any one of the several signal source receiving ends, the signal source receiving end S n is connected in one-to-one correspondence with the first-level signal selection port 100 of any one of the first-level multiplexers si , and any one of the first-level signal output ports 100 so is connected in one-to-one correspondence with the module input port 300 i , and the module output port 300 o is connected in one-to-one correspondence with the second-level signal selection port 200 of any one of the second-level multiplexers si .

[0045] By setting the on or off state of the first-level signal selection port 100 si and the second-level signal selection port 200 si , the signal obtained by any one of the several signal source receiving ends, the signal source receiving end S n , after being processed by the signal processing module 300, is transmitted to the preset second-level signal output port 200 so .

[0046] Schematically, the above signal source receiving end is the signal input pin of the chip.

[0047] Specifically, as Figure 2 shown, the signal processing module 300 includes at least one signal processing unit 310.

[0048] Any one of the at least one signal processing units, the signal processing unit 310, has: a signal processing input port 310 i and a signal processing output port 310 o。

[0049] Signal processing input port 310 i Correspondingly serves as the module input port 300 i , and the signal processing output port 310 o Correspondingly serves as the module output port 300 o 。

[0050] The signal processing unit 310 processes the signal obtained by the corresponding signal processing input port 310 i and outputs it through the corresponding signal processing output port 310 o Output.

[0051] Optionally, the secondary multiplexer 200 further includes a source input port, and the source input port is connected to a plurality of source receivers S n in one-to-one correspondence.

[0052] Preferably, as Figure 3 shown, the circuit further includes at least one tertiary multiplexer 400.

[0053] Any one of the at least one tertiary multiplexer 400 has: a tertiary signal input port 400 si and a tertiary signal gating port 400 so 。

[0054] The tertiary signal input port 400 si is connected to the secondary signal output port 200 so in one-to-one correspondence.

[0055] The tertiary signal gating port 400 so outputs the signal transmitted by the secondary signal gating port 200 that is set to be conductive among the secondary signal gating ports of the corresponding secondary multiplexer 200 si transmitted.

[0056] The number of tertiary multiplexers is equal to the number of secondary multiplexers.

[0057] Preferably, the tertiary signal gating port 400 so is connected to the module. The selected path transmits the signal from the preset source receiver to the corresponding module for processing.

[0058] Preferably, the circuit further includes: a channel selection module.

[0059] The channel selection module generates a control signal for controlling the conduction of the corresponding multiplexer channel. Schematically, a multiplexer has four channels, the control signal 00 indicates selecting the first channel, the control signal 01 indicates selecting the second channel, the control signal 10 indicates selecting the third channel, and the control signal 11 indicates selecting the fourth channel.

[0060] The channel selection module is connected to the first-stage multiplexer, the second-stage multiplexer, and the third-stage multiplexer (not shown in the figure), and is used to set the on or off state of the first-stage signal gating port, the second-stage signal gating port, and the third-stage signal gating port.

[0061] In some other embodiments, such as Figure 7 shown, the signal processing module 300 includes a first signal processing unit 310a.

[0062] The first signal processing unit 310a has at least two first unit signal input ports 310a i , and a first unit signal output port 310a o .

[0063] At least two first unit signal input ports 310a i correspondingly serve as the module input ports 300 i .

[0064] The first unit signal output port 310a o serves as the module output port 300 o .

[0065] Specifically, the first signal processing unit is a logic operation unit.

[0066] The logic operation unit includes: one or at least two combinations of basic logic gates, arithmetic units, numerical comparators, selectors, distributors, parity checkers, shift operation units, encoders, decoders, and numerical converters.

[0067] Schematically, the basic logic gates include at least one of: AND gate, OR gate, NAND gate, NOR gate, XOR gate, and XNOR gate.

[0068] The arithmetic unit includes at least one of: half adder, full adder, half subtractor, full subtractor, and carry generator.

[0069] The numerical comparator includes at least one of: one-bit comparator and multi-bit comparator.

[0070] The encoder includes at least: priority encoder.

[0071] The decoder includes at least: binary decoder.

[0072] In some other embodiments, such as Figure 6 shown, the signal processing module 300 includes: a second signal processing unit 310b and a third signal processing unit 310c.

[0073] The second signal processing unit 310b has a second unit signal output port 310bo The third signal processing unit has a third unit signal output port 310c o .

[0074] The first - stage multiplexer 100 also has a processing signal receiving port 100 pi .

[0075] The second unit signal output port 310b o is connected to the processing signal receiving port 100 of the first - stage multiplexer 100 connected to the third signal processing unit 310c pi for connection.

[0076] The third unit signal output port 310c o is connected to the processing signal receiving port 100 of the first - stage multiplexer 100 connected to the second signal processing unit 310b pi for connection.

[0077] Optionally, the second signal processing unit 310b is a low - pass filter, and the third signal processing unit 310c is a high - pass filter.

[0078] By setting the conduction or cut - off of the selected ports of the signal pre - processing circuit described in the embodiments of the present application, a group of signal processing modules are used to process the input signals of any signal source and output them to the corresponding subsequent chip modules. Low - pass, high - pass, and band - pass filtering of signals can be achieved, and logical operations on signals can be realized. The circuit area is saved, and the multiplexing degree of the signal processing module is improved.

[0079] Embodiment 1 A signal pre - processing circuit, as Figure 4 shown, includes four first - stage multiplexers 100, four second - stage multiplexers 200, four third - stage multiplexers 400, a signal processing module 300, and four signal source receiving ends.

[0080] The signal source receiving ends are respectively: the first signal source receiving end S 1 , the second signal source receiving end S 2 , the third signal source receiving end S 3 , and the fourth signal source receiving end S 4 .

[0081] Any one of the first - stage multiplexers 100 respectively has four first - stage signal selection ports 100 si , and a first - stage signal output port 100 so .

[0082] Any one of the second - stage multiplexers 200 respectively has four second - stage signal selection ports 200 si , and a second - stage signal output port 200 so .

[0083] Each three - stage multiplexer 400 has a number of three - stage signal gating ports 400 so , and a three - stage signal input port 400 si .

[0084] The signal processing module 300 has four module input ports 300 i and four module output ports 300 o .

[0085] The signal processing module 300 includes four signal processing units 310.

[0086] Each signal processing unit 310 has: a signal processing input port 310 i and a signal processing output port 310 o .

[0087] The signal processing input port 310 i corresponds one - to - one to a module input port 300 i , and the signal processing output port 310 o corresponds one - to - one to a module output port 300 o .

[0088] The signal processing unit 310 processes the signal obtained by the corresponding signal processing input port 310 i and outputs it through the corresponding signal processing output port 310 o .

[0089] Optionally, each signal processing unit 310 is one of a low - pass filter, a high - pass filter, a band - pass filter, and a special filter.

[0090] Preferably, the above - mentioned filter is a digital filter.

[0091] Any signal source receiving end is connected to a first - stage signal gating port 100 of any first - stage multiplexer si in a one - to - one correspondence. Any first - stage signal output port 100 so is connected to a module input port 300 i in a one - to - one correspondence. Any module output port 300 o is connected to a second - stage signal gating port 200 of any second - stage multiplexer si in a one - to - one correspondence. The second - stage signal output port 200 so is connected to a three - stage signal input port 400 si in a one - to - one correspondence.

[0092] The circuit further includes a channel selection module ( Figure 4 not shown in the figure). Through the channel selection module, Figure 4Among them, the first first-level signal selection port 100 of the second first-level multiplexer from top to bottom si is set to be conductive, and the second second-level signal selection port 200 of the third second-level multiplexer from top to bottom 200 si is set to be conductive, and the first third-level signal selection port 400 of the third third-level multiplexer from top to bottom 400 so is set to be conductive.

[0093] The signal input by the first signal source receiving end S 1 passes through the second first-level multiplexer 100 from top to bottom, is processed by the second signal processing unit 310 from top to bottom in the signal processing module 300, and then passes through the second-level signal output port 200 of the third second-level multiplexer from top to bottom so and is transmitted to the first third-level signal selection port 400 of the third third-level multiplexer from top to bottom so , as Figure 4 shown by the arrow path in. The first third-level signal selection port 400 of the third third-level multiplexer from top to bottom so is connected to module 31 for module 31 to process the signal.

[0094] In this embodiment, by setting the conversion channel selection module, other signal paths can also be selected. For example: the second first-level signal selection port 100 of the first first-level multiplexer from top to bottom si is set to be conductive, and the first second-level signal selection port 200 of the second second-level multiplexer from top to bottom si is set to be conductive, and the first third-level signal selection port 400 of the second third-level multiplexer from top to bottom so is set to be conductive.

[0095] The signal input by the second signal source receiving end S 2 passes through the first and multiplexers from top to bottom, is processed by the first signal processing unit from top to bottom in the signal processing module, and then is transmitted from the first second-level signal selection port of the second second-level multiplexer from top to bottom to the first third-level signal selection port 400 of the second third-level multiplexer from top to bottom so and is transmitted to module 21 to process the signal.

[0096] Multiple signal path settings can also be carried out simultaneously for the corresponding modules to process signals simultaneously.

[0097] Embodiment 2 A signal preprocessing circuit, as Figure 5 shown, includes two first-level multiplexers 100, four second-level multiplexers 200, four third-level multiplexers 400, a signal processing module 300, and four signal source receiving ends.

[0098] The source receiving ends are respectively: the first source receiving end S 1 , the second source receiving end S 2 , the third source receiving end S 3 , the fourth source receiving end S 4 .

[0099] Any one-level multiplexer 100 respectively has four one-level signal selection ports 100 si , and one one-level signal output port 100 so .

[0100] Any two-level multiplexer 200 respectively has two two-level signal selection ports 200 si , and one two-level signal output port 200 so . Figure 5 The top-down first two-level multiplexer 200 also has two source input ports 200 ssi , which are respectively connected to the first source receiving end S 1 and the second source receiving end S 2 .

[0101] Any three-level multiplexer 400 respectively has a number of three-level signal selection ports 400 so , and one three-level signal input port 400 si .

[0102] The signal processing module 300 has two module input ports 300 i and two module output ports 300 o .

[0103] The signal processing module 300 includes two signal processing units 310.

[0104] Any signal processing unit 310 has: a signal processing input port 310 i and a signal processing output port 310 o .

[0105] The signal processing input port 310 i corresponds one-to-one to the module input port 300 i , and the signal processing output port 310 o corresponds one-to-one to the module output port 300 o .

[0106] The signal processing unit 310 processes the signal obtained by the corresponding signal processing input port 310 i , and outputs it through the corresponding signal processing output port 310 o .

[0107] Optionally, each signal processing unit 310 is one of a low-pass filter, a high-pass filter, a band-pass filter, and a special filter.

[0108] Preferably, the above filters are digital filters.

[0109] Any source receiving end is connected to a signal selection port 100 of any first-level multiplexer si in a one-to-one correspondence. Any first-level signal output port 100 so is connected to the module input port 300 i in a one-to-one correspondence. Any module output port 300 o is connected to a second-level signal selection port 200 of any second-level multiplexer si in a one-to-one correspondence. The second-level signal output port 200 so is connected to the third-level signal input port 400 si in a one-to-one correspondence.

[0110] The circuit further includes a channel selection module ( Figure 5 not shown in the figure). Through the channel selection module, Figure 5 in the figure, the third first-level signal selection port 100 of the second first-level multiplexer from top to bottom si is set to be conductive, and the second second-level signal selection port 200 of the third second-level multiplexer 200 from top to bottom si is set to be conductive, and the first third-level signal selection port 400 of the third third-level multiplexer 400 from top to bottom so is set to be conductive.

[0111] The signal input by the third source receiving end S 3 passes through the third first-level multiplexer 100 from top to bottom, is processed by the second signal processing unit 310 from top to bottom in the signal processing module 300, and is transmitted from the second-level signal output port 200 of the third second-level multiplexer 200 from top to bottom so to the first third-level signal selection port 400 of the third third-level multiplexer 400 from top to bottom so , as Figure 5 shown by the solid arrow path in the figure. The first third-level signal selection port 400 of the third third-level multiplexer 400 from top to bottom so is connected to module 31 for module 31 to process the signal.

[0112] Through the channel selection module, Figure 5 in the figure, the first source input port 200 of the first second-level multiplexer 200 from top to bottom ssi is set to be conductive, and the first third-level signal selection port 400 of the first third-level multiplexer 400 from top to bottom soSet to be conductive. The first three-stage signal selection port 400 of the top-down first three-stage multiplexer 400 so is connected to module 11, and the signal received by the first signal source receiving end S 1 is transmitted to module 11 for processing, as shown by the dashed arrow in Figure 5 the figure.

[0113] The setting method of the channel selection module is as described in Embodiment 1 and will not be elaborated here.

[0114] Embodiment 3 A signal preprocessing circuit, as shown in Figure 6 the figure, includes two first-stage multiplexers 100, four second-stage multiplexers 200, four third-stage multiplexers 400, a signal processing module 300, and four signal source receiving ends.

[0115] The signal source receiving ends are respectively: the first signal source receiving end S 1 , the second signal source receiving end S 2 , the third signal source receiving end S 3 , and the fourth signal source receiving end S 4 .

[0116] Any one of the first-stage multiplexers 100 respectively has four first-stage signal selection ports 100 si , and one first-stage signal output port 100 so .

[0117] Any one of the second-stage multiplexers 200 respectively has two second-stage signal selection ports 200 si , and one second-stage signal output port 200 so .

[0118] Any one of the third-stage multiplexers 400 respectively has several third-stage signal selection ports 400 so , and one third-stage signal input port 400 si .

[0119] The signal processing module 300 has two module input ports 300 i and two module output ports 300 o .

[0120] The signal processing module 300 includes a second signal processing unit 310b and a third signal processing unit 310c.

[0121] The second signal processing unit has: a second signal unit input port 310b i and a second unit signal output port 310b o .

[0122] The third signal processing unit has: a third signal unit input port 310c i and a third unit signal output port 310c o .

[0123] The second signal processing unit 310b is a low-pass filter, and the third signal processing unit 310c is a high-pass filter.

[0124] Preferably, the above filters are digital filters.

[0125] Any one of the first-level multiplexers also has a processed signal receiving port 100 sri .

[0126] The second unit signal output port 310b o is connected to the processed signal receiving port 100 of the first-level multiplexer connected to the third unit signal processing unit sri ; The third unit signal output port 310c o is connected to the processed signal receiving port 100 of the first-level multiplexer connected to the second unit signal processing unit sri ;

[0127] The second signal unit input port 310b i serves as a module input port 300 i , and the third signal unit input port 310c i serves as another module input port 300 i .

[0128] The signal processing input port 310 i serves as a module input port 300 one by one i , and the signal processing output port 310 o serves as a module output port 300 one by one o .

[0129] After the signal processing unit 310 processes the signal obtained from the corresponding signal processing input port 310 i , it is output by the corresponding signal processing output port 310 o .

[0130] Any signal source receiving end is connected to a pole signal gating port 100 of any one of the first-level multiplexers one by one si , any one of the signal output ports 100 so is connected to the module input port 300 one by one i , and any module output port 300 o is connected to a second-level signal gating port 200 of any one of the second-level multiplexers one by one si . The second-level signal output port 200so is correspondingly connected to the third-level signal input port 400 si one by one.

[0131] The circuit further includes a channel selection module ( Figure 6 not shown in the figure). Through the channel selection module, Figure 6 in the figure, the third first-level signal selection port 100 of the second first-level multiplexer from top to bottom si is set to be conducting, and the first second-level signal selection port 200 of the third second-level multiplexer 200 from top to bottom si is set to be conducting, and the first third-level signal selection port 400 of the third third-level multiplexer 400 from top to bottom so is set to be conducting.

[0132] The signal input by the third signal source receiving end S 3 passes through the third first-level multiplexer 100 from top to bottom, successively passes through the third signal processing unit 310c and the second signal processing unit 310b, and is transmitted from the second-level signal output port 200 of the third second-level multiplexer 200 from top to bottom so to the first third-level signal selection port 400 of the third third-level multiplexer 400 from top to bottom so , as Figure 6 shown by the arrow path in the figure. The first third-level signal selection port 400 of the third third-level multiplexer 400 from top to bottom so is connected to module 31 for module 31 to process the signal.

[0133] The setting method of the channel selection module is as described in Embodiment 1 and will not be elaborated here.

[0134] Embodiment 4 A signal preprocessing circuit, as Figure 7 shown in the figure, includes two first-level multiplexers 100, four second-level multiplexers 200, four third-level multiplexers 400, a signal processing module 300, and four signal source receiving ends.

[0135] The signal source receiving ends are respectively: the first signal source receiving end S 1 , the second signal source receiving end S 2 , the third signal source receiving end S 3 , and the fourth signal source receiving end S 4 .

[0136] Any one of the first-level multiplexers 100 respectively has four first-level signal selection ports 100 si , and one first-level signal output port 100 so .

[0137] Any one of the second-level multiplexers 200 respectively has two second-level signal selection ports 200si , and a secondary signal output port 200 so .

[0138] Any one of the tertiary multiplexers 400 respectively has a plurality of tertiary signal gating ports 400 so , and a tertiary signal input port 400 si .

[0139] The signal processing module 300 has two module input ports 300 i and a module output port 300 o .

[0140] The signal processing module 300 includes a first signal processing unit 310a.

[0141] The first signal processing unit 310a has: two first signal unit input ports 310a i and a first unit signal output port 310a o .

[0142] The first signal processing unit 310a is a logic operation unit.

[0143] The logic operation unit includes: one or a combination of at least two of basic logic gates, arithmetic units, numerical comparators, selectors, distributors, parity checkers, shift operation units, encoders, decoders, and numerical converters.

[0144] The two first signal unit input ports 310 ai respectively serve as the module input ports 300 i , and the first unit signal output port 310 ao serves as the module output port 300 o .

[0145] The signal processing unit 310 processes the signals obtained by the corresponding first signal unit input ports 310 ai and outputs them from the corresponding signal processing output ports 310 o .

[0146] Any one of the signal source receiving ends is connected in one-to-one correspondence with a primary signal gating port 100 of any one of the primary multiplexers si , and any one of the primary signal output ports 100 so is connected in one-to-one correspondence with the module input port 300 i , and any one of the module output ports 300 o is connected in one-to-one correspondence with a secondary signal gating port 200 of any one of the secondary multiplexers si . The secondary signal output port 200 so is connected to the tertiary signal input port 400si One-to-one connection.

[0147] The circuit further includes a channel selection module ( Figure 7 not shown in the figure). Through the channel selection module, Figure 7 in the figure, the first first-level signal selection port 100 of the first first-level multiplexer from top to bottom si , and the second and signal selection port 100 of the second first-level multiplexer si are set to be conductive; the first second-level signal selection port 200 of the third second-level multiplexer 200 from top to bottom si is set to be conductive, and the first third-level signal selection port 400 of the third third-level multiplexer 400 from top to bottom so is set to be conductive.

[0148] The signals input by the first signal source receiving end S 1 and the second signal source receiving end S 2 are logically operated by the first signal processing unit 310a and then transmitted to the first third-level signal selection port 400 of the third third-level multiplexer 400 from top to bottom so , as Figure 7 shown by the arrow path in the figure. The first third-level signal selection port 400 of the third third-level multiplexer 400 from top to bottom so is connected to module 31 for module 31 to process the signal.

[0149] The setting method of the channel selection module is as described in Embodiment 1 and will not be elaborated here.

[0150] All the above optional technical solutions can be combined arbitrarily to form optional embodiments of the present application, which will not be elaborated one by one here.

[0151] Note that the above is only a preferred embodiment of the present invention and the applied technical principles. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described here, and various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A signal preprocessing circuit, characterized in that: include: At least one primary multiplexer, at least one secondary multiplexer, a signal processing module and a plurality of signal source receiving terminals; Any one of the at least one first-level multiplexer has: a first-level signal selection port and a first-level signal output port; Any of the at least one secondary multiplexer has: a secondary signal selection port and a secondary signal output port; The signal processing module has: a module input port and a module output port; Any one of the plurality of information source receiving ends is connected to the primary signal gating port of any one of the primary multiplexers in a one-to-one correspondence, any one of the primary signal output ports is connected to the module input port in a one-to-one correspondence, and the module output port is connected to the secondary signal gating port of any one of the secondary multiplexers in a one-to-one correspondence; By setting the on or off state of the primary signal selection port and the secondary signal selection port, a signal obtained by any one of the plurality of signal source receiving ends is transmitted to a preset secondary signal output port after being processed by a signal processing module.

2. The signal preprocessing circuit according to claim 1, characterized in that: The signal processing module includes at least one signal processing unit; Any signal processing unit of the at least one signal processing unit has a signal processing input port and a signal processing output port; The signal processing input ports are used as the module input ports in a one-to-one correspondence, and the signal processing output ports are used as the module output ports in a one-to-one correspondence; The signal processing unit processes the signal acquired by the corresponding signal processing input port and outputs the processed signal through the corresponding signal processing output port.

3. The signal preprocessing circuit according to claim 1, characterized in that: The secondary multiplexer also includes a source input port; The information source input port is connected to the plurality of information source receiving ends in a one-to-one correspondence.

4. The signal preprocessing circuit according to claim 1, characterized in that: The circuit also includes at least one three-stage multiplexer; Any of the at least one three-stage multiplexer has: a three-stage signal input port and a three-stage signal selection port; The third-level signal input port is connected to the second-level signal output port in a one-to-one correspondence; The third-level signal selection port outputs a signal received by the second-level signal selection port that is set to be turned on among the second-level signal input ports of the correspondingly connected second-level multiplexer.

5. The signal preprocessing circuit according to claim 4, characterized in that: The number of the three-stage multiplexers is equal to the number of the two-stage multiplexers.

6. The signal preprocessing circuit according to claim 1, characterized in that: The circuit further comprises: a channel selection module; The channel selection module is connected to the primary multiplexer, the secondary multiplexer and the tertiary multiplexer, and is used to set the on or off state of the primary signal gating port, the secondary signal gating port and the tertiary signal gating port.

7. The signal preprocessing circuit according to any one of claims 1 to 6, characterized in that: The signal processing module includes a first signal processing unit; The first signal processing unit has at least two first unit signal input ports and a first unit signal output port; The at least two first unit signal input ports are used as the module input ports in a one-to-one correspondence; The first unit signal output port serves as a module output port.

8. The signal preprocessing circuit according to claim 7, characterized in that: The first signal processing unit is a logic operation unit; The logic operation unit includes: one or a combination of at least two of a basic logic gate, an arithmetic operator, a numerical comparator, a selector, a distributor, a parity checker, a shift operator, an encoder, a decoder, and a numerical converter.

9. The signal preprocessing circuit according to any one of claims 1 to 6, characterized in that: The signal processing module includes: a second signal processing unit and a third signal processing unit; The second signal processing unit has a second unit signal output port; The third signal processing unit has a third unit signal output port; The first-level multiplexer also has a processing signal receiving port; The second unit signal output port is connected to the processing signal receiving port of the first-level multiplexer connected to the third unit signal processing unit; The third unit signal output port is connected to the processing signal receiving port of the first-level multiplexer connected to the second unit signal processing unit.

10. The signal preprocessing circuit according to claim 9, characterized in that: The second signal processing unit is a low-pass filter, and the third signal processing unit is a high-pass filter.

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