Universal digital beam forming weighting circuit

Abstract

The invention discloses a universal digital beam forming weighting circuit, which comprises a power multiplication module and a beam forming module, and is used for matching different channel numbers, beam numbers and single calculation path beam numbers in a mode of external parameter configuration so as to realize the operation of signed fixed-point channel data power multiplication and beam forming. Wherein the power-multiplying module is divided into 32 power-multiplying calculation channels, dispatches input channel data to copy and distribute the data to different power-multiplying calculation channels for parallel power-multiplying operation, and then outputs beam data in parallel; and the beam forming module receives the 32-path beam data output by the power module, rearranges the 32-path beam data, and outputs the 32-path beam data after hierarchical parallel addition. By externally configuring adjustable parameters such as the number of channels in the circuit, the number of wave beams and the number of wave beams of a single calculation path, the circuit can be automatically adapted to different application scenes, channel data input by a SerDes high-speed interface can be received, and power multiplication and wave beam synthesis operation can be completed.

Description

Technical Field

[0001] The invention belongs to the technical field of digital chips, and in particular relates to a universal digital beamforming weighting circuit. Background Art

[0002] At present, digital beamforming technology is widely used in radar, communication, sonar and other fields. Its core is to achieve dynamic control of beam pointing by weighting and synthesizing multi-channel signals.

[0003] Traditional solutions are mostly based on FPGA (field programmable gate array), which has certain flexibility. However, as the application scenarios have increasingly stringent requirements for real-time, power consumption, integration and reliability, the limitations of FPGA are gradually highlighted. For example: Processing performance bottleneck: FPGA's parallel computing capabilities are limited by logic resources, and it is difficult to meet the real-time requirements of large-scale channels (such as hundreds of channels) and dense beam synthesis; power consumption and volume limitations: FPGA has high static power consumption and needs to be matched with peripheral circuits, which is difficult to meet the low power consumption and high integration requirements of miniaturized devices; Lack of flexibility: FPGA needs to be reprogrammed through hardware description language to adapt to different parameter configurations, with a long development cycle and limited dynamic adjustment capabilities.

[0004] On the other hand, although application-specific integrated circuits (ASICs) can improve performance and energy efficiency, their designs are usually targeted at specific application scenarios and have poor versatility. For example, it is difficult to expand after parameters such as the number of channels and the number of beams are fixed, resulting in low chip reuse and high development costs. Therefore, how to achieve universal design of digital beamforming circuits while ensuring high performance and low power consumption has become a key issue that needs to be solved in this field. Summary of the invention

[0005] In order to solve the above problems, the present invention proposes a universal digital beamforming weighting circuit, including a weighting module and a beamforming module, which matches different channel numbers, beam numbers and single calculation path beam numbers through external parameter configuration to realize the operations of signed fixed-point channel data multiplication and beamforming; wherein the weighting module is divided into 32 weighting calculation paths, and the input channel data is copied and distributed to different weighting calculation paths for parallel weighting operations, and then the beam data is output in parallel; the beamforming module receives the 32 beam data output by the weighting module, reorders them, and then performs hierarchical parallel addition and outputs them.

[0006] Further, the weighting module includes a channel data replication and distribution sub-module and a weighting calculation path. The channel data replication and distribution sub-module serially receives the channel data of each channel according to the range gate and the dimension order of the channels, and controls the number of copies of the currently input channel data to be replicated and the weighting calculation path to be distributed according to the number of channels, the number of beams, and the number of beams per single calculation path. The corresponding weighting calculation paths perform the weighting operation on the channel data in parallel.

[0007] Further, the selection principle for distribution to different weighting calculation paths is that the lower serial number is preferred. After the channel data of the same range gate is replicated, a synchronization control signal is generated to control the distribution of these channel data to each weighting calculation path in the same clock cycle.

[0008] Further, each weighting calculation path includes a complex multiplier and two weight RAMs. The complex multiplier is used to multiply the channel data and the weights to generate beams with different directions. The weight RAM is used to store the weights of the corresponding calculation path. Rotation operations are performed between the two weight RAMs to store the weights of different frames. When one weight RAM participates in the weighting operation, the other weight RAM pre-stores the subsequent weights.

[0009] Further, the complex multiplier has two 32-bit input interfaces and one 64-bit output interface. One of the input interfaces is connected to the output interface of the channel data replication and distribution sub-module. The other input interface is connected to the output interface of one of the weight RAMs under the control of the read RAM selection signal. The output interface is connected to the beam synthesis module for sending the 64-bit beam data generated by weighting.

[0010] Further, the weighting module further includes a weighting calculation control sub-module, and the weighting calculation control sub-module includes a weight RAM write control sub-module. The weight RAM write control sub-module is responsible for generating the write enable and address signals of the weight RAM according to the number of channels, the replication multiple, the weight valid flag, and the weight end flag when writing the weights, and distributing and storing the input weight data to a total of 64 weight RAMs in 32 weighting calculation paths according to the dimension order of the channels and beams.

[0011] Further, the weighting calculation control sub-module further includes a weight RAM read control sub-module. The weight RAM read control sub-module is responsible for generating the read address signal and output selection signal of the weight RAM according to the number of beams per single calculation path, the calculation path data valid flag, and the end flag when reading the weights of the current frame, and providing the weights for each complex multiplier.

[0012] Further, the beam synthesis module receives the beam data generated by each weighting calculation path and synthesizes the beam data according to the principle of adding the beams with the same direction for different channels.

[0013] Further, the beam synthesis module includes a beam synthesis control sub-module; the beam synthesis control sub-module includes a parameter recording sub-module and a data rearrangement sub-module. The parameter recording sub-module is used to record the number of channels, the number of beams, and the number of beams per single calculation path input externally. The data rearrangement sub-module rearranges the 32-channel beam data received from the weighting module according to the above parameters, so that the beam data of different channels, the same range gate, and the same direction can be superimposed in the beam superposition sub-module, and at the same time, the number of superposition levels is output.

[0014] Further, the beam synthesis module further includes a beam superposition sub-module. The beam superposition sub-module performs pipelined superposition on the input 32-channel beam data, and selects the output of a certain level adder as the output of the beam superposition according to the number of superposition levels.

[0015] Further, the number of levels of beam synthesis is related to the number of channels. By extending the sign bit, the bit width of the synthesized beam data is kept consistent.

[0016] Further, according to the configured parameter values, the weighting calculation paths participating in the weighting operation are automatically identified, and the weighting calculation paths not participating in the operation are clocked off.

[0017] Compared with the prior art, the present invention has the following advantages: (1) High generality and configurability: Dynamically configure the number of channels, the number of beams, and the number of beams per single calculation path through external parameters to adapt to different application scenarios (such as radar, 5G Massive MIMO), without re-designing the hardware; support signed fixed-point data operations, be compatible with multiple signal formats, and expand the application range.

[0018] (2) Efficient parallel processing architecture: The weighting module adopts 32 parallel calculation paths, combined with the data replication and distribution strategy, significantly improving the throughput of the weighting operation; the beam synthesis module realizes the low-latency synthesis of multi-channel beam data through hierarchical pipelined superposition (such as a 4-level adder) and dynamic data rearrangement.

[0019] (3) Low-power optimization: The calculation paths not participating in the operation can reduce the dynamic power consumption through the clock-off technology, improving the energy efficiency ratio; the dual-buffer design of the weight RAM (rotation of RAMA / RAMB) supports weight preloading, avoiding operation interruption and reducing redundant power consumption.

[0020] (4) Guarantee of data bit width consistency: Through the sign bit extension technology, ensure that the bit width of the synthesized beam data is consistent under different numbers of channels, avoiding overflow or precision loss in subsequent signal processing links.

[0021] (5) Maximize resource utilization: The weight distribution strategy of the weighting module and the dynamic sorting mechanism of beamforming effectively reduce hardware resource redundancy and improve the reuse rate of computing paths; support SerDes high-speed interface input to meet the high-bandwidth data transmission requirements. Description of the Drawings

[0022] Figure 1 It is the circuit structure diagram of an embodiment of the present invention.

[0023] Figure 2 It is the functional block diagram of the weighting module of an embodiment of the present invention.

[0024] Figure 3 It is the functional block diagram of the beamforming module of an embodiment of the present invention.

[0025] Figure 4 It is the data flow diagram of the weighting module of an embodiment of the present invention.

[0026] Figure 5 It is the data flow diagram of the beam superposition sub-module of an embodiment of the present invention. Specific Embodiments

[0027] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein in the description of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0029] It can be understood that the terms "first", "second", etc. used in the present application can be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element.

[0030] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. can be used herein to describe the relationship of one element or feature shown in the figure with other elements or features. It should be understood that, in addition to the orientations shown in the figure, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the attached drawing is flipped, an element or feature described as "under other elements" or "beneath them" or "under it" will be oriented "above" the other elements or features. Therefore, the exemplary terms "under" and "beneath" can include both the upper and lower orientations. In addition, the device may also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are accordingly interpreted.

[0031] It should be noted that when an element is considered to be "connected" to another element, it may be directly connected to the other element or connected to the other element through an intermediate element. In addition, for "connection" in the following embodiments, if there is a transfer of electrical signals or data between the connected objects, it should be understood as "electrically connected", "communicatively connected", etc.

[0032] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprise / include" or "have" etc. specify the presence of the stated features, wholes, steps, operations, components, parts or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the related listed items.

[0033] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0034] The present invention discloses a general-purpose digital beamforming weighting circuit, which adopts a parallel operation architecture, integrates a multiplication weighting module and a beamforming module, and matches different numbers of channels, beams and beams per single calculation path through external parameter configuration, so as to realize the operation of signed fixed-point channel data multiplication weighting and beamforming. Among them, the multiplication weighting module is divided into 32 multiplication weighting calculation paths. Externally, by configuring parameters such as the number of channels, the number of beams and the number of beams per single calculation path, the input channel data is scheduled to be replicated and distributed to different calculation paths for parallel multiplication weighting operations, and then the beam data is output in parallel; the beamforming module receives the 32-way beam data output by the multiplication weighting module, reorders them, and then outputs them after hierarchical parallel addition.

[0035] The composition and functions of the weighting module and the beamforming module will be described in detail below.

[0036] The weighting module mainly consists of sub-modules such as 1 channel data replication and distribution, 32 weighting calculation paths, and 1 weighting calculation control.

[0037] The channel data replication and distribution sub-module serially receives 32-bit data (each of the real part and the imaginary part contains 1-bit sign bit and 15-bit data bit) of each channel in the order of range gate and channel dimensions. Then, according to parameters such as the number of channels, the number of beams, and the number of beams per single calculation path, it controls the number of copies of the currently input channel data to be replicated and the weighting calculation paths to be distributed. The corresponding weighting calculation paths perform the weighting operation on the channel data in parallel. The selection principle of the weighting calculation path is that the lower serial number is preferred. For example, if the number of channels is 3, the number of beams is 64, and the number of beams per single calculation path is 16, then the replication multiple = number of beams ÷ number of beams per single calculation path = 64 ÷ 16 = 4, and a total of number of channels × replication multiple = 3 × 4 = 12 calculation paths are occupied. Then, calculation paths numbered 0 to 11 are selected. Among them, channel 0 is replicated to calculation paths numbered 0 to 3, channel 1 is replicated to calculation paths numbered 4 to 7, and channel 2 is replicated to calculation paths numbered 8 to 11. After the channel data of the same range gate is replicated, a synchronization control signal is generated to control the distribution of these channel data to each weighting calculation path in the same clock cycle. According to the configured parameter values, it automatically identifies the weighting calculation paths participating in the weighting operation and shuts off the clocks of the weighting calculation paths that do not participate in the operation, thereby reducing the circuit power consumption.

[0038] Each weighting calculation path contains 1 complex multiplier and 2 weight RAMs (as Figure 2 shown, specifically weight RAM A and weight RAM B). The complex multiplier is used to multiply the channel data and the weights to generate beams with different directions; the weight RAM is used to store the weights of this calculation path, and rotation operations are performed between the 2 RAMs to store the weights of different frames. When one of the RAMs participates in the weighting operation, the other RAM pre-stores the subsequent weights.

[0039] The complex multiplier has two 32-bit input interfaces and 1 64-bit output interface. One of the input interfaces is connected to the output interface of the channel data replication and distribution sub-module; the other input interface is connected to the output interface of one of the weight RAMs (each of the real part and the imaginary part contains 1-bit sign bit and 15-bit data bit) under the control of the read RAM selection signal (implemented through a MUX (multiplexer)); the output interface is connected to the beamforming module for sending the 64-bit beam data generated by the weighting.

[0040] The multiplication weight calculation control sub-module mainly includes sub-modules such as weight RAM write control and weight RAM read control. The weight RAM write control sub-module is responsible for generating the write enable and address signals of the weight RAM when writing weights, and distributing and storing the input weight data to a total of 64 weight RAMs in 32 multiplication weight calculation paths according to information such as the number of channels, replication factor, weight valid flag, and weight end flag, in the order of the dimensions of channels and beams. The weight RAM read control sub-module is responsible for generating the read address signal and output selection signal of the weight RAM when reading the weights of the current frame, and providing weights for each complex multiplier according to information such as the number of beams in a single calculation path, calculation path data valid flag, and end flag.

[0041] The beam synthesis module mainly consists of 1 beam synthesis control sub-module and 1 beam superposition sub-module. The beam synthesis module receives the beam data generated by each multiplication weight calculation path, and synthesizes the beam data according to the principle of adding beams with the same direction for different channels.

[0042] The beam synthesis control sub-module mainly includes a parameter recording sub-module and a data rearrangement sub-module. The parameter recording sub-module is used to record parameter information such as the number of channels, number of beams, and number of beams in a single calculation path input externally; the data rearrangement sub-module rearranges the 32-way beam data received from the multiplication weight module according to the above parameters, so that the beam data with the same range gate and the same direction for different channels can be superimposed in the beam superposition sub-module, and at the same time outputs the number of superposition levels; the beam superposition sub-module performs pipelined superposition on the input 32-way beam data, and selects the output of a certain adder as the output of the beam superposition according to the number of superposition levels. The number of levels of beam synthesis is related to the number of channels, and the bit width of the synthesized beam data is kept consistent by extending the sign bit.

[0043] The following combines the accompanying drawings and takes the parameter values: number of channels 8, number of beams 64, and number of beams in a single calculation path 16 as an example to specifically illustrate the technical solution of the present invention.

[0044] The functional block diagram of the multiplication weight module is as Figure 1As shown in the figure, before the weight and channel data are input, parameters such as the number of channels, the number of beams, and the number of beams in a single calculation path are input externally through the control interface. After all the parameters are recorded by the module, the weight data is input externally in the order of the dimensions of channels and beams. Under the control of the weight multiplication calculation control sub-module, these weights are sequentially distributed to 32 weight multiplication calculation paths and are designated to be stored in one of the weight RAM A and weight RAM B. After a set of weights is stored, the multi-channel data is input serially and crosswise externally. The channel data replication and distribution sub-module replicates and distributes the channel data to 32 weight multiplication calculation paths and ensures that the data of the same range gate is distributed to each weight multiplication calculation path simultaneously after replication. Under the control of the weight multiplication calculation control sub-module, each calculation path reads the weights in the specified RAM simultaneously and multiplies them with the input channel data to obtain the beam data responsible for its own calculation.

[0045] The data flow of the weight multiplication module is as Figure 4 shown in the figure. In the figure, D0Ch0 represents the data of the 0th range gate and the 0th channel, and B0Ch0 represents the 0th beam generated by the 0th channel. The 0th path sequentially outputs the 0th to 15th beams (B0Ch0~B15Ch0) of channel 0, the 1st path sequentially outputs the 16th to 31st beams (B16Ch0~B31Ch0) of channel 0, the 2nd path sequentially outputs the 32nd to 47th beams (B32Ch0~B47Ch0) of channel 0, the 3rd path sequentially outputs the 48th to 63rd beams (B48Ch0~B63Ch0) of channel 0, the 4th path sequentially outputs the 0th to 15th beams (B0Ch1~B15Ch1) of channel 1, and so on. After 16 clock cycles, 8 channels × 4 times × 16 beams = 512 beams are output in parallel.

[0046] The functional block diagram of the beam synthesis sub-module is as Figure 3 shown. The beam synthesis control sub-module reorders the 32-way beam data sent by the weight multiplication module and then sends it to the beam superposition sub-module. The beam superposition sub-module receives the above 32-way beam data that has been sorted, and after passing through a 4-stage adder, synthesizes 64 beams and outputs them in parallel from 4 output interfaces.

[0047] The data flow of the beam superposition sub-module is shown in Figure 5 , where D0Ch0B0 in the figure represents the 0th beam generated by the 0th range gate and the 0th channel, and D0CH 0-1 B0 represents the synthesis result of the 0th beam generated by the 0th channel and the 0th beam generated by the 1st channel in the 0th range gate.

[0048] The present invention enables the circuit to automatically adapt to different application scenarios by externally configuring adjustable parameters such as the number of internal channels, the number of beams, and the number of beams per computational path in the circuit. It can receive channel data input from a SerDes high-speed interface and complete multiplication-weighting and beamforming operations.

[0049] The general-purpose digital beamforming weighting circuit proposed by the present invention has the following significant advantages compared with the prior art: (1) High versatility and configurability: Dynamically configure the number of channels, the number of beams, and the number of beams per computational path through external parameters to adapt to different application scenarios (such as radar, 5G Massive MIMO), without the need to redesign the hardware; support signed fixed-point data operations, be compatible with multiple signal formats, and expand the application scope.

[0050] (2) Efficient parallel processing architecture: The multiplication-weighting module adopts 32 parallel computational paths and combines a data replication and distribution strategy to significantly improve the throughput of multiplication-weighting operations; the beamforming module realizes low-latency synthesis of multi-channel beam data through hierarchical pipelining superposition (such as a 4-stage adder) and dynamic data rearrangement.

[0051] (3) Low-power optimization: The computational paths not participating in the operation can reduce the dynamic power consumption through clock gating technology, improving the energy efficiency ratio; the dual-buffer design of the weight RAM (rotation of RAMA / RAMB) supports weight preloading, avoids operation interruption, and reduces redundant power consumption.

[0052] (4) Guarantee of data bit-width consistency: Through sign-bit extension technology, ensure that the bit-width of the synthesized beam data is consistent under different numbers of channels, avoiding overflow or precision loss in subsequent signal processing.

[0053] (5) Maximization of resource utilization: The weight distribution strategy of the multiplication-weighting module and the dynamic sorting mechanism of beamforming effectively reduce hardware resource redundancy and improve the reuse rate of computational paths; support input from a SerDes high-speed interface to meet the high-bandwidth data transmission requirements.

[0054] In summary, the present invention is superior to traditional FPGA solutions and fixed-function ASICs in terms of versatility, real-time performance, power consumption control, and resource efficiency, providing an efficient and flexible technical foundation for the design of the next-generation digital beamforming chips.

[0055] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A general digital beamforming weighting circuit, characterized in that: It includes a weighted multiplication module and a beam synthesis module. Through external parameter configuration, different channel numbers, beam numbers and single calculation path beam numbers are matched to realize the operations of signed fixed-point channel data multiplication and beam synthesis. Among them, the weighted multiplication module is divided into 32 weighted multiplication calculation paths, and the input channel data is copied and distributed to different weighted multiplication calculation paths for parallel weighted multiplication operations, and then the beam data is output in parallel. The beam synthesis module receives the 32 beam data output by the weighted multiplication module, reorders them, and then outputs them after hierarchical parallel addition.

2. The universal digital beamforming weighting circuit according to claim 1, characterized in that: The multiplication module includes a channel data replication and distribution submodule and a multiplication calculation path; the channel data replication and distribution submodule receives the channel data in serial order according to the dimensional order of the range gate and the channel, and controls the number of copies of the current input channel data to be copied and the multiplication calculation path to be distributed according to the number of channels, the number of beams and the number of beams of a single calculation path. The corresponding multiplication calculation path completes the multiplication operation of the channel data in parallel.

3. The universal digital beamforming weighting circuit according to claim 1, characterized in that: The selection principle when distributing to different weighted calculation paths is that low sequence numbers are given priority; after the data of each channel of the same distance gate is copied, a synchronization control signal is generated to control the distribution of these channel data to each weighted calculation path in the same clock cycle.

4. The universal digital beamforming weighting circuit according to claim 1, characterized in that: Each weighted calculation path includes a complex multiplier and two weight RAMs; the complex multiplier is used to multiply channel data and weights to generate beams with different directions; the weight RAM is used to store the weights of the corresponding calculation path. The two weight RAMs are rotated to store weights of different frames. When one of the weight RAMs participates in the weighted calculation, the other weight RAM stores the subsequent weights.

5. The universal digital beamforming weighting circuit according to claim 4, characterized in that: The complex multiplier has two 32-bit input interfaces and one 64-bit output interface. One of the input interfaces is connected to the output interface of the channel data replication and distribution submodule; the other input interface is connected to the output interface of one of the weight RAMs under the control of the read RAM selection signal; the output interface is connected to the beam synthesis module to send the 64-bit beam data generated by the multiplication.

6. The universal digital beamforming weighting circuit according to claim 1, characterized in that: The multiplication weight module also includes a multiplication weight calculation control submodule, and the multiplication weight calculation control submodule includes a weight RAM write control submodule; The weight RAM write control submodule is responsible for generating the write enable and address signals of the weight RAM according to the number of channels, replication multiples, weight validity flag and weight end flag when writing weights, and distributes and stores the input weight data to the 64 weight RAMs in the 32-way multiplication calculation path in the order of channel and beam dimensions.

7. The universal digital beamforming weighting circuit according to claim 6, characterized in that: The multiplication weight calculation control submodule also includes a weight RAM read control submodule; The weight RAM read control submodule is responsible for generating the read address signal and output selection signal of the weight RAM according to the single calculation path beam number, calculation path data valid flag and end flag when reading the current frame weight, and providing weights for each complex multiplier.

8. The universal digital beamforming weighting circuit according to claim 1, characterized in that: The beam synthesis module receives the beam data generated by each weight calculation path, and synthesizes the beam data according to the principle of adding beams of different channels and the same direction.

9. The universal digital beamforming weighting circuit according to claim 8, characterized in that: The beamforming module includes a beamforming control submodule; the beamforming control submodule includes a parameter recording submodule and a data rearrangement submodule, the parameter recording submodule is used to record the number of channels, the number of beams and the number of beams of a single calculation path input externally; The data rearrangement submodule reorders the 32 beam data received from the weighting module according to the above parameters, so that beam data of different channels, the same range gate and the same direction can be superimposed in the beam superposition submodule, and the superposition level is output at the same time.

10. The universal digital beamforming weighting circuit according to claim 9, characterized in that: The beam synthesis module also includes a beam superposition submodule, which performs pipeline superposition on the input 32-way beam data and selects a certain level of adder output as the output of beam superposition according to the number of superposition levels.

11. The universal digital beamforming weighting circuit according to claim 9 or 10, characterized in that: The level of beamforming is related to the number of channels. By extending the sign bit, the bit width of the synthesized beam data remains consistent.

12. The universal digital beamforming weighting circuit according to claim 1, characterized in that: According to the configured parameter values, the multiplication calculation paths participating in the multiplication calculation are automatically identified, and the clocks of the multiplication calculation paths not participating in the calculation are turned off.

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